Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 0 18 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 0 18 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 384 1 T38 22 T61 10 T62 17
all_values[1] 384 1 T38 22 T61 10 T62 17
all_values[2] 384 1 T38 22 T61 10 T62 17


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 628 1 T38 35 T61 17 T62 29
auto[1] 524 1 T38 31 T61 13 T62 22


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 415 1 T38 25 T61 11 T62 23
auto[1] 737 1 T38 41 T61 19 T62 28


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 666 1 T38 39 T61 18 T62 33
auto[1] 486 1 T38 27 T61 12 T62 18


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 0 18 100.00
Automatically Generated Cross Bins 18 0 18 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 78 1 T38 5 T61 1 T62 3
all_values[0] auto[0] auto[0] auto[1] 41 1 T38 3 T61 5 T62 3
all_values[0] auto[0] auto[1] auto[0] 68 1 T38 6 T61 1 T62 1
all_values[0] auto[0] auto[1] auto[1] 37 1 T38 1 T62 2 T70 2
all_values[0] auto[1] auto[0] auto[1] 92 1 T38 4 T61 2 T62 4
all_values[0] auto[1] auto[1] auto[1] 68 1 T38 3 T61 1 T62 4
all_values[1] auto[0] auto[0] auto[0] 69 1 T61 1 T62 6 T70 2
all_values[1] auto[0] auto[0] auto[1] 57 1 T38 2 T61 2 T62 3
all_values[1] auto[0] auto[1] auto[0] 49 1 T38 7 T61 4 T62 2
all_values[1] auto[0] auto[1] auto[1] 39 1 T38 1 T62 1 T140 1
all_values[1] auto[1] auto[0] auto[1] 96 1 T38 7 T61 2 T62 2
all_values[1] auto[1] auto[1] auto[1] 74 1 T38 5 T61 1 T62 3
all_values[2] auto[0] auto[0] auto[0] 79 1 T38 3 T61 2 T62 6
all_values[2] auto[0] auto[0] auto[1] 37 1 T38 6 T72 1 T141 1
all_values[2] auto[0] auto[1] auto[0] 72 1 T38 4 T61 2 T62 5
all_values[2] auto[0] auto[1] auto[1] 40 1 T38 1 T62 1 T70 1
all_values[2] auto[1] auto[0] auto[1] 79 1 T38 5 T61 2 T62 2
all_values[2] auto[1] auto[1] auto[1] 77 1 T38 3 T61 4 T62 3


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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