Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::cfg_cg

Group : hmac_env_pkg::hmac_env_cov::cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
76.47	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	2	18	90.00
Crosses	82	22	60	73.17

Variables for Group hmac_env_pkg::hmac_env_cov::cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_size	5	1	4	80.00	100	1	1	0
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	0
key_length	7	1	6	85.71	100	1	1	0
sha_en	2	0	2	100.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cfg_cross	8	0	8	100.00	100	1	1	0
hmac_dis_x_sha_en	4	0	4	100.00	100	1	1	0
key_x_digest_mismatch	35	11	24	68.57	100	1	1	0
key_length_x_digest_size	35	11	24	68.57	100	1	1	0

Summary for Variable digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	1	4	80.00

User Defined Bins for digest_size

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
sha2_invalid	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sha2_none	60	1			T32	1		T112	1		T113	4
sha2_512	19802	1			T1	6		T2	386		T11	386
sha2_384	20132	1			T1	14		T3	2		T5	2
sha2_256	11392	1			T1	7		T5	1		T4	194

---

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

49021

1

T1

11

T2

386

T3

2

auto[1]

2365

1

T1

16

T5

1

T6

16

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2352

1

T1

13

T3

2

T5

3

auto[1]

49034

1

T1

14

T2

386

T4

194

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

2412

1

T1

14

T5

2

T15

4

disabled

48974

1

T1

13

T2

386

T3

2

---

Summary for Variable key_length

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	1	6	85.71

User Defined Bins for key_length

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
key_invalid	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_none	924	1			T1	5		T6	3		T114	1
key_1024	670	1			T1	4		T5	1		T6	6
key_512	804	1			T1	5		T6	5		T52	1
key_384	824	1			T1	4		T5	1		T6	5
key_256	47372	1			T1	3		T2	386		T3	2
key_128	792	1			T1	6		T6	7		T114	1

---

Summary for Variable sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

51240

1

T1

27

T2

386

T3

1

disabled

146

1

T3

1

T30

2

T32

1

---

Summary for Cross cfg_cross

Samples crossed: hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cfg_cross

Bins

hmac_en	endian_swap	digest_swap	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
enabled	auto[0]	auto[0]	579	1			T1	1		T5	2		T6	2
enabled	auto[0]	auto[1]	505	1			T1	6		T6	4		T16	1
enabled	auto[1]	auto[0]	761	1			T1	3		T15	4		T6	1
enabled	auto[1]	auto[1]	567	1			T1	4		T6	5		T13	1
disabled	auto[0]	auto[0]	640	1			T1	4		T3	2		T6	3
disabled	auto[0]	auto[1]	628	1			T1	2		T5	1		T6	4
disabled	auto[1]	auto[0]	47041	1			T1	3		T2	386		T4	194
disabled	auto[1]	auto[1]	665	1			T1	4		T6	3		T26	2

---

Summary for Cross hmac_dis_x_sha_en

Samples crossed: hmac_en sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	3	0	3	100.00
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for hmac_dis_x_sha_en

Bins

hmac_en

sha_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

enabled

2334

1

T1

14

T5

2

T15

4

enabled

disabled

78

1

T30

1

T32

1

T112

2

disabled

disabled

68

1

T3

1

T30

1

T31

1

User Defined Cross Bins for hmac_dis_x_sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

48906

1

T1

13

T2

386

T3

1

---

Summary for Cross key_x_digest_mismatch

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	35	11	24	68.57	11
Automatically Generated Cross Bins	34	11	23	67.65	11
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for key_x_digest_mismatch

Element holes

key_length	digest_size	COUNT	AT LEAST	NUMBER	STATUS
[key_invalid]	*	--	--	5

Uncovered bins

key_length	digest_size	COUNT	AT LEAST	NUMBER	STATUS
[key_none , key_1024 , key_512 , key_384 , key_256 , key_128]	[sha2_invalid]	--	--	6

Covered bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_none	sha2_none	24	1			T112	1		T115	1		T116	1
key_none	sha2_512	315	1			T1	2		T114	1		T16	1
key_none	sha2_384	282	1			T1	3		T6	2		T13	1
key_none	sha2_256	303	1			T6	1		T13	1		T16	2
key_1024	sha2_none	9	1			T32	1		T113	1		T117	1
key_1024	sha2_512	277	1			T1	1		T6	2		T13	1
key_1024	sha2_384	281	1			T1	3		T6	2		T13	1
key_512	sha2_none	5	1			T118	1		T119	1		T120	1
key_512	sha2_512	254	1			T6	1		T16	2		T35	3
key_512	sha2_384	287	1			T1	4		T16	2		T35	2
key_512	sha2_256	258	1			T1	1		T6	4		T52	1
key_384	sha2_none	11	1			T113	1		T121	1		T122	1
key_384	sha2_512	281	1			T1	1		T6	1		T16	4
key_384	sha2_384	250	1			T1	2		T5	1		T6	1
key_384	sha2_256	282	1			T1	1		T6	3		T13	1
key_256	sha2_none	6	1			T113	1		T123	1		T115	1
key_256	sha2_512	18411	1			T1	1		T2	386		T11	386
key_256	sha2_384	18780	1			T3	2		T5	1		T16	3
key_256	sha2_256	10175	1			T1	2		T4	194		T9	194
key_128	sha2_none	5	1			T113	1		T124	1		T125	1
key_128	sha2_512	264	1			T1	1		T6	5		T7	1
key_128	sha2_384	252	1			T1	2		T114	1		T16	2
key_128	sha2_256	271	1			T1	3		T6	2		T16	1

User Defined Cross Bins for key_x_digest_mismatch

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

103

1

T5

1

T6

2

T7

1

---

Summary for Cross key_length_x_digest_size

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	35	11	24	68.57	11

Automatically Generated Cross Bins for key_length_x_digest_size

Element holes

key_length	digest_size	COUNT	AT LEAST	NUMBER	STATUS
[key_invalid]	*	--	--	5

Uncovered bins

key_length	digest_size	COUNT	AT LEAST	NUMBER	STATUS
[key_none , key_1024 , key_512 , key_384 , key_256 , key_128]	[sha2_invalid]	--	--	6

Covered bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_none	sha2_none	24	1			T112	1		T115	1		T116	1
key_none	sha2_512	315	1			T1	2		T114	1		T16	1
key_none	sha2_384	282	1			T1	3		T6	2		T13	1
key_none	sha2_256	303	1			T6	1		T13	1		T16	2
key_1024	sha2_none	9	1			T32	1		T113	1		T117	1
key_1024	sha2_512	277	1			T1	1		T6	2		T13	1
key_1024	sha2_384	281	1			T1	3		T6	2		T13	1
key_1024	sha2_256	103	1			T5	1		T6	2		T7	1
key_512	sha2_none	5	1			T118	1		T119	1		T120	1
key_512	sha2_512	254	1			T6	1		T16	2		T35	3
key_512	sha2_384	287	1			T1	4		T16	2		T35	2
key_512	sha2_256	258	1			T1	1		T6	4		T52	1
key_384	sha2_none	11	1			T113	1		T121	1		T122	1
key_384	sha2_512	281	1			T1	1		T6	1		T16	4
key_384	sha2_384	250	1			T1	2		T5	1		T6	1
key_384	sha2_256	282	1			T1	1		T6	3		T13	1
key_256	sha2_none	6	1			T113	1		T123	1		T115	1
key_256	sha2_512	18411	1			T1	1		T2	386		T11	386
key_256	sha2_384	18780	1			T3	2		T5	1		T16	3
key_256	sha2_256	10175	1			T1	2		T4	194		T9	194
key_128	sha2_none	5	1			T113	1		T124	1		T125	1
key_128	sha2_512	264	1			T1	1		T6	5		T7	1
key_128	sha2_384	252	1			T1	2		T114	1		T16	2
key_128	sha2_256	271	1			T1	3		T6	2		T16	1