Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	49003357	1			T1	300338		T2	9099		T3	25242
all_values[1]	49003357	1			T1	300338		T2	9099		T3	25242
all_values[2]	49003357	1			T1	300338		T2	9099		T3	25242

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

136705

1

T11

3

T7

2

T9

2

auto[1]

146873366

1

T1

901014

T2

27297

T3

75726

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

121670123

1

T1

748497

T2

24160

T3

53496

auto[1]

25339948

1

T1

152517

T2

3137

T3

22230

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	39230	1			T4	420		T19	642		T34	3
all_values[0]	auto[0]	auto[1]	286	1			T19	9		T34	2		T14	2
all_values[0]	auto[1]	auto[0]	48891417	1			T1	299952		T2	9084		T3	25237
all_values[0]	auto[1]	auto[1]	72424	1			T1	386		T2	15		T3	5
all_values[1]	auto[0]	auto[0]	56325	1			T9	2		T31	47		T19	368
all_values[1]	auto[0]	auto[1]	128	1			T19	2		T34	3		T36	6
all_values[1]	auto[1]	auto[0]	48943479	1			T1	300338		T2	9099		T3	25242
all_values[1]	auto[1]	auto[1]	3425	1			T19	1		T12	126		T14	42
all_values[2]	auto[0]	auto[0]	16118	1			T11	3		T7	1		T19	281
all_values[2]	auto[0]	auto[1]	24618	1			T7	1		T19	1629		T20	450
all_values[2]	auto[1]	auto[0]	23723554	1			T1	148207		T2	5977		T3	3017
all_values[2]	auto[1]	auto[1]	25239067	1			T1	152131		T2	3122		T3	22225