Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::msg_len_cg

Group : hmac_env_pkg::hmac_env_cov::msg_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
84.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	2	16	88.89
Crosses	32	6	26	81.25

Variables for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
hmac_en	2	0	2	100.00	100	1	1	2
msg_len_lower_cp	15	1	14	93.33	100	1	1	0
msg_len_upper_cp	1	1	0	0.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
msg_len_lower_cross	30	4	26	86.67	100	1	1	0
msg_len_upper_cross	2	2	0	0.00	100	1	1	0

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

162196

1

T1

386

T2

22

T3

18

auto[1]

103694

1

T2

10

T3

24

T6

4

---

Summary for Variable msg_len_lower_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	1	14	93.33

User Defined Bins for msg_len_lower_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
len_1023	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_2050_plus	44390	1			T1	58		T2	6		T3	16
len_1026_2046	30143	1			T1	9		T2	5		T3	4
len_514_1022	9312	1			T1	3		T10	3		T8	4
len_2_510	39710	1			T1	122		T2	3		T3	1
len_2049	8	1			T36	2		T91	2		T128	1
len_2048	52	1			T129	2		T123	1		T21	1
len_2047	18	1			T73	7		T128	6		T130	1
len_1025	24	1			T131	2		T132	1		T133	3
len_1024	98	1			T129	2		T123	15		T21	3
len_513	3	1			T134	1		T69	2		-	-
len_512	100	1			T36	1		T129	1		T123	2
len_511	2	1			T135	2		-	-		-	-
len_1	1156	1			T1	1		T10	1		T8	2
len_0	7929	1			T2	2		T11	1		T10	1

---

Summary for Variable msg_len_upper_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	1	0	0.00

User Defined Bins for msg_len_upper_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
len_upper	0	1	1

---

Summary for Cross msg_len_lower_cross

Samples crossed: hmac_en msg_len_lower_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	4	26	86.67	4

Automatically Generated Cross Bins for msg_len_lower_cross

Uncovered bins

hmac_en	msg_len_lower_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[len_1023 , len_513]	--	--	2
[auto[1]]	[len_1023]	0	1	1
[auto[1]]	[len_511]	0	1	1

Covered bins

hmac_en	msg_len_lower_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	len_2050_plus	25490	1			T1	58		T2	2		T3	6
auto[0]	len_1026_2046	16285	1			T1	9		T2	5		T3	2
auto[0]	len_514_1022	5655	1			T1	3		T10	3		T8	4
auto[0]	len_2_510	29984	1			T1	122		T2	3		T3	1
auto[0]	len_2049	3	1			T91	2		T128	1		-	-
auto[0]	len_2048	28	1			T129	1		T21	1		T73	1
auto[0]	len_2047	10	1			T73	4		T128	2		T130	1
auto[0]	len_1025	4	1			T133	2		T136	2		-	-
auto[0]	len_1024	60	1			T129	2		T123	13		T21	3
auto[0]	len_512	55	1			T129	1		T21	2		T73	2
auto[0]	len_511	2	1			T135	2		-	-		-	-
auto[0]	len_1	199	1			T1	1		T10	1		T8	2
auto[0]	len_0	3323	1			T2	1		T11	1		T10	1
auto[1]	len_2050_plus	18900	1			T2	4		T3	10		T7	3
auto[1]	len_1026_2046	13858	1			T3	2		T7	4		T4	8
auto[1]	len_514_1022	3657	1			T9	2		T4	2		T5	11
auto[1]	len_2_510	9726	1			T6	2		T9	1		T15	11
auto[1]	len_2049	5	1			T36	2		T133	2		T137	1
auto[1]	len_2048	24	1			T129	1		T123	1		T131	1
auto[1]	len_2047	8	1			T73	3		T128	4		T71	1
auto[1]	len_1025	20	1			T131	2		T132	1		T133	1
auto[1]	len_1024	38	1			T123	2		T131	1		T32	1
auto[1]	len_513	3	1			T134	1		T69	2		-	-
auto[1]	len_512	45	1			T36	1		T123	2		T21	1
auto[1]	len_1	957	1			T19	10		T88	17		T36	7
auto[1]	len_0	4606	1			T2	1		T7	1		T15	2

---

Summary for Cross msg_len_upper_cross

Samples crossed: hmac_en msg_len_upper_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	2	2	0	0.00	2

Automatically Generated Cross Bins for msg_len_upper_cross

Uncovered bins

hmac_en	msg_len_upper_cp	COUNT	AT LEAST	NUMBER	STATUS
*	*	--	--	2