Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::status_cg

Group : hmac_env_pkg::hmac_env_cov::status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	96	0	96	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	2
sta_fifo_depth	8	0	8	100.00	100	1	1	0
sta_fifo_empty	2	0	2	100.00	100	1	1	2
sta_fifo_full	2	0	2	100.00	100	1	1	2

Crosses for Group hmac_env_pkg::hmac_env_cov::status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
fifo_empty_cross	16	0	16	100.00	100	1	1	0
fifo_full_cross	16	0	16	100.00	100	1	1	0
fifo_depth_cross	64	0	64	100.00	100	1	1	0

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23915211

1

T1

147820

T2

3244

T3

1858

auto[1]

2306640

1

T2

5783

T3

1848

T7

3788

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2255382

1

T2

6172

T3

1658

T7

2224

auto[1]

23966469

1

T1

147820

T2

2855

T3

2048

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22930273

1

T1

147820

T2

4895

T3

1475

auto[1]

3291578

1

T2

4132

T3

2231

T6

30

---

Summary for Variable sta_fifo_depth

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for sta_fifo_depth

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	23012524	1			T1	144541		T2	8396		T3	3644
fifo_depth[1]	671754	1			T1	2264		T2	258		T3	33
fifo_depth[2]	506791	1			T1	761		T2	191		T3	15
fifo_depth[3]	399297	1			T1	197		T2	116		T3	8
fifo_depth[4]	310450	1			T1	44		T2	44		T3	4
fifo_depth[5]	242466	1			T1	13		T2	16		T3	1
fifo_depth[6]	210719	1			T2	6		T3	1		T6	2
fifo_depth[7]	187205	1			T6	3		T10	2640		T15	10

---

Summary for Variable sta_fifo_empty

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_empty

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3209327

1

T1

3279

T2

631

T3

62

auto[1]

23012524

1

T1

144541

T2

8396

T3

3644

---

Summary for Variable sta_fifo_full

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_full

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26214530

1

T1

147820

T2

9027

T3

3706

auto[1]

7321

1

T5

150

T12

2

T14

1

---

Summary for Cross fifo_empty_cross

Samples crossed: sta_fifo_empty hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for fifo_empty_cross

Bins

sta_fifo_empty

hmac_en

endian_swap

digest_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

53910

1

T2

22

T7

15

T4

249

auto[0]

auto[0]

auto[0]

auto[1]

62239

1

T2

80

T7

19

T4

95

auto[0]

auto[0]

auto[1]

auto[0]

2639135

1

T1

3279

T2

109

T10

36102

auto[0]

auto[0]

auto[1]

auto[1]

54150

1

T2

58

T7

23

T4

327

auto[0]

auto[1]

auto[0]

auto[0]

96984

1

T7

67

T9

1

T15

3

auto[0]

auto[1]

auto[0]

auto[1]

87177

1

T2

362

T3

7

T9

3

auto[0]

auto[1]

auto[1]

auto[0]

101519

1

T3

19

T6

28

T15

29

auto[0]

auto[1]

auto[1]

auto[1]

114213

1

T3

36

T15

19

T4

555

auto[1]

auto[0]

auto[0]

auto[0]

252107

1

T2

1071

T3

475

T7

411

auto[1]

auto[0]

auto[0]

auto[1]

248577

1

T2

867

T3

699

T7

647

auto[1]

auto[0]

auto[1]

auto[0]

19372200

1

T1

144541

T2

1728

T3

6

auto[1]

auto[0]

auto[1]

auto[1]

247955

1

T2

960

T3

295

T7

1168

auto[1]

auto[1]

auto[0]

auto[0]

700074

1

T2

314

T3

5

T7

1064

auto[1]

auto[1]

auto[0]

auto[1]

754314

1

T2

3456

T3

472

T7

1

auto[1]

auto[1]

auto[1]

auto[0]

699282

1

T3

1353

T6

2

T7

99

auto[1]

auto[1]

auto[1]

auto[1]

738015

1

T3

339

T7

1930

T9

2

---

Summary for Cross fifo_full_cross

Samples crossed: sta_fifo_full hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for fifo_full_cross

Bins

sta_fifo_full

hmac_en

endian_swap

digest_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

304866

1

T2

1093

T3

475

T7

426

auto[0]

auto[0]

auto[0]

auto[1]

309706

1

T2

947

T3

699

T7

666

auto[0]

auto[0]

auto[1]

auto[0]

22010480

1

T1

147820

T2

1837

T3

6

auto[0]

auto[0]

auto[1]

auto[1]

301255

1

T2

1018

T3

295

T7

1191

auto[0]

auto[1]

auto[0]

auto[0]

796739

1

T2

314

T3

5

T7

1131

auto[0]

auto[1]

auto[0]

auto[1]

840887

1

T2

3818

T3

479

T7

1

auto[0]

auto[1]

auto[1]

auto[0]

800411

1

T3

1372

T6

30

T7

99

auto[0]

auto[1]

auto[1]

auto[1]

850186

1

T3

375

T7

1930

T9

2

auto[1]

auto[0]

auto[0]

auto[0]

1151

1

T129

3

T21

13

T22

4

auto[1]

auto[0]

auto[0]

auto[1]

1110

1

T5

24

T21

67

T22

20

auto[1]

auto[0]

auto[1]

auto[0]

855

1

T14

1

T129

34

T21

247

auto[1]

auto[0]

auto[1]

auto[1]

850

1

T5

54

T12

1

T129

28

auto[1]

auto[1]

auto[0]

auto[0]

319

1

T5

72

T146

1

T21

30

auto[1]

auto[1]

auto[0]

auto[1]

604

1

T12

1

T129

500

T21

18

auto[1]

auto[1]

auto[1]

auto[0]

390

1

T129

6

T21

24

T25

9

auto[1]

auto[1]

auto[1]

auto[1]

2042

1

T21

550

T32

8

T149

1

---

Summary for Cross fifo_depth_cross

Samples crossed: sta_fifo_depth hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for fifo_depth_cross

Bins

sta_fifo_depth	hmac_en	endian_swap	digest_swap	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	auto[0]	auto[0]	auto[0]	252107	1			T2	1071		T3	475		T7	411
fifo_depth[0]	auto[0]	auto[0]	auto[1]	248577	1			T2	867		T3	699		T7	647
fifo_depth[0]	auto[0]	auto[1]	auto[0]	19372200	1			T1	144541		T2	1728		T3	6
fifo_depth[0]	auto[0]	auto[1]	auto[1]	247955	1			T2	960		T3	295		T7	1168
fifo_depth[0]	auto[1]	auto[0]	auto[0]	700074	1			T2	314		T3	5		T7	1064
fifo_depth[0]	auto[1]	auto[0]	auto[1]	754314	1			T2	3456		T3	472		T7	1
fifo_depth[0]	auto[1]	auto[1]	auto[0]	699282	1			T3	1353		T6	2		T7	99
fifo_depth[0]	auto[1]	auto[1]	auto[1]	738015	1			T3	339		T7	1930		T9	2
fifo_depth[1]	auto[0]	auto[0]	auto[0]	6719	1			T2	7		T7	7		T4	23
fifo_depth[1]	auto[0]	auto[0]	auto[1]	6372	1			T2	33		T7	6		T4	8
fifo_depth[1]	auto[0]	auto[1]	auto[0]	606783	1			T1	2264		T2	45		T10	5147
fifo_depth[1]	auto[0]	auto[1]	auto[1]	5809	1			T2	27		T7	13		T4	46
fifo_depth[1]	auto[1]	auto[0]	auto[0]	11420	1			T7	28		T15	1		T4	70
fifo_depth[1]	auto[1]	auto[0]	auto[1]	10104	1			T2	146		T3	6		T15	1
fifo_depth[1]	auto[1]	auto[1]	auto[0]	11226	1			T3	13		T6	3		T15	2
fifo_depth[1]	auto[1]	auto[1]	auto[1]	13321	1			T3	14		T4	58		T19	370
fifo_depth[2]	auto[0]	auto[0]	auto[0]	5721	1			T2	8		T7	5		T4	19
fifo_depth[2]	auto[0]	auto[0]	auto[1]	5379	1			T2	23		T7	8		T4	8
fifo_depth[2]	auto[0]	auto[1]	auto[0]	449187	1			T1	761		T2	31		T10	4911
fifo_depth[2]	auto[0]	auto[1]	auto[1]	4913	1			T2	18		T7	6		T4	34
fifo_depth[2]	auto[1]	auto[0]	auto[0]	10394	1			T7	26		T4	65		T5	8
fifo_depth[2]	auto[1]	auto[0]	auto[1]	9128	1			T2	111		T3	1		T15	1
fifo_depth[2]	auto[1]	auto[1]	auto[0]	10398	1			T3	6		T6	4		T15	2
fifo_depth[2]	auto[1]	auto[1]	auto[1]	11671	1			T3	8		T4	50		T19	206
fifo_depth[3]	auto[0]	auto[0]	auto[0]	4496	1			T2	3		T7	3		T4	22
fifo_depth[3]	auto[0]	auto[0]	auto[1]	4226	1			T2	15		T7	3		T4	7
fifo_depth[3]	auto[0]	auto[1]	auto[0]	351549	1			T1	197		T2	24		T10	4562
fifo_depth[3]	auto[0]	auto[1]	auto[1]	3556	1			T2	9		T7	3		T4	30
fifo_depth[3]	auto[1]	auto[0]	auto[0]	8917	1			T7	7		T4	59		T5	8
fifo_depth[3]	auto[1]	auto[0]	auto[1]	7798	1			T2	65		T15	3		T4	12
fifo_depth[3]	auto[1]	auto[1]	auto[0]	8906	1			T6	4		T15	2		T4	104
fifo_depth[3]	auto[1]	auto[1]	auto[1]	9849	1			T3	8		T4	57		T19	94
fifo_depth[4]	auto[0]	auto[0]	auto[0]	4281	1			T2	3		T4	23		T5	10
fifo_depth[4]	auto[0]	auto[0]	auto[1]	4006	1			T2	6		T7	2		T4	6
fifo_depth[4]	auto[0]	auto[1]	auto[0]	265137	1			T1	44		T2	5		T10	3830
fifo_depth[4]	auto[0]	auto[1]	auto[1]	3453	1			T2	4		T7	1		T4	32
fifo_depth[4]	auto[1]	auto[0]	auto[0]	8669	1			T7	4		T4	66		T5	8
fifo_depth[4]	auto[1]	auto[0]	auto[1]	7487	1			T2	26		T15	2		T4	11
fifo_depth[4]	auto[1]	auto[1]	auto[0]	8519	1			T6	4		T15	2		T4	91
fifo_depth[4]	auto[1]	auto[1]	auto[1]	8898	1			T3	4		T15	1		T4	53
fifo_depth[5]	auto[0]	auto[0]	auto[0]	3559	1			T4	21		T5	10		T31	2
fifo_depth[5]	auto[0]	auto[0]	auto[1]	3473	1			T2	2		T4	15		T19	3
fifo_depth[5]	auto[0]	auto[1]	auto[0]	202233	1			T1	13		T2	2		T10	3090
fifo_depth[5]	auto[0]	auto[1]	auto[1]	2785	1			T4	32		T5	8		T31	1
fifo_depth[5]	auto[1]	auto[0]	auto[0]	7660	1			T7	1		T4	61		T5	6
fifo_depth[5]	auto[1]	auto[0]	auto[1]	6626	1			T2	12		T15	2		T4	11
fifo_depth[5]	auto[1]	auto[1]	auto[0]	7963	1			T6	4		T15	4		T4	87
fifo_depth[5]	auto[1]	auto[1]	auto[1]	8167	1			T3	1		T15	2		T4	48
fifo_depth[6]	auto[0]	auto[0]	auto[0]	3322	1			T2	1		T4	23		T5	10
fifo_depth[6]	auto[0]	auto[0]	auto[1]	3401	1			T2	1		T4	12		T19	3
fifo_depth[6]	auto[0]	auto[1]	auto[0]	170986	1			T2	2		T10	2848		T8	2
fifo_depth[6]	auto[0]	auto[1]	auto[1]	2975	1			T4	43		T5	46		T27	1
fifo_depth[6]	auto[1]	auto[0]	auto[0]	7798	1			T7	1		T4	86		T5	12
fifo_depth[6]	auto[1]	auto[0]	auto[1]	6632	1			T2	2		T15	4		T4	12
fifo_depth[6]	auto[1]	auto[1]	auto[0]	7669	1			T6	2		T15	3		T4	95
fifo_depth[6]	auto[1]	auto[1]	auto[1]	7936	1			T3	1		T4	59		T19	1
fifo_depth[7]	auto[0]	auto[0]	auto[0]	3035	1			T4	20		T5	10		T31	1
fifo_depth[7]	auto[0]	auto[0]	auto[1]	3054	1			T4	6		T82	47		T13	19
fifo_depth[7]	auto[0]	auto[1]	auto[0]	149902	1			T10	2640		T16	1		T4	20
fifo_depth[7]	auto[0]	auto[1]	auto[1]	2685	1			T4	34		T5	38		T31	1
fifo_depth[7]	auto[1]	auto[0]	auto[0]	7192	1			T15	1		T4	45		T5	5
fifo_depth[7]	auto[1]	auto[0]	auto[1]	6303	1			T4	13		T5	9		T82	12
fifo_depth[7]	auto[1]	auto[1]	auto[0]	7333	1			T6	3		T15	7		T4	83
fifo_depth[7]	auto[1]	auto[1]	auto[1]	7701	1			T15	2		T4	62		T19	1