Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	49003357	1			T1	300338		T2	9099		T3	25242
all_pins[1]	49003357	1			T1	300338		T2	9099		T3	25242
all_pins[2]	49003357	1			T1	300338		T2	9099		T3	25242

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	121694394	1			T1	748497		T2	24159		T3	53495
values[0x1]	25315677	1			T1	152517		T2	3138		T3	22231
transitions[0x0=>0x1]	25315431	1			T1	152517		T2	3138		T3	22231
transitions[0x1=>0x0]	25315443	1			T1	152517		T2	3138		T3	22231

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	48930265	1			T1	299952		T2	9083		T3	25236
all_pins[0]	values[0x1]	73092	1			T1	386		T2	16		T3	6
all_pins[0]	transitions[0x0=>0x1]	73038	1			T1	386		T2	16		T3	6
all_pins[0]	transitions[0x1=>0x0]	25239025	1			T1	152131		T2	3122		T3	22225
all_pins[1]	values[0x0]	48999839	1			T1	300338		T2	9099		T3	25242
all_pins[1]	values[0x1]	3518	1			T19	1		T12	129		T14	43
all_pins[1]	transitions[0x0=>0x1]	3364	1			T19	1		T12	125		T14	41
all_pins[1]	transitions[0x1=>0x0]	72938	1			T1	386		T2	16		T3	6
all_pins[2]	values[0x0]	23764290	1			T1	148207		T2	5977		T3	3017
all_pins[2]	values[0x1]	25239067	1			T1	152131		T2	3122		T3	22225
all_pins[2]	transitions[0x0=>0x1]	25239029	1			T1	152131		T2	3122		T3	22225
all_pins[2]	transitions[0x1=>0x0]	3480	1			T19	1		T12	129		T14	43