Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 0 18 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 0 18 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 644 1 T19 7 T34 7 T36 14
all_values[1] 644 1 T19 7 T34 7 T36 14
all_values[2] 644 1 T19 7 T34 7 T36 14


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1037 1 T19 14 T34 12 T36 27
auto[1] 895 1 T19 7 T34 9 T36 15


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 690 1 T19 4 T34 8 T36 8
auto[1] 1242 1 T19 17 T34 13 T36 34


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1112 1 T19 10 T34 14 T36 21
auto[1] 820 1 T19 11 T34 7 T36 21


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 0 18 100.00
Automatically Generated Cross Bins 18 0 18 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 128 1 T19 1 T34 3 T36 1
all_values[0] auto[0] auto[0] auto[1] 81 1 T34 1 T36 4 T123 3
all_values[0] auto[0] auto[1] auto[0] 92 1 T19 1 T36 2 T73 4
all_values[0] auto[0] auto[1] auto[1] 55 1 T34 1 T36 1 T123 1
all_values[0] auto[1] auto[0] auto[1] 167 1 T19 5 T34 1 T36 5
all_values[0] auto[1] auto[1] auto[1] 121 1 T34 1 T36 1 T131 2
all_values[1] auto[0] auto[0] auto[0] 123 1 T34 1 T36 1 T123 1
all_values[1] auto[0] auto[0] auto[1] 76 1 T19 2 T34 3 T36 3
all_values[1] auto[0] auto[1] auto[0] 94 1 T19 1 T73 1 T22 2
all_values[1] auto[0] auto[1] auto[1] 86 1 T19 1 T36 2 T123 1
all_values[1] auto[1] auto[0] auto[1] 123 1 T19 2 T34 3 T36 5
all_values[1] auto[1] auto[1] auto[1] 142 1 T19 1 T36 3 T123 3
all_values[2] auto[0] auto[0] auto[0] 130 1 T19 1 T36 2 T123 3
all_values[2] auto[0] auto[0] auto[1] 72 1 T19 1 T36 2 T123 3
all_values[2] auto[0] auto[1] auto[0] 123 1 T34 4 T36 2 T123 1
all_values[2] auto[0] auto[1] auto[1] 52 1 T19 2 T34 1 T36 1
all_values[2] auto[1] auto[0] auto[1] 137 1 T19 2 T36 4 T123 2
all_values[2] auto[1] auto[1] auto[1] 130 1 T19 1 T34 2 T36 3


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%