Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::cfg_cg

Group : hmac_env_pkg::hmac_env_cov::cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
76.47	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	2	18	90.00
Crosses	82	22	60	73.17

Variables for Group hmac_env_pkg::hmac_env_cov::cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_size	5	1	4	80.00	100	1	1	0
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	0
key_length	7	1	6	85.71	100	1	1	0
sha_en	2	0	2	100.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cfg_cross	8	0	8	100.00	100	1	1	0
hmac_dis_x_sha_en	4	0	4	100.00	100	1	1	0
key_x_digest_mismatch	35	11	24	68.57	100	1	1	0
key_length_x_digest_size	35	11	24	68.57	100	1	1	0

Summary for Variable digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	1	4	80.00

User Defined Bins for digest_size

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
sha2_invalid	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sha2_none	145	1			T3	3		T27	2		T35	2
sha2_512	28483	1			T1	386		T2	3		T3	4
sha2_384	28035	1			T2	6		T3	14		T11	1
sha2_256	15064	1			T2	3		T6	4		T7	1

---

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

67366

1

T1

386

T2

5

T3

6

auto[1]

4361

1

T2

7

T3

15

T7

2

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4397

1

T2

8

T3

7

T7

5

auto[1]

67330

1

T1

386

T2

4

T3

14

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

4145

1

T2

2

T3

17

T6

4

disabled

67582

1

T1

386

T2

10

T3

4

---

Summary for Variable key_length

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	1	6	85.71

User Defined Bins for key_length

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
key_invalid	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_none	1636	1			T2	3		T3	1		T7	1
key_1024	1243	1			T3	13		T11	1		T7	2
key_512	1523	1			T2	2		T3	5		T7	2
key_384	1407	1			T2	2		T9	1		T15	4
key_256	64466	1			T1	386		T2	3		T3	2
key_128	1452	1			T2	2		T15	3		T4	4

---

Summary for Variable sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

71420

1

T1

386

T2

12

T3

16

disabled

307

1

T3

5

T27

4

T35

4

---

Summary for Cross cfg_cross

Samples crossed: hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cfg_cross

Bins

hmac_en	endian_swap	digest_swap	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
enabled	auto[0]	auto[0]	1022	1			T7	3		T9	1		T15	1
enabled	auto[0]	auto[1]	958	1			T2	2		T3	4		T9	3
enabled	auto[1]	auto[0]	1180	1			T3	3		T6	4		T15	1
enabled	auto[1]	auto[1]	985	1			T3	10		T15	2		T4	2
disabled	auto[0]	auto[0]	1173	1			T2	3		T3	2		T7	1
disabled	auto[0]	auto[1]	1244	1			T2	3		T3	1		T7	1
disabled	auto[1]	auto[0]	63991	1			T1	386		T2	2		T3	1
disabled	auto[1]	auto[1]	1174	1			T2	2		T7	1		T15	1

---

Summary for Cross hmac_dis_x_sha_en

Samples crossed: hmac_en sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	3	0	3	100.00
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for hmac_dis_x_sha_en

Bins

hmac_en

sha_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

enabled

4001

1

T2

2

T3

15

T6

4

enabled

disabled

144

1

T3

2

T27

2

T35

2

disabled

disabled

163

1

T3

3

T27

2

T35

2

User Defined Cross Bins for hmac_dis_x_sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

67419

1

T1

386

T2

10

T3

1

---

Summary for Cross key_x_digest_mismatch

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	35	11	24	68.57	11
Automatically Generated Cross Bins	34	11	23	67.65	11
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for key_x_digest_mismatch

Element holes

key_length	digest_size	COUNT	AT LEAST	NUMBER	STATUS
[key_invalid]	*	--	--	5

Uncovered bins

key_length	digest_size	COUNT	AT LEAST	NUMBER	STATUS
[key_none , key_1024 , key_512 , key_384 , key_256 , key_128]	[sha2_invalid]	--	--	6

Covered bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_none	sha2_none	44	1			T36	1		T126	1		T21	1
key_none	sha2_512	522	1			T2	2		T3	1		T31	1
key_none	sha2_384	517	1			T2	1		T7	1		T31	1
key_none	sha2_256	553	1			T15	1		T27	15		T31	2
key_1024	sha2_none	22	1			T3	1		T123	1		T21	1
key_1024	sha2_512	455	1			T3	2		T7	1		T9	1
key_1024	sha2_384	558	1			T3	10		T11	1		T7	1
key_512	sha2_none	22	1			T3	1		T35	1		T127	2
key_512	sha2_512	509	1			T2	1		T7	2		T9	1
key_512	sha2_384	469	1			T2	1		T3	4		T19	8
key_512	sha2_256	523	1			T9	1		T4	3		T5	2
key_384	sha2_none	21	1			T27	1		T123	1		T21	1
key_384	sha2_512	468	1			T15	2		T4	1		T19	6
key_384	sha2_384	431	1			T9	1		T27	1		T19	7
key_384	sha2_256	487	1			T2	2		T15	2		T27	5
key_256	sha2_none	18	1			T3	1		T27	1		T36	1
key_256	sha2_512	26088	1			T1	386		T3	1		T10	386
key_256	sha2_384	25583	1			T2	3		T4	4		T30	386
key_256	sha2_256	12777	1			T6	4		T7	1		T8	194
key_128	sha2_none	18	1			T35	1		T123	1		T21	1
key_128	sha2_512	441	1			T15	1		T4	1		T5	1
key_128	sha2_384	477	1			T2	1		T15	2		T4	1
key_128	sha2_256	516	1			T2	1		T4	2		T5	2

User Defined Cross Bins for key_x_digest_mismatch

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

208

1

T19

1

T12

2

T34

1

---

Summary for Cross key_length_x_digest_size

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	35	11	24	68.57	11

Automatically Generated Cross Bins for key_length_x_digest_size

Element holes

key_length	digest_size	COUNT	AT LEAST	NUMBER	STATUS
[key_invalid]	*	--	--	5

Uncovered bins

key_length	digest_size	COUNT	AT LEAST	NUMBER	STATUS
[key_none , key_1024 , key_512 , key_384 , key_256 , key_128]	[sha2_invalid]	--	--	6

Covered bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_none	sha2_none	44	1			T36	1		T126	1		T21	1
key_none	sha2_512	522	1			T2	2		T3	1		T31	1
key_none	sha2_384	517	1			T2	1		T7	1		T31	1
key_none	sha2_256	553	1			T15	1		T27	15		T31	2
key_1024	sha2_none	22	1			T3	1		T123	1		T21	1
key_1024	sha2_512	455	1			T3	2		T7	1		T9	1
key_1024	sha2_384	558	1			T3	10		T11	1		T7	1
key_1024	sha2_256	208	1			T19	1		T12	2		T34	1
key_512	sha2_none	22	1			T3	1		T35	1		T127	2
key_512	sha2_512	509	1			T2	1		T7	2		T9	1
key_512	sha2_384	469	1			T2	1		T3	4		T19	8
key_512	sha2_256	523	1			T9	1		T4	3		T5	2
key_384	sha2_none	21	1			T27	1		T123	1		T21	1
key_384	sha2_512	468	1			T15	2		T4	1		T19	6
key_384	sha2_384	431	1			T9	1		T27	1		T19	7
key_384	sha2_256	487	1			T2	2		T15	2		T27	5
key_256	sha2_none	18	1			T3	1		T27	1		T36	1
key_256	sha2_512	26088	1			T1	386		T3	1		T10	386
key_256	sha2_384	25583	1			T2	3		T4	4		T30	386
key_256	sha2_256	12777	1			T6	4		T7	1		T8	194
key_128	sha2_none	18	1			T35	1		T123	1		T21	1
key_128	sha2_512	441	1			T15	1		T4	1		T5	1
key_128	sha2_384	477	1			T2	1		T15	2		T4	1
key_128	sha2_256	516	1			T2	1		T4	2		T5	2