Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
94.06 95.94 94.34 100.00 82.05 92.33 99.49 94.27


Total test records in report: 815
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html
T760 /workspace/coverage/cover_reg_top/28.hmac_intr_test.3968032890 Jun 27 06:09:54 PM PDT 24 Jun 27 06:09:59 PM PDT 24 24797836 ps
T761 /workspace/coverage/cover_reg_top/1.hmac_csr_rw.1748966911 Jun 27 06:09:30 PM PDT 24 Jun 27 06:09:34 PM PDT 24 58758721 ps
T762 /workspace/coverage/cover_reg_top/19.hmac_intr_test.503864181 Jun 27 06:09:45 PM PDT 24 Jun 27 06:09:53 PM PDT 24 38557751 ps
T763 /workspace/coverage/cover_reg_top/0.hmac_tl_errors.3656769039 Jun 27 06:09:25 PM PDT 24 Jun 27 06:09:27 PM PDT 24 89249071 ps
T764 /workspace/coverage/cover_reg_top/45.hmac_intr_test.654266491 Jun 27 06:10:00 PM PDT 24 Jun 27 06:10:04 PM PDT 24 22567756 ps
T765 /workspace/coverage/cover_reg_top/15.hmac_csr_rw.3543007999 Jun 27 06:09:43 PM PDT 24 Jun 27 06:09:49 PM PDT 24 34642636 ps
T766 /workspace/coverage/cover_reg_top/20.hmac_intr_test.2061969042 Jun 27 06:09:46 PM PDT 24 Jun 27 06:09:54 PM PDT 24 45838885 ps
T767 /workspace/coverage/cover_reg_top/10.hmac_intr_test.3826593435 Jun 27 06:09:41 PM PDT 24 Jun 27 06:09:45 PM PDT 24 16054538 ps
T768 /workspace/coverage/cover_reg_top/26.hmac_intr_test.2413072958 Jun 27 06:09:45 PM PDT 24 Jun 27 06:09:53 PM PDT 24 20943402 ps
T108 /workspace/coverage/cover_reg_top/19.hmac_csr_rw.25824729 Jun 27 06:09:45 PM PDT 24 Jun 27 06:09:53 PM PDT 24 222147879 ps
T769 /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.51487258 Jun 27 06:09:49 PM PDT 24 Jun 27 06:09:58 PM PDT 24 809565297 ps
T770 /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.838104860 Jun 27 06:09:40 PM PDT 24 Jun 27 06:09:45 PM PDT 24 296284353 ps
T771 /workspace/coverage/cover_reg_top/44.hmac_intr_test.319806783 Jun 27 06:09:56 PM PDT 24 Jun 27 06:10:01 PM PDT 24 16167074 ps
T772 /workspace/coverage/cover_reg_top/19.hmac_tl_errors.3012280173 Jun 27 06:09:45 PM PDT 24 Jun 27 06:09:55 PM PDT 24 181557153 ps
T773 /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.2681099634 Jun 27 06:09:43 PM PDT 24 Jun 27 06:09:52 PM PDT 24 144872605 ps
T774 /workspace/coverage/cover_reg_top/9.hmac_intr_test.2686142799 Jun 27 06:09:47 PM PDT 24 Jun 27 06:09:55 PM PDT 24 13933746 ps
T110 /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.2567937607 Jun 27 06:09:29 PM PDT 24 Jun 27 06:09:32 PM PDT 24 75480909 ps
T775 /workspace/coverage/cover_reg_top/6.hmac_tl_errors.2578522807 Jun 27 06:09:43 PM PDT 24 Jun 27 06:09:50 PM PDT 24 209053699 ps
T776 /workspace/coverage/cover_reg_top/31.hmac_intr_test.3882331175 Jun 27 06:09:55 PM PDT 24 Jun 27 06:10:00 PM PDT 24 39942853 ps
T60 /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.2087454297 Jun 27 06:09:43 PM PDT 24 Jun 27 06:09:53 PM PDT 24 951125455 ps
T777 /workspace/coverage/cover_reg_top/18.hmac_tl_errors.1817780419 Jun 27 06:09:46 PM PDT 24 Jun 27 06:09:57 PM PDT 24 310954182 ps
T778 /workspace/coverage/cover_reg_top/34.hmac_intr_test.3225549867 Jun 27 06:09:56 PM PDT 24 Jun 27 06:10:01 PM PDT 24 63232003 ps
T779 /workspace/coverage/cover_reg_top/36.hmac_intr_test.177418870 Jun 27 06:10:01 PM PDT 24 Jun 27 06:10:05 PM PDT 24 28994597 ps
T111 /workspace/coverage/cover_reg_top/3.hmac_csr_rw.1768521145 Jun 27 06:09:27 PM PDT 24 Jun 27 06:09:29 PM PDT 24 15432976 ps
T780 /workspace/coverage/cover_reg_top/8.hmac_csr_rw.2968262068 Jun 27 06:09:42 PM PDT 24 Jun 27 06:09:47 PM PDT 24 187729037 ps
T781 /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.3672014357 Jun 27 06:09:43 PM PDT 24 Jun 27 06:09:51 PM PDT 24 165163982 ps
T139 /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.1565413322 Jun 27 06:09:45 PM PDT 24 Jun 27 06:09:56 PM PDT 24 734501285 ps
T782 /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.2449381648 Jun 27 06:09:42 PM PDT 24 Jun 27 06:09:47 PM PDT 24 57161742 ps
T783 /workspace/coverage/cover_reg_top/8.hmac_tl_errors.4149407652 Jun 27 06:09:41 PM PDT 24 Jun 27 06:09:46 PM PDT 24 197918140 ps
T59 /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.3506427557 Jun 27 06:09:28 PM PDT 24 Jun 27 06:09:33 PM PDT 24 108908128 ps
T784 /workspace/coverage/cover_reg_top/17.hmac_tl_errors.2334560464 Jun 27 06:09:48 PM PDT 24 Jun 27 06:09:58 PM PDT 24 831881572 ps
T785 /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.1312531467 Jun 27 06:09:30 PM PDT 24 Jun 27 06:09:34 PM PDT 24 142318876 ps
T786 /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.2212017159 Jun 27 06:09:31 PM PDT 24 Jun 27 06:09:37 PM PDT 24 1711779871 ps
T112 /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.1711481826 Jun 27 06:09:30 PM PDT 24 Jun 27 06:09:39 PM PDT 24 109455919 ps
T787 /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.3129303686 Jun 27 06:09:29 PM PDT 24 Jun 27 06:09:41 PM PDT 24 910184317 ps
T788 /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.435101997 Jun 27 06:09:43 PM PDT 24 Jun 27 06:09:51 PM PDT 24 38200308 ps
T140 /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.337179283 Jun 27 06:09:27 PM PDT 24 Jun 27 06:09:30 PM PDT 24 389376584 ps
T789 /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.2194173506 Jun 27 06:09:39 PM PDT 24 Jun 27 06:09:44 PM PDT 24 500081291 ps
T790 /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.3921300367 Jun 27 06:09:44 PM PDT 24 Jun 27 06:09:52 PM PDT 24 78769365 ps
T791 /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.3254515688 Jun 27 06:09:45 PM PDT 24 Jun 27 06:09:57 PM PDT 24 129786956 ps
T792 /workspace/coverage/cover_reg_top/2.hmac_intr_test.1714764234 Jun 27 06:09:26 PM PDT 24 Jun 27 06:09:28 PM PDT 24 14706128 ps
T793 /workspace/coverage/cover_reg_top/47.hmac_intr_test.3709695721 Jun 27 06:09:55 PM PDT 24 Jun 27 06:09:59 PM PDT 24 15783341 ps
T794 /workspace/coverage/cover_reg_top/1.hmac_intr_test.1409720154 Jun 27 06:09:28 PM PDT 24 Jun 27 06:09:31 PM PDT 24 46720176 ps
T795 /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.3002630989 Jun 27 06:09:28 PM PDT 24 Jun 27 06:09:31 PM PDT 24 99086260 ps
T796 /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.4110199179 Jun 27 06:09:44 PM PDT 24 Jun 27 06:09:54 PM PDT 24 155631355 ps
T797 /workspace/coverage/cover_reg_top/48.hmac_intr_test.2743439900 Jun 27 06:09:55 PM PDT 24 Jun 27 06:10:00 PM PDT 24 57797302 ps
T798 /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.102459126 Jun 27 06:09:30 PM PDT 24 Jun 27 06:09:36 PM PDT 24 93076696 ps
T145 /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.691216894 Jun 27 06:09:41 PM PDT 24 Jun 27 06:09:47 PM PDT 24 2279323981 ps
T799 /workspace/coverage/cover_reg_top/18.hmac_intr_test.1615640289 Jun 27 06:09:43 PM PDT 24 Jun 27 06:09:49 PM PDT 24 14642836 ps
T800 /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.2756168293 Jun 27 06:09:27 PM PDT 24 Jun 27 06:09:29 PM PDT 24 20140504 ps
T801 /workspace/coverage/cover_reg_top/12.hmac_tl_errors.1739150552 Jun 27 06:09:43 PM PDT 24 Jun 27 06:09:52 PM PDT 24 126883934 ps
T802 /workspace/coverage/cover_reg_top/21.hmac_intr_test.454627494 Jun 27 06:09:46 PM PDT 24 Jun 27 06:09:55 PM PDT 24 13727569 ps
T803 /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.3904048695 Jun 27 06:09:41 PM PDT 24 Jun 27 06:09:46 PM PDT 24 783665145 ps
T804 /workspace/coverage/cover_reg_top/40.hmac_intr_test.1730203962 Jun 27 06:09:55 PM PDT 24 Jun 27 06:10:00 PM PDT 24 62705326 ps
T805 /workspace/coverage/cover_reg_top/13.hmac_csr_rw.1890461439 Jun 27 06:09:44 PM PDT 24 Jun 27 06:09:51 PM PDT 24 33017663 ps
T806 /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.824685300 Jun 27 06:09:29 PM PDT 24 Jun 27 06:09:37 PM PDT 24 1428976155 ps
T807 /workspace/coverage/cover_reg_top/7.hmac_intr_test.2002541483 Jun 27 06:09:47 PM PDT 24 Jun 27 06:09:55 PM PDT 24 23296698 ps
T808 /workspace/coverage/cover_reg_top/14.hmac_intr_test.2993704018 Jun 27 06:09:45 PM PDT 24 Jun 27 06:09:54 PM PDT 24 13053388 ps
T809 /workspace/coverage/cover_reg_top/14.hmac_tl_errors.966998290 Jun 27 06:09:44 PM PDT 24 Jun 27 06:09:55 PM PDT 24 65327402 ps
T810 /workspace/coverage/cover_reg_top/4.hmac_intr_test.792281035 Jun 27 06:09:26 PM PDT 24 Jun 27 06:09:27 PM PDT 24 21937415 ps
T811 /workspace/coverage/cover_reg_top/23.hmac_intr_test.2252182018 Jun 27 06:09:46 PM PDT 24 Jun 27 06:09:54 PM PDT 24 189758631 ps
T812 /workspace/coverage/cover_reg_top/49.hmac_intr_test.2476406573 Jun 27 06:09:54 PM PDT 24 Jun 27 06:09:59 PM PDT 24 15725651 ps
T813 /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.1444618764 Jun 27 06:09:31 PM PDT 24 Jun 27 06:09:35 PM PDT 24 93585553 ps
T814 /workspace/coverage/cover_reg_top/17.hmac_csr_rw.1894308080 Jun 27 06:09:45 PM PDT 24 Jun 27 06:09:54 PM PDT 24 66694953 ps
T815 /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.2809731102 Jun 27 06:09:44 PM PDT 24 Jun 27 06:09:53 PM PDT 24 82552201 ps

Test location /workspace/coverage/default/11.hmac_long_msg.607200747
Short name T2
Test name
Test status
Simulation time 13733648134 ps
CPU time 70.82 seconds
Started Jun 27 06:46:35 PM PDT 24
Finished Jun 27 06:47:59 PM PDT 24
Peak memory 200264 kb
Host smart-93e14acb-d012-4472-ae9a-992be2979d67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607200747 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_long_msg.607200747
Directory /workspace/11.hmac_long_msg/latest

Test location /workspace/coverage/default/29.hmac_stress_all.3294100643
Short name T19
Test name
Test status
Simulation time 163873359682 ps
CPU time 1891.98 seconds
Started Jun 27 06:47:29 PM PDT 24
Finished Jun 27 07:19:04 PM PDT 24
Peak memory 774672 kb
Host smart-71268700-0b0e-4310-b681-e56d62ab272b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294100643 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.hmac_stress_all.3294100643
Directory /workspace/29.hmac_stress_all/latest

Test location /workspace/coverage/default/2.hmac_stress_all_with_rand_reset.3222577504
Short name T17
Test name
Test status
Simulation time 36544775506 ps
CPU time 886.03 seconds
Started Jun 27 06:46:29 PM PDT 24
Finished Jun 27 07:01:29 PM PDT 24
Peak memory 680648 kb
Host smart-cddf30f5-6d01-43af-9108-16e1eb66f1de
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3222577504 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all_with_rand_reset.3222577504
Directory /workspace/2.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.hmac_stress_all.1771733601
Short name T21
Test name
Test status
Simulation time 575580366130 ps
CPU time 6945.83 seconds
Started Jun 27 06:48:21 PM PDT 24
Finished Jun 27 08:44:15 PM PDT 24
Peak memory 460824 kb
Host smart-0a65e270-b01a-4c73-b501-fe0cfedc407d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771733601 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.hmac_stress_all.1771733601
Directory /workspace/49.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.2551448522
Short name T54
Test name
Test status
Simulation time 94225074 ps
CPU time 2.95 seconds
Started Jun 27 06:09:44 PM PDT 24
Finished Jun 27 06:09:53 PM PDT 24
Peak memory 199724 kb
Host smart-31d6d473-b209-4990-b003-36e4cedeef4a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551448522 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_intg_err.2551448522
Directory /workspace/13.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/4.hmac_stress_all.2528590969
Short name T36
Test name
Test status
Simulation time 4903457026 ps
CPU time 317.5 seconds
Started Jun 27 06:46:26 PM PDT 24
Finished Jun 27 06:51:56 PM PDT 24
Peak memory 586524 kb
Host smart-e5cc809a-bbbd-4974-9ce9-a02c3bde97e5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528590969 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all.2528590969
Directory /workspace/4.hmac_stress_all/latest

Test location /workspace/coverage/default/0.hmac_sec_cm.2663173357
Short name T41
Test name
Test status
Simulation time 92113750 ps
CPU time 0.99 seconds
Started Jun 27 06:46:23 PM PDT 24
Finished Jun 27 06:46:32 PM PDT 24
Peak memory 219440 kb
Host smart-4322d878-e66d-4832-a1c8-24bf87afd2bd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663173357 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_sec_cm.2663173357
Directory /workspace/0.hmac_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.2090021844
Short name T98
Test name
Test status
Simulation time 417908849 ps
CPU time 9.44 seconds
Started Jun 27 06:09:27 PM PDT 24
Finished Jun 27 06:09:37 PM PDT 24
Peak memory 198760 kb
Host smart-43110d61-5be9-4ded-96c3-8d8651aeee2d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090021844 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_bit_bash.2090021844
Directory /workspace/0.hmac_csr_bit_bash/latest

Test location /workspace/coverage/default/18.hmac_stress_all.1744166511
Short name T128
Test name
Test status
Simulation time 386290479349 ps
CPU time 1067.28 seconds
Started Jun 27 06:46:51 PM PDT 24
Finished Jun 27 07:04:49 PM PDT 24
Peak memory 216364 kb
Host smart-b6610fdf-9b45-4e0d-ae86-812c5b2d63ea
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744166511 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.hmac_stress_all.1744166511
Directory /workspace/18.hmac_stress_all/latest

Test location /workspace/coverage/default/44.hmac_long_msg.1120230422
Short name T4
Test name
Test status
Simulation time 2061614966 ps
CPU time 125.62 seconds
Started Jun 27 06:48:02 PM PDT 24
Finished Jun 27 06:50:12 PM PDT 24
Peak memory 199980 kb
Host smart-595c487d-5c6e-4d84-a0c1-cbecf544e442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120230422 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_long_msg.1120230422
Directory /workspace/44.hmac_long_msg/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.2991213052
Short name T61
Test name
Test status
Simulation time 973367689 ps
CPU time 4 seconds
Started Jun 27 06:09:27 PM PDT 24
Finished Jun 27 06:09:33 PM PDT 24
Peak memory 199680 kb
Host smart-d31cea54-5483-4faf-af5c-b3495cdc7f11
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991213052 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_intg_err.2991213052
Directory /workspace/0.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/26.hmac_back_pressure.2562329308
Short name T14
Test name
Test status
Simulation time 200122230 ps
CPU time 8.64 seconds
Started Jun 27 06:47:09 PM PDT 24
Finished Jun 27 06:47:24 PM PDT 24
Peak memory 199812 kb
Host smart-1541527e-2dca-441d-b35a-ef2fa535eeba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2562329308 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_back_pressure.2562329308
Directory /workspace/26.hmac_back_pressure/latest

Test location /workspace/coverage/default/0.hmac_alert_test.995435165
Short name T212
Test name
Test status
Simulation time 22711980 ps
CPU time 0.58 seconds
Started Jun 27 06:46:26 PM PDT 24
Finished Jun 27 06:46:39 PM PDT 24
Peak memory 195972 kb
Host smart-40c40c1e-18d5-43b7-bd32-c7328e6c56bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995435165 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_alert_test.995435165
Directory /workspace/0.hmac_alert_test/latest

Test location /workspace/coverage/default/15.hmac_stress_all.2214111013
Short name T133
Test name
Test status
Simulation time 269569260617 ps
CPU time 4072.93 seconds
Started Jun 27 06:46:37 PM PDT 24
Finished Jun 27 07:54:44 PM PDT 24
Peak memory 866788 kb
Host smart-ecf9f69d-7c53-4b0c-972e-89cd434e56b4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214111013 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.hmac_stress_all.2214111013
Directory /workspace/15.hmac_stress_all/latest

Test location /workspace/coverage/default/18.hmac_back_pressure.3104405376
Short name T135
Test name
Test status
Simulation time 5162969499 ps
CPU time 45.21 seconds
Started Jun 27 06:46:51 PM PDT 24
Finished Jun 27 06:47:45 PM PDT 24
Peak memory 200144 kb
Host smart-b624a4aa-d88e-433e-b2d5-331ee096484e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3104405376 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_back_pressure.3104405376
Directory /workspace/18.hmac_back_pressure/latest

Test location /workspace/coverage/default/48.hmac_datapath_stress.1494382299
Short name T134
Test name
Test status
Simulation time 12937196999 ps
CPU time 874.21 seconds
Started Jun 27 06:48:21 PM PDT 24
Finished Jun 27 07:03:02 PM PDT 24
Peak memory 710128 kb
Host smart-8a2e881b-56a7-4fcf-92a0-18010c9c87bb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1494382299 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_datapath_stress.1494382299
Directory /workspace/48.hmac_datapath_stress/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.1711481826
Short name T112
Test name
Test status
Simulation time 109455919 ps
CPU time 5.67 seconds
Started Jun 27 06:09:30 PM PDT 24
Finished Jun 27 06:09:39 PM PDT 24
Peak memory 199664 kb
Host smart-3970c189-86c6-4d57-a4ef-e408d411b6f0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711481826 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_aliasing.1711481826
Directory /workspace/0.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.344722668
Short name T115
Test name
Test status
Simulation time 42012555 ps
CPU time 1.97 seconds
Started Jun 27 06:09:42 PM PDT 24
Finished Jun 27 06:09:48 PM PDT 24
Peak memory 199580 kb
Host smart-1875c439-fab0-4439-a193-5a1a88f22ca3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344722668 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_same_csr
_outstanding.344722668
Directory /workspace/11.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.2087454297
Short name T60
Test name
Test status
Simulation time 951125455 ps
CPU time 4.35 seconds
Started Jun 27 06:09:43 PM PDT 24
Finished Jun 27 06:09:53 PM PDT 24
Peak memory 199736 kb
Host smart-ab5f6bd3-d1ef-4be5-8764-b5f69462f354
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087454297 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_intg_err.2087454297
Directory /workspace/7.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.337179283
Short name T140
Test name
Test status
Simulation time 389376584 ps
CPU time 1.9 seconds
Started Jun 27 06:09:27 PM PDT 24
Finished Jun 27 06:09:30 PM PDT 24
Peak memory 199656 kb
Host smart-b29b3d54-3137-49b7-ac5a-6e0b2e1df610
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337179283 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_intg_err.337179283
Directory /workspace/1.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/13.hmac_long_msg.4259161662
Short name T196
Test name
Test status
Simulation time 4027371288 ps
CPU time 54.74 seconds
Started Jun 27 06:46:46 PM PDT 24
Finished Jun 27 06:47:52 PM PDT 24
Peak memory 200044 kb
Host smart-aa940cae-4624-443e-b6c4-29fc5f89f916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4259161662 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_long_msg.4259161662
Directory /workspace/13.hmac_long_msg/latest

Test location /workspace/coverage/default/10.hmac_smoke.3673423989
Short name T15
Test name
Test status
Simulation time 512161371 ps
CPU time 6.52 seconds
Started Jun 27 06:46:33 PM PDT 24
Finished Jun 27 06:46:53 PM PDT 24
Peak memory 199972 kb
Host smart-103b7121-a983-4783-9417-f8bc5b579055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673423989 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_smoke.3673423989
Directory /workspace/10.hmac_smoke/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.3506427557
Short name T59
Test name
Test status
Simulation time 108908128 ps
CPU time 2.93 seconds
Started Jun 27 06:09:28 PM PDT 24
Finished Jun 27 06:09:33 PM PDT 24
Peak memory 199680 kb
Host smart-009c238d-7c0f-42c1-8a9a-4f8bbcdbc3af
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506427557 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_intg_err.3506427557
Directory /workspace/4.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.2567937607
Short name T110
Test name
Test status
Simulation time 75480909 ps
CPU time 1 seconds
Started Jun 27 06:09:29 PM PDT 24
Finished Jun 27 06:09:32 PM PDT 24
Peak memory 199440 kb
Host smart-5a3f06fd-2d0d-4870-b5da-846b2ba9cb84
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567937607 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_hw_reset.2567937607
Directory /workspace/0.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.3672713421
Short name T723
Test name
Test status
Simulation time 5225747036 ps
CPU time 40.83 seconds
Started Jun 27 06:09:29 PM PDT 24
Finished Jun 27 06:10:12 PM PDT 24
Peak memory 215408 kb
Host smart-6ad9fb32-4c51-4229-a6f1-49818f342b45
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672713421 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.hmac_csr_mem_rw_with_rand_reset.3672713421
Directory /workspace/0.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_rw.1826494321
Short name T78
Test name
Test status
Simulation time 87348070 ps
CPU time 0.89 seconds
Started Jun 27 06:09:28 PM PDT 24
Finished Jun 27 06:09:31 PM PDT 24
Peak memory 199288 kb
Host smart-ce40119f-8179-4ed9-ade5-1190687b7ee8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826494321 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_rw.1826494321
Directory /workspace/0.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_intr_test.3517882870
Short name T742
Test name
Test status
Simulation time 19523143 ps
CPU time 0.61 seconds
Started Jun 27 06:09:29 PM PDT 24
Finished Jun 27 06:09:32 PM PDT 24
Peak memory 194488 kb
Host smart-7e9cac1d-c6d9-42d8-80b0-40a5f5551905
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517882870 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_intr_test.3517882870
Directory /workspace/0.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.983966472
Short name T737
Test name
Test status
Simulation time 36928669 ps
CPU time 1.64 seconds
Started Jun 27 06:09:28 PM PDT 24
Finished Jun 27 06:09:32 PM PDT 24
Peak memory 199628 kb
Host smart-156c4bcb-6b21-4615-ae61-29aac09dbbe0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983966472 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_same_csr_
outstanding.983966472
Directory /workspace/0.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_errors.3656769039
Short name T763
Test name
Test status
Simulation time 89249071 ps
CPU time 1.33 seconds
Started Jun 27 06:09:25 PM PDT 24
Finished Jun 27 06:09:27 PM PDT 24
Peak memory 199972 kb
Host smart-fe6b3828-8c83-4038-a7a6-e76cead19a2f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656769039 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_errors.3656769039
Directory /workspace/0.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.1720757678
Short name T100
Test name
Test status
Simulation time 323207007 ps
CPU time 8.09 seconds
Started Jun 27 06:09:30 PM PDT 24
Finished Jun 27 06:09:40 PM PDT 24
Peak memory 199248 kb
Host smart-67ef4cbe-d132-41d6-9519-287d1815ab39
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720757678 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_aliasing.1720757678
Directory /workspace/1.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.3129303686
Short name T787
Test name
Test status
Simulation time 910184317 ps
CPU time 10.67 seconds
Started Jun 27 06:09:29 PM PDT 24
Finished Jun 27 06:09:41 PM PDT 24
Peak memory 199688 kb
Host smart-9b166f27-dca6-49c2-9972-7449d50b9125
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129303686 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_bit_bash.3129303686
Directory /workspace/1.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.3285007142
Short name T104
Test name
Test status
Simulation time 49077703 ps
CPU time 0.92 seconds
Started Jun 27 06:09:29 PM PDT 24
Finished Jun 27 06:09:32 PM PDT 24
Peak memory 198856 kb
Host smart-fbb5bba5-09bf-4690-a4d7-6ae87ac87430
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285007142 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_hw_reset.3285007142
Directory /workspace/1.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.1312531467
Short name T785
Test name
Test status
Simulation time 142318876 ps
CPU time 2.31 seconds
Started Jun 27 06:09:30 PM PDT 24
Finished Jun 27 06:09:34 PM PDT 24
Peak memory 199844 kb
Host smart-fb0c7b43-7c9b-4a3f-8abd-5e065f932594
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312531467 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.hmac_csr_mem_rw_with_rand_reset.1312531467
Directory /workspace/1.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_rw.1748966911
Short name T761
Test name
Test status
Simulation time 58758721 ps
CPU time 0.74 seconds
Started Jun 27 06:09:30 PM PDT 24
Finished Jun 27 06:09:34 PM PDT 24
Peak memory 197008 kb
Host smart-32e2e045-0ae9-4267-9dd0-a050aeb2b703
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748966911 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_rw.1748966911
Directory /workspace/1.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_intr_test.1409720154
Short name T794
Test name
Test status
Simulation time 46720176 ps
CPU time 0.65 seconds
Started Jun 27 06:09:28 PM PDT 24
Finished Jun 27 06:09:31 PM PDT 24
Peak memory 194392 kb
Host smart-aa2979bb-ef3a-416a-a35e-f04178053ee2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409720154 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_intr_test.1409720154
Directory /workspace/1.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.1444618764
Short name T813
Test name
Test status
Simulation time 93585553 ps
CPU time 1.16 seconds
Started Jun 27 06:09:31 PM PDT 24
Finished Jun 27 06:09:35 PM PDT 24
Peak memory 198180 kb
Host smart-d9169116-8ac1-4a4a-9a43-f66bc6747327
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444618764 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_same_csr
_outstanding.1444618764
Directory /workspace/1.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_errors.163835288
Short name T758
Test name
Test status
Simulation time 101180575 ps
CPU time 1.94 seconds
Started Jun 27 06:09:26 PM PDT 24
Finished Jun 27 06:09:29 PM PDT 24
Peak memory 199700 kb
Host smart-be54c0c4-20e1-4339-9f0e-06c22618fb91
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163835288 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_errors.163835288
Directory /workspace/1.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.3466265739
Short name T79
Test name
Test status
Simulation time 287320588 ps
CPU time 1.94 seconds
Started Jun 27 06:09:44 PM PDT 24
Finished Jun 27 06:09:52 PM PDT 24
Peak memory 199748 kb
Host smart-f8d88ebc-a4f3-41b4-a3d9-9f3f8adbff12
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466265739 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.hmac_csr_mem_rw_with_rand_reset.3466265739
Directory /workspace/10.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_rw.3218134087
Short name T748
Test name
Test status
Simulation time 34937699 ps
CPU time 0.95 seconds
Started Jun 27 06:09:49 PM PDT 24
Finished Jun 27 06:09:56 PM PDT 24
Peak memory 199444 kb
Host smart-909b298e-ee50-4c8c-a39e-66bb2c39d100
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218134087 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_rw.3218134087
Directory /workspace/10.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_intr_test.3826593435
Short name T767
Test name
Test status
Simulation time 16054538 ps
CPU time 0.64 seconds
Started Jun 27 06:09:41 PM PDT 24
Finished Jun 27 06:09:45 PM PDT 24
Peak memory 194520 kb
Host smart-feaaa593-3ac8-4ecb-a662-509fbe67213f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826593435 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_intr_test.3826593435
Directory /workspace/10.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.4181571990
Short name T744
Test name
Test status
Simulation time 128242082 ps
CPU time 2.11 seconds
Started Jun 27 06:09:42 PM PDT 24
Finished Jun 27 06:09:48 PM PDT 24
Peak memory 199752 kb
Host smart-c9030a30-b566-486e-a78f-183547ad558b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181571990 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_same_cs
r_outstanding.4181571990
Directory /workspace/10.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_errors.3570240047
Short name T58
Test name
Test status
Simulation time 119901298 ps
CPU time 1.8 seconds
Started Jun 27 06:09:42 PM PDT 24
Finished Jun 27 06:09:48 PM PDT 24
Peak memory 199784 kb
Host smart-06a3152c-3954-4020-a6db-188021d676e7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570240047 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_errors.3570240047
Directory /workspace/10.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.1805477544
Short name T56
Test name
Test status
Simulation time 88810071 ps
CPU time 2.84 seconds
Started Jun 27 06:09:47 PM PDT 24
Finished Jun 27 06:09:57 PM PDT 24
Peak memory 199728 kb
Host smart-8a835f14-822b-4909-8a02-d6a3e0516b83
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805477544 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_intg_err.1805477544
Directory /workspace/10.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.733854402
Short name T722
Test name
Test status
Simulation time 125945307 ps
CPU time 2.62 seconds
Started Jun 27 06:09:44 PM PDT 24
Finished Jun 27 06:09:54 PM PDT 24
Peak memory 199840 kb
Host smart-54020bc0-f239-45e4-8863-6e2726230d86
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733854402 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.hmac_csr_mem_rw_with_rand_reset.733854402
Directory /workspace/11.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_rw.2650857793
Short name T105
Test name
Test status
Simulation time 14837367 ps
CPU time 0.81 seconds
Started Jun 27 06:09:44 PM PDT 24
Finished Jun 27 06:09:53 PM PDT 24
Peak memory 199080 kb
Host smart-14a674ef-78a6-49c9-b888-0c1f7a4642d3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650857793 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_rw.2650857793
Directory /workspace/11.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_intr_test.3821334208
Short name T80
Test name
Test status
Simulation time 45991545 ps
CPU time 0.62 seconds
Started Jun 27 06:09:42 PM PDT 24
Finished Jun 27 06:09:46 PM PDT 24
Peak memory 194496 kb
Host smart-346a7d2f-c641-4231-bf4e-e7bc61bcff11
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821334208 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_intr_test.3821334208
Directory /workspace/11.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_errors.3479326287
Short name T753
Test name
Test status
Simulation time 702316563 ps
CPU time 3.42 seconds
Started Jun 27 06:09:43 PM PDT 24
Finished Jun 27 06:09:52 PM PDT 24
Peak memory 199692 kb
Host smart-4e3172b3-e403-42f5-b293-d5d5747b454c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479326287 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_errors.3479326287
Directory /workspace/11.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.1565413322
Short name T139
Test name
Test status
Simulation time 734501285 ps
CPU time 3.13 seconds
Started Jun 27 06:09:45 PM PDT 24
Finished Jun 27 06:09:56 PM PDT 24
Peak memory 199656 kb
Host smart-dd9bcb9a-7cd8-4422-8e9f-b659373a4fd9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565413322 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_intg_err.1565413322
Directory /workspace/11.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.3180572081
Short name T42
Test name
Test status
Simulation time 250963476508 ps
CPU time 929.37 seconds
Started Jun 27 06:09:44 PM PDT 24
Finished Jun 27 06:25:20 PM PDT 24
Peak memory 224552 kb
Host smart-b8fe2898-2eb7-4e8d-be23-e1fdf32a6b18
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180572081 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.hmac_csr_mem_rw_with_rand_reset.3180572081
Directory /workspace/12.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_rw.1236934693
Short name T109
Test name
Test status
Simulation time 32216573 ps
CPU time 0.72 seconds
Started Jun 27 06:09:44 PM PDT 24
Finished Jun 27 06:09:53 PM PDT 24
Peak memory 197808 kb
Host smart-6d2c2dec-c87b-4cdf-a6fc-6f02a0a515fa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236934693 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_rw.1236934693
Directory /workspace/12.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_intr_test.320342009
Short name T736
Test name
Test status
Simulation time 74787285 ps
CPU time 0.61 seconds
Started Jun 27 06:09:43 PM PDT 24
Finished Jun 27 06:09:50 PM PDT 24
Peak memory 194556 kb
Host smart-879768c8-ce05-48c7-a1eb-6ed068a0e716
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320342009 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_intr_test.320342009
Directory /workspace/12.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.511678879
Short name T118
Test name
Test status
Simulation time 413049306 ps
CPU time 2.13 seconds
Started Jun 27 06:09:48 PM PDT 24
Finished Jun 27 06:09:57 PM PDT 24
Peak memory 199652 kb
Host smart-cf5b9219-82e5-4d83-a8e0-1b91826884e8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511678879 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_same_csr
_outstanding.511678879
Directory /workspace/12.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_errors.1739150552
Short name T801
Test name
Test status
Simulation time 126883934 ps
CPU time 2.91 seconds
Started Jun 27 06:09:43 PM PDT 24
Finished Jun 27 06:09:52 PM PDT 24
Peak memory 199716 kb
Host smart-c6a17882-6b6d-4170-ba67-31d5227b01b3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739150552 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_errors.1739150552
Directory /workspace/12.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.3904048695
Short name T803
Test name
Test status
Simulation time 783665145 ps
CPU time 1.92 seconds
Started Jun 27 06:09:41 PM PDT 24
Finished Jun 27 06:09:46 PM PDT 24
Peak memory 199812 kb
Host smart-fabb1fb8-ac19-48dd-bc4c-1f5574c9af37
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904048695 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_intg_err.3904048695
Directory /workspace/12.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.3921300367
Short name T790
Test name
Test status
Simulation time 78769365 ps
CPU time 1.31 seconds
Started Jun 27 06:09:44 PM PDT 24
Finished Jun 27 06:09:52 PM PDT 24
Peak memory 199888 kb
Host smart-1fd1d19d-80a4-4b8f-9ded-2514cc2cbe47
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921300367 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.hmac_csr_mem_rw_with_rand_reset.3921300367
Directory /workspace/13.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_rw.1890461439
Short name T805
Test name
Test status
Simulation time 33017663 ps
CPU time 0.69 seconds
Started Jun 27 06:09:44 PM PDT 24
Finished Jun 27 06:09:51 PM PDT 24
Peak memory 197504 kb
Host smart-a7b51754-c452-4b3f-b241-5f7702a838fb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890461439 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_rw.1890461439
Directory /workspace/13.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_intr_test.671570000
Short name T728
Test name
Test status
Simulation time 10881041 ps
CPU time 0.6 seconds
Started Jun 27 06:09:43 PM PDT 24
Finished Jun 27 06:09:49 PM PDT 24
Peak memory 194452 kb
Host smart-3bdb1621-462d-44e9-9062-3b93b5b73308
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671570000 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_intr_test.671570000
Directory /workspace/13.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.1573708735
Short name T121
Test name
Test status
Simulation time 608666625 ps
CPU time 2.33 seconds
Started Jun 27 06:09:47 PM PDT 24
Finished Jun 27 06:09:57 PM PDT 24
Peak memory 199752 kb
Host smart-6f5e96fe-527a-48f0-bc74-f4cfa6ed075a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573708735 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_same_cs
r_outstanding.1573708735
Directory /workspace/13.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_errors.373669236
Short name T53
Test name
Test status
Simulation time 341479194 ps
CPU time 3.82 seconds
Started Jun 27 06:09:42 PM PDT 24
Finished Jun 27 06:09:50 PM PDT 24
Peak memory 199780 kb
Host smart-4e6ee7c9-2ca3-4d71-9c35-7a0c52c2eee6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373669236 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_errors.373669236
Directory /workspace/13.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.51487258
Short name T769
Test name
Test status
Simulation time 809565297 ps
CPU time 2.24 seconds
Started Jun 27 06:09:49 PM PDT 24
Finished Jun 27 06:09:58 PM PDT 24
Peak memory 199848 kb
Host smart-01890460-b2ac-4461-9ddf-9bbabaafe43c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51487258 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.hmac_csr_mem_rw_with_rand_reset.51487258
Directory /workspace/14.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_rw.3123589709
Short name T120
Test name
Test status
Simulation time 16718283 ps
CPU time 0.7 seconds
Started Jun 27 06:09:44 PM PDT 24
Finished Jun 27 06:09:51 PM PDT 24
Peak memory 197456 kb
Host smart-42a1e792-1f52-436e-ac82-995190a1c3ac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123589709 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_rw.3123589709
Directory /workspace/14.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_intr_test.2993704018
Short name T808
Test name
Test status
Simulation time 13053388 ps
CPU time 0.6 seconds
Started Jun 27 06:09:45 PM PDT 24
Finished Jun 27 06:09:54 PM PDT 24
Peak memory 194524 kb
Host smart-17f6728f-5054-4653-8957-772bc53db47c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993704018 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_intr_test.2993704018
Directory /workspace/14.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.2449381648
Short name T782
Test name
Test status
Simulation time 57161742 ps
CPU time 1.17 seconds
Started Jun 27 06:09:42 PM PDT 24
Finished Jun 27 06:09:47 PM PDT 24
Peak memory 199716 kb
Host smart-da95b049-d78d-42ec-8466-d3c4e6a45090
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449381648 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_same_cs
r_outstanding.2449381648
Directory /workspace/14.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_errors.966998290
Short name T809
Test name
Test status
Simulation time 65327402 ps
CPU time 3.48 seconds
Started Jun 27 06:09:44 PM PDT 24
Finished Jun 27 06:09:55 PM PDT 24
Peak memory 199716 kb
Host smart-c2eb2cc7-7b7d-4399-bba3-4a965025ce63
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966998290 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_errors.966998290
Directory /workspace/14.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.1316587940
Short name T725
Test name
Test status
Simulation time 190348373 ps
CPU time 1.83 seconds
Started Jun 27 06:09:43 PM PDT 24
Finished Jun 27 06:09:51 PM PDT 24
Peak memory 199704 kb
Host smart-ac21f6f3-98bd-4fa8-b04b-78549d0a1a6b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316587940 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_intg_err.1316587940
Directory /workspace/14.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.4214974377
Short name T711
Test name
Test status
Simulation time 101239317 ps
CPU time 2.45 seconds
Started Jun 27 06:09:42 PM PDT 24
Finished Jun 27 06:09:49 PM PDT 24
Peak memory 199852 kb
Host smart-0b37de08-3dd5-4749-b73b-c329f23cc01c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214974377 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.hmac_csr_mem_rw_with_rand_reset.4214974377
Directory /workspace/15.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_rw.3543007999
Short name T765
Test name
Test status
Simulation time 34642636 ps
CPU time 0.96 seconds
Started Jun 27 06:09:43 PM PDT 24
Finished Jun 27 06:09:49 PM PDT 24
Peak memory 199476 kb
Host smart-8bec198d-d364-4dc5-969f-d2b22d2c200c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543007999 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_rw.3543007999
Directory /workspace/15.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_intr_test.1607783186
Short name T706
Test name
Test status
Simulation time 17208630 ps
CPU time 0.59 seconds
Started Jun 27 06:09:40 PM PDT 24
Finished Jun 27 06:09:43 PM PDT 24
Peak memory 194508 kb
Host smart-c8cec06d-96ba-48cd-b006-7509610d57ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607783186 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_intr_test.1607783186
Directory /workspace/15.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.1106150006
Short name T759
Test name
Test status
Simulation time 306411282 ps
CPU time 2.45 seconds
Started Jun 27 06:09:42 PM PDT 24
Finished Jun 27 06:09:49 PM PDT 24
Peak memory 199692 kb
Host smart-0ed3cf00-91f1-4e0f-a646-873d227d5017
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106150006 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_same_cs
r_outstanding.1106150006
Directory /workspace/15.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_errors.35419543
Short name T757
Test name
Test status
Simulation time 254780055 ps
CPU time 3.54 seconds
Started Jun 27 06:09:44 PM PDT 24
Finished Jun 27 06:09:55 PM PDT 24
Peak memory 199652 kb
Host smart-647a573e-ed9e-4137-8ac6-335b269ec52d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35419543 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_errors.35419543
Directory /workspace/15.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.4110199179
Short name T796
Test name
Test status
Simulation time 155631355 ps
CPU time 3.19 seconds
Started Jun 27 06:09:44 PM PDT 24
Finished Jun 27 06:09:54 PM PDT 24
Peak memory 199720 kb
Host smart-da9e1ad5-8be1-4daf-9add-3b86e1bf6366
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110199179 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_intg_err.4110199179
Directory /workspace/15.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.3133444791
Short name T708
Test name
Test status
Simulation time 45856559567 ps
CPU time 98.74 seconds
Started Jun 27 06:09:44 PM PDT 24
Finished Jun 27 06:11:31 PM PDT 24
Peak memory 215316 kb
Host smart-530ace0f-5115-4b7d-bae2-ed0e53e8367e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133444791 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.hmac_csr_mem_rw_with_rand_reset.3133444791
Directory /workspace/16.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_rw.2687248608
Short name T122
Test name
Test status
Simulation time 15004634 ps
CPU time 0.71 seconds
Started Jun 27 06:09:46 PM PDT 24
Finished Jun 27 06:09:54 PM PDT 24
Peak memory 197556 kb
Host smart-a5edd312-20ea-4a20-b644-83e5a9119bc1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687248608 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_rw.2687248608
Directory /workspace/16.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_intr_test.3441066575
Short name T715
Test name
Test status
Simulation time 47501273 ps
CPU time 0.6 seconds
Started Jun 27 06:09:48 PM PDT 24
Finished Jun 27 06:09:56 PM PDT 24
Peak memory 194624 kb
Host smart-9b2c88fd-1770-481d-894b-fad0f7b5b147
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441066575 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_intr_test.3441066575
Directory /workspace/16.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.843522124
Short name T113
Test name
Test status
Simulation time 262458125 ps
CPU time 1.63 seconds
Started Jun 27 06:09:44 PM PDT 24
Finished Jun 27 06:09:53 PM PDT 24
Peak memory 199584 kb
Host smart-5b73a42c-be7c-4c6a-afff-4cfc3f3d1cc5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843522124 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_same_csr
_outstanding.843522124
Directory /workspace/16.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_errors.2465300469
Short name T754
Test name
Test status
Simulation time 337933502 ps
CPU time 1.94 seconds
Started Jun 27 06:09:45 PM PDT 24
Finished Jun 27 06:09:55 PM PDT 24
Peak memory 199688 kb
Host smart-3526aaa9-a1ac-4062-9465-3e7b47e88c29
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465300469 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_errors.2465300469
Directory /workspace/16.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.691216894
Short name T145
Test name
Test status
Simulation time 2279323981 ps
CPU time 3.19 seconds
Started Jun 27 06:09:41 PM PDT 24
Finished Jun 27 06:09:47 PM PDT 24
Peak memory 199844 kb
Host smart-90b27bf8-3b2f-4024-bfd6-b60d6da8c3fe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691216894 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_intg_err.691216894
Directory /workspace/16.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.1928208735
Short name T43
Test name
Test status
Simulation time 37783983 ps
CPU time 2.23 seconds
Started Jun 27 06:09:48 PM PDT 24
Finished Jun 27 06:09:57 PM PDT 24
Peak memory 199828 kb
Host smart-8e9eed8d-8ee8-4390-8efe-f41ce12dbdd8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928208735 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.hmac_csr_mem_rw_with_rand_reset.1928208735
Directory /workspace/17.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_rw.1894308080
Short name T814
Test name
Test status
Simulation time 66694953 ps
CPU time 0.73 seconds
Started Jun 27 06:09:45 PM PDT 24
Finished Jun 27 06:09:54 PM PDT 24
Peak memory 197480 kb
Host smart-1177b7c7-d743-43ca-9168-87f757c0adf2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894308080 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_rw.1894308080
Directory /workspace/17.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_intr_test.1783628248
Short name T710
Test name
Test status
Simulation time 14808044 ps
CPU time 0.64 seconds
Started Jun 27 06:09:46 PM PDT 24
Finished Jun 27 06:09:54 PM PDT 24
Peak memory 194416 kb
Host smart-a37376b5-bfa7-45ab-9ac0-12df9c137efb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783628248 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_intr_test.1783628248
Directory /workspace/17.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.4228887917
Short name T119
Test name
Test status
Simulation time 86997335 ps
CPU time 1.72 seconds
Started Jun 27 06:09:48 PM PDT 24
Finished Jun 27 06:09:57 PM PDT 24
Peak memory 199744 kb
Host smart-33d639c7-890d-412a-b89f-cbab11884ea9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228887917 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_same_cs
r_outstanding.4228887917
Directory /workspace/17.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_errors.2334560464
Short name T784
Test name
Test status
Simulation time 831881572 ps
CPU time 3.03 seconds
Started Jun 27 06:09:48 PM PDT 24
Finished Jun 27 06:09:58 PM PDT 24
Peak memory 199760 kb
Host smart-d9a83a58-edf8-4781-bc14-cc8eca4dcfc1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334560464 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_errors.2334560464
Directory /workspace/17.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.2137695246
Short name T55
Test name
Test status
Simulation time 502083332 ps
CPU time 2.79 seconds
Started Jun 27 06:09:44 PM PDT 24
Finished Jun 27 06:09:55 PM PDT 24
Peak memory 199692 kb
Host smart-34ccab14-a4dc-4356-9743-e517b33a6e27
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137695246 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_intg_err.2137695246
Directory /workspace/17.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.2232434526
Short name T731
Test name
Test status
Simulation time 177097753 ps
CPU time 1.92 seconds
Started Jun 27 06:09:45 PM PDT 24
Finished Jun 27 06:09:54 PM PDT 24
Peak memory 215244 kb
Host smart-10e25701-cc15-4e68-b50e-a0872e63ce57
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232434526 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.hmac_csr_mem_rw_with_rand_reset.2232434526
Directory /workspace/18.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_rw.2226325689
Short name T107
Test name
Test status
Simulation time 180379490 ps
CPU time 0.81 seconds
Started Jun 27 06:09:44 PM PDT 24
Finished Jun 27 06:09:51 PM PDT 24
Peak memory 199000 kb
Host smart-b300f5e9-19e9-47a9-be2d-ea8255b04d51
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226325689 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_rw.2226325689
Directory /workspace/18.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_intr_test.1615640289
Short name T799
Test name
Test status
Simulation time 14642836 ps
CPU time 0.59 seconds
Started Jun 27 06:09:43 PM PDT 24
Finished Jun 27 06:09:49 PM PDT 24
Peak memory 194528 kb
Host smart-fc91cee8-6956-4ddd-91ec-2063d43f4f85
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615640289 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_intr_test.1615640289
Directory /workspace/18.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.2681099634
Short name T773
Test name
Test status
Simulation time 144872605 ps
CPU time 2.26 seconds
Started Jun 27 06:09:43 PM PDT 24
Finished Jun 27 06:09:52 PM PDT 24
Peak memory 199608 kb
Host smart-2f0ce37f-648b-4d80-bb85-b02445bf7dac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681099634 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_same_cs
r_outstanding.2681099634
Directory /workspace/18.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_errors.1817780419
Short name T777
Test name
Test status
Simulation time 310954182 ps
CPU time 3.6 seconds
Started Jun 27 06:09:46 PM PDT 24
Finished Jun 27 06:09:57 PM PDT 24
Peak memory 199596 kb
Host smart-9ed6820a-6158-414a-b64b-50344bf3192d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817780419 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_errors.1817780419
Directory /workspace/18.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.2118871538
Short name T143
Test name
Test status
Simulation time 321394020 ps
CPU time 4.46 seconds
Started Jun 27 06:09:43 PM PDT 24
Finished Jun 27 06:09:54 PM PDT 24
Peak memory 199636 kb
Host smart-657e109a-a35e-4c8f-9708-9f444690a2f3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118871538 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_intg_err.2118871538
Directory /workspace/18.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.3856241497
Short name T745
Test name
Test status
Simulation time 112319704 ps
CPU time 1.55 seconds
Started Jun 27 06:09:46 PM PDT 24
Finished Jun 27 06:09:56 PM PDT 24
Peak memory 199800 kb
Host smart-81b17400-d1f0-4140-9c5b-7c4b8c5096fc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856241497 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.hmac_csr_mem_rw_with_rand_reset.3856241497
Directory /workspace/19.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_rw.25824729
Short name T108
Test name
Test status
Simulation time 222147879 ps
CPU time 0.83 seconds
Started Jun 27 06:09:45 PM PDT 24
Finished Jun 27 06:09:53 PM PDT 24
Peak memory 199420 kb
Host smart-064004be-5834-4f53-8497-cdc7ae47b1f3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25824729 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_rw.25824729
Directory /workspace/19.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_intr_test.503864181
Short name T762
Test name
Test status
Simulation time 38557751 ps
CPU time 0.6 seconds
Started Jun 27 06:09:45 PM PDT 24
Finished Jun 27 06:09:53 PM PDT 24
Peak memory 194616 kb
Host smart-c9f9d2b1-5246-46ac-af29-e03f375755ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503864181 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_intr_test.503864181
Directory /workspace/19.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.3672014357
Short name T781
Test name
Test status
Simulation time 165163982 ps
CPU time 2.5 seconds
Started Jun 27 06:09:43 PM PDT 24
Finished Jun 27 06:09:51 PM PDT 24
Peak memory 199688 kb
Host smart-53ed20c6-d4cd-41d4-b759-d667b3de145f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672014357 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_same_cs
r_outstanding.3672014357
Directory /workspace/19.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_errors.3012280173
Short name T772
Test name
Test status
Simulation time 181557153 ps
CPU time 2.49 seconds
Started Jun 27 06:09:45 PM PDT 24
Finished Jun 27 06:09:55 PM PDT 24
Peak memory 199576 kb
Host smart-fac66e48-d48a-4f4d-821a-6ffdaed081a0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012280173 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_errors.3012280173
Directory /workspace/19.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.3254515688
Short name T791
Test name
Test status
Simulation time 129786956 ps
CPU time 3.99 seconds
Started Jun 27 06:09:45 PM PDT 24
Finished Jun 27 06:09:57 PM PDT 24
Peak memory 199608 kb
Host smart-75009572-5a0d-470e-8a69-9d7baad6d337
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254515688 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_intg_err.3254515688
Directory /workspace/19.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.736849794
Short name T99
Test name
Test status
Simulation time 584269867 ps
CPU time 8.64 seconds
Started Jun 27 06:09:30 PM PDT 24
Finished Jun 27 06:09:42 PM PDT 24
Peak memory 199332 kb
Host smart-b90fa876-b2c1-499f-8fd6-fadab24b5ef1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736849794 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_aliasing.736849794
Directory /workspace/2.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.824685300
Short name T806
Test name
Test status
Simulation time 1428976155 ps
CPU time 5.73 seconds
Started Jun 27 06:09:29 PM PDT 24
Finished Jun 27 06:09:37 PM PDT 24
Peak memory 199468 kb
Host smart-d2659284-961b-45a2-8998-59f828a238f0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824685300 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_bit_bash.824685300
Directory /workspace/2.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.2535872879
Short name T102
Test name
Test status
Simulation time 199006372 ps
CPU time 0.96 seconds
Started Jun 27 06:09:28 PM PDT 24
Finished Jun 27 06:09:31 PM PDT 24
Peak memory 198888 kb
Host smart-a54388d3-0b66-4ef0-8a3c-77ee40bb6df7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535872879 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_hw_reset.2535872879
Directory /workspace/2.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.2352317078
Short name T709
Test name
Test status
Simulation time 240865076 ps
CPU time 1.75 seconds
Started Jun 27 06:09:27 PM PDT 24
Finished Jun 27 06:09:30 PM PDT 24
Peak memory 199888 kb
Host smart-97805fe9-7d18-4dbd-8abd-0a09fe8971fe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352317078 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.hmac_csr_mem_rw_with_rand_reset.2352317078
Directory /workspace/2.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_rw.608745988
Short name T103
Test name
Test status
Simulation time 20828651 ps
CPU time 0.95 seconds
Started Jun 27 06:09:30 PM PDT 24
Finished Jun 27 06:09:33 PM PDT 24
Peak memory 199480 kb
Host smart-348fc170-e012-4437-bd0f-1c51934dfec8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608745988 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_rw.608745988
Directory /workspace/2.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_intr_test.1714764234
Short name T792
Test name
Test status
Simulation time 14706128 ps
CPU time 0.58 seconds
Started Jun 27 06:09:26 PM PDT 24
Finished Jun 27 06:09:28 PM PDT 24
Peak memory 194544 kb
Host smart-40de56a1-1070-4a7d-9270-0e0c71119b2e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714764234 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_intr_test.1714764234
Directory /workspace/2.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.1554400852
Short name T743
Test name
Test status
Simulation time 1588867851 ps
CPU time 1.67 seconds
Started Jun 27 06:09:29 PM PDT 24
Finished Jun 27 06:09:33 PM PDT 24
Peak memory 199660 kb
Host smart-84dd5d43-a823-4d4a-8724-fbaa17f7b94d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554400852 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_same_csr
_outstanding.1554400852
Directory /workspace/2.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_errors.933479653
Short name T57
Test name
Test status
Simulation time 79763873 ps
CPU time 4.45 seconds
Started Jun 27 06:09:29 PM PDT 24
Finished Jun 27 06:09:35 PM PDT 24
Peak memory 199716 kb
Host smart-ef5d6d82-1076-46a4-ae8e-1251df3d8636
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933479653 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_errors.933479653
Directory /workspace/2.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.850379306
Short name T144
Test name
Test status
Simulation time 371404663 ps
CPU time 1.87 seconds
Started Jun 27 06:09:32 PM PDT 24
Finished Jun 27 06:09:36 PM PDT 24
Peak memory 199700 kb
Host smart-66fca1e3-a441-4997-bca3-f9fd16215cae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850379306 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_intg_err.850379306
Directory /workspace/2.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.hmac_intr_test.2061969042
Short name T766
Test name
Test status
Simulation time 45838885 ps
CPU time 0.62 seconds
Started Jun 27 06:09:46 PM PDT 24
Finished Jun 27 06:09:54 PM PDT 24
Peak memory 194508 kb
Host smart-ebeb9f87-4ac6-49a8-99ce-69d54399677d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061969042 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.hmac_intr_test.2061969042
Directory /workspace/20.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.hmac_intr_test.454627494
Short name T802
Test name
Test status
Simulation time 13727569 ps
CPU time 0.66 seconds
Started Jun 27 06:09:46 PM PDT 24
Finished Jun 27 06:09:55 PM PDT 24
Peak memory 194500 kb
Host smart-6e1e6e92-1d42-4db3-9f64-8906d7e1b06c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454627494 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.hmac_intr_test.454627494
Directory /workspace/21.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.hmac_intr_test.542260768
Short name T727
Test name
Test status
Simulation time 17460692 ps
CPU time 0.65 seconds
Started Jun 27 06:09:46 PM PDT 24
Finished Jun 27 06:09:54 PM PDT 24
Peak memory 194516 kb
Host smart-ab7ba914-1e76-42d0-886b-c88fe6aa4375
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542260768 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.hmac_intr_test.542260768
Directory /workspace/22.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.hmac_intr_test.2252182018
Short name T811
Test name
Test status
Simulation time 189758631 ps
CPU time 0.59 seconds
Started Jun 27 06:09:46 PM PDT 24
Finished Jun 27 06:09:54 PM PDT 24
Peak memory 194508 kb
Host smart-84fe8718-d9f9-4267-b9eb-d827c3619ef7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252182018 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.hmac_intr_test.2252182018
Directory /workspace/23.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.hmac_intr_test.3707437237
Short name T750
Test name
Test status
Simulation time 26075626 ps
CPU time 0.63 seconds
Started Jun 27 06:09:46 PM PDT 24
Finished Jun 27 06:09:54 PM PDT 24
Peak memory 194536 kb
Host smart-69a0bec3-4633-413b-9378-bf1d84c7028f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707437237 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.hmac_intr_test.3707437237
Directory /workspace/24.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.hmac_intr_test.1004910603
Short name T747
Test name
Test status
Simulation time 49127694 ps
CPU time 0.59 seconds
Started Jun 27 06:09:46 PM PDT 24
Finished Jun 27 06:09:54 PM PDT 24
Peak memory 194492 kb
Host smart-ac7493a4-741a-4336-a307-bbb3599212bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004910603 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.hmac_intr_test.1004910603
Directory /workspace/25.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.hmac_intr_test.2413072958
Short name T768
Test name
Test status
Simulation time 20943402 ps
CPU time 0.6 seconds
Started Jun 27 06:09:45 PM PDT 24
Finished Jun 27 06:09:53 PM PDT 24
Peak memory 194512 kb
Host smart-f92b1faa-0136-477d-b8e1-b95060ba05af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413072958 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.hmac_intr_test.2413072958
Directory /workspace/26.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.hmac_intr_test.3258820688
Short name T718
Test name
Test status
Simulation time 37948348 ps
CPU time 0.6 seconds
Started Jun 27 06:09:47 PM PDT 24
Finished Jun 27 06:09:55 PM PDT 24
Peak memory 194536 kb
Host smart-3fed4888-41bf-4cc7-8f24-2a1646703e9a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258820688 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.hmac_intr_test.3258820688
Directory /workspace/27.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.hmac_intr_test.3968032890
Short name T760
Test name
Test status
Simulation time 24797836 ps
CPU time 0.56 seconds
Started Jun 27 06:09:54 PM PDT 24
Finished Jun 27 06:09:59 PM PDT 24
Peak memory 194496 kb
Host smart-4f8bd558-5779-4a78-9dd6-27bc8239f566
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968032890 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.hmac_intr_test.3968032890
Directory /workspace/28.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.hmac_intr_test.1890866035
Short name T705
Test name
Test status
Simulation time 27219130 ps
CPU time 0.59 seconds
Started Jun 27 06:09:59 PM PDT 24
Finished Jun 27 06:10:03 PM PDT 24
Peak memory 194388 kb
Host smart-e867a0ab-a46c-4115-8db6-30d84413263b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890866035 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.hmac_intr_test.1890866035
Directory /workspace/29.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.2212017159
Short name T786
Test name
Test status
Simulation time 1711779871 ps
CPU time 3.53 seconds
Started Jun 27 06:09:31 PM PDT 24
Finished Jun 27 06:09:37 PM PDT 24
Peak memory 199584 kb
Host smart-67bae01d-0955-4fd0-8044-c560718bd280
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212017159 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_aliasing.2212017159
Directory /workspace/3.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.2324850055
Short name T720
Test name
Test status
Simulation time 1492590991 ps
CPU time 5.92 seconds
Started Jun 27 06:09:27 PM PDT 24
Finished Jun 27 06:09:35 PM PDT 24
Peak memory 199632 kb
Host smart-422c5dfa-c174-43d0-a450-25b2a728a0d0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324850055 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_bit_bash.2324850055
Directory /workspace/3.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.2756168293
Short name T800
Test name
Test status
Simulation time 20140504 ps
CPU time 0.89 seconds
Started Jun 27 06:09:27 PM PDT 24
Finished Jun 27 06:09:29 PM PDT 24
Peak memory 199088 kb
Host smart-5bfb6f94-b0b0-454c-bead-03d88fa163d6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756168293 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_hw_reset.2756168293
Directory /workspace/3.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.84942266
Short name T732
Test name
Test status
Simulation time 442871050343 ps
CPU time 1078.7 seconds
Started Jun 27 06:09:27 PM PDT 24
Finished Jun 27 06:27:27 PM PDT 24
Peak memory 216556 kb
Host smart-a767b6f5-ac7b-4a91-8733-876d4cdf66da
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84942266 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.hmac_csr_mem_rw_with_rand_reset.84942266
Directory /workspace/3.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_rw.1768521145
Short name T111
Test name
Test status
Simulation time 15432976 ps
CPU time 0.78 seconds
Started Jun 27 06:09:27 PM PDT 24
Finished Jun 27 06:09:29 PM PDT 24
Peak memory 198948 kb
Host smart-8083dde4-faf4-47df-805c-36e0e7f9ca35
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768521145 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_rw.1768521145
Directory /workspace/3.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_intr_test.902317827
Short name T738
Test name
Test status
Simulation time 70533486 ps
CPU time 0.65 seconds
Started Jun 27 06:09:29 PM PDT 24
Finished Jun 27 06:09:32 PM PDT 24
Peak memory 194640 kb
Host smart-c9af3ba9-04f9-4a4d-9363-4f0520e3f299
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902317827 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_intr_test.902317827
Directory /workspace/3.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.3002630989
Short name T795
Test name
Test status
Simulation time 99086260 ps
CPU time 1.81 seconds
Started Jun 27 06:09:28 PM PDT 24
Finished Jun 27 06:09:31 PM PDT 24
Peak memory 199628 kb
Host smart-e720ab6f-9da8-426a-b164-441226568093
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002630989 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_same_csr
_outstanding.3002630989
Directory /workspace/3.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_errors.3470086627
Short name T714
Test name
Test status
Simulation time 885411443 ps
CPU time 4.03 seconds
Started Jun 27 06:09:29 PM PDT 24
Finished Jun 27 06:09:35 PM PDT 24
Peak memory 199756 kb
Host smart-ff92fe69-f153-4ad3-aaea-aa76ea4f1112
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470086627 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_errors.3470086627
Directory /workspace/3.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.1116494089
Short name T716
Test name
Test status
Simulation time 275700705 ps
CPU time 4.51 seconds
Started Jun 27 06:09:29 PM PDT 24
Finished Jun 27 06:09:35 PM PDT 24
Peak memory 199720 kb
Host smart-27dfd61b-b0a4-4385-9174-f452d28564e1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116494089 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_intg_err.1116494089
Directory /workspace/3.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.hmac_intr_test.1082694011
Short name T755
Test name
Test status
Simulation time 19745690 ps
CPU time 0.58 seconds
Started Jun 27 06:09:55 PM PDT 24
Finished Jun 27 06:10:00 PM PDT 24
Peak memory 194520 kb
Host smart-68afcc7c-f104-4daa-9f4d-7dc2aeb41f24
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082694011 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.hmac_intr_test.1082694011
Directory /workspace/30.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.hmac_intr_test.3882331175
Short name T776
Test name
Test status
Simulation time 39942853 ps
CPU time 0.58 seconds
Started Jun 27 06:09:55 PM PDT 24
Finished Jun 27 06:10:00 PM PDT 24
Peak memory 194516 kb
Host smart-95f38256-168a-4ae9-b9dd-178c19f3dad1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882331175 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.hmac_intr_test.3882331175
Directory /workspace/31.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.hmac_intr_test.3972521153
Short name T739
Test name
Test status
Simulation time 26635041 ps
CPU time 0.58 seconds
Started Jun 27 06:09:58 PM PDT 24
Finished Jun 27 06:10:02 PM PDT 24
Peak memory 194564 kb
Host smart-e2a1387c-e81d-45f8-94b7-21bf5be3f4cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972521153 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.hmac_intr_test.3972521153
Directory /workspace/32.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.hmac_intr_test.4067111896
Short name T77
Test name
Test status
Simulation time 36563895 ps
CPU time 0.62 seconds
Started Jun 27 06:09:57 PM PDT 24
Finished Jun 27 06:10:02 PM PDT 24
Peak memory 194528 kb
Host smart-edc8dcea-efe1-42d4-805c-f30ced0e4450
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067111896 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.hmac_intr_test.4067111896
Directory /workspace/33.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.hmac_intr_test.3225549867
Short name T778
Test name
Test status
Simulation time 63232003 ps
CPU time 0.62 seconds
Started Jun 27 06:09:56 PM PDT 24
Finished Jun 27 06:10:01 PM PDT 24
Peak memory 194572 kb
Host smart-8b14f907-f392-4966-b186-c78d1bfc3901
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225549867 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.hmac_intr_test.3225549867
Directory /workspace/34.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.hmac_intr_test.1830952717
Short name T713
Test name
Test status
Simulation time 18377225 ps
CPU time 0.63 seconds
Started Jun 27 06:09:55 PM PDT 24
Finished Jun 27 06:09:59 PM PDT 24
Peak memory 194464 kb
Host smart-261d959c-d8e5-4397-95c4-dec9e57406ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830952717 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.hmac_intr_test.1830952717
Directory /workspace/35.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.hmac_intr_test.177418870
Short name T779
Test name
Test status
Simulation time 28994597 ps
CPU time 0.61 seconds
Started Jun 27 06:10:01 PM PDT 24
Finished Jun 27 06:10:05 PM PDT 24
Peak memory 194596 kb
Host smart-1351140a-7bf8-4faf-8c9d-e96db7b7be9a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177418870 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.hmac_intr_test.177418870
Directory /workspace/36.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.hmac_intr_test.60236563
Short name T717
Test name
Test status
Simulation time 25936202 ps
CPU time 0.66 seconds
Started Jun 27 06:09:58 PM PDT 24
Finished Jun 27 06:10:02 PM PDT 24
Peak memory 194584 kb
Host smart-4902e17f-b681-4a2d-aa71-2690f8da7665
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60236563 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.hmac_intr_test.60236563
Directory /workspace/37.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.hmac_intr_test.626403789
Short name T752
Test name
Test status
Simulation time 65923286 ps
CPU time 0.67 seconds
Started Jun 27 06:09:55 PM PDT 24
Finished Jun 27 06:10:00 PM PDT 24
Peak memory 194484 kb
Host smart-9fa4d574-b3e0-4389-b150-a6f7083e9023
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626403789 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.hmac_intr_test.626403789
Directory /workspace/38.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.hmac_intr_test.337393680
Short name T702
Test name
Test status
Simulation time 17724288 ps
CPU time 0.59 seconds
Started Jun 27 06:09:58 PM PDT 24
Finished Jun 27 06:10:02 PM PDT 24
Peak memory 194500 kb
Host smart-cdd1cc89-e4a2-40a3-8bfc-21e6ac8a5054
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337393680 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.hmac_intr_test.337393680
Directory /workspace/39.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.3890068675
Short name T101
Test name
Test status
Simulation time 610076454 ps
CPU time 3.41 seconds
Started Jun 27 06:09:31 PM PDT 24
Finished Jun 27 06:09:37 PM PDT 24
Peak memory 199588 kb
Host smart-888c7794-95d5-4d83-9d8e-ac556876bc20
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890068675 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_aliasing.3890068675
Directory /workspace/4.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.2924998562
Short name T724
Test name
Test status
Simulation time 562225353 ps
CPU time 6 seconds
Started Jun 27 06:09:26 PM PDT 24
Finished Jun 27 06:09:32 PM PDT 24
Peak memory 199560 kb
Host smart-776f13ad-ec5e-4043-b4cd-c7b30e3cdbb2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924998562 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_bit_bash.2924998562
Directory /workspace/4.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.2513684613
Short name T97
Test name
Test status
Simulation time 59942554 ps
CPU time 0.75 seconds
Started Jun 27 06:09:28 PM PDT 24
Finished Jun 27 06:09:31 PM PDT 24
Peak memory 197556 kb
Host smart-7e520c65-a4d7-4e07-8b82-0bce9cccc67b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513684613 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_hw_reset.2513684613
Directory /workspace/4.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.102459126
Short name T798
Test name
Test status
Simulation time 93076696 ps
CPU time 2.8 seconds
Started Jun 27 06:09:30 PM PDT 24
Finished Jun 27 06:09:36 PM PDT 24
Peak memory 199792 kb
Host smart-b5e41839-ea28-4ce1-a85b-3eb72b75c160
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102459126 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.hmac_csr_mem_rw_with_rand_reset.102459126
Directory /workspace/4.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_rw.3683218311
Short name T740
Test name
Test status
Simulation time 28898308 ps
CPU time 0.88 seconds
Started Jun 27 06:09:29 PM PDT 24
Finished Jun 27 06:09:32 PM PDT 24
Peak memory 198872 kb
Host smart-09069c12-8f0f-4583-b5bc-9a3137a17a48
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683218311 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_rw.3683218311
Directory /workspace/4.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_intr_test.792281035
Short name T810
Test name
Test status
Simulation time 21937415 ps
CPU time 0.54 seconds
Started Jun 27 06:09:26 PM PDT 24
Finished Jun 27 06:09:27 PM PDT 24
Peak memory 194520 kb
Host smart-2f4d9588-2b4d-46c5-8df4-55934f39f06f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792281035 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_intr_test.792281035
Directory /workspace/4.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.2516630004
Short name T116
Test name
Test status
Simulation time 116893452 ps
CPU time 1.6 seconds
Started Jun 27 06:09:29 PM PDT 24
Finished Jun 27 06:09:33 PM PDT 24
Peak memory 199700 kb
Host smart-4b934c5d-307f-4f57-9558-dbadb0243b3b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516630004 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_same_csr
_outstanding.2516630004
Directory /workspace/4.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_errors.4136470703
Short name T62
Test name
Test status
Simulation time 333753788 ps
CPU time 3.71 seconds
Started Jun 27 06:09:29 PM PDT 24
Finished Jun 27 06:09:36 PM PDT 24
Peak memory 199764 kb
Host smart-a9908a5e-2910-4327-8c4f-7469c001a4ab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136470703 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_errors.4136470703
Directory /workspace/4.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.hmac_intr_test.1730203962
Short name T804
Test name
Test status
Simulation time 62705326 ps
CPU time 0.63 seconds
Started Jun 27 06:09:55 PM PDT 24
Finished Jun 27 06:10:00 PM PDT 24
Peak memory 194484 kb
Host smart-38173838-bf9c-4135-9262-c1f5b3e9241b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730203962 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.hmac_intr_test.1730203962
Directory /workspace/40.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.hmac_intr_test.2570266861
Short name T751
Test name
Test status
Simulation time 32686497 ps
CPU time 0.59 seconds
Started Jun 27 06:09:56 PM PDT 24
Finished Jun 27 06:10:01 PM PDT 24
Peak memory 194520 kb
Host smart-f2fbf7a8-531a-4ce4-a91d-6297b1249d15
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570266861 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.hmac_intr_test.2570266861
Directory /workspace/41.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.hmac_intr_test.195834065
Short name T703
Test name
Test status
Simulation time 24278395 ps
CPU time 0.6 seconds
Started Jun 27 06:09:57 PM PDT 24
Finished Jun 27 06:10:02 PM PDT 24
Peak memory 194608 kb
Host smart-38ae51a9-a0e9-43ab-bf4c-9a49d92723db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195834065 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.hmac_intr_test.195834065
Directory /workspace/42.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.hmac_intr_test.829142657
Short name T729
Test name
Test status
Simulation time 16242726 ps
CPU time 0.64 seconds
Started Jun 27 06:09:55 PM PDT 24
Finished Jun 27 06:10:00 PM PDT 24
Peak memory 194500 kb
Host smart-e6d5dbe1-329f-48d9-a0e7-53f4d70657b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829142657 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.hmac_intr_test.829142657
Directory /workspace/43.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.hmac_intr_test.319806783
Short name T771
Test name
Test status
Simulation time 16167074 ps
CPU time 0.66 seconds
Started Jun 27 06:09:56 PM PDT 24
Finished Jun 27 06:10:01 PM PDT 24
Peak memory 194548 kb
Host smart-4f2c8e79-9499-4ea9-96fc-9df702e46981
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319806783 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.hmac_intr_test.319806783
Directory /workspace/44.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.hmac_intr_test.654266491
Short name T764
Test name
Test status
Simulation time 22567756 ps
CPU time 0.59 seconds
Started Jun 27 06:10:00 PM PDT 24
Finished Jun 27 06:10:04 PM PDT 24
Peak memory 194544 kb
Host smart-bd290056-69c5-4413-9f1c-4f59c6d8139f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654266491 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.hmac_intr_test.654266491
Directory /workspace/45.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.hmac_intr_test.1855346568
Short name T704
Test name
Test status
Simulation time 46692021 ps
CPU time 0.6 seconds
Started Jun 27 06:09:54 PM PDT 24
Finished Jun 27 06:09:59 PM PDT 24
Peak memory 194488 kb
Host smart-234ffcfb-6370-4b74-a7a7-1bdfa8285816
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855346568 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.hmac_intr_test.1855346568
Directory /workspace/46.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.hmac_intr_test.3709695721
Short name T793
Test name
Test status
Simulation time 15783341 ps
CPU time 0.61 seconds
Started Jun 27 06:09:55 PM PDT 24
Finished Jun 27 06:09:59 PM PDT 24
Peak memory 194480 kb
Host smart-1f1e859e-d193-4b01-a5c1-458e51af5e9b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709695721 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.hmac_intr_test.3709695721
Directory /workspace/47.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.hmac_intr_test.2743439900
Short name T797
Test name
Test status
Simulation time 57797302 ps
CPU time 0.59 seconds
Started Jun 27 06:09:55 PM PDT 24
Finished Jun 27 06:10:00 PM PDT 24
Peak memory 194524 kb
Host smart-30642ffc-efe1-489d-88f0-a8717a29bd74
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743439900 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.hmac_intr_test.2743439900
Directory /workspace/48.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.hmac_intr_test.2476406573
Short name T812
Test name
Test status
Simulation time 15725651 ps
CPU time 0.62 seconds
Started Jun 27 06:09:54 PM PDT 24
Finished Jun 27 06:09:59 PM PDT 24
Peak memory 194704 kb
Host smart-79459419-e2df-4616-a03c-9d44e36a7f3b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476406573 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.hmac_intr_test.2476406573
Directory /workspace/49.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.2809731102
Short name T815
Test name
Test status
Simulation time 82552201 ps
CPU time 1.33 seconds
Started Jun 27 06:09:44 PM PDT 24
Finished Jun 27 06:09:53 PM PDT 24
Peak memory 199544 kb
Host smart-587a4458-4850-4128-b46e-237bbc5ad07c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809731102 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.hmac_csr_mem_rw_with_rand_reset.2809731102
Directory /workspace/5.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_rw.2311574877
Short name T712
Test name
Test status
Simulation time 105421677 ps
CPU time 0.97 seconds
Started Jun 27 06:09:40 PM PDT 24
Finished Jun 27 06:09:43 PM PDT 24
Peak memory 199404 kb
Host smart-e830e69c-9b09-47b2-a1c3-188904e5b349
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311574877 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_rw.2311574877
Directory /workspace/5.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_intr_test.3349052213
Short name T741
Test name
Test status
Simulation time 22731282 ps
CPU time 0.61 seconds
Started Jun 27 06:09:47 PM PDT 24
Finished Jun 27 06:09:55 PM PDT 24
Peak memory 194644 kb
Host smart-3d5df3fa-70ad-4ff8-ab3b-8ee8fdd12b4d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349052213 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_intr_test.3349052213
Directory /workspace/5.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.2150697896
Short name T746
Test name
Test status
Simulation time 351460426 ps
CPU time 1.88 seconds
Started Jun 27 06:09:43 PM PDT 24
Finished Jun 27 06:09:50 PM PDT 24
Peak memory 199776 kb
Host smart-81bc7ca5-2c6c-4aea-b835-fb5059176888
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150697896 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_same_csr
_outstanding.2150697896
Directory /workspace/5.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_errors.2769101694
Short name T756
Test name
Test status
Simulation time 81821882 ps
CPU time 1.96 seconds
Started Jun 27 06:09:31 PM PDT 24
Finished Jun 27 06:09:36 PM PDT 24
Peak memory 199688 kb
Host smart-9308cddc-a52e-4c5a-9416-0ffe65f1467e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769101694 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_errors.2769101694
Directory /workspace/5.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.853449024
Short name T141
Test name
Test status
Simulation time 402176931 ps
CPU time 1.74 seconds
Started Jun 27 06:09:39 PM PDT 24
Finished Jun 27 06:09:42 PM PDT 24
Peak memory 199772 kb
Host smart-e5742e95-0a02-4e66-b30c-78b8fa4a15c0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853449024 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_intg_err.853449024
Directory /workspace/5.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.1249785635
Short name T730
Test name
Test status
Simulation time 264491109098 ps
CPU time 617.23 seconds
Started Jun 27 06:09:42 PM PDT 24
Finished Jun 27 06:20:04 PM PDT 24
Peak memory 216256 kb
Host smart-2cb55558-bde4-433e-919e-bbea2b872ef1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249785635 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.hmac_csr_mem_rw_with_rand_reset.1249785635
Directory /workspace/6.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_rw.1544137517
Short name T106
Test name
Test status
Simulation time 69705571 ps
CPU time 0.92 seconds
Started Jun 27 06:09:39 PM PDT 24
Finished Jun 27 06:09:42 PM PDT 24
Peak memory 199216 kb
Host smart-ec31d3fc-6d64-4dbc-ab50-892bf9d8c38e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544137517 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_rw.1544137517
Directory /workspace/6.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_intr_test.4075651724
Short name T707
Test name
Test status
Simulation time 13457521 ps
CPU time 0.59 seconds
Started Jun 27 06:09:44 PM PDT 24
Finished Jun 27 06:09:52 PM PDT 24
Peak memory 194464 kb
Host smart-8f4bee3a-1978-4681-b60b-b1845d5d8476
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075651724 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_intr_test.4075651724
Directory /workspace/6.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.838104860
Short name T770
Test name
Test status
Simulation time 296284353 ps
CPU time 1.69 seconds
Started Jun 27 06:09:40 PM PDT 24
Finished Jun 27 06:09:45 PM PDT 24
Peak memory 199648 kb
Host smart-05774d6c-0d97-4735-bbdb-b7ae0fc1efef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838104860 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_same_csr_
outstanding.838104860
Directory /workspace/6.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_errors.2578522807
Short name T775
Test name
Test status
Simulation time 209053699 ps
CPU time 1.44 seconds
Started Jun 27 06:09:43 PM PDT 24
Finished Jun 27 06:09:50 PM PDT 24
Peak memory 199660 kb
Host smart-bc065ff6-78b3-4f56-9722-ff634657550d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578522807 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_errors.2578522807
Directory /workspace/6.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.2194173506
Short name T789
Test name
Test status
Simulation time 500081291 ps
CPU time 3.83 seconds
Started Jun 27 06:09:39 PM PDT 24
Finished Jun 27 06:09:44 PM PDT 24
Peak memory 199656 kb
Host smart-9215f009-2737-4761-a3cc-0630a0b1ed71
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194173506 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_intg_err.2194173506
Directory /workspace/6.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.435101997
Short name T788
Test name
Test status
Simulation time 38200308 ps
CPU time 2.25 seconds
Started Jun 27 06:09:43 PM PDT 24
Finished Jun 27 06:09:51 PM PDT 24
Peak memory 199796 kb
Host smart-b8146f75-dc46-4ae2-885b-8f9630eb1aaf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435101997 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.hmac_csr_mem_rw_with_rand_reset.435101997
Directory /workspace/7.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_rw.3829062409
Short name T721
Test name
Test status
Simulation time 56398440 ps
CPU time 0.93 seconds
Started Jun 27 06:09:48 PM PDT 24
Finished Jun 27 06:09:56 PM PDT 24
Peak memory 199024 kb
Host smart-3cb73ffc-dcff-4e6a-a7f9-3acac8fd1c96
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829062409 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_rw.3829062409
Directory /workspace/7.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_intr_test.2002541483
Short name T807
Test name
Test status
Simulation time 23296698 ps
CPU time 0.57 seconds
Started Jun 27 06:09:47 PM PDT 24
Finished Jun 27 06:09:55 PM PDT 24
Peak memory 194520 kb
Host smart-4f6a7eea-b08b-46f1-ae99-50acd5fb17b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002541483 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_intr_test.2002541483
Directory /workspace/7.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.2695534711
Short name T734
Test name
Test status
Simulation time 217789412 ps
CPU time 1.08 seconds
Started Jun 27 06:09:39 PM PDT 24
Finished Jun 27 06:09:41 PM PDT 24
Peak memory 199736 kb
Host smart-c707c63b-4d65-44d3-83b6-bdb67639aa8f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695534711 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_same_csr
_outstanding.2695534711
Directory /workspace/7.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_errors.4272749029
Short name T719
Test name
Test status
Simulation time 243014727 ps
CPU time 1.66 seconds
Started Jun 27 06:09:43 PM PDT 24
Finished Jun 27 06:09:51 PM PDT 24
Peak memory 199720 kb
Host smart-2d5fa0b7-7c24-4b4f-bb61-fd74d53dc8af
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272749029 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_errors.4272749029
Directory /workspace/7.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.3277717603
Short name T63
Test name
Test status
Simulation time 157294274 ps
CPU time 1.32 seconds
Started Jun 27 06:09:41 PM PDT 24
Finished Jun 27 06:09:45 PM PDT 24
Peak memory 199760 kb
Host smart-d09921b3-b744-47ce-bec4-6517032f335c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277717603 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.hmac_csr_mem_rw_with_rand_reset.3277717603
Directory /workspace/8.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_rw.2968262068
Short name T780
Test name
Test status
Simulation time 187729037 ps
CPU time 0.83 seconds
Started Jun 27 06:09:42 PM PDT 24
Finished Jun 27 06:09:47 PM PDT 24
Peak memory 199448 kb
Host smart-c64cf410-c9f3-4504-9829-639aaec7128f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968262068 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_rw.2968262068
Directory /workspace/8.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_intr_test.1953343692
Short name T733
Test name
Test status
Simulation time 30181370 ps
CPU time 0.59 seconds
Started Jun 27 06:09:42 PM PDT 24
Finished Jun 27 06:09:47 PM PDT 24
Peak memory 194540 kb
Host smart-93d8dcab-acf7-4342-9aa8-327680c1bf87
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953343692 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_intr_test.1953343692
Directory /workspace/8.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.3808660773
Short name T114
Test name
Test status
Simulation time 105894419 ps
CPU time 2.24 seconds
Started Jun 27 06:09:43 PM PDT 24
Finished Jun 27 06:09:50 PM PDT 24
Peak memory 199728 kb
Host smart-5c95bce1-22bd-49c7-9056-1aa6183e65a5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808660773 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_same_csr
_outstanding.3808660773
Directory /workspace/8.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_errors.4149407652
Short name T783
Test name
Test status
Simulation time 197918140 ps
CPU time 2.77 seconds
Started Jun 27 06:09:41 PM PDT 24
Finished Jun 27 06:09:46 PM PDT 24
Peak memory 199676 kb
Host smart-35bdc269-48d1-4c6d-bcc4-ce1330954d1f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149407652 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_errors.4149407652
Directory /workspace/8.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.3151280373
Short name T142
Test name
Test status
Simulation time 56315530 ps
CPU time 1.7 seconds
Started Jun 27 06:09:44 PM PDT 24
Finished Jun 27 06:09:53 PM PDT 24
Peak memory 199772 kb
Host smart-6f27e699-59c4-4911-931c-f5fea7d27a2e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151280373 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_intg_err.3151280373
Directory /workspace/8.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.2705232179
Short name T726
Test name
Test status
Simulation time 89714578 ps
CPU time 3.1 seconds
Started Jun 27 06:09:44 PM PDT 24
Finished Jun 27 06:09:53 PM PDT 24
Peak memory 208000 kb
Host smart-b7df6cb4-c48c-4b4e-8b11-6323ad662dc7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705232179 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.hmac_csr_mem_rw_with_rand_reset.2705232179
Directory /workspace/9.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_rw.3299412335
Short name T117
Test name
Test status
Simulation time 19150688 ps
CPU time 0.72 seconds
Started Jun 27 06:09:44 PM PDT 24
Finished Jun 27 06:09:52 PM PDT 24
Peak memory 197484 kb
Host smart-0ca819fb-99ce-4eb6-acf2-c05f83a347c6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299412335 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_rw.3299412335
Directory /workspace/9.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_intr_test.2686142799
Short name T774
Test name
Test status
Simulation time 13933746 ps
CPU time 0.59 seconds
Started Jun 27 06:09:47 PM PDT 24
Finished Jun 27 06:09:55 PM PDT 24
Peak memory 194448 kb
Host smart-f610a057-e538-4ccd-9598-2c04f902fd32
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686142799 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_intr_test.2686142799
Directory /workspace/9.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.333480852
Short name T749
Test name
Test status
Simulation time 115580868 ps
CPU time 2.53 seconds
Started Jun 27 06:09:42 PM PDT 24
Finished Jun 27 06:09:49 PM PDT 24
Peak memory 199432 kb
Host smart-c461101d-f870-4275-9129-6c121d1404b5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333480852 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_same_csr_
outstanding.333480852
Directory /workspace/9.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_errors.2420670477
Short name T735
Test name
Test status
Simulation time 87393144 ps
CPU time 2.15 seconds
Started Jun 27 06:09:41 PM PDT 24
Finished Jun 27 06:09:46 PM PDT 24
Peak memory 199716 kb
Host smart-408a1ad9-a280-4df3-b064-b8e24085c462
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420670477 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_errors.2420670477
Directory /workspace/9.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.2523047077
Short name T138
Test name
Test status
Simulation time 191125717 ps
CPU time 3.32 seconds
Started Jun 27 06:09:45 PM PDT 24
Finished Jun 27 06:09:56 PM PDT 24
Peak memory 199656 kb
Host smart-e899754d-e1e7-49da-aef7-2c66a97bb4d9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523047077 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_intg_err.2523047077
Directory /workspace/9.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.hmac_back_pressure.4053697951
Short name T333
Test name
Test status
Simulation time 1798925615 ps
CPU time 18.25 seconds
Started Jun 27 06:46:21 PM PDT 24
Finished Jun 27 06:46:46 PM PDT 24
Peak memory 199932 kb
Host smart-52f74605-33b1-49d7-9414-8ca7ad013b30
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4053697951 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_back_pressure.4053697951
Directory /workspace/0.hmac_back_pressure/latest

Test location /workspace/coverage/default/0.hmac_burst_wr.1936378018
Short name T32
Test name
Test status
Simulation time 1053044662 ps
CPU time 57.12 seconds
Started Jun 27 06:46:22 PM PDT 24
Finished Jun 27 06:47:27 PM PDT 24
Peak memory 199924 kb
Host smart-089a5397-6582-4f87-abfe-ac44d3739a49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936378018 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_burst_wr.1936378018
Directory /workspace/0.hmac_burst_wr/latest

Test location /workspace/coverage/default/0.hmac_datapath_stress.3419985122
Short name T387
Test name
Test status
Simulation time 4663909614 ps
CPU time 346.54 seconds
Started Jun 27 06:46:22 PM PDT 24
Finished Jun 27 06:52:15 PM PDT 24
Peak memory 701244 kb
Host smart-97fca1b1-1e0a-4e29-99b8-8214baf62d02
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3419985122 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_datapath_stress.3419985122
Directory /workspace/0.hmac_datapath_stress/latest

Test location /workspace/coverage/default/0.hmac_error.520883539
Short name T681
Test name
Test status
Simulation time 8615948526 ps
CPU time 147.56 seconds
Started Jun 27 06:46:26 PM PDT 24
Finished Jun 27 06:49:06 PM PDT 24
Peak memory 199992 kb
Host smart-b8d92548-8ab9-4a2d-a1cc-f9c3b6495ab2
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520883539 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_error.520883539
Directory /workspace/0.hmac_error/latest

Test location /workspace/coverage/default/0.hmac_long_msg.3490748466
Short name T516
Test name
Test status
Simulation time 5825136263 ps
CPU time 48.53 seconds
Started Jun 27 06:46:33 PM PDT 24
Finished Jun 27 06:47:35 PM PDT 24
Peak memory 200156 kb
Host smart-b1d82ab2-a888-44d7-8d16-fb3e947ceb53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490748466 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_long_msg.3490748466
Directory /workspace/0.hmac_long_msg/latest

Test location /workspace/coverage/default/0.hmac_smoke.1757971663
Short name T545
Test name
Test status
Simulation time 378114573 ps
CPU time 4.59 seconds
Started Jun 27 06:46:20 PM PDT 24
Finished Jun 27 06:46:31 PM PDT 24
Peak memory 199932 kb
Host smart-d909de51-a3b5-4466-875a-9f2b6779c9a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757971663 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_smoke.1757971663
Directory /workspace/0.hmac_smoke/latest

Test location /workspace/coverage/default/0.hmac_stress_all.960898661
Short name T227
Test name
Test status
Simulation time 295022495119 ps
CPU time 4042.81 seconds
Started Jun 27 06:46:27 PM PDT 24
Finished Jun 27 07:54:01 PM PDT 24
Peak memory 216240 kb
Host smart-04d8408c-29d6-454b-8eab-9678b1aa9f2c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960898661 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all.960898661
Directory /workspace/0.hmac_stress_all/latest

Test location /workspace/coverage/default/0.hmac_test_hmac_vectors.3980613700
Short name T369
Test name
Test status
Simulation time 34864267 ps
CPU time 1.33 seconds
Started Jun 27 06:46:24 PM PDT 24
Finished Jun 27 06:46:34 PM PDT 24
Peak memory 199932 kb
Host smart-927463b2-a12f-4a4a-a477-a164dd475423
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980613700 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac_vectors.3980613700
Directory /workspace/0.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha256_vectors.1829452407
Short name T420
Test name
Test status
Simulation time 100516590822 ps
CPU time 466.3 seconds
Started Jun 27 06:46:22 PM PDT 24
Finished Jun 27 06:54:16 PM PDT 24
Peak memory 200012 kb
Host smart-8507be22-c383-45b2-9931-89425bfded62
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1829452407 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha256_vectors.1829452407
Directory /workspace/0.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha384_vectors.815332161
Short name T566
Test name
Test status
Simulation time 693840395798 ps
CPU time 2092.08 seconds
Started Jun 27 06:46:23 PM PDT 24
Finished Jun 27 07:21:22 PM PDT 24
Peak memory 216040 kb
Host smart-00b9407f-9a54-47e2-806f-c6e4142b567c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=815332161 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha384_vectors.815332161
Directory /workspace/0.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/0.hmac_wipe_secret.1738256491
Short name T264
Test name
Test status
Simulation time 13440452323 ps
CPU time 50.95 seconds
Started Jun 27 06:46:22 PM PDT 24
Finished Jun 27 06:47:20 PM PDT 24
Peak memory 199996 kb
Host smart-587a18f0-43f5-4643-9be3-9a1d950be12a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738256491 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_wipe_secret.1738256491
Directory /workspace/0.hmac_wipe_secret/latest

Test location /workspace/coverage/default/1.hmac_alert_test.1069493891
Short name T634
Test name
Test status
Simulation time 112944894 ps
CPU time 0.59 seconds
Started Jun 27 06:46:27 PM PDT 24
Finished Jun 27 06:46:40 PM PDT 24
Peak memory 195948 kb
Host smart-a8b14cab-ef92-413e-ba12-0caa98428f16
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069493891 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_alert_test.1069493891
Directory /workspace/1.hmac_alert_test/latest

Test location /workspace/coverage/default/1.hmac_back_pressure.3383533826
Short name T421
Test name
Test status
Simulation time 2210297923 ps
CPU time 53.07 seconds
Started Jun 27 06:46:26 PM PDT 24
Finished Jun 27 06:47:31 PM PDT 24
Peak memory 200032 kb
Host smart-205e6fa2-e60a-49b6-90f7-ed64bfb6e535
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3383533826 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_back_pressure.3383533826
Directory /workspace/1.hmac_back_pressure/latest

Test location /workspace/coverage/default/1.hmac_burst_wr.1224295754
Short name T606
Test name
Test status
Simulation time 1394025981 ps
CPU time 13.21 seconds
Started Jun 27 06:46:23 PM PDT 24
Finished Jun 27 06:46:44 PM PDT 24
Peak memory 200008 kb
Host smart-8b115345-8e50-4ef0-931d-fd946caed52c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224295754 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_burst_wr.1224295754
Directory /workspace/1.hmac_burst_wr/latest

Test location /workspace/coverage/default/1.hmac_datapath_stress.1767479160
Short name T517
Test name
Test status
Simulation time 6128679345 ps
CPU time 822.18 seconds
Started Jun 27 06:46:24 PM PDT 24
Finished Jun 27 07:00:16 PM PDT 24
Peak memory 726076 kb
Host smart-24a643e8-f4bf-4f9b-9acf-56aceb3a32c5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1767479160 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_datapath_stress.1767479160
Directory /workspace/1.hmac_datapath_stress/latest

Test location /workspace/coverage/default/1.hmac_error.1949519720
Short name T472
Test name
Test status
Simulation time 71249196877 ps
CPU time 128.86 seconds
Started Jun 27 06:46:23 PM PDT 24
Finished Jun 27 06:48:40 PM PDT 24
Peak memory 200016 kb
Host smart-de2c8621-18fe-4335-8913-d360b5162cc4
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949519720 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_error.1949519720
Directory /workspace/1.hmac_error/latest

Test location /workspace/coverage/default/1.hmac_long_msg.3231160481
Short name T13
Test name
Test status
Simulation time 1802717219 ps
CPU time 106.43 seconds
Started Jun 27 06:46:26 PM PDT 24
Finished Jun 27 06:48:25 PM PDT 24
Peak memory 199956 kb
Host smart-43c30b86-e266-45ef-a24e-cec0f2cdff4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231160481 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_long_msg.3231160481
Directory /workspace/1.hmac_long_msg/latest

Test location /workspace/coverage/default/1.hmac_sec_cm.3616523324
Short name T45
Test name
Test status
Simulation time 164449045 ps
CPU time 0.82 seconds
Started Jun 27 06:46:31 PM PDT 24
Finished Jun 27 06:46:45 PM PDT 24
Peak memory 218452 kb
Host smart-ee0d11f3-00b6-4d34-b916-5a6bc8e9465c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616523324 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_sec_cm.3616523324
Directory /workspace/1.hmac_sec_cm/latest

Test location /workspace/coverage/default/1.hmac_smoke.2678350431
Short name T152
Test name
Test status
Simulation time 537090449 ps
CPU time 10.08 seconds
Started Jun 27 06:46:24 PM PDT 24
Finished Jun 27 06:46:43 PM PDT 24
Peak memory 199920 kb
Host smart-4dd01950-e0ad-4d16-b557-e6a31d5e4902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678350431 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_smoke.2678350431
Directory /workspace/1.hmac_smoke/latest

Test location /workspace/coverage/default/1.hmac_stress_all.2914222051
Short name T495
Test name
Test status
Simulation time 204249592181 ps
CPU time 2553.56 seconds
Started Jun 27 06:46:29 PM PDT 24
Finished Jun 27 07:29:16 PM PDT 24
Peak memory 465700 kb
Host smart-d31af8f2-8640-428d-bdff-af20b857ddd0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914222051 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all.2914222051
Directory /workspace/1.hmac_stress_all/latest

Test location /workspace/coverage/default/1.hmac_test_hmac_vectors.1547263784
Short name T168
Test name
Test status
Simulation time 82516587 ps
CPU time 1.44 seconds
Started Jun 27 06:46:29 PM PDT 24
Finished Jun 27 06:46:43 PM PDT 24
Peak memory 199996 kb
Host smart-afac9122-ca67-4544-a0da-7ff67bc5aa77
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547263784 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac_vectors.1547263784
Directory /workspace/1.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha256_vectors.4279707964
Short name T270
Test name
Test status
Simulation time 56359962217 ps
CPU time 456.22 seconds
Started Jun 27 06:46:18 PM PDT 24
Finished Jun 27 06:53:59 PM PDT 24
Peak memory 200012 kb
Host smart-9b79a40f-5579-40ee-a30e-28be6b4858eb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=4279707964 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha256_vectors.4279707964
Directory /workspace/1.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha384_vectors.1570304350
Short name T180
Test name
Test status
Simulation time 408961433110 ps
CPU time 1877.98 seconds
Started Jun 27 06:46:26 PM PDT 24
Finished Jun 27 07:17:56 PM PDT 24
Peak memory 216412 kb
Host smart-0f1d60bf-5bc1-4384-b78b-0b0ab6b4eafe
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1570304350 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha384_vectors.1570304350
Directory /workspace/1.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha512_vectors.3496472952
Short name T164
Test name
Test status
Simulation time 184271559906 ps
CPU time 2137.67 seconds
Started Jun 27 06:46:26 PM PDT 24
Finished Jun 27 07:22:16 PM PDT 24
Peak memory 215424 kb
Host smart-99723094-deb4-44a6-bd88-2b3f6d16e91d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3496472952 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha512_vectors.3496472952
Directory /workspace/1.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/1.hmac_wipe_secret.456234277
Short name T392
Test name
Test status
Simulation time 2589864762 ps
CPU time 60.36 seconds
Started Jun 27 06:46:25 PM PDT 24
Finished Jun 27 06:47:37 PM PDT 24
Peak memory 200044 kb
Host smart-f8fed1fe-c771-4990-9d65-9a96714f4cf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456234277 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_wipe_secret.456234277
Directory /workspace/1.hmac_wipe_secret/latest

Test location /workspace/coverage/default/10.hmac_alert_test.943753569
Short name T455
Test name
Test status
Simulation time 57338735 ps
CPU time 0.61 seconds
Started Jun 27 06:46:37 PM PDT 24
Finished Jun 27 06:46:51 PM PDT 24
Peak memory 196012 kb
Host smart-7edc5274-fced-46ef-9c3e-3fd4bf34ffe2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943753569 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_alert_test.943753569
Directory /workspace/10.hmac_alert_test/latest

Test location /workspace/coverage/default/10.hmac_back_pressure.668591054
Short name T589
Test name
Test status
Simulation time 875930162 ps
CPU time 47.85 seconds
Started Jun 27 06:46:37 PM PDT 24
Finished Jun 27 06:47:38 PM PDT 24
Peak memory 200184 kb
Host smart-c1536542-72b0-4be5-a16b-e9ccf979db80
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=668591054 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_back_pressure.668591054
Directory /workspace/10.hmac_back_pressure/latest

Test location /workspace/coverage/default/10.hmac_burst_wr.1749072654
Short name T405
Test name
Test status
Simulation time 397868391 ps
CPU time 7.72 seconds
Started Jun 27 06:46:32 PM PDT 24
Finished Jun 27 06:46:53 PM PDT 24
Peak memory 199952 kb
Host smart-5c0c6ef7-ce52-4e27-a77a-887d1636fe4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749072654 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_burst_wr.1749072654
Directory /workspace/10.hmac_burst_wr/latest

Test location /workspace/coverage/default/10.hmac_datapath_stress.477964833
Short name T192
Test name
Test status
Simulation time 4141911568 ps
CPU time 1174.83 seconds
Started Jun 27 06:46:35 PM PDT 24
Finished Jun 27 07:06:23 PM PDT 24
Peak memory 780872 kb
Host smart-7d94d8b5-6be6-469a-bc3d-5b0ba6e09005
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=477964833 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_datapath_stress.477964833
Directory /workspace/10.hmac_datapath_stress/latest

Test location /workspace/coverage/default/10.hmac_error.213666870
Short name T127
Test name
Test status
Simulation time 10591001180 ps
CPU time 39.07 seconds
Started Jun 27 06:46:31 PM PDT 24
Finished Jun 27 06:47:24 PM PDT 24
Peak memory 200004 kb
Host smart-ea9d9f51-2f99-4255-947a-c14414aa9591
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213666870 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_error.213666870
Directory /workspace/10.hmac_error/latest

Test location /workspace/coverage/default/10.hmac_long_msg.22425023
Short name T520
Test name
Test status
Simulation time 36596896564 ps
CPU time 121.16 seconds
Started Jun 27 06:46:32 PM PDT 24
Finished Jun 27 06:48:47 PM PDT 24
Peak memory 200040 kb
Host smart-d0fdd4b8-a489-4773-90e6-e6e2d5fd9b84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22425023 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_long_msg.22425023
Directory /workspace/10.hmac_long_msg/latest

Test location /workspace/coverage/default/10.hmac_stress_all.1040300105
Short name T190
Test name
Test status
Simulation time 147024890156 ps
CPU time 2540.46 seconds
Started Jun 27 06:46:37 PM PDT 24
Finished Jun 27 07:29:11 PM PDT 24
Peak memory 215460 kb
Host smart-aaca4552-f884-44e6-b685-935ef89ec341
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040300105 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.hmac_stress_all.1040300105
Directory /workspace/10.hmac_stress_all/latest

Test location /workspace/coverage/default/10.hmac_test_hmac_vectors.269420431
Short name T502
Test name
Test status
Simulation time 55259111 ps
CPU time 1.07 seconds
Started Jun 27 06:46:42 PM PDT 24
Finished Jun 27 06:46:55 PM PDT 24
Peak memory 199752 kb
Host smart-8f5448a0-3735-4fc8-8c89-b07f8437d8a9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269420431 -assert nopostpr
oc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 10.hmac_test_hmac_vectors.269420431
Directory /workspace/10.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/10.hmac_test_sha256_vectors.2688750429
Short name T263
Test name
Test status
Simulation time 214254347943 ps
CPU time 524.54 seconds
Started Jun 27 06:46:32 PM PDT 24
Finished Jun 27 06:55:30 PM PDT 24
Peak memory 200016 kb
Host smart-ae17c54b-267b-4206-82d0-aeadc29f662f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2688750429 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_test_sha256_vectors.2688750429
Directory /workspace/10.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/10.hmac_test_sha384_vectors.599343123
Short name T518
Test name
Test status
Simulation time 61535632440 ps
CPU time 1883.64 seconds
Started Jun 27 06:46:47 PM PDT 24
Finished Jun 27 07:18:22 PM PDT 24
Peak memory 215520 kb
Host smart-6a8844ff-c07b-4e9e-83e2-c953a3b8b320
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=599343123 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_test_sha384_vectors.599343123
Directory /workspace/10.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/10.hmac_test_sha512_vectors.1546419698
Short name T529
Test name
Test status
Simulation time 467997442875 ps
CPU time 1936.42 seconds
Started Jun 27 06:46:40 PM PDT 24
Finished Jun 27 07:19:09 PM PDT 24
Peak memory 215956 kb
Host smart-397f9b25-502a-4c79-a34e-7d438a53d0c7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1546419698 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_test_sha512_vectors.1546419698
Directory /workspace/10.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/10.hmac_wipe_secret.1566742950
Short name T265
Test name
Test status
Simulation time 3169521711 ps
CPU time 63.98 seconds
Started Jun 27 06:46:47 PM PDT 24
Finished Jun 27 06:48:01 PM PDT 24
Peak memory 200084 kb
Host smart-7968036c-b122-487c-bb0b-ff14261c9dc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566742950 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_wipe_secret.1566742950
Directory /workspace/10.hmac_wipe_secret/latest

Test location /workspace/coverage/default/11.hmac_alert_test.2224136088
Short name T424
Test name
Test status
Simulation time 33634988 ps
CPU time 0.63 seconds
Started Jun 27 06:46:34 PM PDT 24
Finished Jun 27 06:46:48 PM PDT 24
Peak memory 196000 kb
Host smart-3134d618-89c3-4c8f-aa44-b6f871863e9f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224136088 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_alert_test.2224136088
Directory /workspace/11.hmac_alert_test/latest

Test location /workspace/coverage/default/11.hmac_back_pressure.1428883205
Short name T663
Test name
Test status
Simulation time 522701306 ps
CPU time 24.76 seconds
Started Jun 27 06:46:47 PM PDT 24
Finished Jun 27 06:47:22 PM PDT 24
Peak memory 199960 kb
Host smart-1513d5f9-d3de-4f0b-b14d-88dd22d2af20
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1428883205 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_back_pressure.1428883205
Directory /workspace/11.hmac_back_pressure/latest

Test location /workspace/coverage/default/11.hmac_burst_wr.3523548345
Short name T374
Test name
Test status
Simulation time 12349211143 ps
CPU time 47.54 seconds
Started Jun 27 06:46:41 PM PDT 24
Finished Jun 27 06:47:41 PM PDT 24
Peak memory 200060 kb
Host smart-fa9e23c4-64ad-425c-984c-c4439b9443d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523548345 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_burst_wr.3523548345
Directory /workspace/11.hmac_burst_wr/latest

Test location /workspace/coverage/default/11.hmac_datapath_stress.2227425901
Short name T623
Test name
Test status
Simulation time 8198197683 ps
CPU time 465.47 seconds
Started Jun 27 06:46:36 PM PDT 24
Finished Jun 27 06:54:35 PM PDT 24
Peak memory 598748 kb
Host smart-63b03c64-fd91-48c1-bad5-053fead2c21d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2227425901 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_datapath_stress.2227425901
Directory /workspace/11.hmac_datapath_stress/latest

Test location /workspace/coverage/default/11.hmac_error.3822440722
Short name T289
Test name
Test status
Simulation time 2089324623 ps
CPU time 19.34 seconds
Started Jun 27 06:46:42 PM PDT 24
Finished Jun 27 06:47:13 PM PDT 24
Peak memory 199836 kb
Host smart-892dc46b-491c-4318-9240-b3959a4469ea
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822440722 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_error.3822440722
Directory /workspace/11.hmac_error/latest

Test location /workspace/coverage/default/11.hmac_smoke.3220495798
Short name T335
Test name
Test status
Simulation time 1180462395 ps
CPU time 8.56 seconds
Started Jun 27 06:46:31 PM PDT 24
Finished Jun 27 06:46:53 PM PDT 24
Peak memory 199976 kb
Host smart-c118b130-ed5b-407c-9f55-56a80e666b22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220495798 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_smoke.3220495798
Directory /workspace/11.hmac_smoke/latest

Test location /workspace/coverage/default/11.hmac_stress_all.3593166197
Short name T71
Test name
Test status
Simulation time 752975222906 ps
CPU time 2317.23 seconds
Started Jun 27 06:46:35 PM PDT 24
Finished Jun 27 07:25:26 PM PDT 24
Peak memory 208220 kb
Host smart-38ca67d3-735a-4493-927b-96c5fd3bab13
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593166197 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.hmac_stress_all.3593166197
Directory /workspace/11.hmac_stress_all/latest

Test location /workspace/coverage/default/11.hmac_test_hmac_vectors.2534448510
Short name T483
Test name
Test status
Simulation time 93098625 ps
CPU time 1.04 seconds
Started Jun 27 06:46:48 PM PDT 24
Finished Jun 27 06:46:59 PM PDT 24
Peak memory 199712 kb
Host smart-26348948-5ad7-4361-9392-e079e94aacd9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534448510 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 11.hmac_test_hmac_vectors.2534448510
Directory /workspace/11.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/11.hmac_test_sha256_vectors.737486851
Short name T658
Test name
Test status
Simulation time 114997058485 ps
CPU time 521.78 seconds
Started Jun 27 06:46:43 PM PDT 24
Finished Jun 27 06:55:37 PM PDT 24
Peak memory 200028 kb
Host smart-16c0b44f-ac44-4f0b-80a4-7dc4e003792b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=737486851 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_test_sha256_vectors.737486851
Directory /workspace/11.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/11.hmac_test_sha512_vectors.3843280730
Short name T435
Test name
Test status
Simulation time 269627360479 ps
CPU time 1987.36 seconds
Started Jun 27 06:46:37 PM PDT 24
Finished Jun 27 07:19:58 PM PDT 24
Peak memory 215732 kb
Host smart-b53ca63e-d22b-4eef-bd31-6b1b393ce7b3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3843280730 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_test_sha512_vectors.3843280730
Directory /workspace/11.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/11.hmac_wipe_secret.1263967059
Short name T676
Test name
Test status
Simulation time 1242066158 ps
CPU time 17.58 seconds
Started Jun 27 06:46:31 PM PDT 24
Finished Jun 27 06:47:02 PM PDT 24
Peak memory 199960 kb
Host smart-bdeaa211-b62d-4beb-9217-a54864f9207c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263967059 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_wipe_secret.1263967059
Directory /workspace/11.hmac_wipe_secret/latest

Test location /workspace/coverage/default/12.hmac_alert_test.713286345
Short name T614
Test name
Test status
Simulation time 111703054 ps
CPU time 0.58 seconds
Started Jun 27 06:46:42 PM PDT 24
Finished Jun 27 06:46:55 PM PDT 24
Peak memory 196012 kb
Host smart-1662ffc1-81e9-46d2-8113-59ef6ab819ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713286345 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_alert_test.713286345
Directory /workspace/12.hmac_alert_test/latest

Test location /workspace/coverage/default/12.hmac_back_pressure.2722840181
Short name T568
Test name
Test status
Simulation time 418980201 ps
CPU time 11.7 seconds
Started Jun 27 06:46:33 PM PDT 24
Finished Jun 27 06:46:58 PM PDT 24
Peak memory 199984 kb
Host smart-cd729858-97a7-46ec-a0c1-e305bd143d7f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2722840181 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_back_pressure.2722840181
Directory /workspace/12.hmac_back_pressure/latest

Test location /workspace/coverage/default/12.hmac_burst_wr.1133771332
Short name T492
Test name
Test status
Simulation time 644252099 ps
CPU time 33.43 seconds
Started Jun 27 06:46:48 PM PDT 24
Finished Jun 27 06:47:32 PM PDT 24
Peak memory 199964 kb
Host smart-1202d67a-fc45-416b-86a6-3fe5d3a3211e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1133771332 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_burst_wr.1133771332
Directory /workspace/12.hmac_burst_wr/latest

Test location /workspace/coverage/default/12.hmac_datapath_stress.4256570996
Short name T232
Test name
Test status
Simulation time 481152614 ps
CPU time 77.89 seconds
Started Jun 27 06:46:32 PM PDT 24
Finished Jun 27 06:48:03 PM PDT 24
Peak memory 356340 kb
Host smart-91d51225-b11f-49b1-906f-db411a650313
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4256570996 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_datapath_stress.4256570996
Directory /workspace/12.hmac_datapath_stress/latest

Test location /workspace/coverage/default/12.hmac_error.3808907062
Short name T582
Test name
Test status
Simulation time 4811324651 ps
CPU time 129.67 seconds
Started Jun 27 06:46:50 PM PDT 24
Finished Jun 27 06:49:09 PM PDT 24
Peak memory 199964 kb
Host smart-d878c6d8-a55d-4abf-b4e5-b2b20cc43134
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808907062 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_error.3808907062
Directory /workspace/12.hmac_error/latest

Test location /workspace/coverage/default/12.hmac_long_msg.3490649423
Short name T410
Test name
Test status
Simulation time 5242457111 ps
CPU time 78.77 seconds
Started Jun 27 06:46:30 PM PDT 24
Finished Jun 27 06:48:02 PM PDT 24
Peak memory 200040 kb
Host smart-ccedbc12-4935-4db4-83a1-101096dcefe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490649423 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_long_msg.3490649423
Directory /workspace/12.hmac_long_msg/latest

Test location /workspace/coverage/default/12.hmac_smoke.855178413
Short name T205
Test name
Test status
Simulation time 140958016 ps
CPU time 6.84 seconds
Started Jun 27 06:46:44 PM PDT 24
Finished Jun 27 06:47:02 PM PDT 24
Peak memory 199924 kb
Host smart-e670d594-c918-46e8-b579-7b687d23bb0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855178413 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_smoke.855178413
Directory /workspace/12.hmac_smoke/latest

Test location /workspace/coverage/default/12.hmac_stress_all.3564814865
Short name T657
Test name
Test status
Simulation time 1057467515092 ps
CPU time 2126.87 seconds
Started Jun 27 06:46:48 PM PDT 24
Finished Jun 27 07:22:26 PM PDT 24
Peak memory 216012 kb
Host smart-3c179a6f-3bce-405e-8a17-d6b50ead0a24
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564814865 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.hmac_stress_all.3564814865
Directory /workspace/12.hmac_stress_all/latest

Test location /workspace/coverage/default/12.hmac_test_hmac_vectors.1747692337
Short name T543
Test name
Test status
Simulation time 96007353 ps
CPU time 1.15 seconds
Started Jun 27 06:46:34 PM PDT 24
Finished Jun 27 06:46:48 PM PDT 24
Peak memory 199696 kb
Host smart-05e336ac-0c27-4b15-aa75-7f76036ca384
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747692337 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 12.hmac_test_hmac_vectors.1747692337
Directory /workspace/12.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/12.hmac_test_sha256_vectors.3591664377
Short name T513
Test name
Test status
Simulation time 8409160487 ps
CPU time 452.85 seconds
Started Jun 27 06:46:53 PM PDT 24
Finished Jun 27 06:54:35 PM PDT 24
Peak memory 200028 kb
Host smart-e8bd9370-8aa0-4fb0-9e2d-0321f208005a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3591664377 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_test_sha256_vectors.3591664377
Directory /workspace/12.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/12.hmac_test_sha384_vectors.930732672
Short name T30
Test name
Test status
Simulation time 123084895297 ps
CPU time 1791.84 seconds
Started Jun 27 06:46:36 PM PDT 24
Finished Jun 27 07:16:41 PM PDT 24
Peak memory 216068 kb
Host smart-5b5c19bc-9f58-4e1c-8a86-621aaf961b84
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=930732672 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_test_sha384_vectors.930732672
Directory /workspace/12.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/12.hmac_test_sha512_vectors.4266509047
Short name T87
Test name
Test status
Simulation time 104656018131 ps
CPU time 1851.73 seconds
Started Jun 27 06:46:50 PM PDT 24
Finished Jun 27 07:17:51 PM PDT 24
Peak memory 215380 kb
Host smart-a4876f55-b076-4f69-ad76-4146ec52fd80
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4266509047 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_test_sha512_vectors.4266509047
Directory /workspace/12.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/12.hmac_wipe_secret.1700589370
Short name T70
Test name
Test status
Simulation time 10139119749 ps
CPU time 62.27 seconds
Started Jun 27 06:46:47 PM PDT 24
Finished Jun 27 06:47:59 PM PDT 24
Peak memory 200060 kb
Host smart-ea848e35-a2dd-413e-a5c9-beb35b7aa1d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700589370 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_wipe_secret.1700589370
Directory /workspace/12.hmac_wipe_secret/latest

Test location /workspace/coverage/default/13.hmac_alert_test.2599352036
Short name T503
Test name
Test status
Simulation time 21715786 ps
CPU time 0.57 seconds
Started Jun 27 06:46:33 PM PDT 24
Finished Jun 27 06:46:47 PM PDT 24
Peak memory 195532 kb
Host smart-e5c000c2-7a40-443c-9360-59f2093fc754
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599352036 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_alert_test.2599352036
Directory /workspace/13.hmac_alert_test/latest

Test location /workspace/coverage/default/13.hmac_back_pressure.1513193518
Short name T598
Test name
Test status
Simulation time 1165685019 ps
CPU time 13.96 seconds
Started Jun 27 06:46:35 PM PDT 24
Finished Jun 27 06:47:02 PM PDT 24
Peak memory 199932 kb
Host smart-d3157ee8-c05f-41f0-a2c8-f00634ad6664
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1513193518 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_back_pressure.1513193518
Directory /workspace/13.hmac_back_pressure/latest

Test location /workspace/coverage/default/13.hmac_burst_wr.43804725
Short name T283
Test name
Test status
Simulation time 214506760 ps
CPU time 1.98 seconds
Started Jun 27 06:46:33 PM PDT 24
Finished Jun 27 06:46:48 PM PDT 24
Peak memory 200004 kb
Host smart-b1765172-3d81-4ddc-8a5a-e9c68bbb41dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43804725 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_burst_wr.43804725
Directory /workspace/13.hmac_burst_wr/latest

Test location /workspace/coverage/default/13.hmac_datapath_stress.1481441724
Short name T650
Test name
Test status
Simulation time 9217384918 ps
CPU time 1369.01 seconds
Started Jun 27 06:46:47 PM PDT 24
Finished Jun 27 07:09:46 PM PDT 24
Peak memory 768016 kb
Host smart-a94e1957-45b0-47c4-9558-6d1ffbba4101
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1481441724 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_datapath_stress.1481441724
Directory /workspace/13.hmac_datapath_stress/latest

Test location /workspace/coverage/default/13.hmac_error.2464848129
Short name T479
Test name
Test status
Simulation time 339222211 ps
CPU time 5.01 seconds
Started Jun 27 06:46:42 PM PDT 24
Finished Jun 27 06:46:59 PM PDT 24
Peak memory 199876 kb
Host smart-5f91d19f-1b4e-4529-b6aa-f7acd5ba46d5
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464848129 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_error.2464848129
Directory /workspace/13.hmac_error/latest

Test location /workspace/coverage/default/13.hmac_smoke.3733562280
Short name T159
Test name
Test status
Simulation time 235212005 ps
CPU time 9.59 seconds
Started Jun 27 06:46:32 PM PDT 24
Finished Jun 27 06:46:55 PM PDT 24
Peak memory 199972 kb
Host smart-cbf2ca20-c50e-4d8b-9cb9-7e0ba9757f6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3733562280 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_smoke.3733562280
Directory /workspace/13.hmac_smoke/latest

Test location /workspace/coverage/default/13.hmac_stress_all.622360361
Short name T610
Test name
Test status
Simulation time 26281609487 ps
CPU time 1849.13 seconds
Started Jun 27 06:46:47 PM PDT 24
Finished Jun 27 07:17:46 PM PDT 24
Peak memory 769512 kb
Host smart-f32d533f-32be-4eee-82f9-7865be73f2ac
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622360361 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 13.hmac_stress_all.622360361
Directory /workspace/13.hmac_stress_all/latest

Test location /workspace/coverage/default/13.hmac_test_hmac_vectors.2499852640
Short name T613
Test name
Test status
Simulation time 96489319 ps
CPU time 1.16 seconds
Started Jun 27 06:46:43 PM PDT 24
Finished Jun 27 06:46:56 PM PDT 24
Peak memory 199732 kb
Host smart-4a78ead2-3f15-48af-8fb6-7bc17353c54c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499852640 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 13.hmac_test_hmac_vectors.2499852640
Directory /workspace/13.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/13.hmac_test_sha256_vectors.3986379785
Short name T475
Test name
Test status
Simulation time 101909924051 ps
CPU time 539.36 seconds
Started Jun 27 06:46:42 PM PDT 24
Finished Jun 27 06:55:54 PM PDT 24
Peak memory 200028 kb
Host smart-4bdc5397-f285-4ccf-9b7f-7c90ecfd5024
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3986379785 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_test_sha256_vectors.3986379785
Directory /workspace/13.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/13.hmac_test_sha384_vectors.450433586
Short name T466
Test name
Test status
Simulation time 29757320705 ps
CPU time 1607.1 seconds
Started Jun 27 06:46:43 PM PDT 24
Finished Jun 27 07:13:42 PM PDT 24
Peak memory 215756 kb
Host smart-76a533d1-9793-4d17-984e-2bbec2aec05d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=450433586 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_test_sha384_vectors.450433586
Directory /workspace/13.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/13.hmac_test_sha512_vectors.4125361294
Short name T675
Test name
Test status
Simulation time 134184549052 ps
CPU time 1704.73 seconds
Started Jun 27 06:46:37 PM PDT 24
Finished Jun 27 07:15:15 PM PDT 24
Peak memory 216440 kb
Host smart-20156624-2d28-48f9-83ee-1cd2896edc08
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4125361294 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_test_sha512_vectors.4125361294
Directory /workspace/13.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/13.hmac_wipe_secret.646900500
Short name T390
Test name
Test status
Simulation time 6450693601 ps
CPU time 62.77 seconds
Started Jun 27 06:46:44 PM PDT 24
Finished Jun 27 06:47:58 PM PDT 24
Peak memory 199964 kb
Host smart-2ad2faa0-fe46-48db-9398-cae438f86679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646900500 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_wipe_secret.646900500
Directory /workspace/13.hmac_wipe_secret/latest

Test location /workspace/coverage/default/14.hmac_alert_test.4094663098
Short name T399
Test name
Test status
Simulation time 11912691 ps
CPU time 0.56 seconds
Started Jun 27 06:46:52 PM PDT 24
Finished Jun 27 06:47:02 PM PDT 24
Peak memory 194948 kb
Host smart-86673ef6-5310-4ddc-8023-a437228ecbb8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094663098 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_alert_test.4094663098
Directory /workspace/14.hmac_alert_test/latest

Test location /workspace/coverage/default/14.hmac_back_pressure.1756005365
Short name T360
Test name
Test status
Simulation time 1283321342 ps
CPU time 24.33 seconds
Started Jun 27 06:46:42 PM PDT 24
Finished Jun 27 06:47:19 PM PDT 24
Peak memory 199956 kb
Host smart-3a97f15e-4e86-42c4-b13e-847c44338e2a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1756005365 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_back_pressure.1756005365
Directory /workspace/14.hmac_back_pressure/latest

Test location /workspace/coverage/default/14.hmac_burst_wr.4041249113
Short name T349
Test name
Test status
Simulation time 3667504068 ps
CPU time 56.81 seconds
Started Jun 27 06:46:46 PM PDT 24
Finished Jun 27 06:47:53 PM PDT 24
Peak memory 199932 kb
Host smart-8ec793ae-f54e-4eee-b24b-e8219725d7eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041249113 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_burst_wr.4041249113
Directory /workspace/14.hmac_burst_wr/latest

Test location /workspace/coverage/default/14.hmac_datapath_stress.673106655
Short name T677
Test name
Test status
Simulation time 1013681804 ps
CPU time 192.69 seconds
Started Jun 27 06:46:41 PM PDT 24
Finished Jun 27 06:50:06 PM PDT 24
Peak memory 459980 kb
Host smart-c3238d66-c978-4967-a6a7-038dfffecfe5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=673106655 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_datapath_stress.673106655
Directory /workspace/14.hmac_datapath_stress/latest

Test location /workspace/coverage/default/14.hmac_error.875377076
Short name T486
Test name
Test status
Simulation time 4932178646 ps
CPU time 90.85 seconds
Started Jun 27 06:46:37 PM PDT 24
Finished Jun 27 06:48:21 PM PDT 24
Peak memory 200228 kb
Host smart-0bb8cb20-b405-4762-8a24-e0204cbba1c8
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875377076 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_error.875377076
Directory /workspace/14.hmac_error/latest

Test location /workspace/coverage/default/14.hmac_long_msg.3936018491
Short name T49
Test name
Test status
Simulation time 2716963177 ps
CPU time 38.46 seconds
Started Jun 27 06:46:44 PM PDT 24
Finished Jun 27 06:47:34 PM PDT 24
Peak memory 200000 kb
Host smart-73e7dc1b-1723-4be8-895f-2c5a41f8fe3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936018491 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_long_msg.3936018491
Directory /workspace/14.hmac_long_msg/latest

Test location /workspace/coverage/default/14.hmac_smoke.3387208872
Short name T622
Test name
Test status
Simulation time 2253337834 ps
CPU time 9.74 seconds
Started Jun 27 06:46:41 PM PDT 24
Finished Jun 27 06:47:03 PM PDT 24
Peak memory 200024 kb
Host smart-8a100b2c-ddb2-4a92-91ec-e73b57df2d38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387208872 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_smoke.3387208872
Directory /workspace/14.hmac_smoke/latest

Test location /workspace/coverage/default/14.hmac_stress_all.3536741586
Short name T188
Test name
Test status
Simulation time 1701381057 ps
CPU time 46.71 seconds
Started Jun 27 06:46:36 PM PDT 24
Finished Jun 27 06:47:36 PM PDT 24
Peak memory 199956 kb
Host smart-c711a80a-21a6-48fc-8b8f-5342ae6d37b8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536741586 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.hmac_stress_all.3536741586
Directory /workspace/14.hmac_stress_all/latest

Test location /workspace/coverage/default/14.hmac_test_hmac_vectors.1308664806
Short name T550
Test name
Test status
Simulation time 121795878 ps
CPU time 1.05 seconds
Started Jun 27 06:46:42 PM PDT 24
Finished Jun 27 06:46:55 PM PDT 24
Peak memory 199960 kb
Host smart-17301846-e718-4648-ab86-1df1d09b7c3e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308664806 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 14.hmac_test_hmac_vectors.1308664806
Directory /workspace/14.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/14.hmac_test_sha256_vectors.2157815698
Short name T679
Test name
Test status
Simulation time 8851579638 ps
CPU time 478.73 seconds
Started Jun 27 06:46:32 PM PDT 24
Finished Jun 27 06:54:44 PM PDT 24
Peak memory 200020 kb
Host smart-4cf2e76d-ea8d-4348-b22c-6a26aaeb3018
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2157815698 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_test_sha256_vectors.2157815698
Directory /workspace/14.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/14.hmac_test_sha384_vectors.3574875586
Short name T347
Test name
Test status
Simulation time 113911880446 ps
CPU time 1958.55 seconds
Started Jun 27 06:46:48 PM PDT 24
Finished Jun 27 07:19:37 PM PDT 24
Peak memory 216128 kb
Host smart-bb65225e-67c2-4b9c-a803-506d938ad4c5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3574875586 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_test_sha384_vectors.3574875586
Directory /workspace/14.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/14.hmac_test_sha512_vectors.1565413569
Short name T672
Test name
Test status
Simulation time 423886373574 ps
CPU time 1838.32 seconds
Started Jun 27 06:46:46 PM PDT 24
Finished Jun 27 07:17:35 PM PDT 24
Peak memory 216256 kb
Host smart-95adb9ad-3809-4c36-a5df-05ba1fece102
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1565413569 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_test_sha512_vectors.1565413569
Directory /workspace/14.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/14.hmac_wipe_secret.3356866876
Short name T268
Test name
Test status
Simulation time 5005898651 ps
CPU time 38.31 seconds
Started Jun 27 06:46:40 PM PDT 24
Finished Jun 27 06:47:30 PM PDT 24
Peak memory 200028 kb
Host smart-2fc81776-4660-44f8-97bf-74552d020c78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3356866876 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_wipe_secret.3356866876
Directory /workspace/14.hmac_wipe_secret/latest

Test location /workspace/coverage/default/15.hmac_alert_test.1887793995
Short name T688
Test name
Test status
Simulation time 16171261 ps
CPU time 0.59 seconds
Started Jun 27 06:46:34 PM PDT 24
Finished Jun 27 06:46:48 PM PDT 24
Peak memory 196712 kb
Host smart-4b974fba-efee-44e9-8c36-37142c655511
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887793995 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_alert_test.1887793995
Directory /workspace/15.hmac_alert_test/latest

Test location /workspace/coverage/default/15.hmac_back_pressure.361049135
Short name T96
Test name
Test status
Simulation time 739180438 ps
CPU time 6.05 seconds
Started Jun 27 06:46:48 PM PDT 24
Finished Jun 27 06:47:04 PM PDT 24
Peak memory 199936 kb
Host smart-ae7a8859-7781-4358-81a1-932051913fb8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=361049135 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_back_pressure.361049135
Directory /workspace/15.hmac_back_pressure/latest

Test location /workspace/coverage/default/15.hmac_burst_wr.2615828042
Short name T170
Test name
Test status
Simulation time 1910064897 ps
CPU time 25.55 seconds
Started Jun 27 06:46:47 PM PDT 24
Finished Jun 27 06:47:24 PM PDT 24
Peak memory 199940 kb
Host smart-8d718fd3-fd31-483a-801a-b8fc7be18d0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2615828042 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_burst_wr.2615828042
Directory /workspace/15.hmac_burst_wr/latest

Test location /workspace/coverage/default/15.hmac_datapath_stress.3588702138
Short name T661
Test name
Test status
Simulation time 3349826786 ps
CPU time 436.26 seconds
Started Jun 27 06:46:40 PM PDT 24
Finished Jun 27 06:54:08 PM PDT 24
Peak memory 695144 kb
Host smart-f094b8e7-ed0b-485a-9fba-ab7ada74ab13
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3588702138 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_datapath_stress.3588702138
Directory /workspace/15.hmac_datapath_stress/latest

Test location /workspace/coverage/default/15.hmac_error.2533883721
Short name T220
Test name
Test status
Simulation time 14866979631 ps
CPU time 51.18 seconds
Started Jun 27 06:46:40 PM PDT 24
Finished Jun 27 06:47:44 PM PDT 24
Peak memory 200000 kb
Host smart-a7dddf75-8b5c-4899-9328-923e4fb2c9be
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533883721 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_error.2533883721
Directory /workspace/15.hmac_error/latest

Test location /workspace/coverage/default/15.hmac_long_msg.2769170991
Short name T172
Test name
Test status
Simulation time 5492844935 ps
CPU time 82.36 seconds
Started Jun 27 06:46:40 PM PDT 24
Finished Jun 27 06:48:14 PM PDT 24
Peak memory 200072 kb
Host smart-615808cb-f067-458b-ac06-f7d8030d377b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769170991 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_long_msg.2769170991
Directory /workspace/15.hmac_long_msg/latest

Test location /workspace/coverage/default/15.hmac_smoke.1761425804
Short name T522
Test name
Test status
Simulation time 159490506 ps
CPU time 4.26 seconds
Started Jun 27 06:46:33 PM PDT 24
Finished Jun 27 06:46:51 PM PDT 24
Peak memory 200004 kb
Host smart-0426e061-840e-4528-9aed-fd7de3210c36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761425804 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_smoke.1761425804
Directory /workspace/15.hmac_smoke/latest

Test location /workspace/coverage/default/15.hmac_test_hmac_vectors.3830660651
Short name T298
Test name
Test status
Simulation time 232520822 ps
CPU time 1.38 seconds
Started Jun 27 06:46:32 PM PDT 24
Finished Jun 27 06:46:47 PM PDT 24
Peak memory 200068 kb
Host smart-14cf9fb8-9aff-4e96-a9d1-09415a49657a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830660651 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 15.hmac_test_hmac_vectors.3830660651
Directory /workspace/15.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/15.hmac_test_sha256_vectors.3129659134
Short name T519
Test name
Test status
Simulation time 17407772767 ps
CPU time 478.49 seconds
Started Jun 27 06:46:33 PM PDT 24
Finished Jun 27 06:54:45 PM PDT 24
Peak memory 200020 kb
Host smart-171738a1-129d-4189-b609-0ba7a4ae6fa0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3129659134 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_test_sha256_vectors.3129659134
Directory /workspace/15.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/15.hmac_test_sha384_vectors.3393041725
Short name T509
Test name
Test status
Simulation time 459723148425 ps
CPU time 2116.57 seconds
Started Jun 27 06:46:34 PM PDT 24
Finished Jun 27 07:22:04 PM PDT 24
Peak memory 215860 kb
Host smart-570ebf68-feb3-4d62-b78d-9bb2522237e4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3393041725 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_test_sha384_vectors.3393041725
Directory /workspace/15.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/15.hmac_test_sha512_vectors.2895888565
Short name T549
Test name
Test status
Simulation time 579218622267 ps
CPU time 1860.74 seconds
Started Jun 27 06:46:37 PM PDT 24
Finished Jun 27 07:17:51 PM PDT 24
Peak memory 215848 kb
Host smart-98c0b9bd-a36d-4271-97dc-dcd95efb3d4a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2895888565 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_test_sha512_vectors.2895888565
Directory /workspace/15.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/15.hmac_wipe_secret.2329491286
Short name T130
Test name
Test status
Simulation time 4620870310 ps
CPU time 40.28 seconds
Started Jun 27 06:46:34 PM PDT 24
Finished Jun 27 06:47:27 PM PDT 24
Peak memory 200036 kb
Host smart-9eb603e4-b70a-4783-aa61-2440fa95dc0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2329491286 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_wipe_secret.2329491286
Directory /workspace/15.hmac_wipe_secret/latest

Test location /workspace/coverage/default/16.hmac_alert_test.3087856154
Short name T432
Test name
Test status
Simulation time 13024782 ps
CPU time 0.6 seconds
Started Jun 27 06:46:49 PM PDT 24
Finished Jun 27 06:47:00 PM PDT 24
Peak memory 196040 kb
Host smart-2238b323-c74c-4a87-aa56-bf8ca6d594bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087856154 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_alert_test.3087856154
Directory /workspace/16.hmac_alert_test/latest

Test location /workspace/coverage/default/16.hmac_back_pressure.2403989269
Short name T621
Test name
Test status
Simulation time 748065280 ps
CPU time 35.35 seconds
Started Jun 27 06:46:36 PM PDT 24
Finished Jun 27 06:47:25 PM PDT 24
Peak memory 199976 kb
Host smart-da48eef3-a7a6-4473-b711-54105cecf2b7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2403989269 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_back_pressure.2403989269
Directory /workspace/16.hmac_back_pressure/latest

Test location /workspace/coverage/default/16.hmac_burst_wr.2714819351
Short name T169
Test name
Test status
Simulation time 3161666936 ps
CPU time 16.12 seconds
Started Jun 27 06:46:34 PM PDT 24
Finished Jun 27 06:47:03 PM PDT 24
Peak memory 199996 kb
Host smart-7ad65db5-5247-4341-bf75-3cd3e6dbf7bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714819351 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_burst_wr.2714819351
Directory /workspace/16.hmac_burst_wr/latest

Test location /workspace/coverage/default/16.hmac_datapath_stress.2803705002
Short name T608
Test name
Test status
Simulation time 1014595187 ps
CPU time 55.23 seconds
Started Jun 27 06:46:32 PM PDT 24
Finished Jun 27 06:47:41 PM PDT 24
Peak memory 345928 kb
Host smart-10d5d320-68c9-48f7-9a6f-3b69b394adff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2803705002 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_datapath_stress.2803705002
Directory /workspace/16.hmac_datapath_stress/latest

Test location /workspace/coverage/default/16.hmac_error.2488697694
Short name T224
Test name
Test status
Simulation time 2294451781 ps
CPU time 128.27 seconds
Started Jun 27 06:46:30 PM PDT 24
Finished Jun 27 06:48:52 PM PDT 24
Peak memory 200000 kb
Host smart-d314f7cd-4f36-4281-9331-7dd47b0473ca
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488697694 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_error.2488697694
Directory /workspace/16.hmac_error/latest

Test location /workspace/coverage/default/16.hmac_long_msg.4075979925
Short name T541
Test name
Test status
Simulation time 353349383 ps
CPU time 20.65 seconds
Started Jun 27 06:46:32 PM PDT 24
Finished Jun 27 06:47:06 PM PDT 24
Peak memory 200144 kb
Host smart-46c55bf7-11d1-4620-b4f6-3bd24f627cb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075979925 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_long_msg.4075979925
Directory /workspace/16.hmac_long_msg/latest

Test location /workspace/coverage/default/16.hmac_smoke.382054544
Short name T210
Test name
Test status
Simulation time 467400375 ps
CPU time 2.51 seconds
Started Jun 27 06:46:48 PM PDT 24
Finished Jun 27 06:47:01 PM PDT 24
Peak memory 199868 kb
Host smart-ad11080a-8a14-499a-9fa6-52560ef18cb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382054544 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_smoke.382054544
Directory /workspace/16.hmac_smoke/latest

Test location /workspace/coverage/default/16.hmac_stress_all.3656739681
Short name T459
Test name
Test status
Simulation time 887904966 ps
CPU time 7.29 seconds
Started Jun 27 06:46:31 PM PDT 24
Finished Jun 27 06:46:51 PM PDT 24
Peak memory 199992 kb
Host smart-6eb83c9d-4359-4808-8fae-81d97d0d8e96
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656739681 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.hmac_stress_all.3656739681
Directory /workspace/16.hmac_stress_all/latest

Test location /workspace/coverage/default/16.hmac_test_hmac_vectors.4212885670
Short name T327
Test name
Test status
Simulation time 191009619 ps
CPU time 1.17 seconds
Started Jun 27 06:46:30 PM PDT 24
Finished Jun 27 06:46:45 PM PDT 24
Peak memory 199904 kb
Host smart-6abc23a6-b1c7-4a2b-a894-22a9c597a1b6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212885670 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 16.hmac_test_hmac_vectors.4212885670
Directory /workspace/16.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/16.hmac_test_sha256_vectors.1496791218
Short name T656
Test name
Test status
Simulation time 8169688218 ps
CPU time 478.39 seconds
Started Jun 27 06:46:41 PM PDT 24
Finished Jun 27 06:54:52 PM PDT 24
Peak memory 200008 kb
Host smart-6827b0a0-a061-4d6a-b5d3-358b83534962
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1496791218 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_test_sha256_vectors.1496791218
Directory /workspace/16.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/16.hmac_test_sha384_vectors.2850133396
Short name T535
Test name
Test status
Simulation time 62266713542 ps
CPU time 1717.38 seconds
Started Jun 27 06:46:33 PM PDT 24
Finished Jun 27 07:15:24 PM PDT 24
Peak memory 215632 kb
Host smart-91672f0d-ee5c-45af-9dae-381e1a04f4e5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2850133396 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_test_sha384_vectors.2850133396
Directory /workspace/16.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/16.hmac_test_sha512_vectors.3335111593
Short name T578
Test name
Test status
Simulation time 119226957198 ps
CPU time 1586.75 seconds
Started Jun 27 06:46:33 PM PDT 24
Finished Jun 27 07:13:13 PM PDT 24
Peak memory 216112 kb
Host smart-df923f6f-32dc-4642-b291-eaffeb2e2eff
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3335111593 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_test_sha512_vectors.3335111593
Directory /workspace/16.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/16.hmac_wipe_secret.2409759111
Short name T653
Test name
Test status
Simulation time 19208300923 ps
CPU time 83.34 seconds
Started Jun 27 06:46:45 PM PDT 24
Finished Jun 27 06:48:20 PM PDT 24
Peak memory 200008 kb
Host smart-cbe79925-4590-462a-b899-f5c7025be17c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409759111 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_wipe_secret.2409759111
Directory /workspace/16.hmac_wipe_secret/latest

Test location /workspace/coverage/default/17.hmac_alert_test.1272132337
Short name T39
Test name
Test status
Simulation time 45772663 ps
CPU time 0.6 seconds
Started Jun 27 06:47:01 PM PDT 24
Finished Jun 27 06:47:08 PM PDT 24
Peak memory 196740 kb
Host smart-8d5ba5ca-b50e-45da-9029-3924aea77ab7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272132337 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_alert_test.1272132337
Directory /workspace/17.hmac_alert_test/latest

Test location /workspace/coverage/default/17.hmac_back_pressure.3693709437
Short name T245
Test name
Test status
Simulation time 909873295 ps
CPU time 41.47 seconds
Started Jun 27 06:46:37 PM PDT 24
Finished Jun 27 06:47:32 PM PDT 24
Peak memory 199968 kb
Host smart-d3e9fb60-8e57-4654-954b-6fa0bd4f93e0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3693709437 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_back_pressure.3693709437
Directory /workspace/17.hmac_back_pressure/latest

Test location /workspace/coverage/default/17.hmac_burst_wr.2083002208
Short name T586
Test name
Test status
Simulation time 3522906917 ps
CPU time 47.21 seconds
Started Jun 27 06:46:35 PM PDT 24
Finished Jun 27 06:47:36 PM PDT 24
Peak memory 200036 kb
Host smart-3e6f054f-628b-4c5f-8679-a2acd39e7de9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083002208 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_burst_wr.2083002208
Directory /workspace/17.hmac_burst_wr/latest

Test location /workspace/coverage/default/17.hmac_datapath_stress.3634516031
Short name T255
Test name
Test status
Simulation time 6256156511 ps
CPU time 355.97 seconds
Started Jun 27 06:46:35 PM PDT 24
Finished Jun 27 06:52:44 PM PDT 24
Peak memory 673288 kb
Host smart-b196602e-21cf-4472-b5c1-e33cc4fb76ac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3634516031 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_datapath_stress.3634516031
Directory /workspace/17.hmac_datapath_stress/latest

Test location /workspace/coverage/default/17.hmac_error.2052782025
Short name T671
Test name
Test status
Simulation time 44297230605 ps
CPU time 140.32 seconds
Started Jun 27 06:46:35 PM PDT 24
Finished Jun 27 06:49:09 PM PDT 24
Peak memory 200016 kb
Host smart-e90e1c60-375e-42a9-8c68-bab4a222351e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052782025 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_error.2052782025
Directory /workspace/17.hmac_error/latest

Test location /workspace/coverage/default/17.hmac_long_msg.3439436348
Short name T215
Test name
Test status
Simulation time 834882311 ps
CPU time 50.07 seconds
Started Jun 27 06:46:37 PM PDT 24
Finished Jun 27 06:47:40 PM PDT 24
Peak memory 199940 kb
Host smart-1917e9d8-31d0-499e-b9ed-6f0fd658e86c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3439436348 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_long_msg.3439436348
Directory /workspace/17.hmac_long_msg/latest

Test location /workspace/coverage/default/17.hmac_smoke.3435680993
Short name T413
Test name
Test status
Simulation time 197753754 ps
CPU time 9.78 seconds
Started Jun 27 06:46:42 PM PDT 24
Finished Jun 27 06:47:04 PM PDT 24
Peak memory 199988 kb
Host smart-3134cca4-052d-4042-95c0-7225d78f193e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435680993 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_smoke.3435680993
Directory /workspace/17.hmac_smoke/latest

Test location /workspace/coverage/default/17.hmac_stress_all.2537046759
Short name T321
Test name
Test status
Simulation time 118550412094 ps
CPU time 974.07 seconds
Started Jun 27 06:46:50 PM PDT 24
Finished Jun 27 07:03:13 PM PDT 24
Peak memory 704948 kb
Host smart-7c821abc-d270-4a1f-a5ea-4986cf223be4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537046759 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.hmac_stress_all.2537046759
Directory /workspace/17.hmac_stress_all/latest

Test location /workspace/coverage/default/17.hmac_test_hmac_vectors.4106594051
Short name T447
Test name
Test status
Simulation time 102823602 ps
CPU time 1.1 seconds
Started Jun 27 06:46:48 PM PDT 24
Finished Jun 27 06:47:00 PM PDT 24
Peak memory 199756 kb
Host smart-5037f8a3-1593-4750-8008-100d66329d36
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106594051 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 17.hmac_test_hmac_vectors.4106594051
Directory /workspace/17.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/17.hmac_test_sha256_vectors.610621655
Short name T411
Test name
Test status
Simulation time 231609872340 ps
CPU time 523.41 seconds
Started Jun 27 06:46:51 PM PDT 24
Finished Jun 27 06:55:43 PM PDT 24
Peak memory 199992 kb
Host smart-39271f0a-15c2-4383-a4de-0bae11a1cdb0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=610621655 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_test_sha256_vectors.610621655
Directory /workspace/17.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/17.hmac_test_sha384_vectors.2917785064
Short name T612
Test name
Test status
Simulation time 145979952735 ps
CPU time 1754.54 seconds
Started Jun 27 06:46:36 PM PDT 24
Finished Jun 27 07:16:04 PM PDT 24
Peak memory 215940 kb
Host smart-5ee26ea3-c655-4d23-b7ca-a4f0880b1198
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2917785064 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_test_sha384_vectors.2917785064
Directory /workspace/17.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/17.hmac_test_sha512_vectors.552202701
Short name T458
Test name
Test status
Simulation time 110147134674 ps
CPU time 1580.16 seconds
Started Jun 27 06:46:42 PM PDT 24
Finished Jun 27 07:13:14 PM PDT 24
Peak memory 215572 kb
Host smart-485b4c7f-aaae-4e76-a98a-45fd473d75cf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=552202701 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_test_sha512_vectors.552202701
Directory /workspace/17.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/17.hmac_wipe_secret.3192166941
Short name T50
Test name
Test status
Simulation time 1928319366 ps
CPU time 15.73 seconds
Started Jun 27 06:46:31 PM PDT 24
Finished Jun 27 06:47:00 PM PDT 24
Peak memory 200012 kb
Host smart-1a1ffeed-62be-4c92-ad24-6337d890b92a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192166941 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_wipe_secret.3192166941
Directory /workspace/17.hmac_wipe_secret/latest

Test location /workspace/coverage/default/18.hmac_alert_test.2419468790
Short name T37
Test name
Test status
Simulation time 12514975 ps
CPU time 0.61 seconds
Started Jun 27 06:46:46 PM PDT 24
Finished Jun 27 06:46:58 PM PDT 24
Peak memory 194968 kb
Host smart-62b87cbb-919f-4d24-9026-489af54fc27d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419468790 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_alert_test.2419468790
Directory /workspace/18.hmac_alert_test/latest

Test location /workspace/coverage/default/18.hmac_burst_wr.3614725592
Short name T404
Test name
Test status
Simulation time 2082865488 ps
CPU time 38.42 seconds
Started Jun 27 06:46:46 PM PDT 24
Finished Jun 27 06:47:35 PM PDT 24
Peak memory 199976 kb
Host smart-4935ca9c-35c1-4aeb-a9d6-a8448e9247da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614725592 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_burst_wr.3614725592
Directory /workspace/18.hmac_burst_wr/latest

Test location /workspace/coverage/default/18.hmac_datapath_stress.2788743398
Short name T184
Test name
Test status
Simulation time 13917348368 ps
CPU time 845.2 seconds
Started Jun 27 06:46:52 PM PDT 24
Finished Jun 27 07:01:07 PM PDT 24
Peak memory 734296 kb
Host smart-11382316-4097-4a1a-a4f0-3ee262b81906
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2788743398 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_datapath_stress.2788743398
Directory /workspace/18.hmac_datapath_stress/latest

Test location /workspace/coverage/default/18.hmac_error.911061257
Short name T601
Test name
Test status
Simulation time 9841559742 ps
CPU time 132.48 seconds
Started Jun 27 06:46:55 PM PDT 24
Finished Jun 27 06:49:16 PM PDT 24
Peak memory 200000 kb
Host smart-2a338fb5-dc2b-45ca-b30a-9199a0baec3c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911061257 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_error.911061257
Directory /workspace/18.hmac_error/latest

Test location /workspace/coverage/default/18.hmac_long_msg.1001135079
Short name T682
Test name
Test status
Simulation time 63285105161 ps
CPU time 157.89 seconds
Started Jun 27 06:46:53 PM PDT 24
Finished Jun 27 06:49:40 PM PDT 24
Peak memory 200396 kb
Host smart-9d97e00e-da1c-4174-80bb-27f5b8f834b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001135079 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_long_msg.1001135079
Directory /workspace/18.hmac_long_msg/latest

Test location /workspace/coverage/default/18.hmac_smoke.4137482466
Short name T645
Test name
Test status
Simulation time 85461338 ps
CPU time 2.01 seconds
Started Jun 27 06:46:48 PM PDT 24
Finished Jun 27 06:47:01 PM PDT 24
Peak memory 199976 kb
Host smart-65dfe75a-dc6f-4a9a-8b26-70dfe95d0da3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137482466 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_smoke.4137482466
Directory /workspace/18.hmac_smoke/latest

Test location /workspace/coverage/default/18.hmac_test_hmac_vectors.4276804605
Short name T313
Test name
Test status
Simulation time 236904203 ps
CPU time 1.14 seconds
Started Jun 27 06:46:50 PM PDT 24
Finished Jun 27 06:47:00 PM PDT 24
Peak memory 199904 kb
Host smart-996affcd-e4e0-4699-b736-744c6ad30e1f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276804605 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 18.hmac_test_hmac_vectors.4276804605
Directory /workspace/18.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/18.hmac_test_sha256_vectors.1640683613
Short name T66
Test name
Test status
Simulation time 120136673551 ps
CPU time 510.18 seconds
Started Jun 27 06:46:51 PM PDT 24
Finished Jun 27 06:55:31 PM PDT 24
Peak memory 200048 kb
Host smart-4dc9107b-2080-4b1e-822c-fa43454f376b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1640683613 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_test_sha256_vectors.1640683613
Directory /workspace/18.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/18.hmac_test_sha384_vectors.3293085834
Short name T72
Test name
Test status
Simulation time 139167633573 ps
CPU time 1716.73 seconds
Started Jun 27 06:46:59 PM PDT 24
Finished Jun 27 07:15:42 PM PDT 24
Peak memory 215984 kb
Host smart-9f016856-7e31-4635-9490-06b009e42eab
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3293085834 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_test_sha384_vectors.3293085834
Directory /workspace/18.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/18.hmac_test_sha512_vectors.2087057959
Short name T450
Test name
Test status
Simulation time 479751853840 ps
CPU time 2090.03 seconds
Started Jun 27 06:46:47 PM PDT 24
Finished Jun 27 07:21:48 PM PDT 24
Peak memory 215388 kb
Host smart-66283c6c-ffb0-4f93-8cf9-146dbfb219bf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2087057959 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_test_sha512_vectors.2087057959
Directory /workspace/18.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/18.hmac_wipe_secret.2009703478
Short name T320
Test name
Test status
Simulation time 2369996511 ps
CPU time 25.36 seconds
Started Jun 27 06:46:48 PM PDT 24
Finished Jun 27 06:47:24 PM PDT 24
Peak memory 200068 kb
Host smart-954c27ec-ce45-4b50-b1a3-a81d51752f04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009703478 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_wipe_secret.2009703478
Directory /workspace/18.hmac_wipe_secret/latest

Test location /workspace/coverage/default/19.hmac_alert_test.622821035
Short name T309
Test name
Test status
Simulation time 43694098 ps
CPU time 0.61 seconds
Started Jun 27 06:46:52 PM PDT 24
Finished Jun 27 06:47:02 PM PDT 24
Peak memory 196756 kb
Host smart-5f84f3c8-81ce-4644-bfdc-5061542b7993
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622821035 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_alert_test.622821035
Directory /workspace/19.hmac_alert_test/latest

Test location /workspace/coverage/default/19.hmac_back_pressure.4036946501
Short name T662
Test name
Test status
Simulation time 864945448 ps
CPU time 10.63 seconds
Started Jun 27 06:46:46 PM PDT 24
Finished Jun 27 06:47:07 PM PDT 24
Peak memory 199880 kb
Host smart-c680825a-e8f2-48ce-b8c1-9fcddc1ea752
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4036946501 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_back_pressure.4036946501
Directory /workspace/19.hmac_back_pressure/latest

Test location /workspace/coverage/default/19.hmac_burst_wr.3531191923
Short name T353
Test name
Test status
Simulation time 2430480656 ps
CPU time 32.66 seconds
Started Jun 27 06:46:45 PM PDT 24
Finished Jun 27 06:47:29 PM PDT 24
Peak memory 200068 kb
Host smart-928b52d2-b35b-4415-989e-fe3d90e40316
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531191923 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_burst_wr.3531191923
Directory /workspace/19.hmac_burst_wr/latest

Test location /workspace/coverage/default/19.hmac_datapath_stress.2558190708
Short name T683
Test name
Test status
Simulation time 59141790737 ps
CPU time 953.01 seconds
Started Jun 27 06:46:48 PM PDT 24
Finished Jun 27 07:02:52 PM PDT 24
Peak memory 728272 kb
Host smart-af066c22-0fca-463b-a50f-c07d79412356
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2558190708 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_datapath_stress.2558190708
Directory /workspace/19.hmac_datapath_stress/latest

Test location /workspace/coverage/default/19.hmac_error.74896691
Short name T27
Test name
Test status
Simulation time 6399235581 ps
CPU time 117.85 seconds
Started Jun 27 06:46:47 PM PDT 24
Finished Jun 27 06:48:55 PM PDT 24
Peak memory 200020 kb
Host smart-aad3da6c-3a49-45d3-a311-979c0f45d822
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74896691 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_error.74896691
Directory /workspace/19.hmac_error/latest

Test location /workspace/coverage/default/19.hmac_long_msg.3996311982
Short name T590
Test name
Test status
Simulation time 1121256379 ps
CPU time 68.13 seconds
Started Jun 27 06:47:02 PM PDT 24
Finished Jun 27 06:48:16 PM PDT 24
Peak memory 199932 kb
Host smart-47d3b99f-888e-46de-b67a-94ecb31e3d4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996311982 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_long_msg.3996311982
Directory /workspace/19.hmac_long_msg/latest

Test location /workspace/coverage/default/19.hmac_smoke.391648212
Short name T236
Test name
Test status
Simulation time 147107915 ps
CPU time 3.46 seconds
Started Jun 27 06:46:47 PM PDT 24
Finished Jun 27 06:47:01 PM PDT 24
Peak memory 199968 kb
Host smart-ee2f2a22-9c11-490a-92fe-cbf5ba5f8456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391648212 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_smoke.391648212
Directory /workspace/19.hmac_smoke/latest

Test location /workspace/coverage/default/19.hmac_stress_all.3218388223
Short name T326
Test name
Test status
Simulation time 15658556476 ps
CPU time 673.1 seconds
Started Jun 27 06:46:49 PM PDT 24
Finished Jun 27 06:58:12 PM PDT 24
Peak memory 674688 kb
Host smart-89cb4e53-84b0-4c83-9d8a-89b7350189b0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218388223 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.hmac_stress_all.3218388223
Directory /workspace/19.hmac_stress_all/latest

Test location /workspace/coverage/default/19.hmac_test_hmac_vectors.1399291833
Short name T438
Test name
Test status
Simulation time 53005291 ps
CPU time 1.1 seconds
Started Jun 27 06:46:49 PM PDT 24
Finished Jun 27 06:47:00 PM PDT 24
Peak memory 199800 kb
Host smart-011b1f62-346c-48b1-b699-c1ff34a12853
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399291833 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 19.hmac_test_hmac_vectors.1399291833
Directory /workspace/19.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/19.hmac_test_sha256_vectors.80450831
Short name T415
Test name
Test status
Simulation time 185349355818 ps
CPU time 578.9 seconds
Started Jun 27 06:46:47 PM PDT 24
Finished Jun 27 06:56:36 PM PDT 24
Peak memory 200008 kb
Host smart-e11fea46-dfb3-4542-87c5-08e795cf074f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=80450831 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_test_sha256_vectors.80450831
Directory /workspace/19.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/19.hmac_test_sha384_vectors.4025541576
Short name T692
Test name
Test status
Simulation time 539886292351 ps
CPU time 1888.31 seconds
Started Jun 27 06:46:50 PM PDT 24
Finished Jun 27 07:18:28 PM PDT 24
Peak memory 216216 kb
Host smart-d7d9bf41-802f-4729-be78-898223001e9f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4025541576 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_test_sha384_vectors.4025541576
Directory /workspace/19.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/19.hmac_test_sha512_vectors.1473499991
Short name T626
Test name
Test status
Simulation time 162351457750 ps
CPU time 1703.5 seconds
Started Jun 27 06:46:58 PM PDT 24
Finished Jun 27 07:15:29 PM PDT 24
Peak memory 216416 kb
Host smart-368bce44-6af5-415f-ab4b-dbefb7f98dc0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1473499991 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_test_sha512_vectors.1473499991
Directory /workspace/19.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/19.hmac_wipe_secret.389488697
Short name T322
Test name
Test status
Simulation time 2575781801 ps
CPU time 46.76 seconds
Started Jun 27 06:46:49 PM PDT 24
Finished Jun 27 06:47:46 PM PDT 24
Peak memory 200064 kb
Host smart-c5eac7ab-b608-43c4-b5e1-69959083a6ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389488697 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_wipe_secret.389488697
Directory /workspace/19.hmac_wipe_secret/latest

Test location /workspace/coverage/default/2.hmac_alert_test.2582116710
Short name T330
Test name
Test status
Simulation time 25871965 ps
CPU time 0.62 seconds
Started Jun 27 06:46:23 PM PDT 24
Finished Jun 27 06:46:32 PM PDT 24
Peak memory 195992 kb
Host smart-2545073c-0d24-4d4f-913d-fac11fa6e18a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582116710 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_alert_test.2582116710
Directory /workspace/2.hmac_alert_test/latest

Test location /workspace/coverage/default/2.hmac_back_pressure.3000134031
Short name T324
Test name
Test status
Simulation time 124878265 ps
CPU time 2.42 seconds
Started Jun 27 06:46:27 PM PDT 24
Finished Jun 27 06:46:42 PM PDT 24
Peak memory 199924 kb
Host smart-eb4e5fd3-4472-4d13-a625-757803902571
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3000134031 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_back_pressure.3000134031
Directory /workspace/2.hmac_back_pressure/latest

Test location /workspace/coverage/default/2.hmac_burst_wr.2630943209
Short name T5
Test name
Test status
Simulation time 589727285 ps
CPU time 16.93 seconds
Started Jun 27 06:46:33 PM PDT 24
Finished Jun 27 06:47:03 PM PDT 24
Peak memory 199880 kb
Host smart-21669dac-dbc2-49fa-99da-ffb6f7d1308c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630943209 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_burst_wr.2630943209
Directory /workspace/2.hmac_burst_wr/latest

Test location /workspace/coverage/default/2.hmac_datapath_stress.967234532
Short name T276
Test name
Test status
Simulation time 67118678 ps
CPU time 1.29 seconds
Started Jun 27 06:46:33 PM PDT 24
Finished Jun 27 06:46:48 PM PDT 24
Peak memory 199864 kb
Host smart-dfc133dc-d3c7-4446-be7e-23ab4e41f116
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=967234532 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_datapath_stress.967234532
Directory /workspace/2.hmac_datapath_stress/latest

Test location /workspace/coverage/default/2.hmac_error.1392518767
Short name T307
Test name
Test status
Simulation time 4176425717 ps
CPU time 56.33 seconds
Started Jun 27 06:46:29 PM PDT 24
Finished Jun 27 06:47:39 PM PDT 24
Peak memory 200012 kb
Host smart-1488b9b0-212e-4aa4-9ede-0b7083b13562
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392518767 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_error.1392518767
Directory /workspace/2.hmac_error/latest

Test location /workspace/coverage/default/2.hmac_long_msg.1408329435
Short name T237
Test name
Test status
Simulation time 1457158802 ps
CPU time 81.33 seconds
Started Jun 27 06:46:28 PM PDT 24
Finished Jun 27 06:48:02 PM PDT 24
Peak memory 199908 kb
Host smart-1b4f9c9b-1073-4ea2-ac4b-36a48ba74326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408329435 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_long_msg.1408329435
Directory /workspace/2.hmac_long_msg/latest

Test location /workspace/coverage/default/2.hmac_sec_cm.2879817088
Short name T47
Test name
Test status
Simulation time 122311110 ps
CPU time 0.83 seconds
Started Jun 27 06:46:24 PM PDT 24
Finished Jun 27 06:46:35 PM PDT 24
Peak memory 218300 kb
Host smart-06018e16-494d-4caa-8d8a-8463169ae25f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879817088 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_sec_cm.2879817088
Directory /workspace/2.hmac_sec_cm/latest

Test location /workspace/coverage/default/2.hmac_smoke.3068280538
Short name T195
Test name
Test status
Simulation time 122497912 ps
CPU time 5.97 seconds
Started Jun 27 06:46:27 PM PDT 24
Finished Jun 27 06:46:45 PM PDT 24
Peak memory 199972 kb
Host smart-2c0f54da-30c5-4d92-9356-a1052745290b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068280538 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_smoke.3068280538
Directory /workspace/2.hmac_smoke/latest

Test location /workspace/coverage/default/2.hmac_stress_all.1680027681
Short name T659
Test name
Test status
Simulation time 420433379112 ps
CPU time 4235.94 seconds
Started Jun 27 06:46:33 PM PDT 24
Finished Jun 27 07:57:23 PM PDT 24
Peak memory 795432 kb
Host smart-a99fce23-30f3-4795-b239-be18d8d36181
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680027681 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all.1680027681
Directory /workspace/2.hmac_stress_all/latest

Test location /workspace/coverage/default/2.hmac_test_hmac_vectors.1614346915
Short name T331
Test name
Test status
Simulation time 131060059 ps
CPU time 1.04 seconds
Started Jun 27 06:46:20 PM PDT 24
Finished Jun 27 06:46:28 PM PDT 24
Peak memory 199620 kb
Host smart-4e5e0bfb-5b70-4e4a-8c5b-169bdc1366e3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614346915 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac_vectors.1614346915
Directory /workspace/2.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha256_vectors.1275469493
Short name T527
Test name
Test status
Simulation time 32271252198 ps
CPU time 417.01 seconds
Started Jun 27 06:46:33 PM PDT 24
Finished Jun 27 06:53:43 PM PDT 24
Peak memory 200008 kb
Host smart-f24fb006-d228-4d9b-bbb2-8571eec24d60
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1275469493 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha256_vectors.1275469493
Directory /workspace/2.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha384_vectors.989872622
Short name T588
Test name
Test status
Simulation time 385279892741 ps
CPU time 1952.65 seconds
Started Jun 27 06:46:29 PM PDT 24
Finished Jun 27 07:19:15 PM PDT 24
Peak memory 216404 kb
Host smart-1118ea2b-15ba-4544-9c7b-cc7ae513eaad
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=989872622 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha384_vectors.989872622
Directory /workspace/2.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha512_vectors.1861905049
Short name T150
Test name
Test status
Simulation time 288663402467 ps
CPU time 1884.33 seconds
Started Jun 27 06:46:20 PM PDT 24
Finished Jun 27 07:17:51 PM PDT 24
Peak memory 215524 kb
Host smart-69f8a98a-6448-4c42-a16c-1b1102e195f8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1861905049 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha512_vectors.1861905049
Directory /workspace/2.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/2.hmac_wipe_secret.2020138626
Short name T499
Test name
Test status
Simulation time 97818963 ps
CPU time 2.64 seconds
Started Jun 27 06:46:35 PM PDT 24
Finished Jun 27 06:46:51 PM PDT 24
Peak memory 199904 kb
Host smart-6527c3e1-1b1f-45a3-bdb7-64a091608f80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020138626 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_wipe_secret.2020138626
Directory /workspace/2.hmac_wipe_secret/latest

Test location /workspace/coverage/default/20.hmac_alert_test.300362639
Short name T242
Test name
Test status
Simulation time 75204349 ps
CPU time 0.61 seconds
Started Jun 27 06:46:55 PM PDT 24
Finished Jun 27 06:47:04 PM PDT 24
Peak memory 196056 kb
Host smart-9e670013-66db-4d7e-ac79-7106a270610a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300362639 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_alert_test.300362639
Directory /workspace/20.hmac_alert_test/latest

Test location /workspace/coverage/default/20.hmac_back_pressure.3985514040
Short name T9
Test name
Test status
Simulation time 732315993 ps
CPU time 8.35 seconds
Started Jun 27 06:47:01 PM PDT 24
Finished Jun 27 06:47:15 PM PDT 24
Peak memory 199944 kb
Host smart-9a095b3d-fd27-4ce4-a0de-08f0785eba2b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3985514040 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_back_pressure.3985514040
Directory /workspace/20.hmac_back_pressure/latest

Test location /workspace/coverage/default/20.hmac_burst_wr.521097615
Short name T398
Test name
Test status
Simulation time 472079747 ps
CPU time 4.96 seconds
Started Jun 27 06:46:55 PM PDT 24
Finished Jun 27 06:47:08 PM PDT 24
Peak memory 199968 kb
Host smart-aec229bd-34e1-439d-93dd-7c9846ece701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521097615 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_burst_wr.521097615
Directory /workspace/20.hmac_burst_wr/latest

Test location /workspace/coverage/default/20.hmac_datapath_stress.3018367882
Short name T137
Test name
Test status
Simulation time 3654214338 ps
CPU time 949.75 seconds
Started Jun 27 06:46:51 PM PDT 24
Finished Jun 27 07:02:50 PM PDT 24
Peak memory 705372 kb
Host smart-f36015ae-d228-43e8-9646-8798fc000eaa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3018367882 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_datapath_stress.3018367882
Directory /workspace/20.hmac_datapath_stress/latest

Test location /workspace/coverage/default/20.hmac_error.3187433629
Short name T351
Test name
Test status
Simulation time 6478383281 ps
CPU time 94.82 seconds
Started Jun 27 06:46:51 PM PDT 24
Finished Jun 27 06:48:36 PM PDT 24
Peak memory 200052 kb
Host smart-0458639f-b6c6-4280-843a-6296f4fc33eb
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187433629 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_error.3187433629
Directory /workspace/20.hmac_error/latest

Test location /workspace/coverage/default/20.hmac_long_msg.2604404503
Short name T202
Test name
Test status
Simulation time 2168227185 ps
CPU time 31.31 seconds
Started Jun 27 06:46:54 PM PDT 24
Finished Jun 27 06:47:34 PM PDT 24
Peak memory 199956 kb
Host smart-aaf99a7b-b213-4fbc-937c-f58d905a01fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604404503 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_long_msg.2604404503
Directory /workspace/20.hmac_long_msg/latest

Test location /workspace/coverage/default/20.hmac_smoke.534525896
Short name T380
Test name
Test status
Simulation time 631909511 ps
CPU time 9.36 seconds
Started Jun 27 06:46:59 PM PDT 24
Finished Jun 27 06:47:15 PM PDT 24
Peak memory 199860 kb
Host smart-5edeccef-4331-4a98-a1a1-d7a276e1a1fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534525896 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_smoke.534525896
Directory /workspace/20.hmac_smoke/latest

Test location /workspace/coverage/default/20.hmac_stress_all.2975262800
Short name T300
Test name
Test status
Simulation time 131927692040 ps
CPU time 1748.97 seconds
Started Jun 27 06:46:58 PM PDT 24
Finished Jun 27 07:16:14 PM PDT 24
Peak memory 216208 kb
Host smart-7f828c9c-d42d-4f4b-934b-52720dfb23b0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975262800 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.hmac_stress_all.2975262800
Directory /workspace/20.hmac_stress_all/latest

Test location /workspace/coverage/default/20.hmac_test_hmac_vectors.4063405695
Short name T28
Test name
Test status
Simulation time 36865582 ps
CPU time 1.04 seconds
Started Jun 27 06:46:58 PM PDT 24
Finished Jun 27 06:47:06 PM PDT 24
Peak memory 199688 kb
Host smart-0cbbebb2-d6c9-428b-bf68-a4343b120157
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063405695 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 20.hmac_test_hmac_vectors.4063405695
Directory /workspace/20.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/20.hmac_test_sha256_vectors.399880744
Short name T381
Test name
Test status
Simulation time 146657516824 ps
CPU time 511.03 seconds
Started Jun 27 06:46:58 PM PDT 24
Finished Jun 27 06:55:36 PM PDT 24
Peak memory 200000 kb
Host smart-14479a47-405a-4a1c-a269-7d5f13dea815
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=399880744 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_test_sha256_vectors.399880744
Directory /workspace/20.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/20.hmac_test_sha384_vectors.4151111573
Short name T197
Test name
Test status
Simulation time 29329523708 ps
CPU time 1565.8 seconds
Started Jun 27 06:46:56 PM PDT 24
Finished Jun 27 07:13:10 PM PDT 24
Peak memory 216040 kb
Host smart-9a8e3d85-f658-43b4-8855-05c634e21cea
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4151111573 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_test_sha384_vectors.4151111573
Directory /workspace/20.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/20.hmac_test_sha512_vectors.614372708
Short name T449
Test name
Test status
Simulation time 143202668992 ps
CPU time 1972.45 seconds
Started Jun 27 06:47:03 PM PDT 24
Finished Jun 27 07:20:01 PM PDT 24
Peak memory 215512 kb
Host smart-a4c04b39-a6dc-4a86-ac4c-76a1c84d52f3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=614372708 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_test_sha512_vectors.614372708
Directory /workspace/20.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/20.hmac_wipe_secret.3455952067
Short name T262
Test name
Test status
Simulation time 604974103 ps
CPU time 34.15 seconds
Started Jun 27 06:46:51 PM PDT 24
Finished Jun 27 06:47:34 PM PDT 24
Peak memory 200008 kb
Host smart-7280ae61-c60b-453b-b005-54e202ddaa47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455952067 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_wipe_secret.3455952067
Directory /workspace/20.hmac_wipe_secret/latest

Test location /workspace/coverage/default/21.hmac_alert_test.3189115800
Short name T526
Test name
Test status
Simulation time 31595586 ps
CPU time 0.57 seconds
Started Jun 27 06:46:57 PM PDT 24
Finished Jun 27 06:47:05 PM PDT 24
Peak memory 195724 kb
Host smart-4831836c-10dc-4156-99f1-1ecddfb6db00
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189115800 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_alert_test.3189115800
Directory /workspace/21.hmac_alert_test/latest

Test location /workspace/coverage/default/21.hmac_back_pressure.4085472028
Short name T539
Test name
Test status
Simulation time 114383292 ps
CPU time 1.72 seconds
Started Jun 27 06:46:53 PM PDT 24
Finished Jun 27 06:47:03 PM PDT 24
Peak memory 199952 kb
Host smart-81885a04-20d9-482d-bc07-787f1d27aae6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4085472028 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_back_pressure.4085472028
Directory /workspace/21.hmac_back_pressure/latest

Test location /workspace/coverage/default/21.hmac_burst_wr.4189750028
Short name T587
Test name
Test status
Simulation time 6161993390 ps
CPU time 33.07 seconds
Started Jun 27 06:46:56 PM PDT 24
Finished Jun 27 06:47:37 PM PDT 24
Peak memory 200016 kb
Host smart-a696db35-b049-44e7-8f70-ef7053f81c7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189750028 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_burst_wr.4189750028
Directory /workspace/21.hmac_burst_wr/latest

Test location /workspace/coverage/default/21.hmac_datapath_stress.402048466
Short name T689
Test name
Test status
Simulation time 8055381087 ps
CPU time 1121.68 seconds
Started Jun 27 06:46:56 PM PDT 24
Finished Jun 27 07:05:46 PM PDT 24
Peak memory 756764 kb
Host smart-ec3b9e76-b712-4b12-890e-fb6e188f9b63
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=402048466 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_datapath_stress.402048466
Directory /workspace/21.hmac_datapath_stress/latest

Test location /workspace/coverage/default/21.hmac_error.2748646299
Short name T544
Test name
Test status
Simulation time 14204619301 ps
CPU time 56.5 seconds
Started Jun 27 06:47:03 PM PDT 24
Finished Jun 27 06:48:06 PM PDT 24
Peak memory 199996 kb
Host smart-e0f1e52b-9382-4240-86bd-2944a6023879
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748646299 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_error.2748646299
Directory /workspace/21.hmac_error/latest

Test location /workspace/coverage/default/21.hmac_long_msg.2535377042
Short name T165
Test name
Test status
Simulation time 16415486456 ps
CPU time 90.95 seconds
Started Jun 27 06:46:50 PM PDT 24
Finished Jun 27 06:48:31 PM PDT 24
Peak memory 200012 kb
Host smart-02c5145d-af4e-4334-8a91-e068a28035ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535377042 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_long_msg.2535377042
Directory /workspace/21.hmac_long_msg/latest

Test location /workspace/coverage/default/21.hmac_smoke.2899314076
Short name T357
Test name
Test status
Simulation time 10202782384 ps
CPU time 31.86 seconds
Started Jun 27 06:46:58 PM PDT 24
Finished Jun 27 06:47:37 PM PDT 24
Peak memory 199968 kb
Host smart-d5fa7712-2400-4680-a7e3-54c811e5efa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899314076 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_smoke.2899314076
Directory /workspace/21.hmac_smoke/latest

Test location /workspace/coverage/default/21.hmac_stress_all.1092595847
Short name T323
Test name
Test status
Simulation time 51108433518 ps
CPU time 314.62 seconds
Started Jun 27 06:47:04 PM PDT 24
Finished Jun 27 06:52:25 PM PDT 24
Peak memory 627224 kb
Host smart-3ae441eb-d098-458a-a251-9ed9c32f4375
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092595847 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.hmac_stress_all.1092595847
Directory /workspace/21.hmac_stress_all/latest

Test location /workspace/coverage/default/21.hmac_test_hmac_vectors.1861012130
Short name T470
Test name
Test status
Simulation time 98280016 ps
CPU time 1.17 seconds
Started Jun 27 06:46:58 PM PDT 24
Finished Jun 27 06:47:06 PM PDT 24
Peak memory 199896 kb
Host smart-038a5fa6-2994-4b63-99a1-dc93bcea2c5b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861012130 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 21.hmac_test_hmac_vectors.1861012130
Directory /workspace/21.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/21.hmac_test_sha256_vectors.2765136578
Short name T67
Test name
Test status
Simulation time 14889363151 ps
CPU time 414.01 seconds
Started Jun 27 06:46:48 PM PDT 24
Finished Jun 27 06:53:53 PM PDT 24
Peak memory 200048 kb
Host smart-61f0b0d7-618a-4284-bab4-7543830322f1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2765136578 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_test_sha256_vectors.2765136578
Directory /workspace/21.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/21.hmac_test_sha512_vectors.2676357162
Short name T355
Test name
Test status
Simulation time 321114442663 ps
CPU time 1991.62 seconds
Started Jun 27 06:46:58 PM PDT 24
Finished Jun 27 07:20:17 PM PDT 24
Peak memory 208388 kb
Host smart-23609a0b-23e3-4d57-8bc9-313ff3d9430e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2676357162 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_test_sha512_vectors.2676357162
Directory /workspace/21.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/21.hmac_wipe_secret.1115427001
Short name T206
Test name
Test status
Simulation time 14206786259 ps
CPU time 101.6 seconds
Started Jun 27 06:47:03 PM PDT 24
Finished Jun 27 06:48:51 PM PDT 24
Peak memory 200028 kb
Host smart-9d6dfda1-c6d4-49f9-b3a9-7c0931a582db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115427001 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_wipe_secret.1115427001
Directory /workspace/21.hmac_wipe_secret/latest

Test location /workspace/coverage/default/22.hmac_alert_test.2256868194
Short name T507
Test name
Test status
Simulation time 23883236 ps
CPU time 0.64 seconds
Started Jun 27 06:46:48 PM PDT 24
Finished Jun 27 06:46:59 PM PDT 24
Peak memory 196024 kb
Host smart-86ed3990-1462-456d-b34e-c3b6d3ec109b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256868194 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_alert_test.2256868194
Directory /workspace/22.hmac_alert_test/latest

Test location /workspace/coverage/default/22.hmac_back_pressure.130765546
Short name T363
Test name
Test status
Simulation time 695053025 ps
CPU time 14.83 seconds
Started Jun 27 06:46:50 PM PDT 24
Finished Jun 27 06:47:15 PM PDT 24
Peak memory 199944 kb
Host smart-20ddfa00-52f2-4ac7-a994-07cfc1d4a624
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=130765546 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_back_pressure.130765546
Directory /workspace/22.hmac_back_pressure/latest

Test location /workspace/coverage/default/22.hmac_burst_wr.2658517583
Short name T642
Test name
Test status
Simulation time 560553269 ps
CPU time 30.91 seconds
Started Jun 27 06:47:09 PM PDT 24
Finished Jun 27 06:47:46 PM PDT 24
Peak memory 199948 kb
Host smart-775db261-938b-4884-9f4b-5e14cbbf4342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658517583 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_burst_wr.2658517583
Directory /workspace/22.hmac_burst_wr/latest

Test location /workspace/coverage/default/22.hmac_datapath_stress.1769169088
Short name T88
Test name
Test status
Simulation time 2431710139 ps
CPU time 715.29 seconds
Started Jun 27 06:47:04 PM PDT 24
Finished Jun 27 06:59:06 PM PDT 24
Peak memory 693652 kb
Host smart-a11bff3a-0d97-48fb-8fc8-e15a51869f5b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1769169088 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_datapath_stress.1769169088
Directory /workspace/22.hmac_datapath_stress/latest

Test location /workspace/coverage/default/22.hmac_error.4029115280
Short name T191
Test name
Test status
Simulation time 14245194654 ps
CPU time 102.1 seconds
Started Jun 27 06:46:55 PM PDT 24
Finished Jun 27 06:48:46 PM PDT 24
Peak memory 200000 kb
Host smart-f30ab6a9-c5db-4fd3-ac3a-3322bcbcc6dc
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029115280 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_error.4029115280
Directory /workspace/22.hmac_error/latest

Test location /workspace/coverage/default/22.hmac_long_msg.3498256550
Short name T288
Test name
Test status
Simulation time 6524526571 ps
CPU time 97.54 seconds
Started Jun 27 06:47:03 PM PDT 24
Finished Jun 27 06:48:46 PM PDT 24
Peak memory 216224 kb
Host smart-7c7cba3c-1949-49d3-9791-9fce52fa2dac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3498256550 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_long_msg.3498256550
Directory /workspace/22.hmac_long_msg/latest

Test location /workspace/coverage/default/22.hmac_smoke.1432681133
Short name T393
Test name
Test status
Simulation time 253142166 ps
CPU time 10.27 seconds
Started Jun 27 06:47:00 PM PDT 24
Finished Jun 27 06:47:17 PM PDT 24
Peak memory 200012 kb
Host smart-c7b2d71a-3c1d-4dc0-a99c-559674593d56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432681133 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_smoke.1432681133
Directory /workspace/22.hmac_smoke/latest

Test location /workspace/coverage/default/22.hmac_stress_all.2195181102
Short name T131
Test name
Test status
Simulation time 144518481912 ps
CPU time 4053.43 seconds
Started Jun 27 06:46:47 PM PDT 24
Finished Jun 27 07:54:31 PM PDT 24
Peak memory 785520 kb
Host smart-16603859-004e-464a-9eee-66f2bdd01c73
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195181102 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.hmac_stress_all.2195181102
Directory /workspace/22.hmac_stress_all/latest

Test location /workspace/coverage/default/22.hmac_test_hmac_vectors.1851808733
Short name T528
Test name
Test status
Simulation time 582960199 ps
CPU time 1.39 seconds
Started Jun 27 06:46:45 PM PDT 24
Finished Jun 27 06:46:58 PM PDT 24
Peak memory 199920 kb
Host smart-f263eed2-3ffd-4a8b-bd5c-e5cf8fa6cae6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851808733 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 22.hmac_test_hmac_vectors.1851808733
Directory /workspace/22.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/22.hmac_test_sha256_vectors.1881150329
Short name T409
Test name
Test status
Simulation time 163851095099 ps
CPU time 549.8 seconds
Started Jun 27 06:46:54 PM PDT 24
Finished Jun 27 06:56:12 PM PDT 24
Peak memory 200016 kb
Host smart-f1147aa0-2827-4539-93b7-48a21c16eae3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1881150329 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_test_sha256_vectors.1881150329
Directory /workspace/22.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/22.hmac_test_sha384_vectors.1441338184
Short name T51
Test name
Test status
Simulation time 702794067026 ps
CPU time 2213.09 seconds
Started Jun 27 06:46:48 PM PDT 24
Finished Jun 27 07:23:52 PM PDT 24
Peak memory 215912 kb
Host smart-efb709b1-256e-449c-8e19-c8271300526d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1441338184 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_test_sha384_vectors.1441338184
Directory /workspace/22.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/22.hmac_test_sha512_vectors.2799279690
Short name T308
Test name
Test status
Simulation time 711440242210 ps
CPU time 2050.74 seconds
Started Jun 27 06:46:57 PM PDT 24
Finished Jun 27 07:21:15 PM PDT 24
Peak memory 216068 kb
Host smart-faa179b3-98ec-4a7f-a828-38ef77ddc61a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2799279690 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_test_sha512_vectors.2799279690
Directory /workspace/22.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/22.hmac_wipe_secret.1074805200
Short name T603
Test name
Test status
Simulation time 2718718417 ps
CPU time 30.06 seconds
Started Jun 27 06:46:49 PM PDT 24
Finished Jun 27 06:47:29 PM PDT 24
Peak memory 200008 kb
Host smart-29a1a255-b117-4509-a8bd-bd284b8d9394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1074805200 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_wipe_secret.1074805200
Directory /workspace/22.hmac_wipe_secret/latest

Test location /workspace/coverage/default/23.hmac_alert_test.479770693
Short name T515
Test name
Test status
Simulation time 17268110 ps
CPU time 0.57 seconds
Started Jun 27 06:46:50 PM PDT 24
Finished Jun 27 06:47:01 PM PDT 24
Peak memory 194980 kb
Host smart-5ab752e0-6ded-4ab6-b6d0-681c70fb6cea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479770693 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_alert_test.479770693
Directory /workspace/23.hmac_alert_test/latest

Test location /workspace/coverage/default/23.hmac_back_pressure.28497532
Short name T574
Test name
Test status
Simulation time 1402947203 ps
CPU time 18.29 seconds
Started Jun 27 06:46:55 PM PDT 24
Finished Jun 27 06:47:22 PM PDT 24
Peak memory 199964 kb
Host smart-2c679d33-f51c-4ba7-b9fa-60da29864a4d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=28497532 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_back_pressure.28497532
Directory /workspace/23.hmac_back_pressure/latest

Test location /workspace/coverage/default/23.hmac_burst_wr.3729523612
Short name T356
Test name
Test status
Simulation time 961487119 ps
CPU time 51.27 seconds
Started Jun 27 06:46:47 PM PDT 24
Finished Jun 27 06:47:50 PM PDT 24
Peak memory 199968 kb
Host smart-40de2788-56fb-4a6f-bf12-b9d1882aece9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3729523612 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_burst_wr.3729523612
Directory /workspace/23.hmac_burst_wr/latest

Test location /workspace/coverage/default/23.hmac_datapath_stress.1985929822
Short name T453
Test name
Test status
Simulation time 4693186977 ps
CPU time 292.77 seconds
Started Jun 27 06:46:58 PM PDT 24
Finished Jun 27 06:51:58 PM PDT 24
Peak memory 639516 kb
Host smart-53503083-4cc3-4b38-bba3-75ab86b3d016
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1985929822 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_datapath_stress.1985929822
Directory /workspace/23.hmac_datapath_stress/latest

Test location /workspace/coverage/default/23.hmac_error.3998200323
Short name T35
Test name
Test status
Simulation time 6198914831 ps
CPU time 74.84 seconds
Started Jun 27 06:46:47 PM PDT 24
Finished Jun 27 06:48:12 PM PDT 24
Peak memory 200020 kb
Host smart-0be945e5-bd38-4333-acaa-2586834febb3
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998200323 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_error.3998200323
Directory /workspace/23.hmac_error/latest

Test location /workspace/coverage/default/23.hmac_long_msg.2003238511
Short name T329
Test name
Test status
Simulation time 1969299102 ps
CPU time 35.81 seconds
Started Jun 27 06:46:48 PM PDT 24
Finished Jun 27 06:47:34 PM PDT 24
Peak memory 200024 kb
Host smart-33399f90-3e01-4e2a-b02a-313c90937854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003238511 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_long_msg.2003238511
Directory /workspace/23.hmac_long_msg/latest

Test location /workspace/coverage/default/23.hmac_smoke.2224832795
Short name T297
Test name
Test status
Simulation time 4359298211 ps
CPU time 6.59 seconds
Started Jun 27 06:46:55 PM PDT 24
Finished Jun 27 06:47:10 PM PDT 24
Peak memory 200040 kb
Host smart-c3a43df2-e9aa-49b6-bae8-6ffafa5693a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224832795 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_smoke.2224832795
Directory /workspace/23.hmac_smoke/latest

Test location /workspace/coverage/default/23.hmac_stress_all.3530137897
Short name T74
Test name
Test status
Simulation time 307485288938 ps
CPU time 4143.39 seconds
Started Jun 27 06:46:49 PM PDT 24
Finished Jun 27 07:56:03 PM PDT 24
Peak memory 489052 kb
Host smart-a9eb36a5-5b19-4327-958b-ef12ce5894bd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530137897 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.hmac_stress_all.3530137897
Directory /workspace/23.hmac_stress_all/latest

Test location /workspace/coverage/default/23.hmac_test_hmac_vectors.3507017229
Short name T208
Test name
Test status
Simulation time 182419789 ps
CPU time 1.24 seconds
Started Jun 27 06:46:49 PM PDT 24
Finished Jun 27 06:47:00 PM PDT 24
Peak memory 199856 kb
Host smart-bcff5127-9c6a-41af-9c86-a39b3f9e9a16
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507017229 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 23.hmac_test_hmac_vectors.3507017229
Directory /workspace/23.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/23.hmac_test_sha256_vectors.693571396
Short name T619
Test name
Test status
Simulation time 31760094138 ps
CPU time 441.01 seconds
Started Jun 27 06:46:49 PM PDT 24
Finished Jun 27 06:54:20 PM PDT 24
Peak memory 200000 kb
Host smart-e236bc8a-641b-4806-869a-cffa811cb591
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=693571396 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_test_sha256_vectors.693571396
Directory /workspace/23.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/23.hmac_test_sha384_vectors.1845578677
Short name T686
Test name
Test status
Simulation time 597847889560 ps
CPU time 2080.18 seconds
Started Jun 27 06:46:49 PM PDT 24
Finished Jun 27 07:21:39 PM PDT 24
Peak memory 215640 kb
Host smart-d3358198-a1e5-42fd-a078-8e6b2944e249
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1845578677 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_test_sha384_vectors.1845578677
Directory /workspace/23.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/23.hmac_test_sha512_vectors.1434440506
Short name T372
Test name
Test status
Simulation time 609787254901 ps
CPU time 1939.19 seconds
Started Jun 27 06:46:47 PM PDT 24
Finished Jun 27 07:19:18 PM PDT 24
Peak memory 215864 kb
Host smart-f0cf03db-be9b-49b9-889f-4cf5d35b87f1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1434440506 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_test_sha512_vectors.1434440506
Directory /workspace/23.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/23.hmac_wipe_secret.3165426753
Short name T426
Test name
Test status
Simulation time 14910167382 ps
CPU time 65.92 seconds
Started Jun 27 06:46:48 PM PDT 24
Finished Jun 27 06:48:04 PM PDT 24
Peak memory 200028 kb
Host smart-e393cc24-12ba-419a-b1db-5e75314e6933
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165426753 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_wipe_secret.3165426753
Directory /workspace/23.hmac_wipe_secret/latest

Test location /workspace/coverage/default/24.hmac_alert_test.602612097
Short name T175
Test name
Test status
Simulation time 44868925 ps
CPU time 0.58 seconds
Started Jun 27 06:47:11 PM PDT 24
Finished Jun 27 06:47:18 PM PDT 24
Peak memory 196004 kb
Host smart-b3d48d10-c395-4283-be5a-e6171c560a45
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602612097 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_alert_test.602612097
Directory /workspace/24.hmac_alert_test/latest

Test location /workspace/coverage/default/24.hmac_back_pressure.2983005946
Short name T473
Test name
Test status
Simulation time 433805041 ps
CPU time 20.68 seconds
Started Jun 27 06:46:57 PM PDT 24
Finished Jun 27 06:47:25 PM PDT 24
Peak memory 199892 kb
Host smart-1d14d20a-17f5-4c73-9a19-9ae27c2ca5a6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2983005946 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_back_pressure.2983005946
Directory /workspace/24.hmac_back_pressure/latest

Test location /workspace/coverage/default/24.hmac_burst_wr.1114687650
Short name T655
Test name
Test status
Simulation time 1187457344 ps
CPU time 14.41 seconds
Started Jun 27 06:46:51 PM PDT 24
Finished Jun 27 06:47:15 PM PDT 24
Peak memory 199960 kb
Host smart-c73a5bce-5b97-459e-91de-95b240ef8003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114687650 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_burst_wr.1114687650
Directory /workspace/24.hmac_burst_wr/latest

Test location /workspace/coverage/default/24.hmac_datapath_stress.541538379
Short name T362
Test name
Test status
Simulation time 17317440367 ps
CPU time 709.09 seconds
Started Jun 27 06:47:03 PM PDT 24
Finished Jun 27 06:58:58 PM PDT 24
Peak memory 669344 kb
Host smart-c9cf99ab-4091-4375-8684-e7289cba7bdc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=541538379 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_datapath_stress.541538379
Directory /workspace/24.hmac_datapath_stress/latest

Test location /workspace/coverage/default/24.hmac_error.3952985096
Short name T271
Test name
Test status
Simulation time 7844979991 ps
CPU time 78.9 seconds
Started Jun 27 06:46:53 PM PDT 24
Finished Jun 27 06:48:21 PM PDT 24
Peak memory 199932 kb
Host smart-007e8a20-8f3a-478c-8ec4-0cf9cc960bf7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952985096 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_error.3952985096
Directory /workspace/24.hmac_error/latest

Test location /workspace/coverage/default/24.hmac_long_msg.2568155425
Short name T487
Test name
Test status
Simulation time 796678571 ps
CPU time 23.53 seconds
Started Jun 27 06:46:57 PM PDT 24
Finished Jun 27 06:47:28 PM PDT 24
Peak memory 199964 kb
Host smart-07410fcc-aafb-41e1-9986-22f489fa21ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568155425 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_long_msg.2568155425
Directory /workspace/24.hmac_long_msg/latest

Test location /workspace/coverage/default/24.hmac_smoke.3318425015
Short name T538
Test name
Test status
Simulation time 237656967 ps
CPU time 4.48 seconds
Started Jun 27 06:47:04 PM PDT 24
Finished Jun 27 06:47:15 PM PDT 24
Peak memory 199936 kb
Host smart-8021a96a-f279-4e41-a212-67a526614198
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3318425015 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_smoke.3318425015
Directory /workspace/24.hmac_smoke/latest

Test location /workspace/coverage/default/24.hmac_stress_all.4124843269
Short name T350
Test name
Test status
Simulation time 1329106237431 ps
CPU time 5687.66 seconds
Started Jun 27 06:47:07 PM PDT 24
Finished Jun 27 08:22:02 PM PDT 24
Peak memory 215652 kb
Host smart-053c4e5b-d09c-414e-9fc0-be91b5070abc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124843269 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.hmac_stress_all.4124843269
Directory /workspace/24.hmac_stress_all/latest

Test location /workspace/coverage/default/24.hmac_test_hmac_vectors.1028755316
Short name T84
Test name
Test status
Simulation time 234825074 ps
CPU time 1.39 seconds
Started Jun 27 06:47:08 PM PDT 24
Finished Jun 27 06:47:15 PM PDT 24
Peak memory 199892 kb
Host smart-cb1db456-0435-481b-947e-cdf0d5572927
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028755316 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 24.hmac_test_hmac_vectors.1028755316
Directory /workspace/24.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/24.hmac_test_sha256_vectors.1436340514
Short name T454
Test name
Test status
Simulation time 45154527681 ps
CPU time 579.68 seconds
Started Jun 27 06:47:10 PM PDT 24
Finished Jun 27 06:56:56 PM PDT 24
Peak memory 200016 kb
Host smart-29e3951c-c3e6-42ed-b47f-6b1c71d72067
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1436340514 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_test_sha256_vectors.1436340514
Directory /workspace/24.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/24.hmac_test_sha384_vectors.3262337481
Short name T367
Test name
Test status
Simulation time 272135088789 ps
CPU time 1864.64 seconds
Started Jun 27 06:47:05 PM PDT 24
Finished Jun 27 07:18:16 PM PDT 24
Peak memory 216324 kb
Host smart-59f26421-feee-4aea-84ae-065b1141f84a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3262337481 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_test_sha384_vectors.3262337481
Directory /workspace/24.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/24.hmac_test_sha512_vectors.1643788844
Short name T579
Test name
Test status
Simulation time 151297261317 ps
CPU time 1947.77 seconds
Started Jun 27 06:47:10 PM PDT 24
Finished Jun 27 07:19:45 PM PDT 24
Peak memory 216396 kb
Host smart-2e693e13-6eb0-486d-b7f1-53aa1a96d352
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1643788844 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_test_sha512_vectors.1643788844
Directory /workspace/24.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/24.hmac_wipe_secret.275638564
Short name T7
Test name
Test status
Simulation time 5893596069 ps
CPU time 43.05 seconds
Started Jun 27 06:47:04 PM PDT 24
Finished Jun 27 06:47:54 PM PDT 24
Peak memory 200000 kb
Host smart-b607345d-989f-4573-ab55-6e5d17aebd2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275638564 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_wipe_secret.275638564
Directory /workspace/24.hmac_wipe_secret/latest

Test location /workspace/coverage/default/25.hmac_alert_test.2092322803
Short name T667
Test name
Test status
Simulation time 19296354 ps
CPU time 0.59 seconds
Started Jun 27 06:47:08 PM PDT 24
Finished Jun 27 06:47:16 PM PDT 24
Peak memory 194960 kb
Host smart-53aa9eab-d2e7-401f-a0dd-03b398328579
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092322803 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_alert_test.2092322803
Directory /workspace/25.hmac_alert_test/latest

Test location /workspace/coverage/default/25.hmac_back_pressure.1997282221
Short name T189
Test name
Test status
Simulation time 721713427 ps
CPU time 35.67 seconds
Started Jun 27 06:47:11 PM PDT 24
Finished Jun 27 06:47:52 PM PDT 24
Peak memory 199932 kb
Host smart-fdeeb09e-5106-4007-a8a0-365d2b70a206
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1997282221 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_back_pressure.1997282221
Directory /workspace/25.hmac_back_pressure/latest

Test location /workspace/coverage/default/25.hmac_burst_wr.2665350566
Short name T452
Test name
Test status
Simulation time 2171953366 ps
CPU time 30.14 seconds
Started Jun 27 06:47:06 PM PDT 24
Finished Jun 27 06:47:43 PM PDT 24
Peak memory 200040 kb
Host smart-9fbebaa1-5fdc-4063-8615-b4ebf7b91e07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665350566 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_burst_wr.2665350566
Directory /workspace/25.hmac_burst_wr/latest

Test location /workspace/coverage/default/25.hmac_datapath_stress.1521805603
Short name T553
Test name
Test status
Simulation time 10217293260 ps
CPU time 1521.82 seconds
Started Jun 27 06:47:11 PM PDT 24
Finished Jun 27 07:12:39 PM PDT 24
Peak memory 763776 kb
Host smart-e029ca33-a70e-4730-ba43-21a5a22783c5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1521805603 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_datapath_stress.1521805603
Directory /workspace/25.hmac_datapath_stress/latest

Test location /workspace/coverage/default/25.hmac_error.3160586532
Short name T162
Test name
Test status
Simulation time 6666258110 ps
CPU time 94.69 seconds
Started Jun 27 06:47:07 PM PDT 24
Finished Jun 27 06:48:48 PM PDT 24
Peak memory 200048 kb
Host smart-bd971995-4909-467b-91e5-23b785fd17e0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160586532 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_error.3160586532
Directory /workspace/25.hmac_error/latest

Test location /workspace/coverage/default/25.hmac_long_msg.1315332792
Short name T163
Test name
Test status
Simulation time 28027371743 ps
CPU time 138.7 seconds
Started Jun 27 06:47:08 PM PDT 24
Finished Jun 27 06:49:33 PM PDT 24
Peak memory 216212 kb
Host smart-cbbc2785-61a2-4213-9154-d0ea00076ef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315332792 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_long_msg.1315332792
Directory /workspace/25.hmac_long_msg/latest

Test location /workspace/coverage/default/25.hmac_smoke.2131096820
Short name T181
Test name
Test status
Simulation time 320673024 ps
CPU time 3.83 seconds
Started Jun 27 06:47:04 PM PDT 24
Finished Jun 27 06:47:14 PM PDT 24
Peak memory 200012 kb
Host smart-3fb50425-a713-40d3-bcc8-0edcb11fe9d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2131096820 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_smoke.2131096820
Directory /workspace/25.hmac_smoke/latest

Test location /workspace/coverage/default/25.hmac_stress_all.2799162836
Short name T243
Test name
Test status
Simulation time 191077508389 ps
CPU time 2419.36 seconds
Started Jun 27 06:47:07 PM PDT 24
Finished Jun 27 07:27:33 PM PDT 24
Peak memory 216440 kb
Host smart-cd91e5ae-d490-48fe-807a-68e38927f170
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799162836 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.hmac_stress_all.2799162836
Directory /workspace/25.hmac_stress_all/latest

Test location /workspace/coverage/default/25.hmac_test_hmac_vectors.3524517393
Short name T274
Test name
Test status
Simulation time 71517864 ps
CPU time 1.35 seconds
Started Jun 27 06:47:08 PM PDT 24
Finished Jun 27 06:47:15 PM PDT 24
Peak memory 200124 kb
Host smart-ac22a5c3-cf04-471b-b693-8c4aaf26ee8b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524517393 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 25.hmac_test_hmac_vectors.3524517393
Directory /workspace/25.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/25.hmac_test_sha256_vectors.854082136
Short name T260
Test name
Test status
Simulation time 46643998431 ps
CPU time 602.19 seconds
Started Jun 27 06:47:06 PM PDT 24
Finished Jun 27 06:57:15 PM PDT 24
Peak memory 200052 kb
Host smart-650efb48-50fd-46d2-b753-b1005595ddb7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=854082136 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_test_sha256_vectors.854082136
Directory /workspace/25.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/25.hmac_test_sha384_vectors.115983762
Short name T557
Test name
Test status
Simulation time 503550373468 ps
CPU time 1996.44 seconds
Started Jun 27 06:47:09 PM PDT 24
Finished Jun 27 07:20:32 PM PDT 24
Peak memory 215500 kb
Host smart-f1450318-d95f-4f38-a9df-04bcd5d2ee9e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=115983762 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_test_sha384_vectors.115983762
Directory /workspace/25.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/25.hmac_test_sha512_vectors.2710810069
Short name T594
Test name
Test status
Simulation time 329447742083 ps
CPU time 1633.57 seconds
Started Jun 27 06:47:11 PM PDT 24
Finished Jun 27 07:14:31 PM PDT 24
Peak memory 215772 kb
Host smart-8c81ff3c-860c-440a-a4bb-7a8da3050211
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2710810069 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_test_sha512_vectors.2710810069
Directory /workspace/25.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/25.hmac_wipe_secret.1568577173
Short name T332
Test name
Test status
Simulation time 1590833831 ps
CPU time 8.03 seconds
Started Jun 27 06:47:08 PM PDT 24
Finished Jun 27 06:47:22 PM PDT 24
Peak memory 199948 kb
Host smart-adc04b82-fdba-4cfe-bcbf-c153a81d7b02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568577173 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_wipe_secret.1568577173
Directory /workspace/25.hmac_wipe_secret/latest

Test location /workspace/coverage/default/26.hmac_alert_test.2424763856
Short name T551
Test name
Test status
Simulation time 57249456 ps
CPU time 0.58 seconds
Started Jun 27 06:47:08 PM PDT 24
Finished Jun 27 06:47:15 PM PDT 24
Peak memory 195756 kb
Host smart-31ca7148-6db9-4e26-abd5-4678098a40cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424763856 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_alert_test.2424763856
Directory /workspace/26.hmac_alert_test/latest

Test location /workspace/coverage/default/26.hmac_burst_wr.1347225180
Short name T488
Test name
Test status
Simulation time 8594159207 ps
CPU time 50.09 seconds
Started Jun 27 06:47:09 PM PDT 24
Finished Jun 27 06:48:06 PM PDT 24
Peak memory 200144 kb
Host smart-c850cc69-82b8-456a-9328-df1d2f05ed18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347225180 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_burst_wr.1347225180
Directory /workspace/26.hmac_burst_wr/latest

Test location /workspace/coverage/default/26.hmac_datapath_stress.1380904941
Short name T361
Test name
Test status
Simulation time 1878106207 ps
CPU time 266.38 seconds
Started Jun 27 06:47:10 PM PDT 24
Finished Jun 27 06:51:43 PM PDT 24
Peak memory 421128 kb
Host smart-8aa75e3b-e3bb-492b-b549-098b2db7eb4a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1380904941 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_datapath_stress.1380904941
Directory /workspace/26.hmac_datapath_stress/latest

Test location /workspace/coverage/default/26.hmac_error.3529940704
Short name T364
Test name
Test status
Simulation time 6974111885 ps
CPU time 125.2 seconds
Started Jun 27 06:47:08 PM PDT 24
Finished Jun 27 06:49:19 PM PDT 24
Peak memory 199992 kb
Host smart-70acf8df-ba1d-40a2-817e-c1118cb40711
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529940704 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_error.3529940704
Directory /workspace/26.hmac_error/latest

Test location /workspace/coverage/default/26.hmac_long_msg.4136383973
Short name T178
Test name
Test status
Simulation time 897377072 ps
CPU time 50.95 seconds
Started Jun 27 06:47:06 PM PDT 24
Finished Jun 27 06:48:03 PM PDT 24
Peak memory 199964 kb
Host smart-9bc172d4-0e5f-4f56-8d81-8f3919fe1b50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136383973 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_long_msg.4136383973
Directory /workspace/26.hmac_long_msg/latest

Test location /workspace/coverage/default/26.hmac_smoke.1786460405
Short name T542
Test name
Test status
Simulation time 167687303 ps
CPU time 2.57 seconds
Started Jun 27 06:47:08 PM PDT 24
Finished Jun 27 06:47:17 PM PDT 24
Peak memory 200000 kb
Host smart-253c80c4-5b98-44bd-a65d-45701082f6ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786460405 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_smoke.1786460405
Directory /workspace/26.hmac_smoke/latest

Test location /workspace/coverage/default/26.hmac_stress_all.4048089710
Short name T695
Test name
Test status
Simulation time 89874466475 ps
CPU time 470.52 seconds
Started Jun 27 06:47:05 PM PDT 24
Finished Jun 27 06:55:02 PM PDT 24
Peak memory 579536 kb
Host smart-a86f5c06-a513-4b5b-b2ae-99791aba4cf3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048089710 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.hmac_stress_all.4048089710
Directory /workspace/26.hmac_stress_all/latest

Test location /workspace/coverage/default/26.hmac_test_hmac_vectors.3857212884
Short name T685
Test name
Test status
Simulation time 227452493 ps
CPU time 1.14 seconds
Started Jun 27 06:47:07 PM PDT 24
Finished Jun 27 06:47:15 PM PDT 24
Peak memory 199728 kb
Host smart-1b4bbc3e-a25b-46f7-b42e-919db6ca6a67
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857212884 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 26.hmac_test_hmac_vectors.3857212884
Directory /workspace/26.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/26.hmac_test_sha256_vectors.2986463140
Short name T334
Test name
Test status
Simulation time 15761861645 ps
CPU time 425.39 seconds
Started Jun 27 06:47:13 PM PDT 24
Finished Jun 27 06:54:23 PM PDT 24
Peak memory 200000 kb
Host smart-79f45adb-d604-4b54-b960-be33651c43f1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2986463140 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_test_sha256_vectors.2986463140
Directory /workspace/26.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/26.hmac_test_sha384_vectors.258931183
Short name T637
Test name
Test status
Simulation time 136346196207 ps
CPU time 1844.79 seconds
Started Jun 27 06:47:05 PM PDT 24
Finished Jun 27 07:17:56 PM PDT 24
Peak memory 216196 kb
Host smart-6527f296-d8b9-45da-b092-46afdd009597
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=258931183 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_test_sha384_vectors.258931183
Directory /workspace/26.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/26.hmac_test_sha512_vectors.2382406870
Short name T200
Test name
Test status
Simulation time 512515955291 ps
CPU time 1761.14 seconds
Started Jun 27 06:47:10 PM PDT 24
Finished Jun 27 07:16:38 PM PDT 24
Peak memory 216436 kb
Host smart-b33d83bc-468c-4a4c-8bd0-372a8612820c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2382406870 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_test_sha512_vectors.2382406870
Directory /workspace/26.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/26.hmac_wipe_secret.1769347177
Short name T359
Test name
Test status
Simulation time 7584756060 ps
CPU time 25.38 seconds
Started Jun 27 06:47:08 PM PDT 24
Finished Jun 27 06:47:40 PM PDT 24
Peak memory 200204 kb
Host smart-6f70b9a0-f1d7-4aff-964a-306c945d5080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769347177 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_wipe_secret.1769347177
Directory /workspace/26.hmac_wipe_secret/latest

Test location /workspace/coverage/default/27.hmac_alert_test.1794793685
Short name T547
Test name
Test status
Simulation time 15035177 ps
CPU time 0.62 seconds
Started Jun 27 06:47:07 PM PDT 24
Finished Jun 27 06:47:14 PM PDT 24
Peak memory 196016 kb
Host smart-e0f349ca-d4b9-4697-abaf-e1577df221cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794793685 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_alert_test.1794793685
Directory /workspace/27.hmac_alert_test/latest

Test location /workspace/coverage/default/27.hmac_back_pressure.3692456857
Short name T252
Test name
Test status
Simulation time 1905151115 ps
CPU time 45.84 seconds
Started Jun 27 06:47:07 PM PDT 24
Finished Jun 27 06:47:59 PM PDT 24
Peak memory 200004 kb
Host smart-38ccb075-2c30-45a8-8e31-4b31c7e516a4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3692456857 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_back_pressure.3692456857
Directory /workspace/27.hmac_back_pressure/latest

Test location /workspace/coverage/default/27.hmac_burst_wr.3759500866
Short name T155
Test name
Test status
Simulation time 427440590 ps
CPU time 4.62 seconds
Started Jun 27 06:47:09 PM PDT 24
Finished Jun 27 06:47:20 PM PDT 24
Peak memory 199908 kb
Host smart-5d396737-0960-4552-8a15-3f513294dd1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759500866 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_burst_wr.3759500866
Directory /workspace/27.hmac_burst_wr/latest

Test location /workspace/coverage/default/27.hmac_datapath_stress.190571354
Short name T280
Test name
Test status
Simulation time 7014601498 ps
CPU time 412.85 seconds
Started Jun 27 06:47:17 PM PDT 24
Finished Jun 27 06:54:12 PM PDT 24
Peak memory 668876 kb
Host smart-2098ebe9-5107-45af-9afa-c72239612c8b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=190571354 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_datapath_stress.190571354
Directory /workspace/27.hmac_datapath_stress/latest

Test location /workspace/coverage/default/27.hmac_error.1044833007
Short name T154
Test name
Test status
Simulation time 157274358 ps
CPU time 1.2 seconds
Started Jun 27 06:47:07 PM PDT 24
Finished Jun 27 06:47:14 PM PDT 24
Peak memory 199856 kb
Host smart-eddd7e97-c2b4-4491-a56c-ad3ee02abcb3
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044833007 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_error.1044833007
Directory /workspace/27.hmac_error/latest

Test location /workspace/coverage/default/27.hmac_long_msg.3755873356
Short name T33
Test name
Test status
Simulation time 18417541339 ps
CPU time 119.95 seconds
Started Jun 27 06:47:04 PM PDT 24
Finished Jun 27 06:49:10 PM PDT 24
Peak memory 200072 kb
Host smart-9ccb6e82-fb89-4b11-aa0b-883e13803246
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755873356 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_long_msg.3755873356
Directory /workspace/27.hmac_long_msg/latest

Test location /workspace/coverage/default/27.hmac_smoke.3949278342
Short name T153
Test name
Test status
Simulation time 5106946918 ps
CPU time 22.49 seconds
Started Jun 27 06:47:06 PM PDT 24
Finished Jun 27 06:47:35 PM PDT 24
Peak memory 200032 kb
Host smart-d44a80a8-332c-4bd6-8d07-939b35e16aa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949278342 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_smoke.3949278342
Directory /workspace/27.hmac_smoke/latest

Test location /workspace/coverage/default/27.hmac_stress_all.2372947169
Short name T75
Test name
Test status
Simulation time 417790167688 ps
CPU time 3570.17 seconds
Started Jun 27 06:47:10 PM PDT 24
Finished Jun 27 07:46:47 PM PDT 24
Peak memory 741836 kb
Host smart-55d98cfc-6d2c-470a-8c56-7800fb190de3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372947169 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.hmac_stress_all.2372947169
Directory /workspace/27.hmac_stress_all/latest

Test location /workspace/coverage/default/27.hmac_test_hmac_vectors.839991399
Short name T425
Test name
Test status
Simulation time 84828887 ps
CPU time 1.4 seconds
Started Jun 27 06:47:10 PM PDT 24
Finished Jun 27 06:47:18 PM PDT 24
Peak memory 199996 kb
Host smart-0cbab09e-3cbc-423f-816b-a9193ab44b9f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839991399 -assert nopostpr
oc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 27.hmac_test_hmac_vectors.839991399
Directory /workspace/27.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/27.hmac_test_sha256_vectors.3637881040
Short name T314
Test name
Test status
Simulation time 41264398294 ps
CPU time 523.48 seconds
Started Jun 27 06:47:05 PM PDT 24
Finished Jun 27 06:55:55 PM PDT 24
Peak memory 200048 kb
Host smart-0f32b24a-e2af-4171-884f-5dc84ad8cb22
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3637881040 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_test_sha256_vectors.3637881040
Directory /workspace/27.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/27.hmac_test_sha512_vectors.3848532048
Short name T514
Test name
Test status
Simulation time 416893837698 ps
CPU time 1897.52 seconds
Started Jun 27 06:47:10 PM PDT 24
Finished Jun 27 07:18:54 PM PDT 24
Peak memory 216388 kb
Host smart-c361dfb6-7bab-4127-ab13-a9881260b253
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3848532048 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_test_sha512_vectors.3848532048
Directory /workspace/27.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/27.hmac_wipe_secret.3859205759
Short name T617
Test name
Test status
Simulation time 3626818748 ps
CPU time 39.02 seconds
Started Jun 27 06:47:07 PM PDT 24
Finished Jun 27 06:47:53 PM PDT 24
Peak memory 200072 kb
Host smart-00fbb0c2-252c-4814-b1be-082e34e8e018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859205759 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_wipe_secret.3859205759
Directory /workspace/27.hmac_wipe_secret/latest

Test location /workspace/coverage/default/28.hmac_alert_test.109920393
Short name T312
Test name
Test status
Simulation time 25062429 ps
CPU time 0.58 seconds
Started Jun 27 06:47:07 PM PDT 24
Finished Jun 27 06:47:13 PM PDT 24
Peak memory 196772 kb
Host smart-14f07e0d-889d-4e50-be90-c88ca0e5db76
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109920393 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_alert_test.109920393
Directory /workspace/28.hmac_alert_test/latest

Test location /workspace/coverage/default/28.hmac_back_pressure.3347455419
Short name T437
Test name
Test status
Simulation time 3218373585 ps
CPU time 33.58 seconds
Started Jun 27 06:47:04 PM PDT 24
Finished Jun 27 06:47:44 PM PDT 24
Peak memory 200056 kb
Host smart-b0fddb33-5815-44ac-8ac9-ffadef1fa7c8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3347455419 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_back_pressure.3347455419
Directory /workspace/28.hmac_back_pressure/latest

Test location /workspace/coverage/default/28.hmac_burst_wr.325556074
Short name T505
Test name
Test status
Simulation time 2639431426 ps
CPU time 39.96 seconds
Started Jun 27 06:47:08 PM PDT 24
Finished Jun 27 06:47:54 PM PDT 24
Peak memory 200032 kb
Host smart-1e671758-b8aa-423d-bd2a-fa389a10be2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325556074 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_burst_wr.325556074
Directory /workspace/28.hmac_burst_wr/latest

Test location /workspace/coverage/default/28.hmac_datapath_stress.2096728820
Short name T158
Test name
Test status
Simulation time 12394749379 ps
CPU time 325.95 seconds
Started Jun 27 06:47:09 PM PDT 24
Finished Jun 27 06:52:42 PM PDT 24
Peak memory 478112 kb
Host smart-bfdcbcb7-cbc2-40c1-8687-8344c11a4b17
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2096728820 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_datapath_stress.2096728820
Directory /workspace/28.hmac_datapath_stress/latest

Test location /workspace/coverage/default/28.hmac_error.4282200899
Short name T584
Test name
Test status
Simulation time 18917186672 ps
CPU time 79.45 seconds
Started Jun 27 06:47:06 PM PDT 24
Finished Jun 27 06:48:31 PM PDT 24
Peak memory 200008 kb
Host smart-0715bcc2-cdd8-4148-a1e1-58d028fe7c4b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282200899 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_error.4282200899
Directory /workspace/28.hmac_error/latest

Test location /workspace/coverage/default/28.hmac_long_msg.557617871
Short name T534
Test name
Test status
Simulation time 7617934727 ps
CPU time 102.8 seconds
Started Jun 27 06:47:08 PM PDT 24
Finished Jun 27 06:48:58 PM PDT 24
Peak memory 200024 kb
Host smart-24897460-7d25-49c8-a68f-cf042f0ed5b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=557617871 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_long_msg.557617871
Directory /workspace/28.hmac_long_msg/latest

Test location /workspace/coverage/default/28.hmac_smoke.1477164707
Short name T414
Test name
Test status
Simulation time 926970817 ps
CPU time 8.46 seconds
Started Jun 27 06:47:06 PM PDT 24
Finished Jun 27 06:47:21 PM PDT 24
Peak memory 199980 kb
Host smart-a7c05b23-9657-4c5b-9e81-65628361b08b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1477164707 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_smoke.1477164707
Directory /workspace/28.hmac_smoke/latest

Test location /workspace/coverage/default/28.hmac_stress_all.3680051510
Short name T434
Test name
Test status
Simulation time 41481573785 ps
CPU time 619.66 seconds
Started Jun 27 06:47:08 PM PDT 24
Finished Jun 27 06:57:34 PM PDT 24
Peak memory 472520 kb
Host smart-9dff41b4-78f2-4916-92d8-70a1ea00e50a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680051510 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.hmac_stress_all.3680051510
Directory /workspace/28.hmac_stress_all/latest

Test location /workspace/coverage/default/28.hmac_test_hmac_vectors.439184391
Short name T530
Test name
Test status
Simulation time 85437379 ps
CPU time 1.48 seconds
Started Jun 27 06:47:10 PM PDT 24
Finished Jun 27 06:47:18 PM PDT 24
Peak memory 200000 kb
Host smart-a042e6a3-11a4-4099-9ec7-e15086a8933b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439184391 -assert nopostpr
oc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 28.hmac_test_hmac_vectors.439184391
Directory /workspace/28.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/28.hmac_test_sha256_vectors.3197772956
Short name T412
Test name
Test status
Simulation time 138870495227 ps
CPU time 470.48 seconds
Started Jun 27 06:47:09 PM PDT 24
Finished Jun 27 06:55:06 PM PDT 24
Peak memory 199908 kb
Host smart-db51c86e-b01d-4510-b0cf-15d95b73e5dc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3197772956 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_test_sha256_vectors.3197772956
Directory /workspace/28.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/28.hmac_test_sha384_vectors.1252314251
Short name T446
Test name
Test status
Simulation time 132733790140 ps
CPU time 1926.81 seconds
Started Jun 27 06:47:10 PM PDT 24
Finished Jun 27 07:19:23 PM PDT 24
Peak memory 216328 kb
Host smart-c8086141-2e54-4b89-b541-6772284a2fad
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1252314251 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_test_sha384_vectors.1252314251
Directory /workspace/28.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/28.hmac_test_sha512_vectors.4192372908
Short name T52
Test name
Test status
Simulation time 152548191148 ps
CPU time 1988.12 seconds
Started Jun 27 06:47:06 PM PDT 24
Finished Jun 27 07:20:21 PM PDT 24
Peak memory 216368 kb
Host smart-0000e962-5dfe-4986-8d16-1478b1b290a2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4192372908 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_test_sha512_vectors.4192372908
Directory /workspace/28.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/28.hmac_wipe_secret.1220001557
Short name T431
Test name
Test status
Simulation time 1775788383 ps
CPU time 58.88 seconds
Started Jun 27 06:47:08 PM PDT 24
Finished Jun 27 06:48:13 PM PDT 24
Peak memory 199968 kb
Host smart-fed657b7-9d8b-4797-88fb-3930fa7a642b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220001557 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_wipe_secret.1220001557
Directory /workspace/28.hmac_wipe_secret/latest

Test location /workspace/coverage/default/29.hmac_alert_test.1457021256
Short name T209
Test name
Test status
Simulation time 33383934 ps
CPU time 0.57 seconds
Started Jun 27 06:47:22 PM PDT 24
Finished Jun 27 06:47:25 PM PDT 24
Peak memory 194972 kb
Host smart-92d732ab-92d6-4dd0-8187-10cff54ed47f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457021256 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_alert_test.1457021256
Directory /workspace/29.hmac_alert_test/latest

Test location /workspace/coverage/default/29.hmac_back_pressure.3064292963
Short name T440
Test name
Test status
Simulation time 829782785 ps
CPU time 37.13 seconds
Started Jun 27 06:47:08 PM PDT 24
Finished Jun 27 06:47:52 PM PDT 24
Peak memory 199904 kb
Host smart-f8ee5fca-303a-47dd-9f77-c149cf437688
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3064292963 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_back_pressure.3064292963
Directory /workspace/29.hmac_back_pressure/latest

Test location /workspace/coverage/default/29.hmac_burst_wr.2334988483
Short name T354
Test name
Test status
Simulation time 3196576944 ps
CPU time 61.39 seconds
Started Jun 27 06:47:22 PM PDT 24
Finished Jun 27 06:48:27 PM PDT 24
Peak memory 200008 kb
Host smart-3884fa5c-07a8-4aad-8ae3-70ca3611e1b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334988483 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_burst_wr.2334988483
Directory /workspace/29.hmac_burst_wr/latest

Test location /workspace/coverage/default/29.hmac_datapath_stress.325898031
Short name T281
Test name
Test status
Simulation time 8698736729 ps
CPU time 1175.73 seconds
Started Jun 27 06:47:21 PM PDT 24
Finished Jun 27 07:06:59 PM PDT 24
Peak memory 733144 kb
Host smart-7cca23d3-0c55-45bb-bb8a-69520c320bcc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=325898031 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_datapath_stress.325898031
Directory /workspace/29.hmac_datapath_stress/latest

Test location /workspace/coverage/default/29.hmac_error.4088816369
Short name T562
Test name
Test status
Simulation time 40622349662 ps
CPU time 243.67 seconds
Started Jun 27 06:47:23 PM PDT 24
Finished Jun 27 06:51:30 PM PDT 24
Peak memory 199960 kb
Host smart-2e5e0fc5-89f1-4ead-9443-acac4adb4528
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088816369 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_error.4088816369
Directory /workspace/29.hmac_error/latest

Test location /workspace/coverage/default/29.hmac_long_msg.1505295558
Short name T257
Test name
Test status
Simulation time 1719249468 ps
CPU time 73.86 seconds
Started Jun 27 06:47:10 PM PDT 24
Finished Jun 27 06:48:30 PM PDT 24
Peak memory 199900 kb
Host smart-791edbf0-54c8-45ec-9ebc-905219b7bea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1505295558 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_long_msg.1505295558
Directory /workspace/29.hmac_long_msg/latest

Test location /workspace/coverage/default/29.hmac_smoke.299625661
Short name T207
Test name
Test status
Simulation time 532811198 ps
CPU time 8.18 seconds
Started Jun 27 06:47:07 PM PDT 24
Finished Jun 27 06:47:21 PM PDT 24
Peak memory 199972 kb
Host smart-1bad8969-3881-4225-866e-3c860649f869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299625661 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_smoke.299625661
Directory /workspace/29.hmac_smoke/latest

Test location /workspace/coverage/default/29.hmac_test_hmac_vectors.1409688343
Short name T465
Test name
Test status
Simulation time 538597856 ps
CPU time 1.08 seconds
Started Jun 27 06:47:20 PM PDT 24
Finished Jun 27 06:47:23 PM PDT 24
Peak memory 199912 kb
Host smart-384b153f-85b4-46b7-8ec8-b777a42a7259
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409688343 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 29.hmac_test_hmac_vectors.1409688343
Directory /workspace/29.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/29.hmac_test_sha256_vectors.3954367305
Short name T86
Test name
Test status
Simulation time 55368669268 ps
CPU time 518.62 seconds
Started Jun 27 06:47:24 PM PDT 24
Finished Jun 27 06:56:07 PM PDT 24
Peak memory 200036 kb
Host smart-3b8148da-db5c-40ca-886b-509e6cafc130
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3954367305 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_test_sha256_vectors.3954367305
Directory /workspace/29.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/29.hmac_test_sha384_vectors.1832171687
Short name T310
Test name
Test status
Simulation time 121288968482 ps
CPU time 1667.4 seconds
Started Jun 27 06:47:23 PM PDT 24
Finished Jun 27 07:15:13 PM PDT 24
Peak memory 215440 kb
Host smart-715a13e9-da19-44b3-bed6-b16b84b4f20f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1832171687 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_test_sha384_vectors.1832171687
Directory /workspace/29.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/29.hmac_test_sha512_vectors.445646467
Short name T83
Test name
Test status
Simulation time 277298908048 ps
CPU time 1873.14 seconds
Started Jun 27 06:47:26 PM PDT 24
Finished Jun 27 07:18:44 PM PDT 24
Peak memory 215668 kb
Host smart-a393ab2c-06e5-40b6-8ccf-0ecadbcd3bb7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=445646467 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_test_sha512_vectors.445646467
Directory /workspace/29.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/29.hmac_wipe_secret.2552508984
Short name T548
Test name
Test status
Simulation time 3303337976 ps
CPU time 40.79 seconds
Started Jun 27 06:47:21 PM PDT 24
Finished Jun 27 06:48:05 PM PDT 24
Peak memory 200024 kb
Host smart-7ccde503-6ef3-4937-8675-e84c8b2d201e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552508984 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_wipe_secret.2552508984
Directory /workspace/29.hmac_wipe_secret/latest

Test location /workspace/coverage/default/3.hmac_alert_test.2660826009
Short name T497
Test name
Test status
Simulation time 47796467 ps
CPU time 0.59 seconds
Started Jun 27 06:46:27 PM PDT 24
Finished Jun 27 06:46:40 PM PDT 24
Peak memory 195996 kb
Host smart-ff9c7b4a-1ffd-409b-893c-c2b11aa25e91
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660826009 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_alert_test.2660826009
Directory /workspace/3.hmac_alert_test/latest

Test location /workspace/coverage/default/3.hmac_back_pressure.1990415145
Short name T241
Test name
Test status
Simulation time 624387026 ps
CPU time 28.8 seconds
Started Jun 27 06:46:23 PM PDT 24
Finished Jun 27 06:46:59 PM PDT 24
Peak memory 200008 kb
Host smart-bbf785af-b43a-4f67-901a-8ea3549fd15f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1990415145 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_back_pressure.1990415145
Directory /workspace/3.hmac_back_pressure/latest

Test location /workspace/coverage/default/3.hmac_burst_wr.2113432074
Short name T136
Test name
Test status
Simulation time 8003536747 ps
CPU time 28.51 seconds
Started Jun 27 06:46:20 PM PDT 24
Finished Jun 27 06:46:54 PM PDT 24
Peak memory 200032 kb
Host smart-17331e36-b727-418a-8c44-47878cf58b9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113432074 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_burst_wr.2113432074
Directory /workspace/3.hmac_burst_wr/latest

Test location /workspace/coverage/default/3.hmac_datapath_stress.3990282481
Short name T305
Test name
Test status
Simulation time 16581714369 ps
CPU time 1272.94 seconds
Started Jun 27 06:46:22 PM PDT 24
Finished Jun 27 07:07:42 PM PDT 24
Peak memory 744160 kb
Host smart-9cf85fa3-de7a-4a89-aa59-b4af9cefb04a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3990282481 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_datapath_stress.3990282481
Directory /workspace/3.hmac_datapath_stress/latest

Test location /workspace/coverage/default/3.hmac_error.2764503622
Short name T186
Test name
Test status
Simulation time 34519584211 ps
CPU time 212.67 seconds
Started Jun 27 06:46:22 PM PDT 24
Finished Jun 27 06:50:01 PM PDT 24
Peak memory 199968 kb
Host smart-b171fde9-c361-440b-bef3-38f63342cf7c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764503622 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_error.2764503622
Directory /workspace/3.hmac_error/latest

Test location /workspace/coverage/default/3.hmac_long_msg.1627745285
Short name T301
Test name
Test status
Simulation time 9738143951 ps
CPU time 33.76 seconds
Started Jun 27 06:46:26 PM PDT 24
Finished Jun 27 06:47:11 PM PDT 24
Peak memory 199960 kb
Host smart-c2736f76-3bbc-4cbc-b968-44c1e2e26be9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627745285 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_long_msg.1627745285
Directory /workspace/3.hmac_long_msg/latest

Test location /workspace/coverage/default/3.hmac_sec_cm.3485618862
Short name T46
Test name
Test status
Simulation time 639987844 ps
CPU time 0.84 seconds
Started Jun 27 06:46:23 PM PDT 24
Finished Jun 27 06:46:32 PM PDT 24
Peak memory 218460 kb
Host smart-8f74c011-7bca-41cf-9ce3-77d3ea52ca6a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485618862 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_sec_cm.3485618862
Directory /workspace/3.hmac_sec_cm/latest

Test location /workspace/coverage/default/3.hmac_smoke.1141424227
Short name T591
Test name
Test status
Simulation time 694625989 ps
CPU time 10.52 seconds
Started Jun 27 06:46:33 PM PDT 24
Finished Jun 27 06:46:57 PM PDT 24
Peak memory 199964 kb
Host smart-c4f15b62-8c69-43f8-b0bb-22d9be79129f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141424227 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_smoke.1141424227
Directory /workspace/3.hmac_smoke/latest

Test location /workspace/coverage/default/3.hmac_stress_all.1408739374
Short name T443
Test name
Test status
Simulation time 1938997111698 ps
CPU time 7599.03 seconds
Started Jun 27 06:46:21 PM PDT 24
Finished Jun 27 08:53:08 PM PDT 24
Peak memory 645584 kb
Host smart-eec15a38-d657-4017-91ca-2a3fd27b0d74
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408739374 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all.1408739374
Directory /workspace/3.hmac_stress_all/latest

Test location /workspace/coverage/default/3.hmac_test_hmac_vectors.2446609617
Short name T668
Test name
Test status
Simulation time 99412323 ps
CPU time 1.11 seconds
Started Jun 27 06:46:23 PM PDT 24
Finished Jun 27 06:46:33 PM PDT 24
Peak memory 199968 kb
Host smart-9f5abbb8-8b31-4b92-aad0-e251bd44bcc5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446609617 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac_vectors.2446609617
Directory /workspace/3.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha256_vectors.890376739
Short name T199
Test name
Test status
Simulation time 30183586160 ps
CPU time 430.5 seconds
Started Jun 27 06:46:29 PM PDT 24
Finished Jun 27 06:53:53 PM PDT 24
Peak memory 199988 kb
Host smart-0617ce46-3f19-4345-817d-c6ca547445de
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=890376739 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha256_vectors.890376739
Directory /workspace/3.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha384_vectors.4222955430
Short name T254
Test name
Test status
Simulation time 124278047018 ps
CPU time 1766.04 seconds
Started Jun 27 06:46:20 PM PDT 24
Finished Jun 27 07:15:52 PM PDT 24
Peak memory 215860 kb
Host smart-30858e16-4608-4f2a-991f-75df52e8adf8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4222955430 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha384_vectors.4222955430
Directory /workspace/3.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/3.hmac_wipe_secret.1665437322
Short name T701
Test name
Test status
Simulation time 19711230093 ps
CPU time 69.96 seconds
Started Jun 27 06:46:22 PM PDT 24
Finished Jun 27 06:47:39 PM PDT 24
Peak memory 200016 kb
Host smart-bd20a4df-9bd8-4c6f-9594-d242eab19e4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665437322 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_wipe_secret.1665437322
Directory /workspace/3.hmac_wipe_secret/latest

Test location /workspace/coverage/default/30.hmac_alert_test.2982342886
Short name T216
Test name
Test status
Simulation time 15910186 ps
CPU time 0.58 seconds
Started Jun 27 06:47:21 PM PDT 24
Finished Jun 27 06:47:24 PM PDT 24
Peak memory 194932 kb
Host smart-18f8545d-12a6-44ca-9195-7de7142c2d05
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982342886 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_alert_test.2982342886
Directory /workspace/30.hmac_alert_test/latest

Test location /workspace/coverage/default/30.hmac_back_pressure.3633967640
Short name T23
Test name
Test status
Simulation time 3556556251 ps
CPU time 43.37 seconds
Started Jun 27 06:47:28 PM PDT 24
Finished Jun 27 06:48:15 PM PDT 24
Peak memory 200060 kb
Host smart-82ca7743-9960-4ed1-812d-cbb4de1cf5ad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3633967640 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_back_pressure.3633967640
Directory /workspace/30.hmac_back_pressure/latest

Test location /workspace/coverage/default/30.hmac_burst_wr.2462183093
Short name T65
Test name
Test status
Simulation time 880037051 ps
CPU time 14.69 seconds
Started Jun 27 06:47:23 PM PDT 24
Finished Jun 27 06:47:41 PM PDT 24
Peak memory 199944 kb
Host smart-7be2c5f8-7554-46e3-942f-64490fad9c2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462183093 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_burst_wr.2462183093
Directory /workspace/30.hmac_burst_wr/latest

Test location /workspace/coverage/default/30.hmac_datapath_stress.1564954107
Short name T296
Test name
Test status
Simulation time 1684190503 ps
CPU time 361.96 seconds
Started Jun 27 06:47:19 PM PDT 24
Finished Jun 27 06:53:23 PM PDT 24
Peak memory 652884 kb
Host smart-9fc9f127-c6e7-42f4-9622-6499bd389c05
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1564954107 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_datapath_stress.1564954107
Directory /workspace/30.hmac_datapath_stress/latest

Test location /workspace/coverage/default/30.hmac_error.3109284021
Short name T291
Test name
Test status
Simulation time 6617875437 ps
CPU time 81.6 seconds
Started Jun 27 06:47:22 PM PDT 24
Finished Jun 27 06:48:46 PM PDT 24
Peak memory 199956 kb
Host smart-de0cf361-05ae-4f72-8f36-4df4e057d3d3
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109284021 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_error.3109284021
Directory /workspace/30.hmac_error/latest

Test location /workspace/coverage/default/30.hmac_long_msg.2079551419
Short name T636
Test name
Test status
Simulation time 3232844784 ps
CPU time 46.37 seconds
Started Jun 27 06:47:20 PM PDT 24
Finished Jun 27 06:48:09 PM PDT 24
Peak memory 200060 kb
Host smart-c8c07635-3e5b-454c-99ad-bc77c276e32e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079551419 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_long_msg.2079551419
Directory /workspace/30.hmac_long_msg/latest

Test location /workspace/coverage/default/30.hmac_smoke.478320062
Short name T341
Test name
Test status
Simulation time 2852138514 ps
CPU time 16.48 seconds
Started Jun 27 06:47:21 PM PDT 24
Finished Jun 27 06:47:40 PM PDT 24
Peak memory 200036 kb
Host smart-dabcd66e-20fe-42d5-9c18-3b455a0fdbe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478320062 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_smoke.478320062
Directory /workspace/30.hmac_smoke/latest

Test location /workspace/coverage/default/30.hmac_stress_all.1493238769
Short name T407
Test name
Test status
Simulation time 59402887943 ps
CPU time 4186.86 seconds
Started Jun 27 06:47:20 PM PDT 24
Finished Jun 27 07:57:10 PM PDT 24
Peak memory 833960 kb
Host smart-5d773526-a141-435e-a8d1-26fcc505c7e2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493238769 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.hmac_stress_all.1493238769
Directory /workspace/30.hmac_stress_all/latest

Test location /workspace/coverage/default/30.hmac_test_hmac_vectors.1836524415
Short name T29
Test name
Test status
Simulation time 419729223 ps
CPU time 1.33 seconds
Started Jun 27 06:47:25 PM PDT 24
Finished Jun 27 06:47:31 PM PDT 24
Peak memory 199924 kb
Host smart-e558e98d-986f-4ff8-a535-71e7048405e3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836524415 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 30.hmac_test_hmac_vectors.1836524415
Directory /workspace/30.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/30.hmac_test_sha256_vectors.3944692561
Short name T211
Test name
Test status
Simulation time 8074509891 ps
CPU time 452.58 seconds
Started Jun 27 06:47:21 PM PDT 24
Finished Jun 27 06:54:56 PM PDT 24
Peak memory 199980 kb
Host smart-d0eb7c5d-af1a-41e3-8bc7-42a6c49f939f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3944692561 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_test_sha256_vectors.3944692561
Directory /workspace/30.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/30.hmac_test_sha384_vectors.1938871343
Short name T287
Test name
Test status
Simulation time 139198493519 ps
CPU time 1897.55 seconds
Started Jun 27 06:47:23 PM PDT 24
Finished Jun 27 07:19:05 PM PDT 24
Peak memory 215432 kb
Host smart-7e9422d4-f942-4f33-91c6-06466aa72ae7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1938871343 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_test_sha384_vectors.1938871343
Directory /workspace/30.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/30.hmac_test_sha512_vectors.3477025410
Short name T167
Test name
Test status
Simulation time 59630837695 ps
CPU time 1758.72 seconds
Started Jun 27 06:47:21 PM PDT 24
Finished Jun 27 07:16:43 PM PDT 24
Peak memory 215476 kb
Host smart-e844a9b5-6f2b-4cf9-8a72-ff2aa8441708
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3477025410 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_test_sha512_vectors.3477025410
Directory /workspace/30.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/30.hmac_wipe_secret.2656469868
Short name T571
Test name
Test status
Simulation time 18362278829 ps
CPU time 60.18 seconds
Started Jun 27 06:47:22 PM PDT 24
Finished Jun 27 06:48:24 PM PDT 24
Peak memory 200040 kb
Host smart-9ec9f7ca-f57b-4983-bb59-3150946f071a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656469868 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_wipe_secret.2656469868
Directory /workspace/30.hmac_wipe_secret/latest

Test location /workspace/coverage/default/31.hmac_alert_test.3328273209
Short name T464
Test name
Test status
Simulation time 13097384 ps
CPU time 0.62 seconds
Started Jun 27 06:47:22 PM PDT 24
Finished Jun 27 06:47:25 PM PDT 24
Peak memory 196016 kb
Host smart-fbe48cc0-7a3d-4712-b1a5-c19a8de30489
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328273209 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_alert_test.3328273209
Directory /workspace/31.hmac_alert_test/latest

Test location /workspace/coverage/default/31.hmac_back_pressure.510634925
Short name T18
Test name
Test status
Simulation time 1736544378 ps
CPU time 24.01 seconds
Started Jun 27 06:47:28 PM PDT 24
Finished Jun 27 06:47:55 PM PDT 24
Peak memory 199928 kb
Host smart-1582ab4a-c08c-4ba9-855f-6ad09b705fbf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=510634925 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_back_pressure.510634925
Directory /workspace/31.hmac_back_pressure/latest

Test location /workspace/coverage/default/31.hmac_burst_wr.2050211841
Short name T556
Test name
Test status
Simulation time 2737894258 ps
CPU time 72.71 seconds
Started Jun 27 06:47:24 PM PDT 24
Finished Jun 27 06:48:41 PM PDT 24
Peak memory 200064 kb
Host smart-6944428d-f250-4d8c-9e45-a58cb57d493a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050211841 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_burst_wr.2050211841
Directory /workspace/31.hmac_burst_wr/latest

Test location /workspace/coverage/default/31.hmac_datapath_stress.1960152750
Short name T599
Test name
Test status
Simulation time 2714849921 ps
CPU time 641.47 seconds
Started Jun 27 06:47:26 PM PDT 24
Finished Jun 27 06:58:12 PM PDT 24
Peak memory 686796 kb
Host smart-002cfabd-ace7-4021-a13c-65f9ac92f75a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1960152750 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_datapath_stress.1960152750
Directory /workspace/31.hmac_datapath_stress/latest

Test location /workspace/coverage/default/31.hmac_error.2850892231
Short name T665
Test name
Test status
Simulation time 4481330721 ps
CPU time 82.91 seconds
Started Jun 27 06:47:21 PM PDT 24
Finished Jun 27 06:48:47 PM PDT 24
Peak memory 200008 kb
Host smart-a3e03ead-8210-4e90-8065-5330bf151b76
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850892231 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_error.2850892231
Directory /workspace/31.hmac_error/latest

Test location /workspace/coverage/default/31.hmac_long_msg.3649986523
Short name T605
Test name
Test status
Simulation time 4317963154 ps
CPU time 83.55 seconds
Started Jun 27 06:47:20 PM PDT 24
Finished Jun 27 06:48:45 PM PDT 24
Peak memory 199996 kb
Host smart-c7227f73-e84f-4e8c-987a-6091af6fb88c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649986523 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_long_msg.3649986523
Directory /workspace/31.hmac_long_msg/latest

Test location /workspace/coverage/default/31.hmac_smoke.3290626479
Short name T277
Test name
Test status
Simulation time 702606890 ps
CPU time 8.74 seconds
Started Jun 27 06:47:20 PM PDT 24
Finished Jun 27 06:47:30 PM PDT 24
Peak memory 199908 kb
Host smart-a97878c2-37ff-4014-bfb0-c97b29d20ee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290626479 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_smoke.3290626479
Directory /workspace/31.hmac_smoke/latest

Test location /workspace/coverage/default/31.hmac_stress_all.3672928830
Short name T275
Test name
Test status
Simulation time 69757272667 ps
CPU time 1940.96 seconds
Started Jun 27 06:47:23 PM PDT 24
Finished Jun 27 07:19:48 PM PDT 24
Peak memory 215816 kb
Host smart-b904ad88-4315-4537-8f6f-8baa78328c99
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672928830 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.hmac_stress_all.3672928830
Directory /workspace/31.hmac_stress_all/latest

Test location /workspace/coverage/default/31.hmac_test_hmac_vectors.1209361213
Short name T294
Test name
Test status
Simulation time 100003375 ps
CPU time 1.28 seconds
Started Jun 27 06:47:22 PM PDT 24
Finished Jun 27 06:47:26 PM PDT 24
Peak memory 199960 kb
Host smart-3f9ef76a-d3bb-46ef-8bbb-b9fcfd59236d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209361213 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 31.hmac_test_hmac_vectors.1209361213
Directory /workspace/31.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/31.hmac_test_sha256_vectors.2297194632
Short name T537
Test name
Test status
Simulation time 27014401123 ps
CPU time 524.82 seconds
Started Jun 27 06:47:20 PM PDT 24
Finished Jun 27 06:56:06 PM PDT 24
Peak memory 199976 kb
Host smart-a2a75fcf-f6bd-4de2-b5ed-30ceddf0dae7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2297194632 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_test_sha256_vectors.2297194632
Directory /workspace/31.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/31.hmac_test_sha384_vectors.1338055465
Short name T166
Test name
Test status
Simulation time 353145597258 ps
CPU time 2125.43 seconds
Started Jun 27 06:47:24 PM PDT 24
Finished Jun 27 07:22:54 PM PDT 24
Peak memory 215736 kb
Host smart-d15851c8-d375-49dc-9f1a-ff9d3a7baea7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1338055465 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_test_sha384_vectors.1338055465
Directory /workspace/31.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/31.hmac_test_sha512_vectors.2392866733
Short name T231
Test name
Test status
Simulation time 308229199048 ps
CPU time 1925.99 seconds
Started Jun 27 06:47:25 PM PDT 24
Finished Jun 27 07:19:36 PM PDT 24
Peak memory 215344 kb
Host smart-da387f64-ff70-4bcc-9804-dd68f24a6f8d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2392866733 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_test_sha512_vectors.2392866733
Directory /workspace/31.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/31.hmac_wipe_secret.3265643410
Short name T693
Test name
Test status
Simulation time 518545534 ps
CPU time 16.47 seconds
Started Jun 27 06:47:22 PM PDT 24
Finished Jun 27 06:47:41 PM PDT 24
Peak memory 200000 kb
Host smart-da794be7-2785-4c18-8e61-6782ff3ff5bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265643410 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_wipe_secret.3265643410
Directory /workspace/31.hmac_wipe_secret/latest

Test location /workspace/coverage/default/32.hmac_alert_test.435198426
Short name T646
Test name
Test status
Simulation time 110426156 ps
CPU time 0.63 seconds
Started Jun 27 06:47:24 PM PDT 24
Finished Jun 27 06:47:28 PM PDT 24
Peak memory 194796 kb
Host smart-18a442c2-61d2-4911-9ed6-c35d56beebd9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435198426 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_alert_test.435198426
Directory /workspace/32.hmac_alert_test/latest

Test location /workspace/coverage/default/32.hmac_back_pressure.3383151330
Short name T12
Test name
Test status
Simulation time 1217436459 ps
CPU time 28.46 seconds
Started Jun 27 06:47:23 PM PDT 24
Finished Jun 27 06:47:56 PM PDT 24
Peak memory 199968 kb
Host smart-1076159b-cd09-434d-801a-91667367dc1e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3383151330 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_back_pressure.3383151330
Directory /workspace/32.hmac_back_pressure/latest

Test location /workspace/coverage/default/32.hmac_burst_wr.781899473
Short name T577
Test name
Test status
Simulation time 2356274522 ps
CPU time 42.96 seconds
Started Jun 27 06:47:21 PM PDT 24
Finished Jun 27 06:48:06 PM PDT 24
Peak memory 200044 kb
Host smart-82d85487-2142-4f71-b66b-387765ab4e8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781899473 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_burst_wr.781899473
Directory /workspace/32.hmac_burst_wr/latest

Test location /workspace/coverage/default/32.hmac_datapath_stress.1536990287
Short name T624
Test name
Test status
Simulation time 1153282211 ps
CPU time 17.15 seconds
Started Jun 27 06:47:20 PM PDT 24
Finished Jun 27 06:47:38 PM PDT 24
Peak memory 216364 kb
Host smart-851fe442-952d-40dc-91d7-6be69c13a268
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1536990287 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_datapath_stress.1536990287
Directory /workspace/32.hmac_datapath_stress/latest

Test location /workspace/coverage/default/32.hmac_error.630805740
Short name T462
Test name
Test status
Simulation time 9333514064 ps
CPU time 32.43 seconds
Started Jun 27 06:47:20 PM PDT 24
Finished Jun 27 06:47:55 PM PDT 24
Peak memory 200000 kb
Host smart-56db8fe2-0ac1-4e84-8f44-ae9aa3f5925f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630805740 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_error.630805740
Directory /workspace/32.hmac_error/latest

Test location /workspace/coverage/default/32.hmac_long_msg.3997201955
Short name T690
Test name
Test status
Simulation time 5199023584 ps
CPU time 68.99 seconds
Started Jun 27 06:47:26 PM PDT 24
Finished Jun 27 06:48:40 PM PDT 24
Peak memory 200040 kb
Host smart-1cb58b12-14fe-4427-aa87-871fd70c083a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3997201955 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_long_msg.3997201955
Directory /workspace/32.hmac_long_msg/latest

Test location /workspace/coverage/default/32.hmac_smoke.1812435757
Short name T11
Test name
Test status
Simulation time 19610559 ps
CPU time 0.69 seconds
Started Jun 27 06:47:24 PM PDT 24
Finished Jun 27 06:47:28 PM PDT 24
Peak memory 196520 kb
Host smart-2eaa187a-86cd-4403-b5b2-3c2d4dff8ba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812435757 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_smoke.1812435757
Directory /workspace/32.hmac_smoke/latest

Test location /workspace/coverage/default/32.hmac_stress_all.3946156332
Short name T22
Test name
Test status
Simulation time 555869968073 ps
CPU time 3414.89 seconds
Started Jun 27 06:47:26 PM PDT 24
Finished Jun 27 07:44:26 PM PDT 24
Peak memory 735700 kb
Host smart-508126d8-4eda-402b-ab5e-35068ceaa368
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946156332 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.hmac_stress_all.3946156332
Directory /workspace/32.hmac_stress_all/latest

Test location /workspace/coverage/default/32.hmac_test_hmac_vectors.4213333999
Short name T402
Test name
Test status
Simulation time 229078726 ps
CPU time 1.12 seconds
Started Jun 27 06:47:23 PM PDT 24
Finished Jun 27 06:47:27 PM PDT 24
Peak memory 199708 kb
Host smart-8ae8ac23-04c9-4f70-b0a6-7c2c5144758c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213333999 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 32.hmac_test_hmac_vectors.4213333999
Directory /workspace/32.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/32.hmac_test_sha256_vectors.1121732034
Short name T16
Test name
Test status
Simulation time 55555055432 ps
CPU time 518.22 seconds
Started Jun 27 06:47:23 PM PDT 24
Finished Jun 27 06:56:04 PM PDT 24
Peak memory 200016 kb
Host smart-0141dd10-b8f1-49ef-96d9-71cafdfd63ac
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1121732034 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_test_sha256_vectors.1121732034
Directory /workspace/32.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/32.hmac_test_sha384_vectors.3433244287
Short name T583
Test name
Test status
Simulation time 428992516302 ps
CPU time 1915.96 seconds
Started Jun 27 06:47:25 PM PDT 24
Finished Jun 27 07:19:25 PM PDT 24
Peak memory 215484 kb
Host smart-50e1c151-2908-40d7-8829-7ece6db034f4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3433244287 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_test_sha384_vectors.3433244287
Directory /workspace/32.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/32.hmac_test_sha512_vectors.571805574
Short name T292
Test name
Test status
Simulation time 286196739631 ps
CPU time 1768.27 seconds
Started Jun 27 06:47:21 PM PDT 24
Finished Jun 27 07:16:52 PM PDT 24
Peak memory 215556 kb
Host smart-de0058b4-05b8-462e-8cc0-7937f4cc693d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=571805574 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_test_sha512_vectors.571805574
Directory /workspace/32.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/32.hmac_wipe_secret.316705291
Short name T124
Test name
Test status
Simulation time 254700021 ps
CPU time 17.22 seconds
Started Jun 27 06:47:22 PM PDT 24
Finished Jun 27 06:47:41 PM PDT 24
Peak memory 199936 kb
Host smart-96709c0b-a2c2-4db3-87b5-d4cb7ab95572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316705291 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_wipe_secret.316705291
Directory /workspace/32.hmac_wipe_secret/latest

Test location /workspace/coverage/default/33.hmac_alert_test.3136391422
Short name T40
Test name
Test status
Simulation time 12144396 ps
CPU time 0.57 seconds
Started Jun 27 06:47:22 PM PDT 24
Finished Jun 27 06:47:25 PM PDT 24
Peak memory 194972 kb
Host smart-e01aabed-6fd2-464c-900f-b129d1d7a3a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136391422 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_alert_test.3136391422
Directory /workspace/33.hmac_alert_test/latest

Test location /workspace/coverage/default/33.hmac_back_pressure.1889637079
Short name T238
Test name
Test status
Simulation time 1153938100 ps
CPU time 16.43 seconds
Started Jun 27 06:47:21 PM PDT 24
Finished Jun 27 06:47:40 PM PDT 24
Peak memory 199956 kb
Host smart-a07c99fe-39e2-463d-af11-a288dbcaedb2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1889637079 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_back_pressure.1889637079
Directory /workspace/33.hmac_back_pressure/latest

Test location /workspace/coverage/default/33.hmac_burst_wr.3894165200
Short name T299
Test name
Test status
Simulation time 6647573315 ps
CPU time 12.85 seconds
Started Jun 27 06:47:25 PM PDT 24
Finished Jun 27 06:47:42 PM PDT 24
Peak memory 199992 kb
Host smart-12861333-289b-4795-a4dd-86d4a4436f1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894165200 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_burst_wr.3894165200
Directory /workspace/33.hmac_burst_wr/latest

Test location /workspace/coverage/default/33.hmac_datapath_stress.2665674314
Short name T226
Test name
Test status
Simulation time 27361930437 ps
CPU time 764.19 seconds
Started Jun 27 06:47:23 PM PDT 24
Finished Jun 27 07:00:10 PM PDT 24
Peak memory 741172 kb
Host smart-e634ddf4-dfe3-4046-a680-339580319291
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2665674314 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_datapath_stress.2665674314
Directory /workspace/33.hmac_datapath_stress/latest

Test location /workspace/coverage/default/33.hmac_error.1937362108
Short name T639
Test name
Test status
Simulation time 9437408468 ps
CPU time 56.65 seconds
Started Jun 27 06:47:24 PM PDT 24
Finished Jun 27 06:48:24 PM PDT 24
Peak memory 199804 kb
Host smart-3b9b1421-e5b9-4542-b23c-a344e5897818
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937362108 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_error.1937362108
Directory /workspace/33.hmac_error/latest

Test location /workspace/coverage/default/33.hmac_long_msg.3236785999
Short name T521
Test name
Test status
Simulation time 13705688 ps
CPU time 0.7 seconds
Started Jun 27 06:47:20 PM PDT 24
Finished Jun 27 06:47:22 PM PDT 24
Peak memory 196472 kb
Host smart-34a4aacd-38b3-4cdc-939e-aca19f2fb167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236785999 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_long_msg.3236785999
Directory /workspace/33.hmac_long_msg/latest

Test location /workspace/coverage/default/33.hmac_smoke.1766641750
Short name T563
Test name
Test status
Simulation time 742008377 ps
CPU time 11.27 seconds
Started Jun 27 06:47:24 PM PDT 24
Finished Jun 27 06:47:39 PM PDT 24
Peak memory 199956 kb
Host smart-fb1b928a-8fbb-40ff-a8a9-abe45c0a3c11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1766641750 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_smoke.1766641750
Directory /workspace/33.hmac_smoke/latest

Test location /workspace/coverage/default/33.hmac_stress_all.2167734766
Short name T592
Test name
Test status
Simulation time 77326640941 ps
CPU time 2755.4 seconds
Started Jun 27 06:47:21 PM PDT 24
Finished Jun 27 07:33:19 PM PDT 24
Peak memory 677612 kb
Host smart-98175064-9517-4c3e-8993-38e93fda084a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167734766 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.hmac_stress_all.2167734766
Directory /workspace/33.hmac_stress_all/latest

Test location /workspace/coverage/default/33.hmac_test_hmac_vectors.1069546123
Short name T593
Test name
Test status
Simulation time 116931122 ps
CPU time 1.35 seconds
Started Jun 27 06:47:24 PM PDT 24
Finished Jun 27 06:47:30 PM PDT 24
Peak memory 200064 kb
Host smart-6da2b25a-687f-4788-a999-90e0c0ef8910
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069546123 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 33.hmac_test_hmac_vectors.1069546123
Directory /workspace/33.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/33.hmac_test_sha256_vectors.1690233314
Short name T484
Test name
Test status
Simulation time 7405278371 ps
CPU time 443.87 seconds
Started Jun 27 06:47:23 PM PDT 24
Finished Jun 27 06:54:50 PM PDT 24
Peak memory 200000 kb
Host smart-90ff8790-8519-4b1d-a20a-b1608badb203
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1690233314 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_test_sha256_vectors.1690233314
Directory /workspace/33.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/33.hmac_test_sha384_vectors.2757866886
Short name T451
Test name
Test status
Simulation time 305999811089 ps
CPU time 2196.2 seconds
Started Jun 27 06:47:21 PM PDT 24
Finished Jun 27 07:24:00 PM PDT 24
Peak memory 215608 kb
Host smart-c16ff066-426b-452e-a242-7a5d67615f8c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2757866886 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_test_sha384_vectors.2757866886
Directory /workspace/33.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/33.hmac_test_sha512_vectors.1027379136
Short name T234
Test name
Test status
Simulation time 106696863213 ps
CPU time 1878.43 seconds
Started Jun 27 06:47:26 PM PDT 24
Finished Jun 27 07:18:49 PM PDT 24
Peak memory 215460 kb
Host smart-9c180ba8-61df-4a58-90e7-d473d0acda4b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1027379136 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_test_sha512_vectors.1027379136
Directory /workspace/33.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/33.hmac_wipe_secret.452623943
Short name T91
Test name
Test status
Simulation time 27829607759 ps
CPU time 89.2 seconds
Started Jun 27 06:47:21 PM PDT 24
Finished Jun 27 06:48:53 PM PDT 24
Peak memory 200056 kb
Host smart-fc7073b9-33b5-461e-b55f-399e48231303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452623943 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_wipe_secret.452623943
Directory /workspace/33.hmac_wipe_secret/latest

Test location /workspace/coverage/default/34.hmac_alert_test.1622098179
Short name T564
Test name
Test status
Simulation time 26281249 ps
CPU time 0.6 seconds
Started Jun 27 06:47:28 PM PDT 24
Finished Jun 27 06:47:33 PM PDT 24
Peak memory 196772 kb
Host smart-e7754362-7e89-4ea2-9cb1-d070af8f583e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622098179 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_alert_test.1622098179
Directory /workspace/34.hmac_alert_test/latest

Test location /workspace/coverage/default/34.hmac_back_pressure.957429813
Short name T376
Test name
Test status
Simulation time 302247224 ps
CPU time 6.84 seconds
Started Jun 27 06:47:24 PM PDT 24
Finished Jun 27 06:47:35 PM PDT 24
Peak memory 200124 kb
Host smart-b4635dbc-1240-477d-bbb4-26a6c1792ccf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=957429813 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_back_pressure.957429813
Directory /workspace/34.hmac_back_pressure/latest

Test location /workspace/coverage/default/34.hmac_burst_wr.3162334853
Short name T129
Test name
Test status
Simulation time 950741599 ps
CPU time 50.58 seconds
Started Jun 27 06:47:23 PM PDT 24
Finished Jun 27 06:48:17 PM PDT 24
Peak memory 200000 kb
Host smart-782f3b43-1325-471f-8466-cbc647b37c7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162334853 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_burst_wr.3162334853
Directory /workspace/34.hmac_burst_wr/latest

Test location /workspace/coverage/default/34.hmac_datapath_stress.660193717
Short name T156
Test name
Test status
Simulation time 2954481349 ps
CPU time 211.51 seconds
Started Jun 27 06:47:24 PM PDT 24
Finished Jun 27 06:50:59 PM PDT 24
Peak memory 453096 kb
Host smart-03f5ba25-363e-4e01-b191-9143d881576f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=660193717 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_datapath_stress.660193717
Directory /workspace/34.hmac_datapath_stress/latest

Test location /workspace/coverage/default/34.hmac_error.1331397251
Short name T694
Test name
Test status
Simulation time 7044682163 ps
CPU time 124.1 seconds
Started Jun 27 06:47:24 PM PDT 24
Finished Jun 27 06:49:33 PM PDT 24
Peak memory 200208 kb
Host smart-987fce9d-c45f-46ef-9786-b2f5a10e97ef
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331397251 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_error.1331397251
Directory /workspace/34.hmac_error/latest

Test location /workspace/coverage/default/34.hmac_long_msg.2242540083
Short name T365
Test name
Test status
Simulation time 3102978113 ps
CPU time 59.52 seconds
Started Jun 27 06:47:25 PM PDT 24
Finished Jun 27 06:48:28 PM PDT 24
Peak memory 200072 kb
Host smart-7cf80fff-98c6-4473-bdc9-7b886bc51fad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242540083 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_long_msg.2242540083
Directory /workspace/34.hmac_long_msg/latest

Test location /workspace/coverage/default/34.hmac_smoke.3789015555
Short name T615
Test name
Test status
Simulation time 183824763 ps
CPU time 0.88 seconds
Started Jun 27 06:47:24 PM PDT 24
Finished Jun 27 06:47:29 PM PDT 24
Peak memory 198572 kb
Host smart-186ee1cf-98b2-4607-be9a-9d6ad07ab7f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789015555 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_smoke.3789015555
Directory /workspace/34.hmac_smoke/latest

Test location /workspace/coverage/default/34.hmac_stress_all.2179003078
Short name T76
Test name
Test status
Simulation time 3720869766086 ps
CPU time 4296.78 seconds
Started Jun 27 06:47:27 PM PDT 24
Finished Jun 27 07:59:08 PM PDT 24
Peak memory 215596 kb
Host smart-0d8e2dc0-52a1-41eb-9001-66f24f64abfd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179003078 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.hmac_stress_all.2179003078
Directory /workspace/34.hmac_stress_all/latest

Test location /workspace/coverage/default/34.hmac_test_hmac_vectors.2631711177
Short name T644
Test name
Test status
Simulation time 277357012 ps
CPU time 1.32 seconds
Started Jun 27 06:47:26 PM PDT 24
Finished Jun 27 06:47:31 PM PDT 24
Peak memory 199944 kb
Host smart-02d668ee-1b72-409e-ac22-41a6fdba5b6b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631711177 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 34.hmac_test_hmac_vectors.2631711177
Directory /workspace/34.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/34.hmac_test_sha256_vectors.3126347046
Short name T468
Test name
Test status
Simulation time 41068690306 ps
CPU time 506.29 seconds
Started Jun 27 06:47:23 PM PDT 24
Finished Jun 27 06:55:53 PM PDT 24
Peak memory 199968 kb
Host smart-b1f8c0ee-531f-4d68-894d-d24389ac2d85
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3126347046 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_test_sha256_vectors.3126347046
Directory /workspace/34.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/34.hmac_test_sha384_vectors.3438446192
Short name T474
Test name
Test status
Simulation time 60606428872 ps
CPU time 1702.47 seconds
Started Jun 27 06:47:26 PM PDT 24
Finished Jun 27 07:15:53 PM PDT 24
Peak memory 215644 kb
Host smart-ae497306-00ec-4809-9eea-941cf4e81a9e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3438446192 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_test_sha384_vectors.3438446192
Directory /workspace/34.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/34.hmac_test_sha512_vectors.507063178
Short name T643
Test name
Test status
Simulation time 116371580328 ps
CPU time 1923.57 seconds
Started Jun 27 06:47:26 PM PDT 24
Finished Jun 27 07:19:34 PM PDT 24
Peak memory 216120 kb
Host smart-afcfa18f-4dc1-4fbb-b615-534be8908398
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=507063178 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_test_sha512_vectors.507063178
Directory /workspace/34.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/34.hmac_wipe_secret.2515468149
Short name T68
Test name
Test status
Simulation time 1772876702 ps
CPU time 6.93 seconds
Started Jun 27 06:47:29 PM PDT 24
Finished Jun 27 06:47:40 PM PDT 24
Peak memory 199988 kb
Host smart-a76aae6c-e742-4660-b922-8dcdb1f13de5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515468149 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_wipe_secret.2515468149
Directory /workspace/34.hmac_wipe_secret/latest

Test location /workspace/coverage/default/35.hmac_alert_test.3974906640
Short name T38
Test name
Test status
Simulation time 42203987 ps
CPU time 0.6 seconds
Started Jun 27 06:47:27 PM PDT 24
Finished Jun 27 06:47:32 PM PDT 24
Peak memory 195720 kb
Host smart-68ebc423-1b13-4cc9-a786-beee6783c27e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974906640 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_alert_test.3974906640
Directory /workspace/35.hmac_alert_test/latest

Test location /workspace/coverage/default/35.hmac_back_pressure.2379450210
Short name T498
Test name
Test status
Simulation time 196333936 ps
CPU time 9.12 seconds
Started Jun 27 06:47:25 PM PDT 24
Finished Jun 27 06:47:38 PM PDT 24
Peak memory 199892 kb
Host smart-344ca9c1-5e18-44e0-b13b-feb5ade43b21
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2379450210 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_back_pressure.2379450210
Directory /workspace/35.hmac_back_pressure/latest

Test location /workspace/coverage/default/35.hmac_burst_wr.847293682
Short name T344
Test name
Test status
Simulation time 2648681970 ps
CPU time 49.03 seconds
Started Jun 27 06:47:27 PM PDT 24
Finished Jun 27 06:48:20 PM PDT 24
Peak memory 199992 kb
Host smart-e7370e3e-973e-43a2-ab2a-8828f6d43dbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847293682 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_burst_wr.847293682
Directory /workspace/35.hmac_burst_wr/latest

Test location /workspace/coverage/default/35.hmac_datapath_stress.1936171053
Short name T203
Test name
Test status
Simulation time 572235436 ps
CPU time 81.93 seconds
Started Jun 27 06:47:28 PM PDT 24
Finished Jun 27 06:48:54 PM PDT 24
Peak memory 437552 kb
Host smart-1eac2813-f96c-45d6-91d4-6ada43701c86
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1936171053 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_datapath_stress.1936171053
Directory /workspace/35.hmac_datapath_stress/latest

Test location /workspace/coverage/default/35.hmac_error.450873579
Short name T697
Test name
Test status
Simulation time 7343637892 ps
CPU time 103.4 seconds
Started Jun 27 06:47:21 PM PDT 24
Finished Jun 27 06:49:07 PM PDT 24
Peak memory 200040 kb
Host smart-bb751256-2e72-44a8-ae4c-eaea5c9fd74f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450873579 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_error.450873579
Directory /workspace/35.hmac_error/latest

Test location /workspace/coverage/default/35.hmac_long_msg.1362948441
Short name T506
Test name
Test status
Simulation time 3670359054 ps
CPU time 104.37 seconds
Started Jun 27 06:47:25 PM PDT 24
Finished Jun 27 06:49:14 PM PDT 24
Peak memory 200048 kb
Host smart-58255782-c8fe-45db-9728-c2c5a31a521c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362948441 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_long_msg.1362948441
Directory /workspace/35.hmac_long_msg/latest

Test location /workspace/coverage/default/35.hmac_smoke.3261020773
Short name T554
Test name
Test status
Simulation time 2481265871 ps
CPU time 9.84 seconds
Started Jun 27 06:47:29 PM PDT 24
Finished Jun 27 06:47:42 PM PDT 24
Peak memory 200088 kb
Host smart-7c8a5283-a520-4967-ba4f-ee5c17ed2450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261020773 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_smoke.3261020773
Directory /workspace/35.hmac_smoke/latest

Test location /workspace/coverage/default/35.hmac_stress_all.1450757891
Short name T670
Test name
Test status
Simulation time 123213915955 ps
CPU time 1193.07 seconds
Started Jun 27 06:47:22 PM PDT 24
Finished Jun 27 07:07:18 PM PDT 24
Peak memory 708648 kb
Host smart-b93d1b0c-67f6-480b-ab19-8139292d1e36
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450757891 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.hmac_stress_all.1450757891
Directory /workspace/35.hmac_stress_all/latest

Test location /workspace/coverage/default/35.hmac_test_hmac_vectors.2241136260
Short name T315
Test name
Test status
Simulation time 74187030 ps
CPU time 1.42 seconds
Started Jun 27 06:47:27 PM PDT 24
Finished Jun 27 06:47:32 PM PDT 24
Peak memory 199912 kb
Host smart-3f10aa95-ba5b-4028-a931-0341c4db98c5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241136260 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 35.hmac_test_hmac_vectors.2241136260
Directory /workspace/35.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/35.hmac_test_sha256_vectors.3537150296
Short name T386
Test name
Test status
Simulation time 57884159037 ps
CPU time 532.07 seconds
Started Jun 27 06:47:25 PM PDT 24
Finished Jun 27 06:56:21 PM PDT 24
Peak memory 199784 kb
Host smart-3c9f0b2e-b9ea-460f-913c-7e85546519c2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3537150296 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_test_sha256_vectors.3537150296
Directory /workspace/35.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/35.hmac_test_sha384_vectors.2001935751
Short name T389
Test name
Test status
Simulation time 43934370469 ps
CPU time 1748.35 seconds
Started Jun 27 06:47:26 PM PDT 24
Finished Jun 27 07:16:39 PM PDT 24
Peak memory 215980 kb
Host smart-041df8ad-e181-493d-bb99-efd93f0478d0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2001935751 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_test_sha384_vectors.2001935751
Directory /workspace/35.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/35.hmac_test_sha512_vectors.2381379327
Short name T698
Test name
Test status
Simulation time 117992726617 ps
CPU time 1683.18 seconds
Started Jun 27 06:47:25 PM PDT 24
Finished Jun 27 07:15:32 PM PDT 24
Peak memory 215244 kb
Host smart-a5d0766c-a741-4916-b62d-ae546e8a269e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2381379327 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_test_sha512_vectors.2381379327
Directory /workspace/35.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/35.hmac_wipe_secret.3458538437
Short name T494
Test name
Test status
Simulation time 652211293 ps
CPU time 9.25 seconds
Started Jun 27 06:47:28 PM PDT 24
Finished Jun 27 06:47:41 PM PDT 24
Peak memory 199984 kb
Host smart-db04efc0-7884-43a1-a856-2d8a72939bbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458538437 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_wipe_secret.3458538437
Directory /workspace/35.hmac_wipe_secret/latest

Test location /workspace/coverage/default/36.hmac_alert_test.3411188196
Short name T524
Test name
Test status
Simulation time 55450056 ps
CPU time 0.63 seconds
Started Jun 27 06:47:41 PM PDT 24
Finished Jun 27 06:47:48 PM PDT 24
Peak memory 196076 kb
Host smart-d024febb-9ebe-4153-b7e8-955d41c96d1c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411188196 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_alert_test.3411188196
Directory /workspace/36.hmac_alert_test/latest

Test location /workspace/coverage/default/36.hmac_back_pressure.864478305
Short name T346
Test name
Test status
Simulation time 8547311433 ps
CPU time 52.38 seconds
Started Jun 27 06:47:30 PM PDT 24
Finished Jun 27 06:48:25 PM PDT 24
Peak memory 200032 kb
Host smart-f7f22df3-5ab8-4f60-8a1e-ba501206cc7b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=864478305 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_back_pressure.864478305
Directory /workspace/36.hmac_back_pressure/latest

Test location /workspace/coverage/default/36.hmac_burst_wr.1184727546
Short name T696
Test name
Test status
Simulation time 7119141841 ps
CPU time 49.98 seconds
Started Jun 27 06:47:26 PM PDT 24
Finished Jun 27 06:48:20 PM PDT 24
Peak memory 208180 kb
Host smart-c9b8a34a-20dd-4ce3-bcce-420b90114e1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184727546 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_burst_wr.1184727546
Directory /workspace/36.hmac_burst_wr/latest

Test location /workspace/coverage/default/36.hmac_datapath_stress.4047955127
Short name T575
Test name
Test status
Simulation time 10919385105 ps
CPU time 458.79 seconds
Started Jun 27 06:47:28 PM PDT 24
Finished Jun 27 06:55:11 PM PDT 24
Peak memory 673020 kb
Host smart-20610c10-cf5a-4d29-84ed-506a9e3b26fb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4047955127 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_datapath_stress.4047955127
Directory /workspace/36.hmac_datapath_stress/latest

Test location /workspace/coverage/default/36.hmac_error.1244532739
Short name T560
Test name
Test status
Simulation time 10450394749 ps
CPU time 39.06 seconds
Started Jun 27 06:47:36 PM PDT 24
Finished Jun 27 06:48:17 PM PDT 24
Peak memory 200024 kb
Host smart-8479ee71-cc74-4b83-9557-62413a635a5b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244532739 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_error.1244532739
Directory /workspace/36.hmac_error/latest

Test location /workspace/coverage/default/36.hmac_long_msg.3713641958
Short name T400
Test name
Test status
Simulation time 264362801 ps
CPU time 7.38 seconds
Started Jun 27 06:47:27 PM PDT 24
Finished Jun 27 06:47:39 PM PDT 24
Peak memory 199940 kb
Host smart-02970fb1-e9fc-4b58-8761-17d44885410f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713641958 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_long_msg.3713641958
Directory /workspace/36.hmac_long_msg/latest

Test location /workspace/coverage/default/36.hmac_smoke.768470043
Short name T573
Test name
Test status
Simulation time 132559560 ps
CPU time 2.9 seconds
Started Jun 27 06:47:27 PM PDT 24
Finished Jun 27 06:47:34 PM PDT 24
Peak memory 200000 kb
Host smart-befbc3ed-65ea-4065-9807-ebc61f7209e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768470043 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_smoke.768470043
Directory /workspace/36.hmac_smoke/latest

Test location /workspace/coverage/default/36.hmac_stress_all.3337292526
Short name T640
Test name
Test status
Simulation time 16263868777 ps
CPU time 77.63 seconds
Started Jun 27 06:47:36 PM PDT 24
Finished Jun 27 06:48:56 PM PDT 24
Peak memory 200024 kb
Host smart-facd6948-f1bd-4d46-a524-d4e5494387d1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337292526 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.hmac_stress_all.3337292526
Directory /workspace/36.hmac_stress_all/latest

Test location /workspace/coverage/default/36.hmac_test_hmac_vectors.1351453558
Short name T6
Test name
Test status
Simulation time 44247454 ps
CPU time 1.04 seconds
Started Jun 27 06:47:36 PM PDT 24
Finished Jun 27 06:47:39 PM PDT 24
Peak memory 199708 kb
Host smart-d2524193-b4cd-4c63-9eef-8ef13e4f652e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351453558 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 36.hmac_test_hmac_vectors.1351453558
Directory /workspace/36.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/36.hmac_test_sha256_vectors.1857624542
Short name T193
Test name
Test status
Simulation time 38299003539 ps
CPU time 518.6 seconds
Started Jun 27 06:47:41 PM PDT 24
Finished Jun 27 06:56:27 PM PDT 24
Peak memory 199884 kb
Host smart-67b4b378-aec2-4c60-8a91-1c2da6c9ecda
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1857624542 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_test_sha256_vectors.1857624542
Directory /workspace/36.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/36.hmac_test_sha384_vectors.3089400773
Short name T285
Test name
Test status
Simulation time 132796415333 ps
CPU time 1756.23 seconds
Started Jun 27 06:47:40 PM PDT 24
Finished Jun 27 07:17:03 PM PDT 24
Peak memory 215532 kb
Host smart-6dc4cbfe-c533-4ab2-8d50-39b9c364b65b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3089400773 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_test_sha384_vectors.3089400773
Directory /workspace/36.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/36.hmac_test_sha512_vectors.1125434811
Short name T436
Test name
Test status
Simulation time 628314383513 ps
CPU time 1756.38 seconds
Started Jun 27 06:47:37 PM PDT 24
Finished Jun 27 07:16:59 PM PDT 24
Peak memory 215912 kb
Host smart-21fbe23f-9e61-4072-a410-dd3884529a5c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1125434811 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_test_sha512_vectors.1125434811
Directory /workspace/36.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/36.hmac_wipe_secret.2939518128
Short name T666
Test name
Test status
Simulation time 2509613905 ps
CPU time 34.14 seconds
Started Jun 27 06:47:36 PM PDT 24
Finished Jun 27 06:48:12 PM PDT 24
Peak memory 200072 kb
Host smart-1e427b0b-f8c2-42df-b99c-b93b75f3e6b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939518128 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_wipe_secret.2939518128
Directory /workspace/36.hmac_wipe_secret/latest

Test location /workspace/coverage/default/37.hmac_alert_test.3364352519
Short name T678
Test name
Test status
Simulation time 124436554 ps
CPU time 0.6 seconds
Started Jun 27 06:47:38 PM PDT 24
Finished Jun 27 06:47:44 PM PDT 24
Peak memory 196752 kb
Host smart-6534ce61-1bce-434c-b1fb-80d7d242ed57
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364352519 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_alert_test.3364352519
Directory /workspace/37.hmac_alert_test/latest

Test location /workspace/coverage/default/37.hmac_back_pressure.2622079006
Short name T24
Test name
Test status
Simulation time 514304093 ps
CPU time 22.29 seconds
Started Jun 27 06:47:38 PM PDT 24
Finished Jun 27 06:48:07 PM PDT 24
Peak memory 199864 kb
Host smart-aa21e8ec-ea4e-4b0e-ab91-8cff6c44c567
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2622079006 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_back_pressure.2622079006
Directory /workspace/37.hmac_back_pressure/latest

Test location /workspace/coverage/default/37.hmac_burst_wr.552100241
Short name T429
Test name
Test status
Simulation time 2979583817 ps
CPU time 30.24 seconds
Started Jun 27 06:47:35 PM PDT 24
Finished Jun 27 06:48:07 PM PDT 24
Peak memory 200020 kb
Host smart-c953eb45-3029-4680-96f1-b02a129903fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552100241 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_burst_wr.552100241
Directory /workspace/37.hmac_burst_wr/latest

Test location /workspace/coverage/default/37.hmac_datapath_stress.1477601729
Short name T223
Test name
Test status
Simulation time 4104946207 ps
CPU time 496.74 seconds
Started Jun 27 06:47:35 PM PDT 24
Finished Jun 27 06:55:54 PM PDT 24
Peak memory 663424 kb
Host smart-9c6d2369-f962-4123-bd46-d1ef2d4efe32
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1477601729 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_datapath_stress.1477601729
Directory /workspace/37.hmac_datapath_stress/latest

Test location /workspace/coverage/default/37.hmac_error.2449764570
Short name T396
Test name
Test status
Simulation time 2604920487 ps
CPU time 9.06 seconds
Started Jun 27 06:47:39 PM PDT 24
Finished Jun 27 06:47:54 PM PDT 24
Peak memory 199944 kb
Host smart-082b21f7-6fb7-4f84-a182-fb8e2778f828
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449764570 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_error.2449764570
Directory /workspace/37.hmac_error/latest

Test location /workspace/coverage/default/37.hmac_long_msg.3637005118
Short name T64
Test name
Test status
Simulation time 1394776907 ps
CPU time 78.43 seconds
Started Jun 27 06:47:36 PM PDT 24
Finished Jun 27 06:48:57 PM PDT 24
Peak memory 199884 kb
Host smart-27720ffd-29eb-4f65-b0e3-5e03d0f01946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637005118 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_long_msg.3637005118
Directory /workspace/37.hmac_long_msg/latest

Test location /workspace/coverage/default/37.hmac_smoke.209818273
Short name T90
Test name
Test status
Simulation time 3518465390 ps
CPU time 18.7 seconds
Started Jun 27 06:47:46 PM PDT 24
Finished Jun 27 06:48:10 PM PDT 24
Peak memory 200044 kb
Host smart-9a191da1-ae68-4700-b2de-829d7c76af22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209818273 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_smoke.209818273
Directory /workspace/37.hmac_smoke/latest

Test location /workspace/coverage/default/37.hmac_stress_all.2135579276
Short name T463
Test name
Test status
Simulation time 3057382858 ps
CPU time 45.59 seconds
Started Jun 27 06:47:41 PM PDT 24
Finished Jun 27 06:48:34 PM PDT 24
Peak memory 199880 kb
Host smart-3dffa75b-ef39-4873-b15c-dd44ea928201
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135579276 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.hmac_stress_all.2135579276
Directory /workspace/37.hmac_stress_all/latest

Test location /workspace/coverage/default/37.hmac_test_hmac_vectors.3925858637
Short name T183
Test name
Test status
Simulation time 150410787 ps
CPU time 1.4 seconds
Started Jun 27 06:47:42 PM PDT 24
Finished Jun 27 06:47:50 PM PDT 24
Peak memory 199812 kb
Host smart-6d61a198-9828-4033-977f-c3337c774054
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925858637 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 37.hmac_test_hmac_vectors.3925858637
Directory /workspace/37.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/37.hmac_test_sha256_vectors.3279731141
Short name T279
Test name
Test status
Simulation time 7132105377 ps
CPU time 419.91 seconds
Started Jun 27 06:47:42 PM PDT 24
Finished Jun 27 06:54:49 PM PDT 24
Peak memory 200044 kb
Host smart-74b3248f-9610-4062-9ee8-d4d1c6cda71c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3279731141 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_test_sha256_vectors.3279731141
Directory /workspace/37.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/37.hmac_test_sha384_vectors.3543854361
Short name T651
Test name
Test status
Simulation time 219098403639 ps
CPU time 1986.73 seconds
Started Jun 27 06:47:42 PM PDT 24
Finished Jun 27 07:20:55 PM PDT 24
Peak memory 216304 kb
Host smart-81e5c163-725f-470d-a820-d67723c38033
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3543854361 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_test_sha384_vectors.3543854361
Directory /workspace/37.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/37.hmac_test_sha512_vectors.1433440876
Short name T161
Test name
Test status
Simulation time 149820425591 ps
CPU time 1956.37 seconds
Started Jun 27 06:47:37 PM PDT 24
Finished Jun 27 07:20:19 PM PDT 24
Peak memory 216348 kb
Host smart-578ec5f5-04e5-4139-827f-d6b980f09406
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1433440876 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_test_sha512_vectors.1433440876
Directory /workspace/37.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/37.hmac_wipe_secret.4031496055
Short name T338
Test name
Test status
Simulation time 1254326456 ps
CPU time 21.54 seconds
Started Jun 27 06:47:39 PM PDT 24
Finished Jun 27 06:48:06 PM PDT 24
Peak memory 199968 kb
Host smart-4125f9d3-94ec-45a8-84a6-46c9711f5858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031496055 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_wipe_secret.4031496055
Directory /workspace/37.hmac_wipe_secret/latest

Test location /workspace/coverage/default/38.hmac_alert_test.3988761257
Short name T343
Test name
Test status
Simulation time 19954369 ps
CPU time 0.57 seconds
Started Jun 27 06:47:40 PM PDT 24
Finished Jun 27 06:47:47 PM PDT 24
Peak memory 195992 kb
Host smart-3e7da5e6-1601-4be2-af9a-791c864cff80
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988761257 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_alert_test.3988761257
Directory /workspace/38.hmac_alert_test/latest

Test location /workspace/coverage/default/38.hmac_back_pressure.1540936833
Short name T572
Test name
Test status
Simulation time 1978360757 ps
CPU time 21.31 seconds
Started Jun 27 06:47:40 PM PDT 24
Finished Jun 27 06:48:08 PM PDT 24
Peak memory 199984 kb
Host smart-5d1f3a7c-fcc5-4754-b121-160c499d598c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1540936833 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_back_pressure.1540936833
Directory /workspace/38.hmac_back_pressure/latest

Test location /workspace/coverage/default/38.hmac_burst_wr.3275011863
Short name T146
Test name
Test status
Simulation time 144008247 ps
CPU time 7.38 seconds
Started Jun 27 06:47:37 PM PDT 24
Finished Jun 27 06:47:49 PM PDT 24
Peak memory 199952 kb
Host smart-02c142a0-27fd-418e-a7bd-1178b5350c91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275011863 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_burst_wr.3275011863
Directory /workspace/38.hmac_burst_wr/latest

Test location /workspace/coverage/default/38.hmac_datapath_stress.1323734047
Short name T460
Test name
Test status
Simulation time 1999433781 ps
CPU time 518.27 seconds
Started Jun 27 06:47:37 PM PDT 24
Finished Jun 27 06:56:19 PM PDT 24
Peak memory 714508 kb
Host smart-2a848cd2-9615-41b2-9ce0-0937e53e19fb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1323734047 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_datapath_stress.1323734047
Directory /workspace/38.hmac_datapath_stress/latest

Test location /workspace/coverage/default/38.hmac_error.4206880737
Short name T580
Test name
Test status
Simulation time 18855127739 ps
CPU time 59.28 seconds
Started Jun 27 06:47:39 PM PDT 24
Finished Jun 27 06:48:45 PM PDT 24
Peak memory 199336 kb
Host smart-cde67eb9-27b6-4bc4-980d-4365ccf6902c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206880737 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_error.4206880737
Directory /workspace/38.hmac_error/latest

Test location /workspace/coverage/default/38.hmac_long_msg.1794798120
Short name T478
Test name
Test status
Simulation time 10962567893 ps
CPU time 147.86 seconds
Started Jun 27 06:47:36 PM PDT 24
Finished Jun 27 06:50:06 PM PDT 24
Peak memory 216312 kb
Host smart-366434cc-1465-4525-a196-32c3e6cee019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794798120 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_long_msg.1794798120
Directory /workspace/38.hmac_long_msg/latest

Test location /workspace/coverage/default/38.hmac_smoke.2358557932
Short name T684
Test name
Test status
Simulation time 1586098004 ps
CPU time 8.99 seconds
Started Jun 27 06:47:38 PM PDT 24
Finished Jun 27 06:47:53 PM PDT 24
Peak memory 200104 kb
Host smart-3a0d9f78-4a1c-4d1f-bb64-ec3e2b2c3a00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2358557932 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_smoke.2358557932
Directory /workspace/38.hmac_smoke/latest

Test location /workspace/coverage/default/38.hmac_stress_all.213541615
Short name T25
Test name
Test status
Simulation time 34483663651 ps
CPU time 1457.24 seconds
Started Jun 27 06:47:38 PM PDT 24
Finished Jun 27 07:12:01 PM PDT 24
Peak memory 679716 kb
Host smart-71401918-e1a3-4a91-9e2b-938e1e6338c1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213541615 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 38.hmac_stress_all.213541615
Directory /workspace/38.hmac_stress_all/latest

Test location /workspace/coverage/default/38.hmac_test_hmac_vectors.1113224795
Short name T187
Test name
Test status
Simulation time 233956402 ps
CPU time 1.16 seconds
Started Jun 27 06:47:41 PM PDT 24
Finished Jun 27 06:47:48 PM PDT 24
Peak memory 199924 kb
Host smart-e2dae579-a991-48c8-abac-6f1efde3c7c4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113224795 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 38.hmac_test_hmac_vectors.1113224795
Directory /workspace/38.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/38.hmac_test_sha256_vectors.2378659281
Short name T687
Test name
Test status
Simulation time 56682801268 ps
CPU time 515.47 seconds
Started Jun 27 06:47:38 PM PDT 24
Finished Jun 27 06:56:20 PM PDT 24
Peak memory 200008 kb
Host smart-0487b7a5-c95d-4e1e-9533-13a02dad3bae
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2378659281 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_test_sha256_vectors.2378659281
Directory /workspace/38.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/38.hmac_test_sha384_vectors.3998211754
Short name T485
Test name
Test status
Simulation time 740047178808 ps
CPU time 1775.1 seconds
Started Jun 27 06:47:36 PM PDT 24
Finished Jun 27 07:17:13 PM PDT 24
Peak memory 215516 kb
Host smart-1f66f83f-e8d1-4e6c-9779-065208addd12
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3998211754 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_test_sha384_vectors.3998211754
Directory /workspace/38.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/38.hmac_wipe_secret.344473782
Short name T581
Test name
Test status
Simulation time 4083904557 ps
CPU time 38.32 seconds
Started Jun 27 06:47:38 PM PDT 24
Finished Jun 27 06:48:22 PM PDT 24
Peak memory 200032 kb
Host smart-4bebb513-633d-4f60-886c-d4eea44d4301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344473782 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_wipe_secret.344473782
Directory /workspace/38.hmac_wipe_secret/latest

Test location /workspace/coverage/default/39.hmac_alert_test.4228436900
Short name T467
Test name
Test status
Simulation time 12660321 ps
CPU time 0.6 seconds
Started Jun 27 06:47:43 PM PDT 24
Finished Jun 27 06:47:50 PM PDT 24
Peak memory 196064 kb
Host smart-980cc98e-6277-4724-bee5-e86384c72133
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228436900 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_alert_test.4228436900
Directory /workspace/39.hmac_alert_test/latest

Test location /workspace/coverage/default/39.hmac_back_pressure.941786119
Short name T481
Test name
Test status
Simulation time 141174155 ps
CPU time 5.13 seconds
Started Jun 27 06:47:39 PM PDT 24
Finished Jun 27 06:47:50 PM PDT 24
Peak memory 199980 kb
Host smart-efc942bf-2520-44e7-a48e-8f2933e9e522
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=941786119 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_back_pressure.941786119
Directory /workspace/39.hmac_back_pressure/latest

Test location /workspace/coverage/default/39.hmac_burst_wr.3831775933
Short name T406
Test name
Test status
Simulation time 1254458082 ps
CPU time 35.15 seconds
Started Jun 27 06:47:41 PM PDT 24
Finished Jun 27 06:48:22 PM PDT 24
Peak memory 199980 kb
Host smart-2a0c4e8e-8f2a-4ef1-9cac-47aa4d8521b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831775933 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_burst_wr.3831775933
Directory /workspace/39.hmac_burst_wr/latest

Test location /workspace/coverage/default/39.hmac_datapath_stress.1795921469
Short name T302
Test name
Test status
Simulation time 7959518511 ps
CPU time 1173.82 seconds
Started Jun 27 06:47:37 PM PDT 24
Finished Jun 27 07:07:16 PM PDT 24
Peak memory 768988 kb
Host smart-6da7e6ed-a02d-4d6d-b1ce-e569b556d6a8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1795921469 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_datapath_stress.1795921469
Directory /workspace/39.hmac_datapath_stress/latest

Test location /workspace/coverage/default/39.hmac_error.403051593
Short name T3
Test name
Test status
Simulation time 7841848589 ps
CPU time 135.52 seconds
Started Jun 27 06:47:36 PM PDT 24
Finished Jun 27 06:49:54 PM PDT 24
Peak memory 200008 kb
Host smart-83ab5311-5e24-4bef-9fa3-95a1329ce5cd
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403051593 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_error.403051593
Directory /workspace/39.hmac_error/latest

Test location /workspace/coverage/default/39.hmac_long_msg.3925726733
Short name T669
Test name
Test status
Simulation time 6230997641 ps
CPU time 110.58 seconds
Started Jun 27 06:47:39 PM PDT 24
Finished Jun 27 06:49:36 PM PDT 24
Peak memory 200040 kb
Host smart-db360816-1977-4187-99c2-c9affec17c38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3925726733 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_long_msg.3925726733
Directory /workspace/39.hmac_long_msg/latest

Test location /workspace/coverage/default/39.hmac_smoke.269354756
Short name T512
Test name
Test status
Simulation time 581956122 ps
CPU time 8.55 seconds
Started Jun 27 06:47:39 PM PDT 24
Finished Jun 27 06:47:53 PM PDT 24
Peak memory 199956 kb
Host smart-af190af7-9edb-4685-b151-5b261f472cd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269354756 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_smoke.269354756
Directory /workspace/39.hmac_smoke/latest

Test location /workspace/coverage/default/39.hmac_stress_all.1327951275
Short name T384
Test name
Test status
Simulation time 512584557732 ps
CPU time 4575.12 seconds
Started Jun 27 06:47:37 PM PDT 24
Finished Jun 27 08:03:55 PM PDT 24
Peak memory 409780 kb
Host smart-1d202937-ac08-4df6-b187-0a3f40961532
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327951275 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.hmac_stress_all.1327951275
Directory /workspace/39.hmac_stress_all/latest

Test location /workspace/coverage/default/39.hmac_test_hmac_vectors.4251803284
Short name T649
Test name
Test status
Simulation time 85884872 ps
CPU time 1.45 seconds
Started Jun 27 06:47:42 PM PDT 24
Finished Jun 27 06:47:50 PM PDT 24
Peak memory 199876 kb
Host smart-aed2a6d8-1ce3-4572-8d55-d8698d5dbf93
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251803284 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 39.hmac_test_hmac_vectors.4251803284
Directory /workspace/39.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/39.hmac_test_sha256_vectors.3424424444
Short name T510
Test name
Test status
Simulation time 35245839350 ps
CPU time 488.49 seconds
Started Jun 27 06:47:46 PM PDT 24
Finished Jun 27 06:56:00 PM PDT 24
Peak memory 199912 kb
Host smart-3b45891e-b29f-434e-9a19-951d44fc4881
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3424424444 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_test_sha256_vectors.3424424444
Directory /workspace/39.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/39.hmac_test_sha384_vectors.373877786
Short name T303
Test name
Test status
Simulation time 113241009567 ps
CPU time 1958.08 seconds
Started Jun 27 06:47:37 PM PDT 24
Finished Jun 27 07:20:18 PM PDT 24
Peak memory 216232 kb
Host smart-003e001d-7a7d-4ec3-91d8-261fe41e7886
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=373877786 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_test_sha384_vectors.373877786
Directory /workspace/39.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/39.hmac_test_sha512_vectors.1161713054
Short name T596
Test name
Test status
Simulation time 62803986994 ps
CPU time 1720.92 seconds
Started Jun 27 06:47:35 PM PDT 24
Finished Jun 27 07:16:18 PM PDT 24
Peak memory 216016 kb
Host smart-f5a21fd9-4468-47e3-a592-29722232a82e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1161713054 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_test_sha512_vectors.1161713054
Directory /workspace/39.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/39.hmac_wipe_secret.3905261911
Short name T20
Test name
Test status
Simulation time 1331324292 ps
CPU time 23.97 seconds
Started Jun 27 06:47:35 PM PDT 24
Finished Jun 27 06:48:00 PM PDT 24
Peak memory 199956 kb
Host smart-aeb1b990-8311-4b99-a786-fc9eb993197b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905261911 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_wipe_secret.3905261911
Directory /workspace/39.hmac_wipe_secret/latest

Test location /workspace/coverage/default/4.hmac_alert_test.934328157
Short name T348
Test name
Test status
Simulation time 15723193 ps
CPU time 0.64 seconds
Started Jun 27 06:46:27 PM PDT 24
Finished Jun 27 06:46:39 PM PDT 24
Peak memory 196060 kb
Host smart-746919a5-0f81-4e28-a4e5-3d5dd0147cf6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934328157 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_alert_test.934328157
Directory /workspace/4.hmac_alert_test/latest

Test location /workspace/coverage/default/4.hmac_back_pressure.3685555576
Short name T94
Test name
Test status
Simulation time 118597570 ps
CPU time 6.59 seconds
Started Jun 27 06:46:23 PM PDT 24
Finished Jun 27 06:46:38 PM PDT 24
Peak memory 199940 kb
Host smart-c943d199-7928-4c94-96b2-50ed02d467e8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3685555576 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_back_pressure.3685555576
Directory /workspace/4.hmac_back_pressure/latest

Test location /workspace/coverage/default/4.hmac_burst_wr.2947986220
Short name T627
Test name
Test status
Simulation time 9071689978 ps
CPU time 43.81 seconds
Started Jun 27 06:46:24 PM PDT 24
Finished Jun 27 06:47:16 PM PDT 24
Peak memory 208244 kb
Host smart-feb68ef6-47a7-4bce-ac12-f2419b0094f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947986220 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_burst_wr.2947986220
Directory /workspace/4.hmac_burst_wr/latest

Test location /workspace/coverage/default/4.hmac_datapath_stress.2786537485
Short name T147
Test name
Test status
Simulation time 3891811388 ps
CPU time 946.98 seconds
Started Jun 27 06:46:21 PM PDT 24
Finished Jun 27 07:02:15 PM PDT 24
Peak memory 740156 kb
Host smart-daff412a-2ac5-48fe-b125-815b7c6b4401
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2786537485 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_datapath_stress.2786537485
Directory /workspace/4.hmac_datapath_stress/latest

Test location /workspace/coverage/default/4.hmac_error.3083395334
Short name T248
Test name
Test status
Simulation time 21220726254 ps
CPU time 158.19 seconds
Started Jun 27 06:46:24 PM PDT 24
Finished Jun 27 06:49:11 PM PDT 24
Peak memory 200016 kb
Host smart-104c2286-d40c-4200-af8f-0a69a45aa52d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083395334 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_error.3083395334
Directory /workspace/4.hmac_error/latest

Test location /workspace/coverage/default/4.hmac_long_msg.69611095
Short name T273
Test name
Test status
Simulation time 13440351035 ps
CPU time 67.71 seconds
Started Jun 27 06:46:25 PM PDT 24
Finished Jun 27 06:47:43 PM PDT 24
Peak memory 200044 kb
Host smart-3399fb2e-7200-4f95-a49a-9a4a00776901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69611095 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_long_msg.69611095
Directory /workspace/4.hmac_long_msg/latest

Test location /workspace/coverage/default/4.hmac_sec_cm.2422847284
Short name T44
Test name
Test status
Simulation time 129561475 ps
CPU time 0.92 seconds
Started Jun 27 06:46:27 PM PDT 24
Finished Jun 27 06:46:40 PM PDT 24
Peak memory 218360 kb
Host smart-d95b375b-e8a5-483a-8e3e-f9a72555d2a7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422847284 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_sec_cm.2422847284
Directory /workspace/4.hmac_sec_cm/latest

Test location /workspace/coverage/default/4.hmac_smoke.3695428089
Short name T148
Test name
Test status
Simulation time 202979089 ps
CPU time 9.26 seconds
Started Jun 27 06:46:26 PM PDT 24
Finished Jun 27 06:46:47 PM PDT 24
Peak memory 199996 kb
Host smart-745ebca6-8d88-42c8-8256-e6046af5da0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695428089 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_smoke.3695428089
Directory /workspace/4.hmac_smoke/latest

Test location /workspace/coverage/default/4.hmac_test_hmac_vectors.3915993768
Short name T269
Test name
Test status
Simulation time 36237160 ps
CPU time 1.31 seconds
Started Jun 27 06:46:29 PM PDT 24
Finished Jun 27 06:46:44 PM PDT 24
Peak memory 199904 kb
Host smart-3f2ad9a8-96c2-40a3-bb80-61708e31ae3d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915993768 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac_vectors.3915993768
Directory /workspace/4.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha256_vectors.2440912097
Short name T417
Test name
Test status
Simulation time 34953375852 ps
CPU time 468.59 seconds
Started Jun 27 06:46:29 PM PDT 24
Finished Jun 27 06:54:31 PM PDT 24
Peak memory 200012 kb
Host smart-6359e2ae-25fc-4c35-ac4b-70434358ceb8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2440912097 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha256_vectors.2440912097
Directory /workspace/4.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha384_vectors.3675655685
Short name T597
Test name
Test status
Simulation time 95371864040 ps
CPU time 1623.51 seconds
Started Jun 27 06:46:29 PM PDT 24
Finished Jun 27 07:13:46 PM PDT 24
Peak memory 215484 kb
Host smart-e3ed1506-d9a5-4e69-bfe7-b95e458797e3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3675655685 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha384_vectors.3675655685
Directory /workspace/4.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha512_vectors.3702783153
Short name T558
Test name
Test status
Simulation time 471567626697 ps
CPU time 1634.14 seconds
Started Jun 27 06:46:28 PM PDT 24
Finished Jun 27 07:13:56 PM PDT 24
Peak memory 215860 kb
Host smart-877af6e0-e7b7-4985-a9a3-1684e5a9f6c7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3702783153 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha512_vectors.3702783153
Directory /workspace/4.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/4.hmac_wipe_secret.2402222283
Short name T641
Test name
Test status
Simulation time 9724875477 ps
CPU time 62.78 seconds
Started Jun 27 06:46:28 PM PDT 24
Finished Jun 27 06:47:44 PM PDT 24
Peak memory 199948 kb
Host smart-60f103df-6b8e-4474-b547-03d273280aba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2402222283 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_wipe_secret.2402222283
Directory /workspace/4.hmac_wipe_secret/latest

Test location /workspace/coverage/default/40.hmac_alert_test.3564997176
Short name T648
Test name
Test status
Simulation time 15005396 ps
CPU time 0.59 seconds
Started Jun 27 06:47:41 PM PDT 24
Finished Jun 27 06:47:47 PM PDT 24
Peak memory 196748 kb
Host smart-b4e76ed0-c88b-41ce-a474-cc2a45d99750
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564997176 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_alert_test.3564997176
Directory /workspace/40.hmac_alert_test/latest

Test location /workspace/coverage/default/40.hmac_back_pressure.1173590673
Short name T256
Test name
Test status
Simulation time 1118224472 ps
CPU time 53.03 seconds
Started Jun 27 06:47:39 PM PDT 24
Finished Jun 27 06:48:38 PM PDT 24
Peak memory 199936 kb
Host smart-9e334170-d233-420f-9ddd-9d2a1683004f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1173590673 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_back_pressure.1173590673
Directory /workspace/40.hmac_back_pressure/latest

Test location /workspace/coverage/default/40.hmac_burst_wr.1135512933
Short name T370
Test name
Test status
Simulation time 1327137119 ps
CPU time 24.83 seconds
Started Jun 27 06:47:38 PM PDT 24
Finished Jun 27 06:48:09 PM PDT 24
Peak memory 199936 kb
Host smart-c8b75564-8e15-4fcb-8d50-a5d8762ab9cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135512933 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_burst_wr.1135512933
Directory /workspace/40.hmac_burst_wr/latest

Test location /workspace/coverage/default/40.hmac_datapath_stress.1752683431
Short name T218
Test name
Test status
Simulation time 16250471566 ps
CPU time 965.68 seconds
Started Jun 27 06:47:38 PM PDT 24
Finished Jun 27 07:03:49 PM PDT 24
Peak memory 723816 kb
Host smart-70671db6-9a48-4440-b97a-a84b0cc8cc85
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1752683431 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_datapath_stress.1752683431
Directory /workspace/40.hmac_datapath_stress/latest

Test location /workspace/coverage/default/40.hmac_error.688721187
Short name T317
Test name
Test status
Simulation time 9911799372 ps
CPU time 11.37 seconds
Started Jun 27 06:47:40 PM PDT 24
Finished Jun 27 06:47:57 PM PDT 24
Peak memory 200004 kb
Host smart-d078ca2f-28f3-4bf8-b947-3454b83b7ff9
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688721187 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_error.688721187
Directory /workspace/40.hmac_error/latest

Test location /workspace/coverage/default/40.hmac_long_msg.3744347331
Short name T461
Test name
Test status
Simulation time 1251613069 ps
CPU time 19.66 seconds
Started Jun 27 06:47:36 PM PDT 24
Finished Jun 27 06:47:59 PM PDT 24
Peak memory 199964 kb
Host smart-4fe36118-2970-4415-9958-59aceea03d5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744347331 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_long_msg.3744347331
Directory /workspace/40.hmac_long_msg/latest

Test location /workspace/coverage/default/40.hmac_smoke.3604630609
Short name T602
Test name
Test status
Simulation time 265815410 ps
CPU time 4.18 seconds
Started Jun 27 06:47:39 PM PDT 24
Finished Jun 27 06:47:50 PM PDT 24
Peak memory 199336 kb
Host smart-b4d262ec-dcd0-4e99-a151-756872ddae0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604630609 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_smoke.3604630609
Directory /workspace/40.hmac_smoke/latest

Test location /workspace/coverage/default/40.hmac_stress_all.590301112
Short name T272
Test name
Test status
Simulation time 3169100138 ps
CPU time 57.29 seconds
Started Jun 27 06:47:40 PM PDT 24
Finished Jun 27 06:48:44 PM PDT 24
Peak memory 208240 kb
Host smart-6620d6fc-3a0c-40f1-a6a8-3a537730ad5a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590301112 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 40.hmac_stress_all.590301112
Directory /workspace/40.hmac_stress_all/latest

Test location /workspace/coverage/default/40.hmac_test_hmac_vectors.762146104
Short name T319
Test name
Test status
Simulation time 30276920 ps
CPU time 1.12 seconds
Started Jun 27 06:47:40 PM PDT 24
Finished Jun 27 06:47:48 PM PDT 24
Peak memory 199856 kb
Host smart-95b870b1-36ff-4ad1-9ae5-7c8a99472f56
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762146104 -assert nopostpr
oc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 40.hmac_test_hmac_vectors.762146104
Directory /workspace/40.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/40.hmac_test_sha256_vectors.241740535
Short name T8
Test name
Test status
Simulation time 116474698406 ps
CPU time 527.43 seconds
Started Jun 27 06:47:41 PM PDT 24
Finished Jun 27 06:56:34 PM PDT 24
Peak memory 199900 kb
Host smart-e1518c90-d2cc-4589-a923-e14bc03a2f48
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=241740535 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_test_sha256_vectors.241740535
Directory /workspace/40.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/40.hmac_test_sha384_vectors.3729469682
Short name T401
Test name
Test status
Simulation time 100532489990 ps
CPU time 1734.4 seconds
Started Jun 27 06:47:44 PM PDT 24
Finished Jun 27 07:16:44 PM PDT 24
Peak memory 215692 kb
Host smart-d0bc026d-5f7d-4ccf-a40e-57e0454b87d4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3729469682 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_test_sha384_vectors.3729469682
Directory /workspace/40.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/40.hmac_test_sha512_vectors.1384832633
Short name T10
Test name
Test status
Simulation time 221204164865 ps
CPU time 1668.04 seconds
Started Jun 27 06:47:38 PM PDT 24
Finished Jun 27 07:15:31 PM PDT 24
Peak memory 216236 kb
Host smart-0b7285aa-c53e-4b4e-ab4d-b2cad12efe88
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1384832633 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_test_sha512_vectors.1384832633
Directory /workspace/40.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/40.hmac_wipe_secret.3638875056
Short name T476
Test name
Test status
Simulation time 27719565467 ps
CPU time 54.32 seconds
Started Jun 27 06:47:43 PM PDT 24
Finished Jun 27 06:48:43 PM PDT 24
Peak memory 200032 kb
Host smart-04bf6844-ae60-40cd-9fc5-d025bc950fef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638875056 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_wipe_secret.3638875056
Directory /workspace/40.hmac_wipe_secret/latest

Test location /workspace/coverage/default/41.hmac_alert_test.982937774
Short name T244
Test name
Test status
Simulation time 177667905 ps
CPU time 0.56 seconds
Started Jun 27 06:47:39 PM PDT 24
Finished Jun 27 06:47:46 PM PDT 24
Peak memory 196000 kb
Host smart-87dc5500-6ccb-400d-9746-9c999b2f0def
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982937774 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_alert_test.982937774
Directory /workspace/41.hmac_alert_test/latest

Test location /workspace/coverage/default/41.hmac_back_pressure.1314351830
Short name T95
Test name
Test status
Simulation time 138699862 ps
CPU time 4.17 seconds
Started Jun 27 06:47:38 PM PDT 24
Finished Jun 27 06:47:47 PM PDT 24
Peak memory 199916 kb
Host smart-d95705aa-f3c0-462b-90e6-75c2d0e7050b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1314351830 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_back_pressure.1314351830
Directory /workspace/41.hmac_back_pressure/latest

Test location /workspace/coverage/default/41.hmac_burst_wr.719710359
Short name T222
Test name
Test status
Simulation time 992783065 ps
CPU time 15.87 seconds
Started Jun 27 06:47:39 PM PDT 24
Finished Jun 27 06:48:00 PM PDT 24
Peak memory 199252 kb
Host smart-13c00f42-aea2-4ecb-8938-b422e9d4a5c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719710359 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_burst_wr.719710359
Directory /workspace/41.hmac_burst_wr/latest

Test location /workspace/coverage/default/41.hmac_datapath_stress.3915397071
Short name T214
Test name
Test status
Simulation time 38016529729 ps
CPU time 587.17 seconds
Started Jun 27 06:47:42 PM PDT 24
Finished Jun 27 06:57:36 PM PDT 24
Peak memory 733368 kb
Host smart-c147996c-01d0-46f8-b75d-128752c36f4b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3915397071 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_datapath_stress.3915397071
Directory /workspace/41.hmac_datapath_stress/latest

Test location /workspace/coverage/default/41.hmac_error.3285666943
Short name T456
Test name
Test status
Simulation time 18948983013 ps
CPU time 87.26 seconds
Started Jun 27 06:47:41 PM PDT 24
Finished Jun 27 06:49:15 PM PDT 24
Peak memory 200040 kb
Host smart-8aa07718-dbdb-454f-8ae4-10668be7c930
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285666943 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_error.3285666943
Directory /workspace/41.hmac_error/latest

Test location /workspace/coverage/default/41.hmac_long_msg.2347586242
Short name T157
Test name
Test status
Simulation time 9104117745 ps
CPU time 42.82 seconds
Started Jun 27 06:47:38 PM PDT 24
Finished Jun 27 06:48:27 PM PDT 24
Peak memory 216240 kb
Host smart-e126da4c-2ace-4421-9baf-1f39418d2cc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2347586242 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_long_msg.2347586242
Directory /workspace/41.hmac_long_msg/latest

Test location /workspace/coverage/default/41.hmac_smoke.2551282303
Short name T480
Test name
Test status
Simulation time 2721025748 ps
CPU time 15.18 seconds
Started Jun 27 06:47:42 PM PDT 24
Finished Jun 27 06:48:04 PM PDT 24
Peak memory 200024 kb
Host smart-b60e65f6-aa95-4b06-b6de-efce3150aa88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2551282303 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_smoke.2551282303
Directory /workspace/41.hmac_smoke/latest

Test location /workspace/coverage/default/41.hmac_stress_all.1672823437
Short name T504
Test name
Test status
Simulation time 110238974053 ps
CPU time 184.03 seconds
Started Jun 27 06:47:38 PM PDT 24
Finished Jun 27 06:50:47 PM PDT 24
Peak memory 200328 kb
Host smart-3ae35c8c-26e0-4077-b419-3c66743ce403
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672823437 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.hmac_stress_all.1672823437
Directory /workspace/41.hmac_stress_all/latest

Test location /workspace/coverage/default/41.hmac_test_hmac_vectors.2344428318
Short name T151
Test name
Test status
Simulation time 226582250 ps
CPU time 1.27 seconds
Started Jun 27 06:47:46 PM PDT 24
Finished Jun 27 06:47:52 PM PDT 24
Peak memory 199972 kb
Host smart-43b0fb9e-b293-40d3-a49a-7b339bc0065c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344428318 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 41.hmac_test_hmac_vectors.2344428318
Directory /workspace/41.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/41.hmac_test_sha256_vectors.1733269508
Short name T81
Test name
Test status
Simulation time 7873073658 ps
CPU time 437.04 seconds
Started Jun 27 06:47:46 PM PDT 24
Finished Jun 27 06:55:08 PM PDT 24
Peak memory 200020 kb
Host smart-bc39970c-9087-4669-a43e-749396d299bf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1733269508 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_test_sha256_vectors.1733269508
Directory /workspace/41.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/41.hmac_test_sha384_vectors.2674839227
Short name T253
Test name
Test status
Simulation time 164758784340 ps
CPU time 2026.62 seconds
Started Jun 27 06:47:39 PM PDT 24
Finished Jun 27 07:21:31 PM PDT 24
Peak memory 215416 kb
Host smart-81b9edc1-3b8d-4017-9844-34e25873abb6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2674839227 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_test_sha384_vectors.2674839227
Directory /workspace/41.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/41.hmac_test_sha512_vectors.1650791664
Short name T604
Test name
Test status
Simulation time 152875848054 ps
CPU time 1871.98 seconds
Started Jun 27 06:47:39 PM PDT 24
Finished Jun 27 07:18:57 PM PDT 24
Peak memory 215440 kb
Host smart-d8259621-8241-4f4f-aa0d-4a32e4d3bedf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1650791664 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_test_sha512_vectors.1650791664
Directory /workspace/41.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/41.hmac_wipe_secret.1302463535
Short name T600
Test name
Test status
Simulation time 9569990807 ps
CPU time 44.93 seconds
Started Jun 27 06:47:42 PM PDT 24
Finished Jun 27 06:48:34 PM PDT 24
Peak memory 200036 kb
Host smart-d5818653-4c2f-4e4e-8dc1-3e6fa9e9e714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302463535 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_wipe_secret.1302463535
Directory /workspace/41.hmac_wipe_secret/latest

Test location /workspace/coverage/default/42.hmac_alert_test.2174949811
Short name T286
Test name
Test status
Simulation time 22873149 ps
CPU time 0.61 seconds
Started Jun 27 06:48:02 PM PDT 24
Finished Jun 27 06:48:07 PM PDT 24
Peak memory 195996 kb
Host smart-69e5b8eb-6a6a-449f-b1f2-a8f02f2057d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174949811 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_alert_test.2174949811
Directory /workspace/42.hmac_alert_test/latest

Test location /workspace/coverage/default/42.hmac_back_pressure.3265317669
Short name T345
Test name
Test status
Simulation time 361641242 ps
CPU time 18.52 seconds
Started Jun 27 06:47:39 PM PDT 24
Finished Jun 27 06:48:04 PM PDT 24
Peak memory 199976 kb
Host smart-b3a55232-4ae9-4782-96c1-ae4fe6f370b3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3265317669 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_back_pressure.3265317669
Directory /workspace/42.hmac_back_pressure/latest

Test location /workspace/coverage/default/42.hmac_burst_wr.2556484750
Short name T416
Test name
Test status
Simulation time 259111600 ps
CPU time 3.87 seconds
Started Jun 27 06:47:38 PM PDT 24
Finished Jun 27 06:47:47 PM PDT 24
Peak memory 199976 kb
Host smart-5a423a4b-c092-43ad-aade-a5a085173ef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556484750 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_burst_wr.2556484750
Directory /workspace/42.hmac_burst_wr/latest

Test location /workspace/coverage/default/42.hmac_datapath_stress.247141072
Short name T501
Test name
Test status
Simulation time 17393899032 ps
CPU time 794.83 seconds
Started Jun 27 06:47:40 PM PDT 24
Finished Jun 27 07:01:01 PM PDT 24
Peak memory 649572 kb
Host smart-ee122650-a385-4c59-b6a8-2c4ba9332692
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=247141072 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_datapath_stress.247141072
Directory /workspace/42.hmac_datapath_stress/latest

Test location /workspace/coverage/default/42.hmac_error.3500627057
Short name T532
Test name
Test status
Simulation time 2755011488 ps
CPU time 46.39 seconds
Started Jun 27 06:47:46 PM PDT 24
Finished Jun 27 06:48:38 PM PDT 24
Peak memory 199984 kb
Host smart-3fda9f6b-d56e-4559-9691-7e1234492459
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500627057 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_error.3500627057
Directory /workspace/42.hmac_error/latest

Test location /workspace/coverage/default/42.hmac_long_msg.1535054025
Short name T652
Test name
Test status
Simulation time 4616956956 ps
CPU time 83.22 seconds
Started Jun 27 06:47:36 PM PDT 24
Finished Jun 27 06:49:02 PM PDT 24
Peak memory 200008 kb
Host smart-f763681d-6438-4125-b2f0-17d97f954ac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535054025 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_long_msg.1535054025
Directory /workspace/42.hmac_long_msg/latest

Test location /workspace/coverage/default/42.hmac_smoke.1745495252
Short name T567
Test name
Test status
Simulation time 120447899 ps
CPU time 3.42 seconds
Started Jun 27 06:47:39 PM PDT 24
Finished Jun 27 06:47:48 PM PDT 24
Peak memory 199952 kb
Host smart-280f86bd-ee82-4e6a-811e-4de0b83123fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745495252 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_smoke.1745495252
Directory /workspace/42.hmac_smoke/latest

Test location /workspace/coverage/default/42.hmac_stress_all.2187607793
Short name T249
Test name
Test status
Simulation time 268323718334 ps
CPU time 3287.45 seconds
Started Jun 27 06:48:01 PM PDT 24
Finished Jun 27 07:42:53 PM PDT 24
Peak memory 216408 kb
Host smart-b42f5b36-03c0-41c0-b129-d7f5063e0260
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187607793 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.hmac_stress_all.2187607793
Directory /workspace/42.hmac_stress_all/latest

Test location /workspace/coverage/default/42.hmac_test_hmac_vectors.3323643156
Short name T508
Test name
Test status
Simulation time 63839713 ps
CPU time 1.37 seconds
Started Jun 27 06:47:58 PM PDT 24
Finished Jun 27 06:48:01 PM PDT 24
Peak memory 199872 kb
Host smart-b3a2b49f-76f4-4eb0-b8de-0cc8cd0cd057
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323643156 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 42.hmac_test_hmac_vectors.3323643156
Directory /workspace/42.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/42.hmac_test_sha256_vectors.1505963651
Short name T233
Test name
Test status
Simulation time 92079565387 ps
CPU time 492.73 seconds
Started Jun 27 06:48:00 PM PDT 24
Finished Jun 27 06:56:16 PM PDT 24
Peak memory 200016 kb
Host smart-d5372407-2fae-4095-90fc-82ea0cb6dd1d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1505963651 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_test_sha256_vectors.1505963651
Directory /workspace/42.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/42.hmac_test_sha384_vectors.1963219064
Short name T160
Test name
Test status
Simulation time 473447298956 ps
CPU time 1855.4 seconds
Started Jun 27 06:48:03 PM PDT 24
Finished Jun 27 07:19:03 PM PDT 24
Peak memory 215596 kb
Host smart-a934e903-634f-447c-ae90-3537ced697c1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1963219064 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_test_sha384_vectors.1963219064
Directory /workspace/42.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/42.hmac_test_sha512_vectors.871441862
Short name T340
Test name
Test status
Simulation time 116721075203 ps
CPU time 1564.24 seconds
Started Jun 27 06:47:58 PM PDT 24
Finished Jun 27 07:14:04 PM PDT 24
Peak memory 208404 kb
Host smart-c2af84b0-6036-4ba3-a421-2d313896ceb9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=871441862 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_test_sha512_vectors.871441862
Directory /workspace/42.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/42.hmac_wipe_secret.2897378106
Short name T92
Test name
Test status
Simulation time 6122917860 ps
CPU time 81.94 seconds
Started Jun 27 06:47:45 PM PDT 24
Finished Jun 27 06:49:13 PM PDT 24
Peak memory 199952 kb
Host smart-baacebef-5178-49a3-9551-431521a11149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897378106 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_wipe_secret.2897378106
Directory /workspace/42.hmac_wipe_secret/latest

Test location /workspace/coverage/default/43.hmac_alert_test.1292656470
Short name T318
Test name
Test status
Simulation time 12062563 ps
CPU time 0.6 seconds
Started Jun 27 06:48:02 PM PDT 24
Finished Jun 27 06:48:07 PM PDT 24
Peak memory 195728 kb
Host smart-928b693f-127c-400f-9dad-443f03d8c582
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292656470 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_alert_test.1292656470
Directory /workspace/43.hmac_alert_test/latest

Test location /workspace/coverage/default/43.hmac_back_pressure.2643656586
Short name T493
Test name
Test status
Simulation time 229839335 ps
CPU time 9.19 seconds
Started Jun 27 06:48:00 PM PDT 24
Finished Jun 27 06:48:11 PM PDT 24
Peak memory 199888 kb
Host smart-7f78e457-6510-49e0-9d2e-eea151eafbb5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2643656586 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_back_pressure.2643656586
Directory /workspace/43.hmac_back_pressure/latest

Test location /workspace/coverage/default/43.hmac_burst_wr.3880643969
Short name T500
Test name
Test status
Simulation time 5145697849 ps
CPU time 72.72 seconds
Started Jun 27 06:48:03 PM PDT 24
Finished Jun 27 06:49:20 PM PDT 24
Peak memory 200040 kb
Host smart-4a911b89-eba9-4681-84d1-c6343c65fbad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880643969 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_burst_wr.3880643969
Directory /workspace/43.hmac_burst_wr/latest

Test location /workspace/coverage/default/43.hmac_datapath_stress.3374258466
Short name T198
Test name
Test status
Simulation time 6624901297 ps
CPU time 827.56 seconds
Started Jun 27 06:48:01 PM PDT 24
Finished Jun 27 07:01:52 PM PDT 24
Peak memory 762744 kb
Host smart-ef7587bc-2947-4a6e-8901-98b1719c1de1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3374258466 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_datapath_stress.3374258466
Directory /workspace/43.hmac_datapath_stress/latest

Test location /workspace/coverage/default/43.hmac_error.2033902821
Short name T225
Test name
Test status
Simulation time 8425951337 ps
CPU time 26.32 seconds
Started Jun 27 06:48:00 PM PDT 24
Finished Jun 27 06:48:29 PM PDT 24
Peak memory 199984 kb
Host smart-ef60eb62-cd2f-4d7b-bc9a-d3ad0f85bc6d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033902821 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_error.2033902821
Directory /workspace/43.hmac_error/latest

Test location /workspace/coverage/default/43.hmac_long_msg.2638445165
Short name T229
Test name
Test status
Simulation time 21916460866 ps
CPU time 101.24 seconds
Started Jun 27 06:48:02 PM PDT 24
Finished Jun 27 06:49:47 PM PDT 24
Peak memory 200040 kb
Host smart-a96dc25a-4b16-442b-9878-9a4381f025ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638445165 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_long_msg.2638445165
Directory /workspace/43.hmac_long_msg/latest

Test location /workspace/coverage/default/43.hmac_smoke.1422299465
Short name T490
Test name
Test status
Simulation time 647258104 ps
CPU time 6.16 seconds
Started Jun 27 06:47:59 PM PDT 24
Finished Jun 27 06:48:07 PM PDT 24
Peak memory 199968 kb
Host smart-069660bb-d98e-44ef-b978-ffe5bfe7eb51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422299465 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_smoke.1422299465
Directory /workspace/43.hmac_smoke/latest

Test location /workspace/coverage/default/43.hmac_stress_all.1356302121
Short name T633
Test name
Test status
Simulation time 588839380643 ps
CPU time 1350.07 seconds
Started Jun 27 06:48:02 PM PDT 24
Finished Jun 27 07:10:36 PM PDT 24
Peak memory 711716 kb
Host smart-a85daa90-cc5c-4a53-b764-f04d3735def5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356302121 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.hmac_stress_all.1356302121
Directory /workspace/43.hmac_stress_all/latest

Test location /workspace/coverage/default/43.hmac_test_hmac_vectors.2446775322
Short name T469
Test name
Test status
Simulation time 92130139 ps
CPU time 1.08 seconds
Started Jun 27 06:47:59 PM PDT 24
Finished Jun 27 06:48:01 PM PDT 24
Peak memory 199724 kb
Host smart-a8437480-275b-467e-8599-a5e60d60be21
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446775322 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 43.hmac_test_hmac_vectors.2446775322
Directory /workspace/43.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/43.hmac_test_sha256_vectors.111216017
Short name T647
Test name
Test status
Simulation time 81807230658 ps
CPU time 530.14 seconds
Started Jun 27 06:48:00 PM PDT 24
Finished Jun 27 06:56:53 PM PDT 24
Peak memory 199988 kb
Host smart-f4701a55-1e0b-4575-90b8-e9ecddedc581
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=111216017 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_test_sha256_vectors.111216017
Directory /workspace/43.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/43.hmac_test_sha384_vectors.3075536331
Short name T533
Test name
Test status
Simulation time 143417743086 ps
CPU time 1735.05 seconds
Started Jun 27 06:47:58 PM PDT 24
Finished Jun 27 07:16:54 PM PDT 24
Peak memory 208244 kb
Host smart-21f91279-38fb-4ae4-ae9b-0100eea9007f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3075536331 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_test_sha384_vectors.3075536331
Directory /workspace/43.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/43.hmac_test_sha512_vectors.791401118
Short name T371
Test name
Test status
Simulation time 609532005327 ps
CPU time 2030.34 seconds
Started Jun 27 06:48:02 PM PDT 24
Finished Jun 27 07:21:58 PM PDT 24
Peak memory 215436 kb
Host smart-3dd33ba9-aee4-4aff-b3e8-80f47cf5403d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=791401118 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_test_sha512_vectors.791401118
Directory /workspace/43.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/43.hmac_wipe_secret.3577171819
Short name T377
Test name
Test status
Simulation time 8884192507 ps
CPU time 54.58 seconds
Started Jun 27 06:48:02 PM PDT 24
Finished Jun 27 06:49:01 PM PDT 24
Peak memory 200076 kb
Host smart-5f171ad6-88d4-4eed-b7b1-1b30bae34bd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577171819 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_wipe_secret.3577171819
Directory /workspace/43.hmac_wipe_secret/latest

Test location /workspace/coverage/default/44.hmac_alert_test.4129197957
Short name T482
Test name
Test status
Simulation time 14120134 ps
CPU time 0.62 seconds
Started Jun 27 06:48:03 PM PDT 24
Finished Jun 27 06:48:08 PM PDT 24
Peak memory 195812 kb
Host smart-afa0b8ae-eb8e-44a7-b94c-d8cec4edf815
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129197957 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_alert_test.4129197957
Directory /workspace/44.hmac_alert_test/latest

Test location /workspace/coverage/default/44.hmac_back_pressure.3940653211
Short name T149
Test name
Test status
Simulation time 961216802 ps
CPU time 9.37 seconds
Started Jun 27 06:48:00 PM PDT 24
Finished Jun 27 06:48:12 PM PDT 24
Peak memory 199916 kb
Host smart-ea114a1b-077f-4a9d-9c3b-b40e35069379
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3940653211 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_back_pressure.3940653211
Directory /workspace/44.hmac_back_pressure/latest

Test location /workspace/coverage/default/44.hmac_burst_wr.757992298
Short name T179
Test name
Test status
Simulation time 2826819720 ps
CPU time 16.41 seconds
Started Jun 27 06:48:00 PM PDT 24
Finished Jun 27 06:48:19 PM PDT 24
Peak memory 199968 kb
Host smart-6d6f94ad-40af-47d5-a657-23e940abd899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757992298 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_burst_wr.757992298
Directory /workspace/44.hmac_burst_wr/latest

Test location /workspace/coverage/default/44.hmac_datapath_stress.4045657184
Short name T540
Test name
Test status
Simulation time 16998101083 ps
CPU time 1154.17 seconds
Started Jun 27 06:48:02 PM PDT 24
Finished Jun 27 07:07:21 PM PDT 24
Peak memory 705880 kb
Host smart-f9ec87f2-9ff3-4571-b42e-1ab9f0762925
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4045657184 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_datapath_stress.4045657184
Directory /workspace/44.hmac_datapath_stress/latest

Test location /workspace/coverage/default/44.hmac_error.4162671590
Short name T282
Test name
Test status
Simulation time 22228239172 ps
CPU time 103.08 seconds
Started Jun 27 06:48:01 PM PDT 24
Finished Jun 27 06:49:47 PM PDT 24
Peak memory 200012 kb
Host smart-3d22fb05-a817-4569-b4c4-8ecce72887c8
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162671590 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_error.4162671590
Directory /workspace/44.hmac_error/latest

Test location /workspace/coverage/default/44.hmac_smoke.2806552533
Short name T339
Test name
Test status
Simulation time 5714250256 ps
CPU time 22.53 seconds
Started Jun 27 06:48:03 PM PDT 24
Finished Jun 27 06:48:30 PM PDT 24
Peak memory 200028 kb
Host smart-c89fa02b-e972-4da8-895d-7783a06c5b30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806552533 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_smoke.2806552533
Directory /workspace/44.hmac_smoke/latest

Test location /workspace/coverage/default/44.hmac_stress_all.2415043054
Short name T358
Test name
Test status
Simulation time 267587282050 ps
CPU time 4411.48 seconds
Started Jun 27 06:48:05 PM PDT 24
Finished Jun 27 08:01:41 PM PDT 24
Peak memory 715072 kb
Host smart-b670d79b-09d6-4f36-8c2f-4c6fe5b19e40
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415043054 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.hmac_stress_all.2415043054
Directory /workspace/44.hmac_stress_all/latest

Test location /workspace/coverage/default/44.hmac_test_hmac_vectors.1508757278
Short name T546
Test name
Test status
Simulation time 198287847 ps
CPU time 1.33 seconds
Started Jun 27 06:48:03 PM PDT 24
Finished Jun 27 06:48:09 PM PDT 24
Peak memory 200064 kb
Host smart-1f223622-4c66-49ad-81b2-eb3fd21e93f3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508757278 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 44.hmac_test_hmac_vectors.1508757278
Directory /workspace/44.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/44.hmac_test_sha256_vectors.2233937921
Short name T213
Test name
Test status
Simulation time 15513229121 ps
CPU time 437.86 seconds
Started Jun 27 06:48:01 PM PDT 24
Finished Jun 27 06:55:23 PM PDT 24
Peak memory 200040 kb
Host smart-11b71422-d23f-4bee-b608-670692eebb12
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2233937921 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_test_sha256_vectors.2233937921
Directory /workspace/44.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/44.hmac_test_sha384_vectors.959105555
Short name T559
Test name
Test status
Simulation time 208665844796 ps
CPU time 1874.62 seconds
Started Jun 27 06:48:02 PM PDT 24
Finished Jun 27 07:19:21 PM PDT 24
Peak memory 208244 kb
Host smart-b68838a0-5b44-4f02-9783-06c08a7a7a8f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=959105555 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_test_sha384_vectors.959105555
Directory /workspace/44.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/44.hmac_test_sha512_vectors.1118059045
Short name T219
Test name
Test status
Simulation time 112044929212 ps
CPU time 1973.77 seconds
Started Jun 27 06:48:03 PM PDT 24
Finished Jun 27 07:21:02 PM PDT 24
Peak memory 216120 kb
Host smart-57ea6d32-3d01-4edb-93eb-6cb3a8ca060a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1118059045 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_test_sha512_vectors.1118059045
Directory /workspace/44.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/44.hmac_wipe_secret.1099707655
Short name T477
Test name
Test status
Simulation time 15359668504 ps
CPU time 53.17 seconds
Started Jun 27 06:48:03 PM PDT 24
Finished Jun 27 06:49:01 PM PDT 24
Peak memory 200200 kb
Host smart-095352d5-95cf-48ea-a8d1-4cc5a753927d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099707655 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_wipe_secret.1099707655
Directory /workspace/44.hmac_wipe_secret/latest

Test location /workspace/coverage/default/45.hmac_alert_test.1855136529
Short name T442
Test name
Test status
Simulation time 142393877 ps
CPU time 0.61 seconds
Started Jun 27 06:48:06 PM PDT 24
Finished Jun 27 06:48:11 PM PDT 24
Peak memory 196028 kb
Host smart-220ae825-d0f1-43cf-81d4-87262a0d8dc1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855136529 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_alert_test.1855136529
Directory /workspace/45.hmac_alert_test/latest

Test location /workspace/coverage/default/45.hmac_back_pressure.219360374
Short name T267
Test name
Test status
Simulation time 5324169111 ps
CPU time 17.89 seconds
Started Jun 27 06:48:05 PM PDT 24
Finished Jun 27 06:48:28 PM PDT 24
Peak memory 199932 kb
Host smart-71e2aeb4-dfdb-4a82-a344-2931eb41a11c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=219360374 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_back_pressure.219360374
Directory /workspace/45.hmac_back_pressure/latest

Test location /workspace/coverage/default/45.hmac_burst_wr.1752466217
Short name T654
Test name
Test status
Simulation time 1560908575 ps
CPU time 28.86 seconds
Started Jun 27 06:48:05 PM PDT 24
Finished Jun 27 06:48:39 PM PDT 24
Peak memory 200004 kb
Host smart-31ba7de5-115e-4b4c-bb40-dfe86ba36801
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1752466217 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_burst_wr.1752466217
Directory /workspace/45.hmac_burst_wr/latest

Test location /workspace/coverage/default/45.hmac_datapath_stress.634130672
Short name T185
Test name
Test status
Simulation time 1493269913 ps
CPU time 96.91 seconds
Started Jun 27 06:48:04 PM PDT 24
Finished Jun 27 06:49:46 PM PDT 24
Peak memory 448740 kb
Host smart-3d9c7129-9171-45a4-bcdc-5a1e7b8f90cb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=634130672 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_datapath_stress.634130672
Directory /workspace/45.hmac_datapath_stress/latest

Test location /workspace/coverage/default/45.hmac_error.3246650434
Short name T126
Test name
Test status
Simulation time 7581560264 ps
CPU time 126.02 seconds
Started Jun 27 06:48:05 PM PDT 24
Finished Jun 27 06:50:16 PM PDT 24
Peak memory 200040 kb
Host smart-9df4c1ca-ae92-4abc-8b3b-3b139d594115
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246650434 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_error.3246650434
Directory /workspace/45.hmac_error/latest

Test location /workspace/coverage/default/45.hmac_long_msg.2998827954
Short name T304
Test name
Test status
Simulation time 19844016230 ps
CPU time 69.08 seconds
Started Jun 27 06:48:01 PM PDT 24
Finished Jun 27 06:49:13 PM PDT 24
Peak memory 199960 kb
Host smart-f4474198-e1e2-407a-8589-16220cc845a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998827954 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_long_msg.2998827954
Directory /workspace/45.hmac_long_msg/latest

Test location /workspace/coverage/default/45.hmac_smoke.3680348433
Short name T611
Test name
Test status
Simulation time 59481700 ps
CPU time 2.82 seconds
Started Jun 27 06:48:03 PM PDT 24
Finished Jun 27 06:48:11 PM PDT 24
Peak memory 199976 kb
Host smart-939277b2-78a1-4f64-b69e-a10349648257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680348433 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_smoke.3680348433
Directory /workspace/45.hmac_smoke/latest

Test location /workspace/coverage/default/45.hmac_stress_all.3833363409
Short name T247
Test name
Test status
Simulation time 2705605374 ps
CPU time 68.87 seconds
Started Jun 27 06:48:07 PM PDT 24
Finished Jun 27 06:49:20 PM PDT 24
Peak memory 200040 kb
Host smart-3fbcaddb-38da-4bd6-b03a-86d6a3f251ed
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833363409 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.hmac_stress_all.3833363409
Directory /workspace/45.hmac_stress_all/latest

Test location /workspace/coverage/default/45.hmac_test_hmac_vectors.600667025
Short name T385
Test name
Test status
Simulation time 323460556 ps
CPU time 1.42 seconds
Started Jun 27 06:48:04 PM PDT 24
Finished Jun 27 06:48:10 PM PDT 24
Peak memory 199924 kb
Host smart-39422883-63c9-474a-a6b0-72ee101fc51e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600667025 -assert nopostpr
oc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 45.hmac_test_hmac_vectors.600667025
Directory /workspace/45.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/45.hmac_test_sha256_vectors.3972066142
Short name T491
Test name
Test status
Simulation time 49907630222 ps
CPU time 429.99 seconds
Started Jun 27 06:48:05 PM PDT 24
Finished Jun 27 06:55:20 PM PDT 24
Peak memory 199928 kb
Host smart-0c7510de-05c2-41fa-8cc6-481b9e5a646e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3972066142 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_test_sha256_vectors.3972066142
Directory /workspace/45.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/45.hmac_test_sha384_vectors.2728850578
Short name T660
Test name
Test status
Simulation time 627694032631 ps
CPU time 1779.23 seconds
Started Jun 27 06:48:06 PM PDT 24
Finished Jun 27 07:17:50 PM PDT 24
Peak memory 215604 kb
Host smart-2d05a35a-32a2-4ea5-9289-35055dcb57a9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2728850578 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_test_sha384_vectors.2728850578
Directory /workspace/45.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/45.hmac_test_sha512_vectors.1446970959
Short name T408
Test name
Test status
Simulation time 111855282495 ps
CPU time 1878.92 seconds
Started Jun 27 06:48:05 PM PDT 24
Finished Jun 27 07:19:29 PM PDT 24
Peak memory 215416 kb
Host smart-0bce6faf-5b68-4815-942b-2148467bfb86
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1446970959 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_test_sha512_vectors.1446970959
Directory /workspace/45.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/45.hmac_wipe_secret.4005777726
Short name T337
Test name
Test status
Simulation time 4534066799 ps
CPU time 17.42 seconds
Started Jun 27 06:48:04 PM PDT 24
Finished Jun 27 06:48:26 PM PDT 24
Peak memory 200028 kb
Host smart-5275d606-b888-49c9-8c05-31d89b279a7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005777726 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_wipe_secret.4005777726
Directory /workspace/45.hmac_wipe_secret/latest

Test location /workspace/coverage/default/46.hmac_alert_test.1683255592
Short name T457
Test name
Test status
Simulation time 15081955 ps
CPU time 0.63 seconds
Started Jun 27 06:48:01 PM PDT 24
Finished Jun 27 06:48:06 PM PDT 24
Peak memory 196728 kb
Host smart-eb017692-9214-46a6-9297-71b099de2eac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683255592 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_alert_test.1683255592
Directory /workspace/46.hmac_alert_test/latest

Test location /workspace/coverage/default/46.hmac_back_pressure.2232667360
Short name T311
Test name
Test status
Simulation time 989464726 ps
CPU time 47.17 seconds
Started Jun 27 06:48:07 PM PDT 24
Finished Jun 27 06:48:58 PM PDT 24
Peak memory 199976 kb
Host smart-1c4ec355-b4a4-4d46-a847-c7e35cc74322
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2232667360 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_back_pressure.2232667360
Directory /workspace/46.hmac_back_pressure/latest

Test location /workspace/coverage/default/46.hmac_burst_wr.770991794
Short name T89
Test name
Test status
Simulation time 13192303866 ps
CPU time 49.11 seconds
Started Jun 27 06:48:05 PM PDT 24
Finished Jun 27 06:48:59 PM PDT 24
Peak memory 200076 kb
Host smart-dcd032d3-6d81-4be4-a62e-692de9e011fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770991794 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_burst_wr.770991794
Directory /workspace/46.hmac_burst_wr/latest

Test location /workspace/coverage/default/46.hmac_datapath_stress.813965110
Short name T132
Test name
Test status
Simulation time 7139960343 ps
CPU time 877.38 seconds
Started Jun 27 06:48:07 PM PDT 24
Finished Jun 27 07:02:48 PM PDT 24
Peak memory 729456 kb
Host smart-4557f535-a442-4588-bfb7-bab412c4af70
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=813965110 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_datapath_stress.813965110
Directory /workspace/46.hmac_datapath_stress/latest

Test location /workspace/coverage/default/46.hmac_error.3803495157
Short name T674
Test name
Test status
Simulation time 7633054059 ps
CPU time 113.02 seconds
Started Jun 27 06:48:03 PM PDT 24
Finished Jun 27 06:50:01 PM PDT 24
Peak memory 200000 kb
Host smart-9ad9c9d9-51ea-49ae-a431-fe26a5f6dcde
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803495157 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_error.3803495157
Directory /workspace/46.hmac_error/latest

Test location /workspace/coverage/default/46.hmac_long_msg.652336652
Short name T595
Test name
Test status
Simulation time 3962443025 ps
CPU time 107.19 seconds
Started Jun 27 06:48:03 PM PDT 24
Finished Jun 27 06:49:55 PM PDT 24
Peak memory 200064 kb
Host smart-355bfcb5-308a-4e3d-b4ca-a2ab1c690238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652336652 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_long_msg.652336652
Directory /workspace/46.hmac_long_msg/latest

Test location /workspace/coverage/default/46.hmac_smoke.1604328539
Short name T664
Test name
Test status
Simulation time 74938005 ps
CPU time 0.94 seconds
Started Jun 27 06:48:07 PM PDT 24
Finished Jun 27 06:48:12 PM PDT 24
Peak memory 198452 kb
Host smart-2d05ae7c-ae2c-4972-a669-b88367889353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604328539 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_smoke.1604328539
Directory /workspace/46.hmac_smoke/latest

Test location /workspace/coverage/default/46.hmac_stress_all.1471693664
Short name T352
Test name
Test status
Simulation time 23132503 ps
CPU time 0.7 seconds
Started Jun 27 06:48:02 PM PDT 24
Finished Jun 27 06:48:07 PM PDT 24
Peak memory 195680 kb
Host smart-2111b577-4923-491f-a358-92923447b825
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471693664 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.hmac_stress_all.1471693664
Directory /workspace/46.hmac_stress_all/latest

Test location /workspace/coverage/default/46.hmac_test_hmac_vectors.2435460943
Short name T616
Test name
Test status
Simulation time 461942838 ps
CPU time 1.13 seconds
Started Jun 27 06:48:00 PM PDT 24
Finished Jun 27 06:48:04 PM PDT 24
Peak memory 199788 kb
Host smart-723cdf51-4b6d-4e88-afb7-f4a4f7a16c18
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435460943 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 46.hmac_test_hmac_vectors.2435460943
Directory /workspace/46.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/46.hmac_test_sha256_vectors.2836069367
Short name T201
Test name
Test status
Simulation time 173537590169 ps
CPU time 554.1 seconds
Started Jun 27 06:47:58 PM PDT 24
Finished Jun 27 06:57:13 PM PDT 24
Peak memory 200008 kb
Host smart-bf443146-1389-4349-b753-5eb806990065
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2836069367 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_test_sha256_vectors.2836069367
Directory /workspace/46.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/46.hmac_test_sha384_vectors.1516103717
Short name T290
Test name
Test status
Simulation time 64311662261 ps
CPU time 1777.41 seconds
Started Jun 27 06:48:01 PM PDT 24
Finished Jun 27 07:17:42 PM PDT 24
Peak memory 215532 kb
Host smart-d6b782b6-ca6f-4131-af31-6d478ee0a8f7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1516103717 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_test_sha384_vectors.1516103717
Directory /workspace/46.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/46.hmac_test_sha512_vectors.2721698645
Short name T419
Test name
Test status
Simulation time 121525532719 ps
CPU time 1781.96 seconds
Started Jun 27 06:47:59 PM PDT 24
Finished Jun 27 07:17:42 PM PDT 24
Peak memory 216404 kb
Host smart-8a18d8a7-28b7-4d6a-ac12-a0e229fd4c04
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2721698645 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_test_sha512_vectors.2721698645
Directory /workspace/46.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/46.hmac_wipe_secret.845822206
Short name T125
Test name
Test status
Simulation time 14877351736 ps
CPU time 76.7 seconds
Started Jun 27 06:48:02 PM PDT 24
Finished Jun 27 06:49:22 PM PDT 24
Peak memory 199984 kb
Host smart-7e6c9a38-1abb-4dc9-9ff2-34216a8da186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845822206 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_wipe_secret.845822206
Directory /workspace/46.hmac_wipe_secret/latest

Test location /workspace/coverage/default/47.hmac_alert_test.2124669211
Short name T217
Test name
Test status
Simulation time 13759382 ps
CPU time 0.59 seconds
Started Jun 27 06:48:20 PM PDT 24
Finished Jun 27 06:48:25 PM PDT 24
Peak memory 195992 kb
Host smart-3e2d3797-25aa-48ad-9128-0560d7887393
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124669211 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_alert_test.2124669211
Directory /workspace/47.hmac_alert_test/latest

Test location /workspace/coverage/default/47.hmac_back_pressure.2199266486
Short name T395
Test name
Test status
Simulation time 949617739 ps
CPU time 11.08 seconds
Started Jun 27 06:48:02 PM PDT 24
Finished Jun 27 06:48:18 PM PDT 24
Peak memory 199900 kb
Host smart-2f2137ce-41ba-4865-84a0-82ab66ca6524
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2199266486 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_back_pressure.2199266486
Directory /workspace/47.hmac_back_pressure/latest

Test location /workspace/coverage/default/47.hmac_burst_wr.2325859839
Short name T531
Test name
Test status
Simulation time 256541385 ps
CPU time 4.34 seconds
Started Jun 27 06:48:03 PM PDT 24
Finished Jun 27 06:48:13 PM PDT 24
Peak memory 199912 kb
Host smart-82ea9670-4cee-4608-a4de-9e273690dec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325859839 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_burst_wr.2325859839
Directory /workspace/47.hmac_burst_wr/latest

Test location /workspace/coverage/default/47.hmac_datapath_stress.3021713674
Short name T561
Test name
Test status
Simulation time 21025900152 ps
CPU time 1206.5 seconds
Started Jun 27 06:48:02 PM PDT 24
Finished Jun 27 07:08:13 PM PDT 24
Peak memory 703532 kb
Host smart-2801ce66-cac0-4f3a-b8a2-4b0c71328525
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3021713674 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_datapath_stress.3021713674
Directory /workspace/47.hmac_datapath_stress/latest

Test location /workspace/coverage/default/47.hmac_error.3700552282
Short name T394
Test name
Test status
Simulation time 1179460959 ps
CPU time 69.29 seconds
Started Jun 27 06:48:03 PM PDT 24
Finished Jun 27 06:49:17 PM PDT 24
Peak memory 199976 kb
Host smart-b7f1be2e-2f79-4ecf-8ad3-4fea8ad61c0e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700552282 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_error.3700552282
Directory /workspace/47.hmac_error/latest

Test location /workspace/coverage/default/47.hmac_long_msg.3122003819
Short name T246
Test name
Test status
Simulation time 23458454515 ps
CPU time 62.53 seconds
Started Jun 27 06:47:59 PM PDT 24
Finished Jun 27 06:49:03 PM PDT 24
Peak memory 200064 kb
Host smart-253dc09c-be87-4188-a88c-ff6f53170c38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122003819 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_long_msg.3122003819
Directory /workspace/47.hmac_long_msg/latest

Test location /workspace/coverage/default/47.hmac_smoke.3405591080
Short name T423
Test name
Test status
Simulation time 667414506 ps
CPU time 8.75 seconds
Started Jun 27 06:48:00 PM PDT 24
Finished Jun 27 06:48:13 PM PDT 24
Peak memory 199924 kb
Host smart-c1f15519-1d4f-41d5-8569-0f1a942ff054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405591080 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_smoke.3405591080
Directory /workspace/47.hmac_smoke/latest

Test location /workspace/coverage/default/47.hmac_stress_all.631848380
Short name T328
Test name
Test status
Simulation time 8046706828 ps
CPU time 542.72 seconds
Started Jun 27 06:48:21 PM PDT 24
Finished Jun 27 06:57:30 PM PDT 24
Peak memory 384916 kb
Host smart-6f60f9a0-4f50-40a2-a8bf-fb590b0eaffb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631848380 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 47.hmac_stress_all.631848380
Directory /workspace/47.hmac_stress_all/latest

Test location /workspace/coverage/default/47.hmac_test_hmac_vectors.1103402970
Short name T259
Test name
Test status
Simulation time 83524557 ps
CPU time 1.37 seconds
Started Jun 27 06:48:21 PM PDT 24
Finished Jun 27 06:48:28 PM PDT 24
Peak memory 199912 kb
Host smart-c305af02-336e-4e93-8a1e-3016fc58ba1d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103402970 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 47.hmac_test_hmac_vectors.1103402970
Directory /workspace/47.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/47.hmac_test_sha256_vectors.491054052
Short name T250
Test name
Test status
Simulation time 48905519409 ps
CPU time 449.56 seconds
Started Jun 27 06:48:22 PM PDT 24
Finished Jun 27 06:55:58 PM PDT 24
Peak memory 200048 kb
Host smart-1af99cba-9d9b-4caa-a9f6-568838bfcdb1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=491054052 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_test_sha256_vectors.491054052
Directory /workspace/47.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/47.hmac_test_sha384_vectors.400084138
Short name T293
Test name
Test status
Simulation time 68588691674 ps
CPU time 1820.75 seconds
Started Jun 27 06:48:21 PM PDT 24
Finished Jun 27 07:18:48 PM PDT 24
Peak memory 215476 kb
Host smart-7e4bb370-fcb2-4cfd-b6e1-f2b4984be4be
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=400084138 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_test_sha384_vectors.400084138
Directory /workspace/47.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/47.hmac_test_sha512_vectors.1548410699
Short name T173
Test name
Test status
Simulation time 184866213812 ps
CPU time 1861.65 seconds
Started Jun 27 06:48:20 PM PDT 24
Finished Jun 27 07:19:27 PM PDT 24
Peak memory 216360 kb
Host smart-67a5c94e-5612-45db-981d-dbeb00caf2a2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1548410699 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_test_sha512_vectors.1548410699
Directory /workspace/47.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/47.hmac_wipe_secret.937561527
Short name T445
Test name
Test status
Simulation time 22377122942 ps
CPU time 79.94 seconds
Started Jun 27 06:48:20 PM PDT 24
Finished Jun 27 06:49:46 PM PDT 24
Peak memory 200040 kb
Host smart-1d472c9d-e1f4-4bc1-9dfd-e15994ca3504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937561527 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_wipe_secret.937561527
Directory /workspace/47.hmac_wipe_secret/latest

Test location /workspace/coverage/default/48.hmac_alert_test.397663128
Short name T382
Test name
Test status
Simulation time 20499150 ps
CPU time 0.61 seconds
Started Jun 27 06:48:19 PM PDT 24
Finished Jun 27 06:48:22 PM PDT 24
Peak memory 195904 kb
Host smart-baff7f12-8988-460d-b1b8-0fbc1111fe03
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397663128 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_alert_test.397663128
Directory /workspace/48.hmac_alert_test/latest

Test location /workspace/coverage/default/48.hmac_back_pressure.2613542571
Short name T629
Test name
Test status
Simulation time 1072375453 ps
CPU time 26.9 seconds
Started Jun 27 06:48:20 PM PDT 24
Finished Jun 27 06:48:51 PM PDT 24
Peak memory 199940 kb
Host smart-dcb11710-d007-4d00-8d26-0bc76ea2d41b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2613542571 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_back_pressure.2613542571
Directory /workspace/48.hmac_back_pressure/latest

Test location /workspace/coverage/default/48.hmac_burst_wr.2840218403
Short name T441
Test name
Test status
Simulation time 5575518777 ps
CPU time 77.45 seconds
Started Jun 27 06:48:19 PM PDT 24
Finished Jun 27 06:49:39 PM PDT 24
Peak memory 199984 kb
Host smart-2ebdf7ce-8cc0-486f-8d63-d28a521b2b29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840218403 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_burst_wr.2840218403
Directory /workspace/48.hmac_burst_wr/latest

Test location /workspace/coverage/default/48.hmac_error.1396640886
Short name T433
Test name
Test status
Simulation time 25118135103 ps
CPU time 163.98 seconds
Started Jun 27 06:48:18 PM PDT 24
Finished Jun 27 06:51:04 PM PDT 24
Peak memory 199992 kb
Host smart-95548e08-dc4f-472b-bcca-bdf1c566145e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396640886 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_error.1396640886
Directory /workspace/48.hmac_error/latest

Test location /workspace/coverage/default/48.hmac_long_msg.2265791410
Short name T48
Test name
Test status
Simulation time 1761239560 ps
CPU time 36.27 seconds
Started Jun 27 06:48:21 PM PDT 24
Finished Jun 27 06:49:04 PM PDT 24
Peak memory 200036 kb
Host smart-e18c43ab-055c-46c7-b041-202c3a0e150a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265791410 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_long_msg.2265791410
Directory /workspace/48.hmac_long_msg/latest

Test location /workspace/coverage/default/48.hmac_smoke.1802708196
Short name T378
Test name
Test status
Simulation time 636238097 ps
CPU time 4.59 seconds
Started Jun 27 06:48:19 PM PDT 24
Finished Jun 27 06:48:25 PM PDT 24
Peak memory 200008 kb
Host smart-5ce9174f-1d0a-4468-8675-fe28826c79a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802708196 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_smoke.1802708196
Directory /workspace/48.hmac_smoke/latest

Test location /workspace/coverage/default/48.hmac_stress_all.2252876071
Short name T26
Test name
Test status
Simulation time 6286157995 ps
CPU time 236.87 seconds
Started Jun 27 06:48:19 PM PDT 24
Finished Jun 27 06:52:19 PM PDT 24
Peak memory 199980 kb
Host smart-5ee5bb3a-42af-4c77-b6d6-ab07d29a2ba2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252876071 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.hmac_stress_all.2252876071
Directory /workspace/48.hmac_stress_all/latest

Test location /workspace/coverage/default/48.hmac_test_hmac_vectors.694433596
Short name T85
Test name
Test status
Simulation time 93597598 ps
CPU time 1.39 seconds
Started Jun 27 06:48:19 PM PDT 24
Finished Jun 27 06:48:23 PM PDT 24
Peak memory 199964 kb
Host smart-0ced2554-7b4d-484b-86d0-086c6c70e550
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694433596 -assert nopostpr
oc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 48.hmac_test_hmac_vectors.694433596
Directory /workspace/48.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/48.hmac_test_sha256_vectors.3972934155
Short name T174
Test name
Test status
Simulation time 7397160640 ps
CPU time 415.75 seconds
Started Jun 27 06:48:20 PM PDT 24
Finished Jun 27 06:55:20 PM PDT 24
Peak memory 200004 kb
Host smart-397bf6f2-8025-45c2-b139-0e02d78bf19e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3972934155 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_test_sha256_vectors.3972934155
Directory /workspace/48.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/48.hmac_test_sha384_vectors.339041692
Short name T576
Test name
Test status
Simulation time 123625724562 ps
CPU time 1623.94 seconds
Started Jun 27 06:48:17 PM PDT 24
Finished Jun 27 07:15:23 PM PDT 24
Peak memory 216364 kb
Host smart-3836794e-35e8-4729-9cdb-97b3af1224ce
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=339041692 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_test_sha384_vectors.339041692
Directory /workspace/48.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/48.hmac_test_sha512_vectors.3480305292
Short name T525
Test name
Test status
Simulation time 165666559913 ps
CPU time 1738.75 seconds
Started Jun 27 06:48:20 PM PDT 24
Finished Jun 27 07:17:25 PM PDT 24
Peak memory 215488 kb
Host smart-da6c0507-7dac-4dc6-8760-d3a0b2de7966
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3480305292 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_test_sha512_vectors.3480305292
Directory /workspace/48.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/48.hmac_wipe_secret.718104301
Short name T388
Test name
Test status
Simulation time 1012386843 ps
CPU time 13.76 seconds
Started Jun 27 06:48:19 PM PDT 24
Finished Jun 27 06:48:36 PM PDT 24
Peak memory 199964 kb
Host smart-2156b366-c788-4d19-b91d-4822fec9fccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718104301 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_wipe_secret.718104301
Directory /workspace/48.hmac_wipe_secret/latest

Test location /workspace/coverage/default/49.hmac_alert_test.1176065101
Short name T471
Test name
Test status
Simulation time 14029624 ps
CPU time 0.62 seconds
Started Jun 27 06:48:21 PM PDT 24
Finished Jun 27 06:48:28 PM PDT 24
Peak memory 196732 kb
Host smart-462d5688-6744-4b60-9bd0-41de9a9da2eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176065101 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_alert_test.1176065101
Directory /workspace/49.hmac_alert_test/latest

Test location /workspace/coverage/default/49.hmac_back_pressure.2609629462
Short name T569
Test name
Test status
Simulation time 4038389438 ps
CPU time 29.59 seconds
Started Jun 27 06:48:19 PM PDT 24
Finished Jun 27 06:48:53 PM PDT 24
Peak memory 199988 kb
Host smart-353abf36-b69b-4e56-8727-2142f5bfbecf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2609629462 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_back_pressure.2609629462
Directory /workspace/49.hmac_back_pressure/latest

Test location /workspace/coverage/default/49.hmac_burst_wr.2624189597
Short name T673
Test name
Test status
Simulation time 3969308639 ps
CPU time 57.94 seconds
Started Jun 27 06:48:18 PM PDT 24
Finished Jun 27 06:49:17 PM PDT 24
Peak memory 200040 kb
Host smart-47ab3519-d4c2-430d-92a5-8eac20309d98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624189597 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_burst_wr.2624189597
Directory /workspace/49.hmac_burst_wr/latest

Test location /workspace/coverage/default/49.hmac_datapath_stress.3826761203
Short name T194
Test name
Test status
Simulation time 75356548573 ps
CPU time 1481.86 seconds
Started Jun 27 06:48:21 PM PDT 24
Finished Jun 27 07:13:10 PM PDT 24
Peak memory 792596 kb
Host smart-3437a0e4-52d6-4579-b658-8b4c1bcca860
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3826761203 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_datapath_stress.3826761203
Directory /workspace/49.hmac_datapath_stress/latest

Test location /workspace/coverage/default/49.hmac_error.3308377894
Short name T691
Test name
Test status
Simulation time 56528478984 ps
CPU time 57.48 seconds
Started Jun 27 06:48:21 PM PDT 24
Finished Jun 27 06:49:24 PM PDT 24
Peak memory 199996 kb
Host smart-fad79207-1b41-419b-a8a7-e6d903c459ee
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308377894 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_error.3308377894
Directory /workspace/49.hmac_error/latest

Test location /workspace/coverage/default/49.hmac_long_msg.3440480352
Short name T176
Test name
Test status
Simulation time 7877893455 ps
CPU time 99.33 seconds
Started Jun 27 06:48:21 PM PDT 24
Finished Jun 27 06:50:07 PM PDT 24
Peak memory 200032 kb
Host smart-96f1d116-3910-472e-b305-567d44b2eae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3440480352 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_long_msg.3440480352
Directory /workspace/49.hmac_long_msg/latest

Test location /workspace/coverage/default/49.hmac_smoke.3676867087
Short name T565
Test name
Test status
Simulation time 402164385 ps
CPU time 7.62 seconds
Started Jun 27 06:48:19 PM PDT 24
Finished Jun 27 06:48:30 PM PDT 24
Peak memory 200144 kb
Host smart-51e5db8d-542b-4f52-b571-fa194bb0dcc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676867087 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_smoke.3676867087
Directory /workspace/49.hmac_smoke/latest

Test location /workspace/coverage/default/49.hmac_test_hmac_vectors.53293300
Short name T177
Test name
Test status
Simulation time 86831278 ps
CPU time 1.12 seconds
Started Jun 27 06:48:20 PM PDT 24
Finished Jun 27 06:48:25 PM PDT 24
Peak memory 199524 kb
Host smart-3c8819f2-84ec-45e4-a7ce-e6775566a111
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53293300 -assert nopostpro
c +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 49.hmac_test_hmac_vectors.53293300
Directory /workspace/49.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/49.hmac_test_sha256_vectors.1939109525
Short name T630
Test name
Test status
Simulation time 33195741538 ps
CPU time 504.17 seconds
Started Jun 27 06:48:20 PM PDT 24
Finished Jun 27 06:56:50 PM PDT 24
Peak memory 200012 kb
Host smart-173771e8-0eb0-4498-961d-43058ed15351
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1939109525 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_test_sha256_vectors.1939109525
Directory /workspace/49.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/49.hmac_test_sha384_vectors.3097062943
Short name T496
Test name
Test status
Simulation time 89012177609 ps
CPU time 1822.84 seconds
Started Jun 27 06:48:22 PM PDT 24
Finished Jun 27 07:18:52 PM PDT 24
Peak memory 215660 kb
Host smart-defa9372-7f1d-440c-a0e9-e461d770c8a1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3097062943 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_test_sha384_vectors.3097062943
Directory /workspace/49.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/49.hmac_test_sha512_vectors.2340841288
Short name T221
Test name
Test status
Simulation time 100396069983 ps
CPU time 1784.6 seconds
Started Jun 27 06:48:20 PM PDT 24
Finished Jun 27 07:18:11 PM PDT 24
Peak memory 215548 kb
Host smart-fc2254e8-f6ea-4438-a97c-a5e98a1cc87e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2340841288 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_test_sha512_vectors.2340841288
Directory /workspace/49.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/49.hmac_wipe_secret.2009377708
Short name T93
Test name
Test status
Simulation time 27626253135 ps
CPU time 104.37 seconds
Started Jun 27 06:48:19 PM PDT 24
Finished Jun 27 06:50:05 PM PDT 24
Peak memory 199988 kb
Host smart-dd9ceb25-9d13-4024-96a0-178160815e59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009377708 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_wipe_secret.2009377708
Directory /workspace/49.hmac_wipe_secret/latest

Test location /workspace/coverage/default/5.hmac_alert_test.4211408813
Short name T366
Test name
Test status
Simulation time 46996084 ps
CPU time 0.58 seconds
Started Jun 27 06:46:26 PM PDT 24
Finished Jun 27 06:46:39 PM PDT 24
Peak memory 195952 kb
Host smart-6ed42282-c072-48e1-abdf-ddc764702194
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211408813 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_alert_test.4211408813
Directory /workspace/5.hmac_alert_test/latest

Test location /workspace/coverage/default/5.hmac_back_pressure.2677211017
Short name T444
Test name
Test status
Simulation time 80612127 ps
CPU time 4.19 seconds
Started Jun 27 06:46:33 PM PDT 24
Finished Jun 27 06:46:50 PM PDT 24
Peak memory 199952 kb
Host smart-bcd2574b-b682-4ac1-a933-1fe8d8ecd31d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2677211017 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_back_pressure.2677211017
Directory /workspace/5.hmac_back_pressure/latest

Test location /workspace/coverage/default/5.hmac_burst_wr.3039316754
Short name T258
Test name
Test status
Simulation time 2064489681 ps
CPU time 23.36 seconds
Started Jun 27 06:46:24 PM PDT 24
Finished Jun 27 06:46:56 PM PDT 24
Peak memory 199984 kb
Host smart-5bd799f7-d348-4845-ad25-ccb0ef17b172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039316754 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_burst_wr.3039316754
Directory /workspace/5.hmac_burst_wr/latest

Test location /workspace/coverage/default/5.hmac_datapath_stress.1102923262
Short name T397
Test name
Test status
Simulation time 3507600453 ps
CPU time 1023.45 seconds
Started Jun 27 06:46:33 PM PDT 24
Finished Jun 27 07:03:50 PM PDT 24
Peak memory 716856 kb
Host smart-eab49bc4-049b-4f5d-9946-dc25fe1e8cd7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1102923262 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_datapath_stress.1102923262
Directory /workspace/5.hmac_datapath_stress/latest

Test location /workspace/coverage/default/5.hmac_error.3889864507
Short name T638
Test name
Test status
Simulation time 5385485340 ps
CPU time 19.51 seconds
Started Jun 27 06:46:33 PM PDT 24
Finished Jun 27 06:47:06 PM PDT 24
Peak memory 199808 kb
Host smart-dea2b35c-869f-4bfb-875c-0cf7fd24f6b6
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889864507 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_error.3889864507
Directory /workspace/5.hmac_error/latest

Test location /workspace/coverage/default/5.hmac_long_msg.2683823500
Short name T607
Test name
Test status
Simulation time 18850658317 ps
CPU time 131.62 seconds
Started Jun 27 06:46:33 PM PDT 24
Finished Jun 27 06:48:58 PM PDT 24
Peak memory 200040 kb
Host smart-5c2162ca-a37c-4e28-b9d8-662f63101439
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2683823500 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_long_msg.2683823500
Directory /workspace/5.hmac_long_msg/latest

Test location /workspace/coverage/default/5.hmac_smoke.755144215
Short name T383
Test name
Test status
Simulation time 643937085 ps
CPU time 7.22 seconds
Started Jun 27 06:46:33 PM PDT 24
Finished Jun 27 06:46:54 PM PDT 24
Peak memory 199944 kb
Host smart-5b22b330-d42b-41a0-91f6-a01499e0a7d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755144215 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_smoke.755144215
Directory /workspace/5.hmac_smoke/latest

Test location /workspace/coverage/default/5.hmac_stress_all.2509057535
Short name T73
Test name
Test status
Simulation time 272761833812 ps
CPU time 1644.4 seconds
Started Jun 27 06:46:25 PM PDT 24
Finished Jun 27 07:14:00 PM PDT 24
Peak memory 633600 kb
Host smart-3d19291e-27a1-4631-ae48-eba93f396b6a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509057535 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all.2509057535
Directory /workspace/5.hmac_stress_all/latest

Test location /workspace/coverage/default/5.hmac_test_hmac_vectors.2498157360
Short name T585
Test name
Test status
Simulation time 112056725 ps
CPU time 1.11 seconds
Started Jun 27 06:46:28 PM PDT 24
Finished Jun 27 06:46:42 PM PDT 24
Peak memory 199912 kb
Host smart-cf620c91-5ee9-4375-9d49-44fa1971fffa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498157360 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 5.hmac_test_hmac_vectors.2498157360
Directory /workspace/5.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/5.hmac_test_sha256_vectors.1782625678
Short name T204
Test name
Test status
Simulation time 16241339296 ps
CPU time 440.47 seconds
Started Jun 27 06:46:21 PM PDT 24
Finished Jun 27 06:53:47 PM PDT 24
Peak memory 199948 kb
Host smart-5816ba20-ccec-4273-8f9c-b06d150f8861
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1782625678 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_test_sha256_vectors.1782625678
Directory /workspace/5.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/5.hmac_test_sha384_vectors.2497700657
Short name T391
Test name
Test status
Simulation time 31432012913 ps
CPU time 1765.36 seconds
Started Jun 27 06:46:28 PM PDT 24
Finished Jun 27 07:16:07 PM PDT 24
Peak memory 215676 kb
Host smart-8250d761-115d-4525-89c4-02b3fcde3636
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2497700657 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_test_sha384_vectors.2497700657
Directory /workspace/5.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/5.hmac_test_sha512_vectors.1401932023
Short name T523
Test name
Test status
Simulation time 122979881285 ps
CPU time 1587.13 seconds
Started Jun 27 06:46:28 PM PDT 24
Finished Jun 27 07:13:08 PM PDT 24
Peak memory 215596 kb
Host smart-bf04ac4b-25f7-4568-a42c-24259c877762
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1401932023 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_test_sha512_vectors.1401932023
Directory /workspace/5.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/5.hmac_wipe_secret.1182559677
Short name T230
Test name
Test status
Simulation time 10035966408 ps
CPU time 96.18 seconds
Started Jun 27 06:46:28 PM PDT 24
Finished Jun 27 06:48:17 PM PDT 24
Peak memory 200036 kb
Host smart-425a9c11-4528-4ff3-9c6f-ef94bba83fa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182559677 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_wipe_secret.1182559677
Directory /workspace/5.hmac_wipe_secret/latest

Test location /workspace/coverage/default/6.hmac_alert_test.4235652720
Short name T342
Test name
Test status
Simulation time 12117911 ps
CPU time 0.59 seconds
Started Jun 27 06:46:19 PM PDT 24
Finished Jun 27 06:46:25 PM PDT 24
Peak memory 196024 kb
Host smart-656336bb-c82a-49b7-bffd-ed42a8017380
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235652720 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_alert_test.4235652720
Directory /workspace/6.hmac_alert_test/latest

Test location /workspace/coverage/default/6.hmac_back_pressure.754924415
Short name T239
Test name
Test status
Simulation time 2804485487 ps
CPU time 21 seconds
Started Jun 27 06:46:25 PM PDT 24
Finished Jun 27 06:46:57 PM PDT 24
Peak memory 199976 kb
Host smart-3dfbac6d-6bd2-48b4-8cf6-91845168efe1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=754924415 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_back_pressure.754924415
Directory /workspace/6.hmac_back_pressure/latest

Test location /workspace/coverage/default/6.hmac_burst_wr.1257624686
Short name T635
Test name
Test status
Simulation time 22415650 ps
CPU time 1.24 seconds
Started Jun 27 06:46:28 PM PDT 24
Finished Jun 27 06:46:42 PM PDT 24
Peak memory 199856 kb
Host smart-e0a07aa8-e4f6-46f4-a273-da6bf7a0171d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257624686 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_burst_wr.1257624686
Directory /workspace/6.hmac_burst_wr/latest

Test location /workspace/coverage/default/6.hmac_datapath_stress.417143319
Short name T489
Test name
Test status
Simulation time 2828972158 ps
CPU time 219.13 seconds
Started Jun 27 06:46:28 PM PDT 24
Finished Jun 27 06:50:20 PM PDT 24
Peak memory 672896 kb
Host smart-357bddcf-3240-42a9-b864-e049ccf9eb27
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=417143319 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_datapath_stress.417143319
Directory /workspace/6.hmac_datapath_stress/latest

Test location /workspace/coverage/default/6.hmac_error.3532430214
Short name T609
Test name
Test status
Simulation time 19704541420 ps
CPU time 174.59 seconds
Started Jun 27 06:46:25 PM PDT 24
Finished Jun 27 06:49:30 PM PDT 24
Peak memory 200000 kb
Host smart-c837b6e4-1e12-4e8e-a0d6-2638fa4c59ab
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532430214 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_error.3532430214
Directory /workspace/6.hmac_error/latest

Test location /workspace/coverage/default/6.hmac_long_msg.1840163376
Short name T82
Test name
Test status
Simulation time 1585586770 ps
CPU time 87.47 seconds
Started Jun 27 06:46:28 PM PDT 24
Finished Jun 27 06:48:09 PM PDT 24
Peak memory 199844 kb
Host smart-4f7da8e7-97f7-4750-a5bc-cc031d69cb6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840163376 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_long_msg.1840163376
Directory /workspace/6.hmac_long_msg/latest

Test location /workspace/coverage/default/6.hmac_smoke.205894325
Short name T448
Test name
Test status
Simulation time 471558075 ps
CPU time 6.92 seconds
Started Jun 27 06:46:28 PM PDT 24
Finished Jun 27 06:46:48 PM PDT 24
Peak memory 199924 kb
Host smart-0aec6a98-3e5e-4fbd-b9ad-d57525113e90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205894325 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_smoke.205894325
Directory /workspace/6.hmac_smoke/latest

Test location /workspace/coverage/default/6.hmac_stress_all.4187710531
Short name T34
Test name
Test status
Simulation time 214207786356 ps
CPU time 2089.63 seconds
Started Jun 27 06:46:22 PM PDT 24
Finished Jun 27 07:21:19 PM PDT 24
Peak memory 216172 kb
Host smart-170e714d-e60a-40dd-8fde-506f1b030c87
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187710531 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all.4187710531
Directory /workspace/6.hmac_stress_all/latest

Test location /workspace/coverage/default/6.hmac_test_hmac_vectors.2232052378
Short name T171
Test name
Test status
Simulation time 72917251 ps
CPU time 1.35 seconds
Started Jun 27 06:46:20 PM PDT 24
Finished Jun 27 06:46:28 PM PDT 24
Peak memory 199904 kb
Host smart-01df2fd1-be5d-4a3d-856e-ad9fe3359f93
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232052378 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 6.hmac_test_hmac_vectors.2232052378
Directory /workspace/6.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/6.hmac_test_sha256_vectors.425614057
Short name T555
Test name
Test status
Simulation time 42013526277 ps
CPU time 522.19 seconds
Started Jun 27 06:46:26 PM PDT 24
Finished Jun 27 06:55:19 PM PDT 24
Peak memory 200044 kb
Host smart-27232a4e-8d6a-42de-907d-4fc4ef80504d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=425614057 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_test_sha256_vectors.425614057
Directory /workspace/6.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/6.hmac_test_sha384_vectors.1813340598
Short name T625
Test name
Test status
Simulation time 496963316198 ps
CPU time 1806.25 seconds
Started Jun 27 06:46:24 PM PDT 24
Finished Jun 27 07:16:39 PM PDT 24
Peak memory 216248 kb
Host smart-65872f72-4bfc-4611-9095-69f89199ca93
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1813340598 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_test_sha384_vectors.1813340598
Directory /workspace/6.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/6.hmac_test_sha512_vectors.3636582025
Short name T228
Test name
Test status
Simulation time 30272725644 ps
CPU time 1701.39 seconds
Started Jun 27 06:46:21 PM PDT 24
Finished Jun 27 07:14:48 PM PDT 24
Peak memory 215412 kb
Host smart-7ab07047-c4cb-4e30-8e12-aebd6cbe0bef
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3636582025 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_test_sha512_vectors.3636582025
Directory /workspace/6.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/6.hmac_wipe_secret.2949623155
Short name T240
Test name
Test status
Simulation time 665915589 ps
CPU time 12.5 seconds
Started Jun 27 06:46:22 PM PDT 24
Finished Jun 27 06:46:42 PM PDT 24
Peak memory 199980 kb
Host smart-e9e16c37-7059-440b-8c65-0e11d4f93fb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949623155 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_wipe_secret.2949623155
Directory /workspace/6.hmac_wipe_secret/latest

Test location /workspace/coverage/default/7.hmac_alert_test.4269187972
Short name T251
Test name
Test status
Simulation time 12970678 ps
CPU time 0.6 seconds
Started Jun 27 06:46:25 PM PDT 24
Finished Jun 27 06:46:35 PM PDT 24
Peak memory 195616 kb
Host smart-b5b4aa3c-c8c9-4c1f-83b1-a69c307854b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269187972 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_alert_test.4269187972
Directory /workspace/7.hmac_alert_test/latest

Test location /workspace/coverage/default/7.hmac_back_pressure.1692671610
Short name T570
Test name
Test status
Simulation time 234688216 ps
CPU time 12.65 seconds
Started Jun 27 06:46:27 PM PDT 24
Finished Jun 27 06:46:52 PM PDT 24
Peak memory 199956 kb
Host smart-631bcde8-2862-47ae-b51a-f4f676d3fac0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1692671610 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_back_pressure.1692671610
Directory /workspace/7.hmac_back_pressure/latest

Test location /workspace/coverage/default/7.hmac_burst_wr.942704373
Short name T427
Test name
Test status
Simulation time 211585955 ps
CPU time 3.35 seconds
Started Jun 27 06:46:20 PM PDT 24
Finished Jun 27 06:46:30 PM PDT 24
Peak memory 199980 kb
Host smart-53c35135-6d98-494e-a0e1-0746f6e1223b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942704373 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_burst_wr.942704373
Directory /workspace/7.hmac_burst_wr/latest

Test location /workspace/coverage/default/7.hmac_datapath_stress.1458413976
Short name T632
Test name
Test status
Simulation time 937542029 ps
CPU time 170.83 seconds
Started Jun 27 06:46:20 PM PDT 24
Finished Jun 27 06:49:17 PM PDT 24
Peak memory 415116 kb
Host smart-55613f86-559f-4fd2-9b50-0eb96814c1a0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1458413976 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_datapath_stress.1458413976
Directory /workspace/7.hmac_datapath_stress/latest

Test location /workspace/coverage/default/7.hmac_error.256124088
Short name T373
Test name
Test status
Simulation time 1619891819 ps
CPU time 93.38 seconds
Started Jun 27 06:46:21 PM PDT 24
Finished Jun 27 06:48:01 PM PDT 24
Peak memory 199924 kb
Host smart-4db167ac-db06-41df-9347-1a9e7737c017
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256124088 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_error.256124088
Directory /workspace/7.hmac_error/latest

Test location /workspace/coverage/default/7.hmac_long_msg.806628558
Short name T295
Test name
Test status
Simulation time 637985834 ps
CPU time 29.36 seconds
Started Jun 27 06:46:21 PM PDT 24
Finished Jun 27 06:46:57 PM PDT 24
Peak memory 200016 kb
Host smart-904c6311-260f-4a69-b326-d911dba016e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806628558 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_long_msg.806628558
Directory /workspace/7.hmac_long_msg/latest

Test location /workspace/coverage/default/7.hmac_smoke.2406580809
Short name T700
Test name
Test status
Simulation time 261829313 ps
CPU time 11.26 seconds
Started Jun 27 06:46:23 PM PDT 24
Finished Jun 27 06:46:43 PM PDT 24
Peak memory 199968 kb
Host smart-f6a1ae27-3d6f-46ab-a2a5-afa95e0aae51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406580809 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_smoke.2406580809
Directory /workspace/7.hmac_smoke/latest

Test location /workspace/coverage/default/7.hmac_stress_all.371735387
Short name T123
Test name
Test status
Simulation time 476521044291 ps
CPU time 1584.66 seconds
Started Jun 27 06:46:24 PM PDT 24
Finished Jun 27 07:12:58 PM PDT 24
Peak memory 705024 kb
Host smart-75e8b439-bba8-48ce-a5df-af5c86009253
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371735387 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all.371735387
Directory /workspace/7.hmac_stress_all/latest

Test location /workspace/coverage/default/7.hmac_test_hmac_vectors.3381016338
Short name T261
Test name
Test status
Simulation time 44905509 ps
CPU time 1.29 seconds
Started Jun 27 06:46:22 PM PDT 24
Finished Jun 27 06:46:30 PM PDT 24
Peak memory 199964 kb
Host smart-55569fd4-2a28-4373-a810-fe5459d83904
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381016338 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 7.hmac_test_hmac_vectors.3381016338
Directory /workspace/7.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/7.hmac_test_sha256_vectors.1333761760
Short name T403
Test name
Test status
Simulation time 34053022893 ps
CPU time 447.39 seconds
Started Jun 27 06:46:22 PM PDT 24
Finished Jun 27 06:53:57 PM PDT 24
Peak memory 200012 kb
Host smart-9b9dcc3d-a278-4bb0-bed8-0d2a5533a9ad
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1333761760 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_test_sha256_vectors.1333761760
Directory /workspace/7.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/7.hmac_test_sha384_vectors.853693866
Short name T618
Test name
Test status
Simulation time 31620716210 ps
CPU time 1665.21 seconds
Started Jun 27 06:46:25 PM PDT 24
Finished Jun 27 07:14:20 PM PDT 24
Peak memory 215492 kb
Host smart-0bd91997-254d-4457-a9e8-91436a823302
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=853693866 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_test_sha384_vectors.853693866
Directory /workspace/7.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/7.hmac_test_sha512_vectors.3819196622
Short name T284
Test name
Test status
Simulation time 68658263482 ps
CPU time 1847.74 seconds
Started Jun 27 06:46:24 PM PDT 24
Finished Jun 27 07:17:22 PM PDT 24
Peak memory 215452 kb
Host smart-cc976f98-00a3-4af4-9907-323b0af45c3e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3819196622 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_test_sha512_vectors.3819196622
Directory /workspace/7.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/7.hmac_wipe_secret.272756058
Short name T536
Test name
Test status
Simulation time 4352315173 ps
CPU time 44.28 seconds
Started Jun 27 06:46:21 PM PDT 24
Finished Jun 27 06:47:11 PM PDT 24
Peak memory 200000 kb
Host smart-cb036f90-fccc-4788-9646-37c558efe314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272756058 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_wipe_secret.272756058
Directory /workspace/7.hmac_wipe_secret/latest

Test location /workspace/coverage/default/8.hmac_alert_test.1246562499
Short name T628
Test name
Test status
Simulation time 20130346 ps
CPU time 0.59 seconds
Started Jun 27 06:46:27 PM PDT 24
Finished Jun 27 06:46:40 PM PDT 24
Peak memory 195976 kb
Host smart-b1ab0024-37f4-4fac-b4f2-1f7b34242d8a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246562499 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_alert_test.1246562499
Directory /workspace/8.hmac_alert_test/latest

Test location /workspace/coverage/default/8.hmac_back_pressure.381991682
Short name T511
Test name
Test status
Simulation time 598635090 ps
CPU time 7.9 seconds
Started Jun 27 06:46:28 PM PDT 24
Finished Jun 27 06:46:49 PM PDT 24
Peak memory 199972 kb
Host smart-b9ae36d7-9b29-41bf-9edb-48e5a3a4a939
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=381991682 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_back_pressure.381991682
Directory /workspace/8.hmac_back_pressure/latest

Test location /workspace/coverage/default/8.hmac_burst_wr.185211671
Short name T325
Test name
Test status
Simulation time 520334269 ps
CPU time 9.75 seconds
Started Jun 27 06:46:27 PM PDT 24
Finished Jun 27 06:46:50 PM PDT 24
Peak memory 199944 kb
Host smart-3ff2f726-4f10-4a7d-98e2-9b8066f75cc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185211671 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_burst_wr.185211671
Directory /workspace/8.hmac_burst_wr/latest

Test location /workspace/coverage/default/8.hmac_datapath_stress.3469976944
Short name T699
Test name
Test status
Simulation time 2398746502 ps
CPU time 771.17 seconds
Started Jun 27 06:46:19 PM PDT 24
Finished Jun 27 06:59:15 PM PDT 24
Peak memory 692464 kb
Host smart-72efa2b8-3a16-46c2-8524-e071273f4d67
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3469976944 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_datapath_stress.3469976944
Directory /workspace/8.hmac_datapath_stress/latest

Test location /workspace/coverage/default/8.hmac_error.3587692494
Short name T375
Test name
Test status
Simulation time 19074926885 ps
CPU time 40.23 seconds
Started Jun 27 06:46:28 PM PDT 24
Finished Jun 27 06:47:21 PM PDT 24
Peak memory 199988 kb
Host smart-ec85bff7-aa27-449e-98ce-f3948115bdf3
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587692494 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_error.3587692494
Directory /workspace/8.hmac_error/latest

Test location /workspace/coverage/default/8.hmac_long_msg.3692880241
Short name T680
Test name
Test status
Simulation time 3737750719 ps
CPU time 52.32 seconds
Started Jun 27 06:46:24 PM PDT 24
Finished Jun 27 06:47:25 PM PDT 24
Peak memory 200012 kb
Host smart-6d17d377-88d5-4249-bfd5-c6f70b4697a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3692880241 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_long_msg.3692880241
Directory /workspace/8.hmac_long_msg/latest

Test location /workspace/coverage/default/8.hmac_smoke.712433015
Short name T31
Test name
Test status
Simulation time 296332931 ps
CPU time 4.5 seconds
Started Jun 27 06:46:26 PM PDT 24
Finished Jun 27 06:46:43 PM PDT 24
Peak memory 199908 kb
Host smart-af23e707-b6d2-4bb8-919b-a837f0504af8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=712433015 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_smoke.712433015
Directory /workspace/8.hmac_smoke/latest

Test location /workspace/coverage/default/8.hmac_stress_all.2342345842
Short name T368
Test name
Test status
Simulation time 71029134745 ps
CPU time 3726.96 seconds
Started Jun 27 06:46:29 PM PDT 24
Finished Jun 27 07:48:50 PM PDT 24
Peak memory 215700 kb
Host smart-ef9317ee-ce7d-45be-91f1-faccf92c9f42
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342345842 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all.2342345842
Directory /workspace/8.hmac_stress_all/latest

Test location /workspace/coverage/default/8.hmac_test_hmac_vectors.3190627360
Short name T336
Test name
Test status
Simulation time 214133125 ps
CPU time 1.38 seconds
Started Jun 27 06:46:27 PM PDT 24
Finished Jun 27 06:46:40 PM PDT 24
Peak memory 199956 kb
Host smart-c26246b7-ef60-4384-8f15-1a409158866d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190627360 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 8.hmac_test_hmac_vectors.3190627360
Directory /workspace/8.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/8.hmac_test_sha256_vectors.1780747735
Short name T418
Test name
Test status
Simulation time 27142725099 ps
CPU time 499.23 seconds
Started Jun 27 06:46:26 PM PDT 24
Finished Jun 27 06:54:56 PM PDT 24
Peak memory 199992 kb
Host smart-51b3ec5d-6aaf-43c8-a87f-691542f03705
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1780747735 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_test_sha256_vectors.1780747735
Directory /workspace/8.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/8.hmac_test_sha384_vectors.2709526464
Short name T266
Test name
Test status
Simulation time 49246966199 ps
CPU time 1743.74 seconds
Started Jun 27 06:46:29 PM PDT 24
Finished Jun 27 07:15:46 PM PDT 24
Peak memory 214912 kb
Host smart-4f929182-aa04-4d6c-97f3-8f0a6f2f3449
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2709526464 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_test_sha384_vectors.2709526464
Directory /workspace/8.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/8.hmac_test_sha512_vectors.2406541274
Short name T631
Test name
Test status
Simulation time 60897145598 ps
CPU time 1593.19 seconds
Started Jun 27 06:46:29 PM PDT 24
Finished Jun 27 07:13:15 PM PDT 24
Peak memory 215768 kb
Host smart-f14cd5c3-d92a-4728-ada4-be3a37b5b608
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2406541274 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_test_sha512_vectors.2406541274
Directory /workspace/8.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/8.hmac_wipe_secret.3190528273
Short name T235
Test name
Test status
Simulation time 10674648587 ps
CPU time 38.58 seconds
Started Jun 27 06:46:24 PM PDT 24
Finished Jun 27 06:47:12 PM PDT 24
Peak memory 200036 kb
Host smart-570bc91c-b9a3-47c8-aed8-e79e09a94a1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190528273 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_wipe_secret.3190528273
Directory /workspace/8.hmac_wipe_secret/latest

Test location /workspace/coverage/default/9.hmac_alert_test.1192059258
Short name T422
Test name
Test status
Simulation time 14493351 ps
CPU time 0.6 seconds
Started Jun 27 06:46:37 PM PDT 24
Finished Jun 27 06:46:51 PM PDT 24
Peak memory 196000 kb
Host smart-ec6059df-00d4-49e2-8d99-07fe0a55dfe7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192059258 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_alert_test.1192059258
Directory /workspace/9.hmac_alert_test/latest

Test location /workspace/coverage/default/9.hmac_back_pressure.1975193085
Short name T439
Test name
Test status
Simulation time 3786059116 ps
CPU time 43.15 seconds
Started Jun 27 06:46:28 PM PDT 24
Finished Jun 27 06:47:24 PM PDT 24
Peak memory 200024 kb
Host smart-c6731d34-2bfe-4f4a-a4b0-523cf93adb40
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1975193085 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_back_pressure.1975193085
Directory /workspace/9.hmac_back_pressure/latest

Test location /workspace/coverage/default/9.hmac_burst_wr.678796622
Short name T306
Test name
Test status
Simulation time 4007599423 ps
CPU time 29.83 seconds
Started Jun 27 06:46:34 PM PDT 24
Finished Jun 27 06:47:17 PM PDT 24
Peak memory 200028 kb
Host smart-e26c293c-3304-4242-92f6-8ccf3fcde881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678796622 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_burst_wr.678796622
Directory /workspace/9.hmac_burst_wr/latest

Test location /workspace/coverage/default/9.hmac_datapath_stress.3918173101
Short name T379
Test name
Test status
Simulation time 2740575747 ps
CPU time 623.63 seconds
Started Jun 27 06:46:27 PM PDT 24
Finished Jun 27 06:57:03 PM PDT 24
Peak memory 691684 kb
Host smart-1bf6beb4-6639-4fdb-9f94-fd1c70149c3b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3918173101 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_datapath_stress.3918173101
Directory /workspace/9.hmac_datapath_stress/latest

Test location /workspace/coverage/default/9.hmac_error.2052356569
Short name T620
Test name
Test status
Simulation time 2095510660 ps
CPU time 119.47 seconds
Started Jun 27 06:46:30 PM PDT 24
Finished Jun 27 06:48:43 PM PDT 24
Peak memory 199960 kb
Host smart-b3a674fd-82d8-480b-8748-4dd3f298f06e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052356569 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_error.2052356569
Directory /workspace/9.hmac_error/latest

Test location /workspace/coverage/default/9.hmac_long_msg.269772203
Short name T182
Test name
Test status
Simulation time 6491865427 ps
CPU time 35.87 seconds
Started Jun 27 06:46:33 PM PDT 24
Finished Jun 27 06:47:22 PM PDT 24
Peak memory 200028 kb
Host smart-1cbf27fc-6144-49d8-9f03-4b1411d2b2f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269772203 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_long_msg.269772203
Directory /workspace/9.hmac_long_msg/latest

Test location /workspace/coverage/default/9.hmac_smoke.928135991
Short name T278
Test name
Test status
Simulation time 357063965 ps
CPU time 5.81 seconds
Started Jun 27 06:46:28 PM PDT 24
Finished Jun 27 06:46:47 PM PDT 24
Peak memory 199904 kb
Host smart-08b0e99f-a795-4a53-bb6d-e87969c7119b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928135991 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_smoke.928135991
Directory /workspace/9.hmac_smoke/latest

Test location /workspace/coverage/default/9.hmac_stress_all.3129108466
Short name T69
Test name
Test status
Simulation time 829022374402 ps
CPU time 6778.54 seconds
Started Jun 27 06:46:50 PM PDT 24
Finished Jun 27 08:39:59 PM PDT 24
Peak memory 792092 kb
Host smart-cd19d941-65ed-4205-9f6f-291d8a21a10c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129108466 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all.3129108466
Directory /workspace/9.hmac_stress_all/latest

Test location /workspace/coverage/default/9.hmac_test_hmac_vectors.1832483367
Short name T552
Test name
Test status
Simulation time 34228327 ps
CPU time 1.24 seconds
Started Jun 27 06:46:33 PM PDT 24
Finished Jun 27 06:46:48 PM PDT 24
Peak memory 200008 kb
Host smart-04405eeb-3e50-427b-b790-23f0c3a33f2e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832483367 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 9.hmac_test_hmac_vectors.1832483367
Directory /workspace/9.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/9.hmac_test_sha256_vectors.3589065833
Short name T430
Test name
Test status
Simulation time 26994590232 ps
CPU time 477.34 seconds
Started Jun 27 06:46:34 PM PDT 24
Finished Jun 27 06:54:45 PM PDT 24
Peak memory 199952 kb
Host smart-945abea4-6306-4448-95f2-0d47460f4658
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3589065833 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_test_sha256_vectors.3589065833
Directory /workspace/9.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/9.hmac_test_sha384_vectors.2783638952
Short name T428
Test name
Test status
Simulation time 31989809131 ps
CPU time 1814.52 seconds
Started Jun 27 06:46:35 PM PDT 24
Finished Jun 27 07:17:03 PM PDT 24
Peak memory 215664 kb
Host smart-c4263256-b5ad-46ca-b7a0-1b62fc2d071a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2783638952 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_test_sha384_vectors.2783638952
Directory /workspace/9.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/9.hmac_test_sha512_vectors.1907881459
Short name T1
Test name
Test status
Simulation time 160642947222 ps
CPU time 2062.59 seconds
Started Jun 27 06:46:32 PM PDT 24
Finished Jun 27 07:21:08 PM PDT 24
Peak memory 215936 kb
Host smart-0cc0bd43-9096-45ef-8e1d-1cb6721958a6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1907881459 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_test_sha512_vectors.1907881459
Directory /workspace/9.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/9.hmac_wipe_secret.206295390
Short name T316
Test name
Test status
Simulation time 1312264666 ps
CPU time 26.36 seconds
Started Jun 27 06:46:37 PM PDT 24
Finished Jun 27 06:47:17 PM PDT 24
Peak memory 200144 kb
Host smart-f5f08db3-4484-43ef-ab4d-e7e634c1ac86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=206295390 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_wipe_secret.206295390
Directory /workspace/9.hmac_wipe_secret/latest
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