Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	51305014	1			T1	983		T2	1416		T3	290689
all_values[1]	51305014	1			T1	983		T2	1416		T3	290689
all_values[2]	51305014	1			T1	983		T2	1416		T3	290689

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

144582

1

T1

46

T2

428

T4

10

auto[1]

153770460

1

T1

2903

T2

3820

T3

872067

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

127651152

1

T1

2611

T2

3973

T3

729159

auto[1]

26263890

1

T1

338

T2

275

T3

142908

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	55803	1			T1	21		T2	426		T9	1395
all_values[0]	auto[0]	auto[1]	258	1			T1	2		T2	2		T9	10
all_values[0]	auto[1]	auto[0]	51138096	1			T1	935		T2	986		T3	290303
all_values[0]	auto[1]	auto[1]	110857	1			T1	25		T2	2		T3	386
all_values[1]	auto[0]	auto[0]	33990	1			T12	488		T9	6		T17	8
all_values[1]	auto[0]	auto[1]	185	1			T9	5		T17	1		T64	1
all_values[1]	auto[1]	auto[0]	51267428	1			T1	983		T2	1416		T3	290689
all_values[1]	auto[1]	auto[1]	3411	1			T7	210		T8	118		T9	5
all_values[2]	auto[0]	auto[0]	19466	1			T1	23		T10	372		T8	2
all_values[2]	auto[0]	auto[1]	34880	1			T4	10		T9	300		T17	2
all_values[2]	auto[1]	auto[0]	25136369	1			T1	649		T2	1145		T3	148167
all_values[2]	auto[1]	auto[1]	26114299	1			T1	311		T2	271		T3	142522