Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::msg_len_cg

Group : hmac_env_pkg::hmac_env_cov::msg_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
84.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	2	16	88.89
Crosses	32	6	26	81.25

Variables for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
hmac_en	2	0	2	100.00	100	1	1	2
msg_len_lower_cp	15	1	14	93.33	100	1	1	0
msg_len_upper_cp	1	1	0	0.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
msg_len_lower_cross	30	4	26	86.67	100	1	1	0
msg_len_upper_cross	2	2	0	0.00	100	1	1	0

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

168750

1

T1

34

T2

6

T3

396

auto[1]

150956

1

T1

30

T2

2

T4

24

---

Summary for Variable msg_len_lower_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	1	14	93.33

User Defined Bins for msg_len_lower_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
len_1023	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_2050_plus	49039	1			T2	2		T3	58		T5	16
len_1026_2046	30506	1			T2	2		T3	6		T5	6
len_514_1022	9625	1			T3	5		T6	4		T10	5
len_2_510	59647	1			T1	24		T3	126		T4	21
len_2049	12	1			T84	2		T87	1		T125	2
len_2048	50	1			T14	2		T9	1		T17	2
len_2047	4	1			T126	3		T127	1		-	-
len_1025	6	1			T128	1		T129	2		T130	3
len_1024	94	1			T14	1		T15	1		T9	1
len_513	2	1			T131	2		-	-		-	-
len_512	123	1			T14	1		T15	1		T9	2
len_511	1	1			T132	1		-	-		-	-
len_1	1045	1			T3	1		T5	2		T6	1
len_0	9699	1			T1	8		T3	2		T4	6

---

Summary for Variable msg_len_upper_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	1	0	0.00

User Defined Bins for msg_len_upper_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
len_upper	0	1	1

---

Summary for Cross msg_len_lower_cross

Samples crossed: hmac_en msg_len_lower_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	4	26	86.67	4

Automatically Generated Cross Bins for msg_len_lower_cross

Uncovered bins

hmac_en	msg_len_lower_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[len_1023 , len_513]	--	--	2
[auto[0]]	[len_511]	0	1	1
[auto[1]]	[len_1023]	0	1	1

Covered bins

hmac_en	msg_len_lower_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	len_2050_plus	26770	1			T2	2		T3	58		T5	16
auto[0]	len_1026_2046	15864	1			T2	1		T3	6		T5	6
auto[0]	len_514_1022	5888	1			T3	5		T6	4		T10	4
auto[0]	len_2_510	31316	1			T1	12		T3	126		T4	11
auto[0]	len_2049	2	1			T84	2		-	-		-	-
auto[0]	len_2048	32	1			T14	1		T17	2		T133	2
auto[0]	len_2047	1	1			T127	1		-	-		-	-
auto[0]	len_1025	2	1			T129	2		-	-		-	-
auto[0]	len_1024	52	1			T9	1		T17	3		T133	2
auto[0]	len_512	73	1			T14	1		T15	1		T9	1
auto[0]	len_1	212	1			T3	1		T5	2		T6	1
auto[0]	len_0	4163	1			T1	5		T3	2		T4	4
auto[1]	len_2050_plus	22269	1			T10	1		T11	10		T12	4
auto[1]	len_1026_2046	14642	1			T2	1		T10	4		T12	3
auto[1]	len_514_1022	3737	1			T10	1		T12	1		T14	27
auto[1]	len_2_510	28331	1			T1	12		T4	10		T10	2
auto[1]	len_2049	10	1			T87	1		T125	2		T134	1
auto[1]	len_2048	18	1			T14	1		T9	1		T133	1
auto[1]	len_2047	3	1			T126	3		-	-		-	-
auto[1]	len_1025	4	1			T128	1		T130	3		-	-
auto[1]	len_1024	42	1			T14	1		T15	1		T135	1
auto[1]	len_513	2	1			T131	2		-	-		-	-
auto[1]	len_512	50	1			T9	1		T135	1		T133	1
auto[1]	len_511	1	1			T132	1		-	-		-	-
auto[1]	len_1	833	1			T11	15		T28	8		T17	21
auto[1]	len_0	5536	1			T1	3		T4	2		T12	3

---

Summary for Cross msg_len_upper_cross

Samples crossed: hmac_en msg_len_upper_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	2	2	0	0.00	2

Automatically Generated Cross Bins for msg_len_upper_cross

Uncovered bins

hmac_en	msg_len_upper_cp	COUNT	AT LEAST	NUMBER	STATUS
*	*	--	--	2