Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::status_cg

Group : hmac_env_pkg::hmac_env_cov::status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	96	0	96	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	2
sta_fifo_depth	8	0	8	100.00	100	1	1	0
sta_fifo_empty	2	0	2	100.00	100	1	1	2
sta_fifo_full	2	0	2	100.00	100	1	1	2

Crosses for Group hmac_env_pkg::hmac_env_cov::status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
fifo_empty_cross	16	0	16	100.00	100	1	1	0
fifo_full_cross	16	0	16	100.00	100	1	1	0
fifo_depth_cross	64	0	64	100.00	100	1	1	0

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25276892

1

T1

446

T2

500

T3

147780

auto[1]

2318794

1

T1

267

T2

910

T4

274

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2249436

1

T1

445

T2

229

T4

335

auto[1]

25346250

1

T1

268

T2

1181

T3

147780

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23579404

1

T1

369

T2

1139

T3

147780

auto[1]

4016282

1

T1

344

T2

271

T4

315

---

Summary for Variable sta_fifo_depth

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for sta_fifo_depth

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	23805256	1			T1	555		T2	767		T3	113984
fifo_depth[1]	741796	1			T1	13		T2	69		T3	5056
fifo_depth[2]	573493	1			T1	12		T2	69		T3	4995
fifo_depth[3]	461130	1			T1	11		T2	52		T3	4566
fifo_depth[4]	364805	1			T1	14		T2	73		T3	3741
fifo_depth[5]	287995	1			T1	15		T2	59		T3	3001
fifo_depth[6]	252577	1			T1	14		T2	69		T3	2600
fifo_depth[7]	224005	1			T1	14		T2	67		T3	2333

---

Summary for Variable sta_fifo_empty

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_empty

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3790430

1

T1

158

T2

643

T3

33796

auto[1]

23805256

1

T1

555

T2

767

T3

113984

---

Summary for Variable sta_fifo_full

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_full

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27585794

1

T1

713

T2

1410

T3

147780

auto[1]

9892

1

T8

2

T15

107

T9

587

---

Summary for Cross fifo_empty_cross

Samples crossed: sta_fifo_empty hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for fifo_empty_cross

Bins

sta_fifo_empty

hmac_en

endian_swap

digest_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

88132

1

T2

155

T4

7

T14

28

auto[0]

auto[0]

auto[0]

auto[1]

70724

1

T1

9

T10

25

T12

35

auto[0]

auto[0]

auto[1]

auto[0]

2950663

1

T1

7

T3

33796

T4

2

auto[0]

auto[0]

auto[1]

auto[1]

72131

1

T1

7

T2

488

T4

1

auto[0]

auto[1]

auto[0]

auto[0]

90484

1

T1

43

T10

44

T11

1718

auto[0]

auto[1]

auto[0]

auto[1]

114621

1

T1

30

T10

30

T11

346

auto[0]

auto[1]

auto[1]

auto[0]

281829

1

T1

62

T4

8

T56

2

auto[0]

auto[1]

auto[1]

auto[1]

121846

1

T4

7

T10

52

T11

752

auto[1]

auto[0]

auto[0]

auto[0]

271959

1

T1

134

T2

74

T4

225

auto[1]

auto[0]

auto[0]

auto[1]

274728

1

T1

92

T4

43

T10

287

auto[1]

auto[0]

auto[1]

auto[0]

19597147

1

T1

45

T3

113984

T4

100

auto[1]

auto[0]

auto[1]

auto[1]

253920

1

T1

75

T2

422

T4

81

auto[1]

auto[1]

auto[0]

auto[0]

627363

1

T1

86

T4

11

T10

1670

auto[1]

auto[1]

auto[0]

auto[1]

711425

1

T1

51

T4

49

T10

1186

auto[1]

auto[1]

auto[1]

auto[0]

1369315

1

T1

69

T2

271

T4

147

auto[1]

auto[1]

auto[1]

auto[1]

699399

1

T1

3

T4

93

T10

1267

---

Summary for Cross fifo_full_cross

Samples crossed: sta_fifo_full hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for fifo_full_cross

Bins

sta_fifo_full

hmac_en

endian_swap

digest_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

358601

1

T1

134

T2

229

T4

232

auto[0]

auto[0]

auto[0]

auto[1]

343553

1

T1

101

T4

43

T10

312

auto[0]

auto[0]

auto[1]

auto[0]

22546708

1

T1

52

T3

147780

T4

102

auto[0]

auto[0]

auto[1]

auto[1]

325096

1

T1

82

T2

910

T4

82

auto[0]

auto[1]

auto[0]

auto[0]

717199

1

T1

129

T4

11

T10

1714

auto[0]

auto[1]

auto[0]

auto[1]

824905

1

T1

81

T4

49

T10

1216

auto[0]

auto[1]

auto[1]

auto[0]

1650311

1

T1

131

T2

271

T4

155

auto[0]

auto[1]

auto[1]

auto[1]

819421

1

T1

3

T4

100

T10

1319

auto[1]

auto[0]

auto[0]

auto[0]

1490

1

T9

132

T17

69

T145

28

auto[1]

auto[0]

auto[0]

auto[1]

1899

1

T8

1

T15

28

T9

2

auto[1]

auto[0]

auto[1]

auto[0]

1102

1

T15

6

T17

21

T145

4

auto[1]

auto[0]

auto[1]

auto[1]

955

1

T15

6

T9

50

T17

36

auto[1]

auto[1]

auto[0]

auto[0]

648

1

T8

1

T9

9

T17

17

auto[1]

auto[1]

auto[0]

auto[1]

1141

1

T15

1

T124

18

T149

1

auto[1]

auto[1]

auto[1]

auto[0]

833

1

T15

16

T9

6

T17

1

auto[1]

auto[1]

auto[1]

auto[1]

1824

1

T15

50

T9

388

T17

10

---

Summary for Cross fifo_depth_cross

Samples crossed: sta_fifo_depth hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for fifo_depth_cross

Bins

sta_fifo_depth	hmac_en	endian_swap	digest_swap	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	auto[0]	auto[0]	auto[0]	271959	1			T1	134		T2	74		T4	225
fifo_depth[0]	auto[0]	auto[0]	auto[1]	274728	1			T1	92		T4	43		T10	287
fifo_depth[0]	auto[0]	auto[1]	auto[0]	19597147	1			T1	45		T3	113984		T4	100
fifo_depth[0]	auto[0]	auto[1]	auto[1]	253920	1			T1	75		T2	422		T4	81
fifo_depth[0]	auto[1]	auto[0]	auto[0]	627363	1			T1	86		T4	11		T10	1670
fifo_depth[0]	auto[1]	auto[0]	auto[1]	711425	1			T1	51		T4	49		T10	1186
fifo_depth[0]	auto[1]	auto[1]	auto[0]	1369315	1			T1	69		T2	271		T4	147
fifo_depth[0]	auto[1]	auto[1]	auto[1]	699399	1			T1	3		T4	93		T10	1267
fifo_depth[1]	auto[0]	auto[0]	auto[0]	6967	1			T2	14		T4	3		T14	24
fifo_depth[1]	auto[0]	auto[0]	auto[1]	6731	1			T1	1		T10	4		T12	9
fifo_depth[1]	auto[0]	auto[1]	auto[0]	644454	1			T3	5056		T4	1		T5	1305
fifo_depth[1]	auto[0]	auto[1]	auto[1]	6800	1			T2	55		T10	68		T12	53
fifo_depth[1]	auto[1]	auto[0]	auto[0]	9984	1			T1	4		T10	14		T11	151
fifo_depth[1]	auto[1]	auto[0]	auto[1]	12420	1			T1	1		T10	10		T11	35
fifo_depth[1]	auto[1]	auto[1]	auto[0]	43024	1			T1	7		T4	4		T56	1
fifo_depth[1]	auto[1]	auto[1]	auto[1]	11416	1			T4	4		T10	19		T11	77
fifo_depth[2]	auto[0]	auto[0]	auto[0]	6112	1			T2	20		T4	3		T14	2
fifo_depth[2]	auto[0]	auto[0]	auto[1]	5991	1			T10	9		T12	11		T31	1
fifo_depth[2]	auto[0]	auto[1]	auto[0]	489775	1			T1	1		T3	4995		T5	534
fifo_depth[2]	auto[0]	auto[1]	auto[1]	6054	1			T2	49		T4	1		T10	49
fifo_depth[2]	auto[1]	auto[0]	auto[0]	8935	1			T1	3		T10	10		T11	176
fifo_depth[2]	auto[1]	auto[0]	auto[1]	11430	1			T1	2		T10	6		T11	18
fifo_depth[2]	auto[1]	auto[1]	auto[0]	34865	1			T1	6		T4	2		T56	1
fifo_depth[2]	auto[1]	auto[1]	auto[1]	10331	1			T4	2		T10	17		T11	58
fifo_depth[3]	auto[0]	auto[0]	auto[0]	4785	1			T2	15		T14	2		T34	7
fifo_depth[3]	auto[0]	auto[0]	auto[1]	4745	1			T1	1		T10	9		T12	6
fifo_depth[3]	auto[0]	auto[1]	auto[0]	391064	1			T3	4566		T4	1		T5	209
fifo_depth[3]	auto[0]	auto[1]	auto[1]	4960	1			T1	1		T2	37		T10	28
fifo_depth[3]	auto[1]	auto[0]	auto[0]	7624	1			T1	4		T10	8		T11	148
fifo_depth[3]	auto[1]	auto[0]	auto[1]	10216	1			T1	1		T10	9		T11	30
fifo_depth[3]	auto[1]	auto[1]	auto[0]	28726	1			T1	4		T14	3		T24	3
fifo_depth[3]	auto[1]	auto[1]	auto[1]	9010	1			T10	12		T11	63		T12	7
fifo_depth[4]	auto[0]	auto[0]	auto[0]	4901	1			T2	22		T150	3		T9	211
fifo_depth[4]	auto[0]	auto[0]	auto[1]	4645	1			T1	1		T10	2		T12	4
fifo_depth[4]	auto[0]	auto[1]	auto[0]	299434	1			T1	1		T3	3741		T5	66
fifo_depth[4]	auto[0]	auto[1]	auto[1]	4902	1			T1	1		T2	51		T10	17
fifo_depth[4]	auto[1]	auto[0]	auto[0]	7158	1			T1	3		T10	8		T11	165
fifo_depth[4]	auto[1]	auto[0]	auto[1]	9598	1			T1	2		T10	5		T11	33
fifo_depth[4]	auto[1]	auto[1]	auto[0]	25310	1			T1	6		T4	1		T14	6
fifo_depth[4]	auto[1]	auto[1]	auto[1]	8857	1			T10	2		T11	79		T12	5
fifo_depth[5]	auto[0]	auto[0]	auto[0]	3999	1			T2	15		T4	1		T150	1
fifo_depth[5]	auto[0]	auto[0]	auto[1]	3725	1			T1	1		T12	3		T151	51
fifo_depth[5]	auto[0]	auto[1]	auto[0]	230482	1			T1	1		T3	3001		T5	19
fifo_depth[5]	auto[0]	auto[1]	auto[1]	3941	1			T1	1		T2	44		T10	9
fifo_depth[5]	auto[1]	auto[0]	auto[0]	6529	1			T1	3		T10	3		T11	150
fifo_depth[5]	auto[1]	auto[0]	auto[1]	8926	1			T1	4		T11	33		T12	5
fifo_depth[5]	auto[1]	auto[1]	auto[0]	22145	1			T1	5		T4	1		T14	2
fifo_depth[5]	auto[1]	auto[1]	auto[1]	8248	1			T4	1		T10	2		T11	69
fifo_depth[6]	auto[0]	auto[0]	auto[0]	4147	1			T2	19		T9	198		T17	55
fifo_depth[6]	auto[0]	auto[0]	auto[1]	3744	1			T1	1		T10	1		T12	1
fifo_depth[6]	auto[0]	auto[1]	auto[0]	197450	1			T1	1		T3	2600		T5	3
fifo_depth[6]	auto[0]	auto[1]	auto[1]	3931	1			T2	50		T10	1		T151	17
fifo_depth[6]	auto[1]	auto[0]	auto[0]	6389	1			T1	4		T10	1		T11	150
fifo_depth[6]	auto[1]	auto[0]	auto[1]	8655	1			T1	4		T11	28		T12	1
fifo_depth[6]	auto[1]	auto[1]	auto[0]	19835	1			T1	4		T14	2		T28	167
fifo_depth[6]	auto[1]	auto[1]	auto[1]	8426	1			T11	70		T28	125		T9	8
fifo_depth[7]	auto[0]	auto[0]	auto[0]	3901	1			T2	15		T9	179		T17	35
fifo_depth[7]	auto[0]	auto[0]	auto[1]	3372	1			T1	3		T12	1		T151	45
fifo_depth[7]	auto[0]	auto[1]	auto[0]	173654	1			T1	1		T3	2333		T5	1
fifo_depth[7]	auto[0]	auto[1]	auto[1]	3606	1			T1	1		T2	52		T10	1
fifo_depth[7]	auto[1]	auto[0]	auto[0]	6102	1			T1	2		T11	141		T28	40
fifo_depth[7]	auto[1]	auto[0]	auto[1]	8192	1			T1	1		T11	32		T12	1
fifo_depth[7]	auto[1]	auto[1]	auto[0]	17238	1			T1	6		T14	1		T28	148
fifo_depth[7]	auto[1]	auto[1]	auto[1]	7940	1			T11	72		T28	92		T9	10