Summary for Variable cp_intr_pin
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for cp_intr_pin
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_pins[0] |
51305014 |
1 |
|
|
T1 |
983 |
|
T2 |
1416 |
|
T3 |
290689 |
all_pins[1] |
51305014 |
1 |
|
|
T1 |
983 |
|
T2 |
1416 |
|
T3 |
290689 |
all_pins[2] |
51305014 |
1 |
|
|
T1 |
983 |
|
T2 |
1416 |
|
T3 |
290689 |
Summary for Variable cp_intr_pin_value
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for cp_intr_pin_value
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
values[0x0] |
127685660 |
1 |
|
|
T1 |
2610 |
|
T2 |
3975 |
|
T3 |
729159 |
values[0x1] |
26229382 |
1 |
|
|
T1 |
339 |
|
T2 |
273 |
|
T3 |
142908 |
transitions[0x0=>0x1] |
26229159 |
1 |
|
|
T1 |
339 |
|
T2 |
273 |
|
T3 |
142908 |
transitions[0x1=>0x0] |
26229169 |
1 |
|
|
T1 |
339 |
|
T2 |
273 |
|
T3 |
142908 |
Summary for Cross cp_intr_pins_all_values
Samples crossed: cp_intr_pin cp_intr_pin_value
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
12 |
0 |
12 |
100.00 |
|
Automatically Generated Cross Bins for cp_intr_pins_all_values
Bins
cp_intr_pin | cp_intr_pin_value | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_pins[0] |
values[0x0] |
51193433 |
1 |
|
|
T1 |
955 |
|
T2 |
1414 |
|
T3 |
290303 |
all_pins[0] |
values[0x1] |
111581 |
1 |
|
|
T1 |
28 |
|
T2 |
2 |
|
T3 |
386 |
all_pins[0] |
transitions[0x0=>0x1] |
111533 |
1 |
|
|
T1 |
28 |
|
T2 |
2 |
|
T3 |
386 |
all_pins[0] |
transitions[0x1=>0x0] |
26114261 |
1 |
|
|
T1 |
311 |
|
T2 |
271 |
|
T3 |
142522 |
all_pins[1] |
values[0x0] |
51301512 |
1 |
|
|
T1 |
983 |
|
T2 |
1416 |
|
T3 |
290689 |
all_pins[1] |
values[0x1] |
3502 |
1 |
|
|
T7 |
215 |
|
T8 |
121 |
|
T9 |
6 |
all_pins[1] |
transitions[0x0=>0x1] |
3363 |
1 |
|
|
T7 |
210 |
|
T8 |
117 |
|
T9 |
6 |
all_pins[1] |
transitions[0x1=>0x0] |
111442 |
1 |
|
|
T1 |
28 |
|
T2 |
2 |
|
T3 |
386 |
all_pins[2] |
values[0x0] |
25190715 |
1 |
|
|
T1 |
672 |
|
T2 |
1145 |
|
T3 |
148167 |
all_pins[2] |
values[0x1] |
26114299 |
1 |
|
|
T1 |
311 |
|
T2 |
271 |
|
T3 |
142522 |
all_pins[2] |
transitions[0x0=>0x1] |
26114263 |
1 |
|
|
T1 |
311 |
|
T2 |
271 |
|
T3 |
142522 |
all_pins[2] |
transitions[0x1=>0x0] |
3466 |
1 |
|
|
T7 |
215 |
|
T8 |
121 |
|
T9 |
6 |