Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	18	0	18	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	18	0	18	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	645	1			T9	14		T17	4		T64	7
all_values[1]	645	1			T9	14		T17	4		T64	7
all_values[2]	645	1			T9	14		T17	4		T64	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

998

1

T9

26

T17

5

T64

11

auto[1]

937

1

T9

16

T17

7

T64

10

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

720

1

T9

9

T17

5

T64

9

auto[1]

1215

1

T9

33

T17

7

T64

12

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1123

1

T9

17

T17

9

T64

15

auto[1]

812

1

T9

25

T17

3

T64

6

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	18	0	18	100.00
Automatically Generated Cross Bins	18	0	18	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr

cp_intr_test

cp_intr_en

cp_intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_values[0]

auto[0]

auto[0]

auto[0]

153

1

T9

3

T64

2

T120

3

all_values[0]

auto[0]

auto[0]

auto[1]

48

1

T17

1

T64

1

T143

2

all_values[0]

auto[0]

auto[1]

auto[0]

104

1

T64

1

T120

1

T143

2

all_values[0]

auto[0]

auto[1]

auto[1]

66

1

T17

2

T64

1

T120

1

all_values[0]

auto[1]

auto[0]

auto[1]

134

1

T9

8

T64

1

T120

2

all_values[0]

auto[1]

auto[1]

auto[1]

140

1

T9

3

T17

1

T64

1

all_values[1]

auto[0]

auto[0]

auto[0]

104

1

T9

2

T17

1

T64

2

all_values[1]

auto[0]

auto[0]

auto[1]

82

1

T9

2

T17

1

T64

1

all_values[1]

auto[0]

auto[1]

auto[0]

84

1

T9

1

T64

3

T120

2

all_values[1]

auto[0]

auto[1]

auto[1]

85

1

T9

2

T143

1

T144

1

all_values[1]

auto[1]

auto[0]

auto[1]

158

1

T9

4

T17

1

T64

1

all_values[1]

auto[1]

auto[1]

auto[1]

132

1

T9

3

T17

1

T120

2

all_values[2]

auto[0]

auto[0]

auto[0]

130

1

T9

1

T17

1

T64

1

all_values[2]

auto[0]

auto[0]

auto[1]

63

1

T9

2

T64

1

T120

1

all_values[2]

auto[0]

auto[1]

auto[0]

145

1

T9

2

T17

3

T120

1

all_values[2]

auto[0]

auto[1]

auto[1]

59

1

T9

2

T64

2

T143

1

all_values[2]

auto[1]

auto[0]

auto[1]

126

1

T9

4

T64

1

T73

2

all_values[2]

auto[1]

auto[1]

auto[1]

122

1

T9

3

T64

2

T120

5

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal