Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::cfg_cg

Group : hmac_env_pkg::hmac_env_cov::cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
76.47	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	2	18	90.00
Crosses	82	22	60	73.17

Variables for Group hmac_env_pkg::hmac_env_cov::cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_size	5	1	4	80.00	100	1	1	0
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	0
key_length	7	1	6	85.71	100	1	1	0
sha_en	2	0	2	100.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cfg_cross	8	0	8	100.00	100	1	1	0
hmac_dis_x_sha_en	4	0	4	100.00	100	1	1	0
key_x_digest_mismatch	35	11	24	68.57	100	1	1	0
key_length_x_digest_size	35	11	24	68.57	100	1	1	0

Summary for Variable digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	1	4	80.00

User Defined Bins for digest_size

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
sha2_invalid	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sha2_none	147	1			T16	1		T34	1		T32	3
sha2_512	43764	1			T1	8		T4	7		T10	3
sha2_384	39631	1			T1	7		T2	1		T3	386
sha2_256	26591	1			T1	8		T2	2		T4	7

---

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

105363

1

T1

16

T2

1

T3

386

auto[1]

4770

1

T1

7

T2

2

T4

7

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4675

1

T1

15

T2

1

T4

8

auto[1]

105458

1

T1

8

T2

2

T3

386

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

39895

1

T1

10

T4

6

T10

6

disabled

70238

1

T1

13

T2

3

T3

386

---

Summary for Variable key_length

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	1	6	85.71

User Defined Bins for key_length

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
key_invalid	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_none	66875	1			T1	6		T3	386		T4	5
key_1024	19577	1			T1	5		T4	2		T10	3
key_512	12543	1			T1	3		T4	3		T10	4
key_384	7899	1			T1	4		T2	2		T4	1
key_256	1589	1			T1	4		T4	5		T11	5
key_128	1650	1			T1	1		T2	1		T4	2

---

Summary for Variable sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

109806

1

T1

23

T2

3

T3

386

disabled

327

1

T16

2

T34

2

T32

5

---

Summary for Cross cfg_cross

Samples crossed: hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cfg_cross

Bins

hmac_en	endian_swap	digest_swap	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
enabled	auto[0]	auto[0]	1055	1			T1	2		T10	1		T11	2
enabled	auto[0]	auto[1]	1024	1			T1	2		T10	1		T11	4
enabled	auto[1]	auto[0]	36667	1			T1	6		T4	3		T11	3
enabled	auto[1]	auto[1]	1149	1			T4	3		T10	4		T11	2
disabled	auto[0]	auto[0]	1287	1			T1	7		T2	1		T4	6
disabled	auto[0]	auto[1]	1309	1			T1	4		T4	2		T10	2
disabled	auto[1]	auto[0]	66354	1			T1	1		T3	386		T4	2
disabled	auto[1]	auto[1]	1288	1			T1	1		T2	2		T4	2

---

Summary for Cross hmac_dis_x_sha_en

Samples crossed: hmac_en sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	3	0	3	100.00
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for hmac_dis_x_sha_en

Bins

hmac_en

sha_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

enabled

39733

1

T1

10

T4

6

T10

6

enabled

disabled

162

1

T34

1

T32

3

T33

1

disabled

disabled

165

1

T16

2

T34

1

T32

2

User Defined Cross Bins for hmac_dis_x_sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

70073

1

T1

13

T2

3

T3

386

---

Summary for Cross key_x_digest_mismatch

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	35	11	24	68.57	11
Automatically Generated Cross Bins	34	11	23	67.65	11
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for key_x_digest_mismatch

Element holes

key_length	digest_size	COUNT	AT LEAST	NUMBER	STATUS
[key_invalid]	*	--	--	5

Uncovered bins

key_length	digest_size	COUNT	AT LEAST	NUMBER	STATUS
[key_none , key_1024 , key_512 , key_384 , key_256 , key_128]	[sha2_invalid]	--	--	6

Covered bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_none	sha2_none	47	1			T34	1		T32	2		T33	1
key_none	sha2_512	26813	1			T1	1		T4	2		T12	1
key_none	sha2_384	25315	1			T1	1		T3	386		T4	2
key_none	sha2_256	14700	1			T1	4		T4	1		T5	194
key_1024	sha2_none	16	1			T16	1		T119	1		T87	1
key_1024	sha2_512	14865	1			T1	1		T4	1		T14	1
key_1024	sha2_384	4459	1			T1	3		T10	2		T11	2
key_512	sha2_none	20	1			T121	1		T119	1		T122	1
key_512	sha2_512	521	1			T1	2		T4	2		T10	2
key_512	sha2_384	8294	1			T1	1		T12	1		T8	3
key_512	sha2_256	3708	1			T4	1		T10	2		T12	3
key_384	sha2_none	20	1			T123	1		T122	1		T124	1
key_384	sha2_512	570	1			T1	2		T10	1		T11	1
key_384	sha2_384	501	1			T2	1		T10	2		T11	1
key_384	sha2_256	6808	1			T1	2		T2	1		T4	1
key_256	sha2_none	26	1			T119	1		T94	1		T64	1
key_256	sha2_512	486	1			T1	1		T11	2		T12	3
key_256	sha2_384	524	1			T1	2		T4	2		T11	1
key_256	sha2_256	553	1			T1	1		T4	3		T11	2
key_128	sha2_none	18	1			T32	1		T119	2		T94	1
key_128	sha2_512	509	1			T1	1		T4	2		T12	1
key_128	sha2_384	538	1			T10	1		T11	1		T12	2
key_128	sha2_256	585	1			T2	1		T11	1		T12	2

User Defined Cross Bins for key_x_digest_mismatch

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

237

1

T1

1

T4

1

T10

1

---

Summary for Cross key_length_x_digest_size

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	35	11	24	68.57	11

Automatically Generated Cross Bins for key_length_x_digest_size

Element holes

key_length	digest_size	COUNT	AT LEAST	NUMBER	STATUS
[key_invalid]	*	--	--	5

Uncovered bins

key_length	digest_size	COUNT	AT LEAST	NUMBER	STATUS
[key_none , key_1024 , key_512 , key_384 , key_256 , key_128]	[sha2_invalid]	--	--	6

Covered bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_none	sha2_none	47	1			T34	1		T32	2		T33	1
key_none	sha2_512	26813	1			T1	1		T4	2		T12	1
key_none	sha2_384	25315	1			T1	1		T3	386		T4	2
key_none	sha2_256	14700	1			T1	4		T4	1		T5	194
key_1024	sha2_none	16	1			T16	1		T119	1		T87	1
key_1024	sha2_512	14865	1			T1	1		T4	1		T14	1
key_1024	sha2_384	4459	1			T1	3		T10	2		T11	2
key_1024	sha2_256	237	1			T1	1		T4	1		T10	1
key_512	sha2_none	20	1			T121	1		T119	1		T122	1
key_512	sha2_512	521	1			T1	2		T4	2		T10	2
key_512	sha2_384	8294	1			T1	1		T12	1		T8	3
key_512	sha2_256	3708	1			T4	1		T10	2		T12	3
key_384	sha2_none	20	1			T123	1		T122	1		T124	1
key_384	sha2_512	570	1			T1	2		T10	1		T11	1
key_384	sha2_384	501	1			T2	1		T10	2		T11	1
key_384	sha2_256	6808	1			T1	2		T2	1		T4	1
key_256	sha2_none	26	1			T119	1		T94	1		T64	1
key_256	sha2_512	486	1			T1	1		T11	2		T12	3
key_256	sha2_384	524	1			T1	2		T4	2		T11	1
key_256	sha2_256	553	1			T1	1		T4	3		T11	2
key_128	sha2_none	18	1			T32	1		T119	2		T94	1
key_128	sha2_512	509	1			T1	1		T4	2		T12	1
key_128	sha2_384	538	1			T10	1		T11	1		T12	2
key_128	sha2_256	585	1			T2	1		T11	1		T12	2