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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
92.61 95.85 92.94 100.00 74.36 91.89 99.49 93.75


Total test records in report: 914
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T77 /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.172261066 Jun 29 04:52:04 PM PDT 24 Jun 29 04:52:05 PM PDT 24 29281623 ps
T112 /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.249174284 Jun 29 04:52:11 PM PDT 24 Jun 29 04:52:14 PM PDT 24 1346929817 ps
T39 /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.36277139 Jun 29 04:52:08 PM PDT 24 Jun 29 05:00:37 PM PDT 24 195861427532 ps
T803 /workspace/coverage/cover_reg_top/28.hmac_intr_test.2730278858 Jun 29 04:52:51 PM PDT 24 Jun 29 04:52:52 PM PDT 24 24724885 ps
T40 /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.1577590617 Jun 29 04:52:43 PM PDT 24 Jun 29 04:52:48 PM PDT 24 232699180 ps
T804 /workspace/coverage/cover_reg_top/24.hmac_intr_test.1545681151 Jun 29 04:52:50 PM PDT 24 Jun 29 04:52:51 PM PDT 24 16958338 ps
T41 /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.1286894570 Jun 29 04:52:40 PM PDT 24 Jun 29 04:52:43 PM PDT 24 31613175 ps
T113 /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.3232087023 Jun 29 04:52:34 PM PDT 24 Jun 29 04:52:37 PM PDT 24 161983722 ps
T114 /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.930879127 Jun 29 04:52:41 PM PDT 24 Jun 29 04:52:44 PM PDT 24 116527174 ps
T78 /workspace/coverage/cover_reg_top/21.hmac_intr_test.3154504138 Jun 29 04:52:51 PM PDT 24 Jun 29 04:52:52 PM PDT 24 35230247 ps
T57 /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.3091109277 Jun 29 04:52:11 PM PDT 24 Jun 29 04:52:15 PM PDT 24 171048643 ps
T58 /workspace/coverage/cover_reg_top/2.hmac_tl_errors.2216152718 Jun 29 04:52:11 PM PDT 24 Jun 29 04:52:14 PM PDT 24 196555583 ps
T79 /workspace/coverage/cover_reg_top/8.hmac_intr_test.3559701389 Jun 29 04:52:26 PM PDT 24 Jun 29 04:52:28 PM PDT 24 14740991 ps
T60 /workspace/coverage/cover_reg_top/5.hmac_tl_errors.1160932022 Jun 29 04:52:20 PM PDT 24 Jun 29 04:52:22 PM PDT 24 129974934 ps
T59 /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.813377989 Jun 29 04:52:39 PM PDT 24 Jun 29 04:52:42 PM PDT 24 84803206 ps
T71 /workspace/coverage/cover_reg_top/7.hmac_tl_errors.1473600822 Jun 29 04:52:21 PM PDT 24 Jun 29 04:52:22 PM PDT 24 87215116 ps
T66 /workspace/coverage/cover_reg_top/16.hmac_tl_errors.700562330 Jun 29 04:52:42 PM PDT 24 Jun 29 04:52:44 PM PDT 24 157833598 ps
T72 /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.783089602 Jun 29 04:52:45 PM PDT 24 Jun 29 04:52:47 PM PDT 24 54189809 ps
T80 /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.4094854737 Jun 29 04:52:39 PM PDT 24 Jun 29 04:52:40 PM PDT 24 213519799 ps
T115 /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.1930274793 Jun 29 04:52:11 PM PDT 24 Jun 29 04:52:14 PM PDT 24 399401139 ps
T81 /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.2335494391 Jun 29 04:52:21 PM PDT 24 Jun 29 04:52:23 PM PDT 24 93614921 ps
T805 /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.2317500729 Jun 29 04:52:06 PM PDT 24 Jun 29 04:52:09 PM PDT 24 225175784 ps
T806 /workspace/coverage/cover_reg_top/30.hmac_intr_test.1020433927 Jun 29 04:52:49 PM PDT 24 Jun 29 04:52:50 PM PDT 24 42124314 ps
T807 /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.1856609722 Jun 29 04:52:25 PM PDT 24 Jun 29 04:52:43 PM PDT 24 1857902981 ps
T116 /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.2719316968 Jun 29 04:52:40 PM PDT 24 Jun 29 04:52:43 PM PDT 24 37036579 ps
T117 /workspace/coverage/cover_reg_top/8.hmac_csr_rw.3715314517 Jun 29 04:52:26 PM PDT 24 Jun 29 04:52:28 PM PDT 24 50228632 ps
T808 /workspace/coverage/cover_reg_top/10.hmac_intr_test.2624310041 Jun 29 04:52:28 PM PDT 24 Jun 29 04:52:30 PM PDT 24 46126857 ps
T97 /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.2712489342 Jun 29 04:52:14 PM PDT 24 Jun 29 04:52:18 PM PDT 24 59858690 ps
T809 /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.617854350 Jun 29 04:52:08 PM PDT 24 Jun 29 04:52:24 PM PDT 24 1989896009 ps
T810 /workspace/coverage/cover_reg_top/44.hmac_intr_test.4128484512 Jun 29 04:52:48 PM PDT 24 Jun 29 04:52:50 PM PDT 24 12561511 ps
T107 /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.1130283757 Jun 29 04:52:11 PM PDT 24 Jun 29 04:52:28 PM PDT 24 1540547721 ps
T91 /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.3429645428 Jun 29 04:52:11 PM PDT 24 Jun 29 04:52:15 PM PDT 24 1383002139 ps
T811 /workspace/coverage/cover_reg_top/26.hmac_intr_test.3263736669 Jun 29 04:52:53 PM PDT 24 Jun 29 04:52:54 PM PDT 24 39661815 ps
T812 /workspace/coverage/cover_reg_top/7.hmac_intr_test.247537209 Jun 29 04:52:28 PM PDT 24 Jun 29 04:52:29 PM PDT 24 19369746 ps
T813 /workspace/coverage/cover_reg_top/18.hmac_csr_rw.1134803603 Jun 29 04:52:47 PM PDT 24 Jun 29 04:52:48 PM PDT 24 60063904 ps
T814 /workspace/coverage/cover_reg_top/3.hmac_intr_test.2138915096 Jun 29 04:52:10 PM PDT 24 Jun 29 04:52:11 PM PDT 24 48399172 ps
T118 /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.434956375 Jun 29 04:52:41 PM PDT 24 Jun 29 04:52:44 PM PDT 24 167022986 ps
T65 /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.1429840304 Jun 29 04:52:46 PM PDT 24 Jun 29 04:52:48 PM PDT 24 159999310 ps
T815 /workspace/coverage/cover_reg_top/35.hmac_intr_test.1340594082 Jun 29 04:52:47 PM PDT 24 Jun 29 04:52:48 PM PDT 24 73367017 ps
T816 /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.3394513487 Jun 29 04:52:05 PM PDT 24 Jun 29 04:52:06 PM PDT 24 60947536 ps
T98 /workspace/coverage/cover_reg_top/11.hmac_csr_rw.790782236 Jun 29 04:52:34 PM PDT 24 Jun 29 04:52:35 PM PDT 24 55386270 ps
T817 /workspace/coverage/cover_reg_top/47.hmac_intr_test.137878709 Jun 29 04:52:50 PM PDT 24 Jun 29 04:52:51 PM PDT 24 24326903 ps
T818 /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.2885816054 Jun 29 04:52:05 PM PDT 24 Jun 29 04:52:12 PM PDT 24 558423303 ps
T63 /workspace/coverage/cover_reg_top/17.hmac_tl_errors.630670112 Jun 29 04:52:42 PM PDT 24 Jun 29 04:52:45 PM PDT 24 191184137 ps
T819 /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.3355918407 Jun 29 04:52:10 PM PDT 24 Jun 29 04:52:12 PM PDT 24 145938833 ps
T61 /workspace/coverage/cover_reg_top/11.hmac_tl_errors.4134130351 Jun 29 04:52:33 PM PDT 24 Jun 29 04:52:38 PM PDT 24 78206084 ps
T820 /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.3454219126 Jun 29 04:52:27 PM PDT 24 Jun 29 04:52:28 PM PDT 24 19287478 ps
T136 /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.2635343624 Jun 29 04:52:41 PM PDT 24 Jun 29 04:52:45 PM PDT 24 302045070 ps
T99 /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.728089198 Jun 29 04:52:04 PM PDT 24 Jun 29 04:52:10 PM PDT 24 101761051 ps
T821 /workspace/coverage/cover_reg_top/19.hmac_intr_test.1995544111 Jun 29 04:52:50 PM PDT 24 Jun 29 04:52:51 PM PDT 24 40914293 ps
T69 /workspace/coverage/cover_reg_top/8.hmac_tl_errors.4294348187 Jun 29 04:52:25 PM PDT 24 Jun 29 04:52:26 PM PDT 24 62968447 ps
T68 /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.3667622477 Jun 29 04:52:45 PM PDT 24 Jun 29 04:52:48 PM PDT 24 251532833 ps
T822 /workspace/coverage/cover_reg_top/1.hmac_intr_test.1147568503 Jun 29 04:52:08 PM PDT 24 Jun 29 04:52:09 PM PDT 24 22324787 ps
T823 /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.1565129077 Jun 29 04:52:33 PM PDT 24 Jun 29 04:52:35 PM PDT 24 81709703 ps
T67 /workspace/coverage/cover_reg_top/15.hmac_tl_errors.219606939 Jun 29 04:52:41 PM PDT 24 Jun 29 04:52:45 PM PDT 24 2303876592 ps
T824 /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.1919229249 Jun 29 04:52:50 PM PDT 24 Jun 29 04:52:53 PM PDT 24 515267151 ps
T62 /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.3614060489 Jun 29 04:52:47 PM PDT 24 Jun 29 04:55:19 PM PDT 24 43171399340 ps
T70 /workspace/coverage/cover_reg_top/9.hmac_tl_errors.1895397303 Jun 29 04:52:28 PM PDT 24 Jun 29 04:52:30 PM PDT 24 137152684 ps
T825 /workspace/coverage/cover_reg_top/12.hmac_csr_rw.3981904705 Jun 29 04:52:32 PM PDT 24 Jun 29 04:52:33 PM PDT 24 37117219 ps
T826 /workspace/coverage/cover_reg_top/14.hmac_tl_errors.1538715910 Jun 29 04:52:40 PM PDT 24 Jun 29 04:52:43 PM PDT 24 215918871 ps
T827 /workspace/coverage/cover_reg_top/46.hmac_intr_test.1472625826 Jun 29 04:52:53 PM PDT 24 Jun 29 04:52:54 PM PDT 24 45173170 ps
T139 /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.730159064 Jun 29 04:52:14 PM PDT 24 Jun 29 04:52:16 PM PDT 24 178950387 ps
T828 /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.925710272 Jun 29 04:52:19 PM PDT 24 Jun 29 04:52:21 PM PDT 24 177506125 ps
T829 /workspace/coverage/cover_reg_top/3.hmac_tl_errors.2033507081 Jun 29 04:52:12 PM PDT 24 Jun 29 04:52:16 PM PDT 24 62862514 ps
T830 /workspace/coverage/cover_reg_top/16.hmac_intr_test.4001288504 Jun 29 04:52:42 PM PDT 24 Jun 29 04:52:44 PM PDT 24 32892421 ps
T831 /workspace/coverage/cover_reg_top/41.hmac_intr_test.1725857136 Jun 29 04:52:48 PM PDT 24 Jun 29 04:52:50 PM PDT 24 41279903 ps
T832 /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.3050166755 Jun 29 04:52:21 PM PDT 24 Jun 29 04:52:23 PM PDT 24 161668557 ps
T833 /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.745889146 Jun 29 04:52:50 PM PDT 24 Jun 29 04:52:52 PM PDT 24 44425951 ps
T834 /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.645141363 Jun 29 04:52:22 PM PDT 24 Jun 29 04:52:24 PM PDT 24 223029848 ps
T835 /workspace/coverage/cover_reg_top/49.hmac_intr_test.1163071388 Jun 29 04:52:57 PM PDT 24 Jun 29 04:52:59 PM PDT 24 103996505 ps
T836 /workspace/coverage/cover_reg_top/45.hmac_intr_test.2877063296 Jun 29 04:52:53 PM PDT 24 Jun 29 04:52:54 PM PDT 24 10716680 ps
T141 /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.1168268333 Jun 29 04:52:39 PM PDT 24 Jun 29 04:52:44 PM PDT 24 286895095 ps
T837 /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.1741585549 Jun 29 04:52:50 PM PDT 24 Jun 29 04:52:52 PM PDT 24 229046566 ps
T838 /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.1048033425 Jun 29 04:52:41 PM PDT 24 Jun 29 04:52:45 PM PDT 24 773620884 ps
T839 /workspace/coverage/cover_reg_top/13.hmac_intr_test.1918574635 Jun 29 04:52:44 PM PDT 24 Jun 29 04:52:45 PM PDT 24 19605411 ps
T840 /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.2672005537 Jun 29 04:52:05 PM PDT 24 Jun 29 04:52:08 PM PDT 24 611969921 ps
T841 /workspace/coverage/cover_reg_top/10.hmac_tl_errors.1962831157 Jun 29 04:52:26 PM PDT 24 Jun 29 04:52:29 PM PDT 24 92687517 ps
T842 /workspace/coverage/cover_reg_top/36.hmac_intr_test.3766386899 Jun 29 04:52:48 PM PDT 24 Jun 29 04:52:49 PM PDT 24 56392560 ps
T843 /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.1535478992 Jun 29 04:52:20 PM PDT 24 Jun 29 04:52:22 PM PDT 24 185782892 ps
T844 /workspace/coverage/cover_reg_top/7.hmac_csr_rw.113980906 Jun 29 04:52:25 PM PDT 24 Jun 29 04:52:26 PM PDT 24 149736381 ps
T845 /workspace/coverage/cover_reg_top/15.hmac_intr_test.2676338014 Jun 29 04:52:46 PM PDT 24 Jun 29 04:52:47 PM PDT 24 15467488 ps
T846 /workspace/coverage/cover_reg_top/9.hmac_csr_rw.1631145246 Jun 29 04:52:27 PM PDT 24 Jun 29 04:52:29 PM PDT 24 27247762 ps
T847 /workspace/coverage/cover_reg_top/18.hmac_tl_errors.3385471767 Jun 29 04:52:40 PM PDT 24 Jun 29 04:52:45 PM PDT 24 699875571 ps
T848 /workspace/coverage/cover_reg_top/25.hmac_intr_test.723382324 Jun 29 04:52:49 PM PDT 24 Jun 29 04:52:50 PM PDT 24 29644717 ps
T100 /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.803060838 Jun 29 04:52:11 PM PDT 24 Jun 29 04:52:15 PM PDT 24 60271725 ps
T101 /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.2492627657 Jun 29 04:52:12 PM PDT 24 Jun 29 04:52:23 PM PDT 24 210148404 ps
T849 /workspace/coverage/cover_reg_top/3.hmac_csr_rw.3730161057 Jun 29 04:52:13 PM PDT 24 Jun 29 04:52:14 PM PDT 24 30173397 ps
T850 /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.2452192903 Jun 29 04:52:34 PM PDT 24 Jun 29 04:52:37 PM PDT 24 34036595 ps
T851 /workspace/coverage/cover_reg_top/29.hmac_intr_test.1462596970 Jun 29 04:52:49 PM PDT 24 Jun 29 04:52:50 PM PDT 24 54820190 ps
T102 /workspace/coverage/cover_reg_top/15.hmac_csr_rw.249800997 Jun 29 04:52:44 PM PDT 24 Jun 29 04:52:46 PM PDT 24 15063141 ps
T852 /workspace/coverage/cover_reg_top/12.hmac_intr_test.2308551083 Jun 29 04:52:34 PM PDT 24 Jun 29 04:52:35 PM PDT 24 29838327 ps
T853 /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.3074898614 Jun 29 04:52:08 PM PDT 24 Jun 29 04:52:12 PM PDT 24 162934376 ps
T854 /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.718093436 Jun 29 04:52:26 PM PDT 24 Jun 29 04:52:29 PM PDT 24 42938243 ps
T855 /workspace/coverage/cover_reg_top/4.hmac_intr_test.20862732 Jun 29 04:52:11 PM PDT 24 Jun 29 04:52:12 PM PDT 24 44974755 ps
T856 /workspace/coverage/cover_reg_top/20.hmac_intr_test.3412793519 Jun 29 04:52:53 PM PDT 24 Jun 29 04:52:54 PM PDT 24 67142739 ps
T857 /workspace/coverage/cover_reg_top/17.hmac_intr_test.1804731245 Jun 29 04:52:41 PM PDT 24 Jun 29 04:52:42 PM PDT 24 13533566 ps
T858 /workspace/coverage/cover_reg_top/0.hmac_intr_test.3424522113 Jun 29 04:52:04 PM PDT 24 Jun 29 04:52:05 PM PDT 24 16476835 ps
T859 /workspace/coverage/cover_reg_top/5.hmac_intr_test.1789278811 Jun 29 04:52:20 PM PDT 24 Jun 29 04:52:21 PM PDT 24 52704920 ps
T860 /workspace/coverage/cover_reg_top/19.hmac_tl_errors.3211533364 Jun 29 04:52:50 PM PDT 24 Jun 29 04:52:53 PM PDT 24 50497500 ps
T103 /workspace/coverage/cover_reg_top/17.hmac_csr_rw.831165407 Jun 29 04:52:40 PM PDT 24 Jun 29 04:52:41 PM PDT 24 18281931 ps
T137 /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.3870474084 Jun 29 04:52:28 PM PDT 24 Jun 29 04:52:30 PM PDT 24 112513508 ps
T104 /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.1757645840 Jun 29 04:52:26 PM PDT 24 Jun 29 04:52:33 PM PDT 24 3304887498 ps
T861 /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.1371748041 Jun 29 04:52:26 PM PDT 24 Jun 29 04:52:28 PM PDT 24 190919284 ps
T862 /workspace/coverage/cover_reg_top/0.hmac_csr_rw.1464540161 Jun 29 04:52:04 PM PDT 24 Jun 29 04:52:05 PM PDT 24 52171282 ps
T863 /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.338754674 Jun 29 04:52:21 PM PDT 24 Jun 29 04:52:22 PM PDT 24 42854732 ps
T864 /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.405206093 Jun 29 04:52:08 PM PDT 24 Jun 29 04:52:11 PM PDT 24 203786766 ps
T865 /workspace/coverage/cover_reg_top/48.hmac_intr_test.4020335554 Jun 29 04:52:50 PM PDT 24 Jun 29 04:52:52 PM PDT 24 52161045 ps
T866 /workspace/coverage/cover_reg_top/40.hmac_intr_test.993961766 Jun 29 04:52:50 PM PDT 24 Jun 29 04:52:51 PM PDT 24 18985996 ps
T105 /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.2107814956 Jun 29 04:52:12 PM PDT 24 Jun 29 04:52:13 PM PDT 24 36873426 ps
T867 /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.1422046176 Jun 29 04:52:11 PM PDT 24 Jun 29 05:03:08 PM PDT 24 254888074344 ps
T868 /workspace/coverage/cover_reg_top/5.hmac_csr_rw.1517740638 Jun 29 04:52:19 PM PDT 24 Jun 29 04:52:20 PM PDT 24 24837696 ps
T869 /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.3826790193 Jun 29 04:52:41 PM PDT 24 Jun 29 04:52:44 PM PDT 24 62729887 ps
T870 /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.2130857831 Jun 29 04:52:19 PM PDT 24 Jun 29 04:52:22 PM PDT 24 164659217 ps
T871 /workspace/coverage/cover_reg_top/6.hmac_tl_errors.819364014 Jun 29 04:52:26 PM PDT 24 Jun 29 04:52:27 PM PDT 24 27850064 ps
T872 /workspace/coverage/cover_reg_top/4.hmac_tl_errors.661650802 Jun 29 04:52:11 PM PDT 24 Jun 29 04:52:15 PM PDT 24 266411448 ps
T873 /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.603934933 Jun 29 04:52:25 PM PDT 24 Jun 29 04:52:26 PM PDT 24 223836919 ps
T142 /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.1491534686 Jun 29 04:52:34 PM PDT 24 Jun 29 04:52:39 PM PDT 24 453976889 ps
T140 /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.1288444776 Jun 29 04:52:25 PM PDT 24 Jun 29 04:52:29 PM PDT 24 171110121 ps
T874 /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.710774500 Jun 29 04:52:26 PM PDT 24 Jun 29 04:52:30 PM PDT 24 46072572 ps
T875 /workspace/coverage/cover_reg_top/2.hmac_intr_test.694107501 Jun 29 04:52:13 PM PDT 24 Jun 29 04:52:15 PM PDT 24 54721072 ps
T876 /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.1526203772 Jun 29 04:52:34 PM PDT 24 Jun 29 04:52:37 PM PDT 24 57782328 ps
T877 /workspace/coverage/cover_reg_top/27.hmac_intr_test.3570581784 Jun 29 04:52:48 PM PDT 24 Jun 29 04:52:50 PM PDT 24 43127189 ps
T878 /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.3560176361 Jun 29 04:52:33 PM PDT 24 Jun 29 04:52:35 PM PDT 24 405846908 ps
T879 /workspace/coverage/cover_reg_top/6.hmac_intr_test.1420195490 Jun 29 04:52:21 PM PDT 24 Jun 29 04:52:22 PM PDT 24 43458335 ps
T880 /workspace/coverage/cover_reg_top/0.hmac_tl_errors.691451603 Jun 29 04:51:56 PM PDT 24 Jun 29 04:51:59 PM PDT 24 66481511 ps
T881 /workspace/coverage/cover_reg_top/43.hmac_intr_test.2375057651 Jun 29 04:52:50 PM PDT 24 Jun 29 04:52:51 PM PDT 24 15857242 ps
T882 /workspace/coverage/cover_reg_top/37.hmac_intr_test.3149445177 Jun 29 04:52:50 PM PDT 24 Jun 29 04:52:52 PM PDT 24 13075557 ps
T883 /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.1456089042 Jun 29 04:52:42 PM PDT 24 Jun 29 04:52:46 PM PDT 24 281320648 ps
T138 /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.385559875 Jun 29 04:52:34 PM PDT 24 Jun 29 04:52:38 PM PDT 24 431413750 ps
T884 /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.834309467 Jun 29 04:52:25 PM PDT 24 Jun 29 04:52:27 PM PDT 24 31649634 ps
T885 /workspace/coverage/cover_reg_top/31.hmac_intr_test.1543667822 Jun 29 04:52:51 PM PDT 24 Jun 29 04:52:52 PM PDT 24 18098311 ps
T886 /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.166851155 Jun 29 04:52:40 PM PDT 24 Jun 29 04:52:44 PM PDT 24 291270182 ps
T887 /workspace/coverage/cover_reg_top/13.hmac_tl_errors.2999559940 Jun 29 04:52:40 PM PDT 24 Jun 29 04:52:42 PM PDT 24 101548682 ps
T888 /workspace/coverage/cover_reg_top/34.hmac_intr_test.312584802 Jun 29 04:52:58 PM PDT 24 Jun 29 04:52:59 PM PDT 24 28340721 ps
T889 /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.508022260 Jun 29 04:52:11 PM PDT 24 Jun 29 04:52:14 PM PDT 24 164237230 ps
T890 /workspace/coverage/cover_reg_top/42.hmac_intr_test.2783100130 Jun 29 04:52:51 PM PDT 24 Jun 29 04:52:52 PM PDT 24 75686655 ps
T891 /workspace/coverage/cover_reg_top/38.hmac_intr_test.551528193 Jun 29 04:52:48 PM PDT 24 Jun 29 04:52:50 PM PDT 24 39927478 ps
T106 /workspace/coverage/cover_reg_top/19.hmac_csr_rw.2356504364 Jun 29 04:52:49 PM PDT 24 Jun 29 04:52:50 PM PDT 24 15949728 ps
T892 /workspace/coverage/cover_reg_top/2.hmac_csr_rw.654194619 Jun 29 04:52:10 PM PDT 24 Jun 29 04:52:12 PM PDT 24 24247054 ps
T893 /workspace/coverage/cover_reg_top/11.hmac_intr_test.460458164 Jun 29 04:52:33 PM PDT 24 Jun 29 04:52:34 PM PDT 24 25808142 ps
T894 /workspace/coverage/cover_reg_top/22.hmac_intr_test.1941979829 Jun 29 04:52:58 PM PDT 24 Jun 29 04:53:00 PM PDT 24 39382271 ps
T895 /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.485616153 Jun 29 04:52:25 PM PDT 24 Jun 29 04:52:27 PM PDT 24 77925816 ps
T896 /workspace/coverage/cover_reg_top/12.hmac_tl_errors.1031708813 Jun 29 04:52:35 PM PDT 24 Jun 29 04:52:39 PM PDT 24 181940973 ps
T897 /workspace/coverage/cover_reg_top/23.hmac_intr_test.2834175047 Jun 29 04:52:59 PM PDT 24 Jun 29 04:53:00 PM PDT 24 14583866 ps
T898 /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.591502963 Jun 29 04:52:12 PM PDT 24 Jun 29 04:52:13 PM PDT 24 51698782 ps
T899 /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.3769705712 Jun 29 04:52:05 PM PDT 24 Jun 29 04:52:07 PM PDT 24 143479016 ps
T900 /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.2136313056 Jun 29 04:52:49 PM PDT 24 Jun 29 04:52:51 PM PDT 24 28951561 ps
T901 /workspace/coverage/cover_reg_top/32.hmac_intr_test.948194883 Jun 29 04:52:50 PM PDT 24 Jun 29 04:52:52 PM PDT 24 38204036 ps
T109 /workspace/coverage/cover_reg_top/13.hmac_csr_rw.3530876902 Jun 29 04:52:40 PM PDT 24 Jun 29 04:52:41 PM PDT 24 82465524 ps
T902 /workspace/coverage/cover_reg_top/9.hmac_intr_test.2947062872 Jun 29 04:52:27 PM PDT 24 Jun 29 04:52:28 PM PDT 24 132642529 ps
T903 /workspace/coverage/cover_reg_top/10.hmac_csr_rw.1666349257 Jun 29 04:52:28 PM PDT 24 Jun 29 04:52:29 PM PDT 24 39398616 ps
T904 /workspace/coverage/cover_reg_top/1.hmac_tl_errors.170627427 Jun 29 04:52:04 PM PDT 24 Jun 29 04:52:08 PM PDT 24 69939971 ps
T108 /workspace/coverage/cover_reg_top/16.hmac_csr_rw.3926623253 Jun 29 04:52:42 PM PDT 24 Jun 29 04:52:44 PM PDT 24 53684568 ps
T110 /workspace/coverage/cover_reg_top/6.hmac_csr_rw.2296129618 Jun 29 04:52:25 PM PDT 24 Jun 29 04:52:27 PM PDT 24 17138630 ps
T905 /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.3563891430 Jun 29 04:52:20 PM PDT 24 Jun 29 04:52:24 PM PDT 24 206633680 ps
T906 /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.3000214927 Jun 29 04:52:26 PM PDT 24 Jun 29 04:52:29 PM PDT 24 298092801 ps
T907 /workspace/coverage/cover_reg_top/4.hmac_csr_rw.2359010938 Jun 29 04:52:18 PM PDT 24 Jun 29 04:52:19 PM PDT 24 70268090 ps
T908 /workspace/coverage/cover_reg_top/14.hmac_csr_rw.3161582109 Jun 29 04:52:40 PM PDT 24 Jun 29 04:52:41 PM PDT 24 33883476 ps
T909 /workspace/coverage/cover_reg_top/14.hmac_intr_test.339126368 Jun 29 04:52:40 PM PDT 24 Jun 29 04:52:41 PM PDT 24 12159862 ps
T910 /workspace/coverage/cover_reg_top/1.hmac_csr_rw.782036756 Jun 29 04:52:06 PM PDT 24 Jun 29 04:52:07 PM PDT 24 65248809 ps
T911 /workspace/coverage/cover_reg_top/39.hmac_intr_test.2535719686 Jun 29 04:52:59 PM PDT 24 Jun 29 04:53:01 PM PDT 24 27655250 ps
T912 /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.905352490 Jun 29 04:52:05 PM PDT 24 Jun 29 04:52:09 PM PDT 24 344227301 ps
T913 /workspace/coverage/cover_reg_top/33.hmac_intr_test.3522711915 Jun 29 04:52:48 PM PDT 24 Jun 29 04:52:50 PM PDT 24 12488282 ps
T914 /workspace/coverage/cover_reg_top/18.hmac_intr_test.3335785997 Jun 29 04:52:40 PM PDT 24 Jun 29 04:52:41 PM PDT 24 18235515 ps

Test location /workspace/coverage/default/48.hmac_smoke.1634384533
Short name T1
Test name
Test status
Simulation time 208964525 ps
CPU time 9.39 seconds
Started Jun 29 05:12:11 PM PDT 24
Finished Jun 29 05:12:21 PM PDT 24
Peak memory 200252 kb
Host smart-7453e54f-5aba-4c42-8f72-4de0cf701ecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634384533 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_smoke.1634384533
Directory /workspace/48.hmac_smoke/latest

Test location /workspace/coverage/default/0.hmac_burst_wr.3773456356
Short name T14
Test name
Test status
Simulation time 4854312580 ps
CPU time 28.74 seconds
Started Jun 29 05:08:08 PM PDT 24
Finished Jun 29 05:08:37 PM PDT 24
Peak memory 208420 kb
Host smart-58d065f3-300c-4430-94f5-f037548af798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3773456356 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_burst_wr.3773456356
Directory /workspace/0.hmac_burst_wr/latest

Test location /workspace/coverage/default/11.hmac_stress_all.3042095133
Short name T9
Test name
Test status
Simulation time 34160196983 ps
CPU time 2030.45 seconds
Started Jun 29 05:08:54 PM PDT 24
Finished Jun 29 05:42:45 PM PDT 24
Peak memory 216728 kb
Host smart-67d57f10-e84e-4f55-ae51-d2ce136e373f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042095133 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.hmac_stress_all.3042095133
Directory /workspace/11.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.36277139
Short name T39
Test name
Test status
Simulation time 195861427532 ps
CPU time 507.93 seconds
Started Jun 29 04:52:08 PM PDT 24
Finished Jun 29 05:00:37 PM PDT 24
Peak memory 216404 kb
Host smart-a8a7d6f7-bd26-49e4-a461-afdb16771d4c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36277139 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.hmac_csr_mem_rw_with_rand_reset.36277139
Directory /workspace/0.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.1577590617
Short name T40
Test name
Test status
Simulation time 232699180 ps
CPU time 4.35 seconds
Started Jun 29 04:52:43 PM PDT 24
Finished Jun 29 04:52:48 PM PDT 24
Peak memory 199844 kb
Host smart-bb9f7b86-3218-4a6b-ad59-6f24929c82cb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577590617 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_intg_err.1577590617
Directory /workspace/14.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/26.hmac_stress_all.342760814
Short name T119
Test name
Test status
Simulation time 605266226199 ps
CPU time 4260.98 seconds
Started Jun 29 05:10:11 PM PDT 24
Finished Jun 29 06:21:13 PM PDT 24
Peak memory 752944 kb
Host smart-cf7cbb2c-cc62-4ca8-b81b-fb4719e6fe4b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342760814 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 26.hmac_stress_all.342760814
Directory /workspace/26.hmac_stress_all/latest

Test location /workspace/coverage/default/16.hmac_alert_test.2549979828
Short name T259
Test name
Test status
Simulation time 54658890 ps
CPU time 0.62 seconds
Started Jun 29 05:09:12 PM PDT 24
Finished Jun 29 05:09:13 PM PDT 24
Peak memory 196320 kb
Host smart-03e95bcc-b34f-49e9-af32-f228d4360c07
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549979828 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_alert_test.2549979828
Directory /workspace/16.hmac_alert_test/latest

Test location /workspace/coverage/default/34.hmac_test_sha512_vectors.1907835249
Short name T26
Test name
Test status
Simulation time 413479347596 ps
CPU time 1999.17 seconds
Started Jun 29 05:10:52 PM PDT 24
Finished Jun 29 05:44:12 PM PDT 24
Peak memory 215856 kb
Host smart-64f3d67a-5bc2-436f-b479-c4be548b8ec4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1907835249 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_test_sha512_vectors.1907835249
Directory /workspace/34.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.728089198
Short name T99
Test name
Test status
Simulation time 101761051 ps
CPU time 5.28 seconds
Started Jun 29 04:52:04 PM PDT 24
Finished Jun 29 04:52:10 PM PDT 24
Peak memory 199728 kb
Host smart-f19517b4-7dc1-4101-aa8f-d69fe9df8335
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728089198 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_aliasing.728089198
Directory /workspace/1.hmac_csr_aliasing/latest

Test location /workspace/coverage/default/28.hmac_stress_all.2914058689
Short name T74
Test name
Test status
Simulation time 232086181054 ps
CPU time 4551.9 seconds
Started Jun 29 05:10:26 PM PDT 24
Finished Jun 29 06:26:19 PM PDT 24
Peak memory 790280 kb
Host smart-2f894211-0d7f-48d0-8e11-c530a882294c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914058689 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.hmac_stress_all.2914058689
Directory /workspace/28.hmac_stress_all/latest

Test location /workspace/coverage/default/0.hmac_sec_cm.551533506
Short name T46
Test name
Test status
Simulation time 65362443 ps
CPU time 0.97 seconds
Started Jun 29 05:08:07 PM PDT 24
Finished Jun 29 05:08:08 PM PDT 24
Peak memory 218832 kb
Host smart-6ead8e05-6d47-4d53-92aa-e1d40e533cde
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551533506 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_sec_cm.551533506
Directory /workspace/0.hmac_sec_cm/latest

Test location /workspace/coverage/default/19.hmac_back_pressure.3521557303
Short name T8
Test name
Test status
Simulation time 4302593018 ps
CPU time 47.74 seconds
Started Jun 29 05:09:30 PM PDT 24
Finished Jun 29 05:10:18 PM PDT 24
Peak memory 200340 kb
Host smart-3494b579-30f2-49f3-a911-178c4ac666fc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3521557303 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_back_pressure.3521557303
Directory /workspace/19.hmac_back_pressure/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.385559875
Short name T138
Test name
Test status
Simulation time 431413750 ps
CPU time 4.21 seconds
Started Jun 29 04:52:34 PM PDT 24
Finished Jun 29 04:52:38 PM PDT 24
Peak memory 199908 kb
Host smart-6b93e643-6645-439a-a3f6-5a38587f1593
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385559875 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_intg_err.385559875
Directory /workspace/11.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.813377989
Short name T59
Test name
Test status
Simulation time 84803206 ps
CPU time 2.86 seconds
Started Jun 29 04:52:39 PM PDT 24
Finished Jun 29 04:52:42 PM PDT 24
Peak memory 199844 kb
Host smart-f840d00f-b1da-4d92-8926-b29a5be392b2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813377989 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_intg_err.813377989
Directory /workspace/13.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/1.hmac_datapath_stress.241271583
Short name T578
Test name
Test status
Simulation time 14828880396 ps
CPU time 806.65 seconds
Started Jun 29 05:08:08 PM PDT 24
Finished Jun 29 05:21:36 PM PDT 24
Peak memory 666296 kb
Host smart-8297acbe-021b-47cb-8b70-430152a2e82c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=241271583 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_datapath_stress.241271583
Directory /workspace/1.hmac_datapath_stress/latest

Test location /workspace/coverage/default/10.hmac_long_msg.464415350
Short name T126
Test name
Test status
Simulation time 2211514254 ps
CPU time 126.08 seconds
Started Jun 29 05:08:47 PM PDT 24
Finished Jun 29 05:10:54 PM PDT 24
Peak memory 200336 kb
Host smart-d5697c75-0546-4793-8452-b15813cef50c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464415350 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_long_msg.464415350
Directory /workspace/10.hmac_long_msg/latest

Test location /workspace/coverage/default/13.hmac_back_pressure.924135832
Short name T462
Test name
Test status
Simulation time 908214585 ps
CPU time 42.73 seconds
Started Jun 29 05:08:57 PM PDT 24
Finished Jun 29 05:09:40 PM PDT 24
Peak memory 200288 kb
Host smart-3bcc6ea0-d9d5-4da2-acc4-f01bd2d35649
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=924135832 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_back_pressure.924135832
Directory /workspace/13.hmac_back_pressure/latest

Test location /workspace/coverage/default/14.hmac_stress_all.490244564
Short name T132
Test name
Test status
Simulation time 160173196171 ps
CPU time 3692.05 seconds
Started Jun 29 05:09:05 PM PDT 24
Finished Jun 29 06:10:38 PM PDT 24
Peak memory 747644 kb
Host smart-1f883d1c-56ef-49cb-ba44-5ae903a66e4f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490244564 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 14.hmac_stress_all.490244564
Directory /workspace/14.hmac_stress_all/latest

Test location /workspace/coverage/default/27.hmac_stress_all.3032464181
Short name T131
Test name
Test status
Simulation time 84880281864 ps
CPU time 5955.87 seconds
Started Jun 29 05:10:30 PM PDT 24
Finished Jun 29 06:49:47 PM PDT 24
Peak memory 761396 kb
Host smart-c51ae466-6d51-43d0-8307-d6c025ab7fdd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032464181 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.hmac_stress_all.3032464181
Directory /workspace/27.hmac_stress_all/latest

Test location /workspace/coverage/default/29.hmac_stress_all.3475880726
Short name T129
Test name
Test status
Simulation time 293759245491 ps
CPU time 2168.02 seconds
Started Jun 29 05:10:28 PM PDT 24
Finished Jun 29 05:46:36 PM PDT 24
Peak memory 216676 kb
Host smart-614cbf17-177d-4ce5-a88d-4277af568023
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475880726 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.hmac_stress_all.3475880726
Directory /workspace/29.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.3232087023
Short name T113
Test name
Test status
Simulation time 161983722 ps
CPU time 2.26 seconds
Started Jun 29 04:52:34 PM PDT 24
Finished Jun 29 04:52:37 PM PDT 24
Peak memory 199824 kb
Host smart-0539ab58-9341-4a66-90de-13a5eacf5bc4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232087023 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_same_cs
r_outstanding.3232087023
Directory /workspace/11.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.1288444776
Short name T140
Test name
Test status
Simulation time 171110121 ps
CPU time 3.05 seconds
Started Jun 29 04:52:25 PM PDT 24
Finished Jun 29 04:52:29 PM PDT 24
Peak memory 199864 kb
Host smart-645059e1-c70d-4d64-9e0b-0bd33f4a66c5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288444776 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_intg_err.1288444776
Directory /workspace/9.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/2.hmac_long_msg.997560725
Short name T240
Test name
Test status
Simulation time 7375288038 ps
CPU time 51.12 seconds
Started Jun 29 05:08:12 PM PDT 24
Finished Jun 29 05:09:04 PM PDT 24
Peak memory 200404 kb
Host smart-427cc95b-f660-49f7-9c1d-daf508868a04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997560725 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_long_msg.997560725
Directory /workspace/2.hmac_long_msg/latest

Test location /workspace/coverage/default/3.hmac_long_msg.528073749
Short name T84
Test name
Test status
Simulation time 69639775603 ps
CPU time 123.43 seconds
Started Jun 29 05:08:11 PM PDT 24
Finished Jun 29 05:10:15 PM PDT 24
Peak memory 200364 kb
Host smart-bee9b54a-1393-4a0d-aaa4-269b8468acc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528073749 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_long_msg.528073749
Directory /workspace/3.hmac_long_msg/latest

Test location /workspace/coverage/default/37.hmac_stress_all.2715300643
Short name T130
Test name
Test status
Simulation time 283862217344 ps
CPU time 1607.41 seconds
Started Jun 29 05:11:10 PM PDT 24
Finished Jun 29 05:37:57 PM PDT 24
Peak memory 755440 kb
Host smart-5f406217-dffa-4cb4-a021-1a1e3e97ce20
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715300643 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.hmac_stress_all.2715300643
Directory /workspace/37.hmac_stress_all/latest

Test location /workspace/coverage/default/4.hmac_wipe_secret.1873039243
Short name T127
Test name
Test status
Simulation time 1997116336 ps
CPU time 76.4 seconds
Started Jun 29 05:08:22 PM PDT 24
Finished Jun 29 05:09:39 PM PDT 24
Peak memory 200284 kb
Host smart-e54de86d-ca2c-476c-8525-2a2738ac0566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873039243 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_wipe_secret.1873039243
Directory /workspace/4.hmac_wipe_secret/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.2317500729
Short name T805
Test name
Test status
Simulation time 225175784 ps
CPU time 2.9 seconds
Started Jun 29 04:52:06 PM PDT 24
Finished Jun 29 04:52:09 PM PDT 24
Peak memory 198468 kb
Host smart-62490115-c958-442d-9b9f-93b54c061bcb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317500729 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_aliasing.2317500729
Directory /workspace/0.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.617854350
Short name T809
Test name
Test status
Simulation time 1989896009 ps
CPU time 16.06 seconds
Started Jun 29 04:52:08 PM PDT 24
Finished Jun 29 04:52:24 PM PDT 24
Peak memory 199648 kb
Host smart-5eb2b1fe-40aa-4ba6-a694-266cb4fe6985
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617854350 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_bit_bash.617854350
Directory /workspace/0.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.3394513487
Short name T816
Test name
Test status
Simulation time 60947536 ps
CPU time 0.96 seconds
Started Jun 29 04:52:05 PM PDT 24
Finished Jun 29 04:52:06 PM PDT 24
Peak memory 199540 kb
Host smart-f0f15cfe-311d-4d8b-bb10-75e3d212a2ca
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394513487 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_hw_reset.3394513487
Directory /workspace/0.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_rw.1464540161
Short name T862
Test name
Test status
Simulation time 52171282 ps
CPU time 0.66 seconds
Started Jun 29 04:52:04 PM PDT 24
Finished Jun 29 04:52:05 PM PDT 24
Peak memory 197424 kb
Host smart-350aa173-dbcb-46fd-a69b-60d69b6c52ce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464540161 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_rw.1464540161
Directory /workspace/0.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_intr_test.3424522113
Short name T858
Test name
Test status
Simulation time 16476835 ps
CPU time 0.63 seconds
Started Jun 29 04:52:04 PM PDT 24
Finished Jun 29 04:52:05 PM PDT 24
Peak memory 194508 kb
Host smart-6b4f949f-7284-488e-acc5-3757dd26c513
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424522113 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_intr_test.3424522113
Directory /workspace/0.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.3769705712
Short name T899
Test name
Test status
Simulation time 143479016 ps
CPU time 2.3 seconds
Started Jun 29 04:52:05 PM PDT 24
Finished Jun 29 04:52:07 PM PDT 24
Peak memory 199832 kb
Host smart-f79fc6b6-c171-4e0a-b86f-f00ace0dc30b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769705712 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_same_csr
_outstanding.3769705712
Directory /workspace/0.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_errors.691451603
Short name T880
Test name
Test status
Simulation time 66481511 ps
CPU time 1.87 seconds
Started Jun 29 04:51:56 PM PDT 24
Finished Jun 29 04:51:59 PM PDT 24
Peak memory 199688 kb
Host smart-534432f2-9bb7-46de-ba00-55a7b7834266
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691451603 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_errors.691451603
Directory /workspace/0.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.3074898614
Short name T853
Test name
Test status
Simulation time 162934376 ps
CPU time 3.06 seconds
Started Jun 29 04:52:08 PM PDT 24
Finished Jun 29 04:52:12 PM PDT 24
Peak memory 199848 kb
Host smart-2af8a376-d82e-4646-8614-fe4d9d8b672d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074898614 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_intg_err.3074898614
Directory /workspace/0.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.2885816054
Short name T818
Test name
Test status
Simulation time 558423303 ps
CPU time 6.2 seconds
Started Jun 29 04:52:05 PM PDT 24
Finished Jun 29 04:52:12 PM PDT 24
Peak memory 199672 kb
Host smart-e93787c0-b9e2-4717-960d-f30f6e9ac6bf
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885816054 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_bit_bash.2885816054
Directory /workspace/1.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.172261066
Short name T77
Test name
Test status
Simulation time 29281623 ps
CPU time 0.88 seconds
Started Jun 29 04:52:04 PM PDT 24
Finished Jun 29 04:52:05 PM PDT 24
Peak memory 199104 kb
Host smart-5881c425-7357-4354-8641-3797a8926ac8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172261066 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_hw_reset.172261066
Directory /workspace/1.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.2672005537
Short name T840
Test name
Test status
Simulation time 611969921 ps
CPU time 2.91 seconds
Started Jun 29 04:52:05 PM PDT 24
Finished Jun 29 04:52:08 PM PDT 24
Peak memory 215328 kb
Host smart-fc2aae27-58d6-4080-834d-916d50754e0c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672005537 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.hmac_csr_mem_rw_with_rand_reset.2672005537
Directory /workspace/1.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_rw.782036756
Short name T910
Test name
Test status
Simulation time 65248809 ps
CPU time 0.69 seconds
Started Jun 29 04:52:06 PM PDT 24
Finished Jun 29 04:52:07 PM PDT 24
Peak memory 197492 kb
Host smart-7f287329-30d9-4e64-a35d-c960734a8470
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782036756 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_rw.782036756
Directory /workspace/1.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_intr_test.1147568503
Short name T822
Test name
Test status
Simulation time 22324787 ps
CPU time 0.61 seconds
Started Jun 29 04:52:08 PM PDT 24
Finished Jun 29 04:52:09 PM PDT 24
Peak memory 194704 kb
Host smart-330a5128-3c03-4ebd-8622-6057488ac25e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147568503 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_intr_test.1147568503
Directory /workspace/1.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.405206093
Short name T864
Test name
Test status
Simulation time 203786766 ps
CPU time 1.9 seconds
Started Jun 29 04:52:08 PM PDT 24
Finished Jun 29 04:52:11 PM PDT 24
Peak memory 199872 kb
Host smart-7d82890b-43e6-4ac0-a954-323ecc8fe749
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405206093 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_same_csr_
outstanding.405206093
Directory /workspace/1.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_errors.170627427
Short name T904
Test name
Test status
Simulation time 69939971 ps
CPU time 3.53 seconds
Started Jun 29 04:52:04 PM PDT 24
Finished Jun 29 04:52:08 PM PDT 24
Peak memory 199768 kb
Host smart-b552b557-fbcc-4108-8217-032fe33d95f2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170627427 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_errors.170627427
Directory /workspace/1.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.905352490
Short name T912
Test name
Test status
Simulation time 344227301 ps
CPU time 4.04 seconds
Started Jun 29 04:52:05 PM PDT 24
Finished Jun 29 04:52:09 PM PDT 24
Peak memory 199840 kb
Host smart-e9f3d7de-36dd-474d-a799-2990e555e5a6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905352490 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_intg_err.905352490
Directory /workspace/1.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.2452192903
Short name T850
Test name
Test status
Simulation time 34036595 ps
CPU time 2.04 seconds
Started Jun 29 04:52:34 PM PDT 24
Finished Jun 29 04:52:37 PM PDT 24
Peak memory 199956 kb
Host smart-5225c212-f443-404b-aa88-81fc2b410d2d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452192903 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.hmac_csr_mem_rw_with_rand_reset.2452192903
Directory /workspace/10.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_rw.1666349257
Short name T903
Test name
Test status
Simulation time 39398616 ps
CPU time 0.68 seconds
Started Jun 29 04:52:28 PM PDT 24
Finished Jun 29 04:52:29 PM PDT 24
Peak memory 197140 kb
Host smart-97876c4e-f69e-490c-8aed-8e65ed5fa990
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666349257 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_rw.1666349257
Directory /workspace/10.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_intr_test.2624310041
Short name T808
Test name
Test status
Simulation time 46126857 ps
CPU time 0.62 seconds
Started Jun 29 04:52:28 PM PDT 24
Finished Jun 29 04:52:30 PM PDT 24
Peak memory 194572 kb
Host smart-24ed7d11-8dd3-4f6d-9bf9-f50c906abf8d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624310041 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_intr_test.2624310041
Directory /workspace/10.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.3560176361
Short name T878
Test name
Test status
Simulation time 405846908 ps
CPU time 1.76 seconds
Started Jun 29 04:52:33 PM PDT 24
Finished Jun 29 04:52:35 PM PDT 24
Peak memory 199740 kb
Host smart-bce0f328-f6bf-4f15-bef3-f783cf39c6ca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560176361 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_same_cs
r_outstanding.3560176361
Directory /workspace/10.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_errors.1962831157
Short name T841
Test name
Test status
Simulation time 92687517 ps
CPU time 2.1 seconds
Started Jun 29 04:52:26 PM PDT 24
Finished Jun 29 04:52:29 PM PDT 24
Peak memory 199768 kb
Host smart-d16c91ac-b991-42dc-be87-7dae0ee76cc8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962831157 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_errors.1962831157
Directory /workspace/10.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.3870474084
Short name T137
Test name
Test status
Simulation time 112513508 ps
CPU time 1.78 seconds
Started Jun 29 04:52:28 PM PDT 24
Finished Jun 29 04:52:30 PM PDT 24
Peak memory 199768 kb
Host smart-b3324a28-ca91-4c9f-814b-c13aa6dfb082
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870474084 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_intg_err.3870474084
Directory /workspace/10.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.1526203772
Short name T876
Test name
Test status
Simulation time 57782328 ps
CPU time 1.76 seconds
Started Jun 29 04:52:34 PM PDT 24
Finished Jun 29 04:52:37 PM PDT 24
Peak memory 199892 kb
Host smart-e3c6915d-b745-4b93-a711-aaa29d45e495
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526203772 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.hmac_csr_mem_rw_with_rand_reset.1526203772
Directory /workspace/11.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_rw.790782236
Short name T98
Test name
Test status
Simulation time 55386270 ps
CPU time 0.81 seconds
Started Jun 29 04:52:34 PM PDT 24
Finished Jun 29 04:52:35 PM PDT 24
Peak memory 198984 kb
Host smart-bd242b73-ee40-440c-a670-f16abb7474d9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790782236 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_rw.790782236
Directory /workspace/11.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_intr_test.460458164
Short name T893
Test name
Test status
Simulation time 25808142 ps
CPU time 0.59 seconds
Started Jun 29 04:52:33 PM PDT 24
Finished Jun 29 04:52:34 PM PDT 24
Peak memory 194616 kb
Host smart-79e9db10-137a-4fe5-9796-3f60efa0e3de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460458164 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_intr_test.460458164
Directory /workspace/11.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_errors.4134130351
Short name T61
Test name
Test status
Simulation time 78206084 ps
CPU time 3.96 seconds
Started Jun 29 04:52:33 PM PDT 24
Finished Jun 29 04:52:38 PM PDT 24
Peak memory 199756 kb
Host smart-292075bf-a0b2-42e0-a51f-3c2e209169ff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134130351 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_errors.4134130351
Directory /workspace/11.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.3826790193
Short name T869
Test name
Test status
Simulation time 62729887 ps
CPU time 2.04 seconds
Started Jun 29 04:52:41 PM PDT 24
Finished Jun 29 04:52:44 PM PDT 24
Peak memory 199896 kb
Host smart-9690dd23-30d2-4db4-8ed9-1353f445cc02
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826790193 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.hmac_csr_mem_rw_with_rand_reset.3826790193
Directory /workspace/12.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_rw.3981904705
Short name T825
Test name
Test status
Simulation time 37117219 ps
CPU time 0.75 seconds
Started Jun 29 04:52:32 PM PDT 24
Finished Jun 29 04:52:33 PM PDT 24
Peak memory 197228 kb
Host smart-8de231ef-016d-42f0-b2e2-1c9da42f0784
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981904705 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_rw.3981904705
Directory /workspace/12.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_intr_test.2308551083
Short name T852
Test name
Test status
Simulation time 29838327 ps
CPU time 0.61 seconds
Started Jun 29 04:52:34 PM PDT 24
Finished Jun 29 04:52:35 PM PDT 24
Peak memory 194684 kb
Host smart-8c15dca6-53a4-43a0-9ae6-82220da0542e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308551083 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_intr_test.2308551083
Directory /workspace/12.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.1565129077
Short name T823
Test name
Test status
Simulation time 81709703 ps
CPU time 1.71 seconds
Started Jun 29 04:52:33 PM PDT 24
Finished Jun 29 04:52:35 PM PDT 24
Peak memory 199804 kb
Host smart-25496b45-1ed4-410d-b6b3-2243a1b6e068
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565129077 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_same_cs
r_outstanding.1565129077
Directory /workspace/12.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_errors.1031708813
Short name T896
Test name
Test status
Simulation time 181940973 ps
CPU time 3.51 seconds
Started Jun 29 04:52:35 PM PDT 24
Finished Jun 29 04:52:39 PM PDT 24
Peak memory 199820 kb
Host smart-51f92ba0-e47b-44fb-ab57-ce0cc7a9a9fd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031708813 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_errors.1031708813
Directory /workspace/12.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.1491534686
Short name T142
Test name
Test status
Simulation time 453976889 ps
CPU time 4.28 seconds
Started Jun 29 04:52:34 PM PDT 24
Finished Jun 29 04:52:39 PM PDT 24
Peak memory 199900 kb
Host smart-e63b7b3e-8e42-4f95-8720-3eced0fac473
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491534686 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_intg_err.1491534686
Directory /workspace/12.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.783089602
Short name T72
Test name
Test status
Simulation time 54189809 ps
CPU time 1.65 seconds
Started Jun 29 04:52:45 PM PDT 24
Finished Jun 29 04:52:47 PM PDT 24
Peak memory 199968 kb
Host smart-3a5bb40d-e0ef-4e23-933e-c496827fe2f6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783089602 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.hmac_csr_mem_rw_with_rand_reset.783089602
Directory /workspace/13.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_rw.3530876902
Short name T109
Test name
Test status
Simulation time 82465524 ps
CPU time 0.81 seconds
Started Jun 29 04:52:40 PM PDT 24
Finished Jun 29 04:52:41 PM PDT 24
Peak memory 199540 kb
Host smart-40af95d1-2d5d-4555-82b9-36c9a66a802a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530876902 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_rw.3530876902
Directory /workspace/13.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_intr_test.1918574635
Short name T839
Test name
Test status
Simulation time 19605411 ps
CPU time 0.62 seconds
Started Jun 29 04:52:44 PM PDT 24
Finished Jun 29 04:52:45 PM PDT 24
Peak memory 194644 kb
Host smart-01ee24f0-265a-424c-b230-07b79f972e63
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918574635 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_intr_test.1918574635
Directory /workspace/13.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.4094854737
Short name T80
Test name
Test status
Simulation time 213519799 ps
CPU time 1.16 seconds
Started Jun 29 04:52:39 PM PDT 24
Finished Jun 29 04:52:40 PM PDT 24
Peak memory 199828 kb
Host smart-56c8e5f8-5b4b-4191-8935-015391c018c8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094854737 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_same_cs
r_outstanding.4094854737
Directory /workspace/13.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_errors.2999559940
Short name T887
Test name
Test status
Simulation time 101548682 ps
CPU time 1.3 seconds
Started Jun 29 04:52:40 PM PDT 24
Finished Jun 29 04:52:42 PM PDT 24
Peak memory 199648 kb
Host smart-c9dbaff5-fb7c-4deb-92ae-127f6ace2a06
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999559940 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_errors.2999559940
Directory /workspace/13.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.1286894570
Short name T41
Test name
Test status
Simulation time 31613175 ps
CPU time 1.97 seconds
Started Jun 29 04:52:40 PM PDT 24
Finished Jun 29 04:52:43 PM PDT 24
Peak memory 199856 kb
Host smart-e44252cb-bb62-4328-9f97-249bf2d131d4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286894570 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.hmac_csr_mem_rw_with_rand_reset.1286894570
Directory /workspace/14.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_rw.3161582109
Short name T908
Test name
Test status
Simulation time 33883476 ps
CPU time 0.98 seconds
Started Jun 29 04:52:40 PM PDT 24
Finished Jun 29 04:52:41 PM PDT 24
Peak memory 199532 kb
Host smart-163ff407-1f22-4198-9b47-247d7882dd32
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161582109 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_rw.3161582109
Directory /workspace/14.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_intr_test.339126368
Short name T909
Test name
Test status
Simulation time 12159862 ps
CPU time 0.6 seconds
Started Jun 29 04:52:40 PM PDT 24
Finished Jun 29 04:52:41 PM PDT 24
Peak memory 194760 kb
Host smart-8ac91524-1bea-4d2e-a44b-08b0b63fbf1f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339126368 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_intr_test.339126368
Directory /workspace/14.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.930879127
Short name T114
Test name
Test status
Simulation time 116527174 ps
CPU time 2.33 seconds
Started Jun 29 04:52:41 PM PDT 24
Finished Jun 29 04:52:44 PM PDT 24
Peak memory 199176 kb
Host smart-1062dacd-9e07-475f-9bff-a171b4984a35
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930879127 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_same_csr
_outstanding.930879127
Directory /workspace/14.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_errors.1538715910
Short name T826
Test name
Test status
Simulation time 215918871 ps
CPU time 1.92 seconds
Started Jun 29 04:52:40 PM PDT 24
Finished Jun 29 04:52:43 PM PDT 24
Peak memory 199744 kb
Host smart-6dd5853f-86c5-4aa8-b055-5592ee40f746
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538715910 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_errors.1538715910
Directory /workspace/14.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.1456089042
Short name T883
Test name
Test status
Simulation time 281320648 ps
CPU time 2.8 seconds
Started Jun 29 04:52:42 PM PDT 24
Finished Jun 29 04:52:46 PM PDT 24
Peak memory 199892 kb
Host smart-0b745d77-e566-481b-bddd-1432924d24e7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456089042 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.hmac_csr_mem_rw_with_rand_reset.1456089042
Directory /workspace/15.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_rw.249800997
Short name T102
Test name
Test status
Simulation time 15063141 ps
CPU time 0.72 seconds
Started Jun 29 04:52:44 PM PDT 24
Finished Jun 29 04:52:46 PM PDT 24
Peak memory 197992 kb
Host smart-6b38fdac-caf4-4add-98b4-f8ed60044e7a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249800997 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_rw.249800997
Directory /workspace/15.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_intr_test.2676338014
Short name T845
Test name
Test status
Simulation time 15467488 ps
CPU time 0.59 seconds
Started Jun 29 04:52:46 PM PDT 24
Finished Jun 29 04:52:47 PM PDT 24
Peak memory 194628 kb
Host smart-f6e9c0f2-8af9-4672-a74e-29422f713c5d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676338014 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_intr_test.2676338014
Directory /workspace/15.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.4076264589
Short name T111
Test name
Test status
Simulation time 125417218 ps
CPU time 2.74 seconds
Started Jun 29 04:52:41 PM PDT 24
Finished Jun 29 04:52:45 PM PDT 24
Peak memory 199624 kb
Host smart-82584a72-55d4-4ef2-b044-5e37577db98a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076264589 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_same_cs
r_outstanding.4076264589
Directory /workspace/15.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_errors.219606939
Short name T67
Test name
Test status
Simulation time 2303876592 ps
CPU time 3.94 seconds
Started Jun 29 04:52:41 PM PDT 24
Finished Jun 29 04:52:45 PM PDT 24
Peak memory 199884 kb
Host smart-af15b07b-7310-48d5-b6c7-25270ea778ea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219606939 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_errors.219606939
Directory /workspace/15.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.1168268333
Short name T141
Test name
Test status
Simulation time 286895095 ps
CPU time 4.26 seconds
Started Jun 29 04:52:39 PM PDT 24
Finished Jun 29 04:52:44 PM PDT 24
Peak memory 199912 kb
Host smart-759510d9-84ad-4a5f-85fb-9024d0b97408
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168268333 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_intg_err.1168268333
Directory /workspace/15.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.3667622477
Short name T68
Test name
Test status
Simulation time 251532833 ps
CPU time 2.02 seconds
Started Jun 29 04:52:45 PM PDT 24
Finished Jun 29 04:52:48 PM PDT 24
Peak memory 199972 kb
Host smart-a7724c97-9519-48f1-8a41-bec56b2e734e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667622477 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.hmac_csr_mem_rw_with_rand_reset.3667622477
Directory /workspace/16.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_rw.3926623253
Short name T108
Test name
Test status
Simulation time 53684568 ps
CPU time 0.95 seconds
Started Jun 29 04:52:42 PM PDT 24
Finished Jun 29 04:52:44 PM PDT 24
Peak memory 199232 kb
Host smart-01526a5d-b434-4cf9-b712-90bb62dea5dc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926623253 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_rw.3926623253
Directory /workspace/16.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_intr_test.4001288504
Short name T830
Test name
Test status
Simulation time 32892421 ps
CPU time 0.6 seconds
Started Jun 29 04:52:42 PM PDT 24
Finished Jun 29 04:52:44 PM PDT 24
Peak memory 194624 kb
Host smart-943b39d6-4ee4-4917-9fa5-480e1e80767f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001288504 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_intr_test.4001288504
Directory /workspace/16.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.434956375
Short name T118
Test name
Test status
Simulation time 167022986 ps
CPU time 2.22 seconds
Started Jun 29 04:52:41 PM PDT 24
Finished Jun 29 04:52:44 PM PDT 24
Peak memory 199864 kb
Host smart-769032cd-8d03-4e4e-b9a4-eaa52aeaa8d1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434956375 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_same_csr
_outstanding.434956375
Directory /workspace/16.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_errors.700562330
Short name T66
Test name
Test status
Simulation time 157833598 ps
CPU time 1.43 seconds
Started Jun 29 04:52:42 PM PDT 24
Finished Jun 29 04:52:44 PM PDT 24
Peak memory 199816 kb
Host smart-377b0f50-a70b-46c3-8e79-1afb20f10c53
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700562330 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_errors.700562330
Directory /workspace/16.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.166851155
Short name T886
Test name
Test status
Simulation time 291270182 ps
CPU time 4.35 seconds
Started Jun 29 04:52:40 PM PDT 24
Finished Jun 29 04:52:44 PM PDT 24
Peak memory 199764 kb
Host smart-e5463240-17e7-41b6-9a77-467fca526bda
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166851155 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_intg_err.166851155
Directory /workspace/16.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.1429840304
Short name T65
Test name
Test status
Simulation time 159999310 ps
CPU time 2.24 seconds
Started Jun 29 04:52:46 PM PDT 24
Finished Jun 29 04:52:48 PM PDT 24
Peak memory 199904 kb
Host smart-ce3847f7-0fd3-4e58-8dfd-a1c33305ed28
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429840304 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.hmac_csr_mem_rw_with_rand_reset.1429840304
Directory /workspace/17.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_rw.831165407
Short name T103
Test name
Test status
Simulation time 18281931 ps
CPU time 0.72 seconds
Started Jun 29 04:52:40 PM PDT 24
Finished Jun 29 04:52:41 PM PDT 24
Peak memory 197920 kb
Host smart-92de8cda-49f2-4a77-b26a-791aca806d3a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831165407 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_rw.831165407
Directory /workspace/17.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_intr_test.1804731245
Short name T857
Test name
Test status
Simulation time 13533566 ps
CPU time 0.59 seconds
Started Jun 29 04:52:41 PM PDT 24
Finished Jun 29 04:52:42 PM PDT 24
Peak memory 194600 kb
Host smart-0deac857-b9f0-4e24-90df-e10d83dcf69a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804731245 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_intr_test.1804731245
Directory /workspace/17.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.2719316968
Short name T116
Test name
Test status
Simulation time 37036579 ps
CPU time 1.76 seconds
Started Jun 29 04:52:40 PM PDT 24
Finished Jun 29 04:52:43 PM PDT 24
Peak memory 199784 kb
Host smart-22436d09-ccf3-4a42-aa0d-847c7a82c475
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719316968 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_same_cs
r_outstanding.2719316968
Directory /workspace/17.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_errors.630670112
Short name T63
Test name
Test status
Simulation time 191184137 ps
CPU time 2.55 seconds
Started Jun 29 04:52:42 PM PDT 24
Finished Jun 29 04:52:45 PM PDT 24
Peak memory 199776 kb
Host smart-5a5bd8c9-fb64-4122-b820-941c7422be8e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630670112 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_errors.630670112
Directory /workspace/17.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.2635343624
Short name T136
Test name
Test status
Simulation time 302045070 ps
CPU time 3.17 seconds
Started Jun 29 04:52:41 PM PDT 24
Finished Jun 29 04:52:45 PM PDT 24
Peak memory 199900 kb
Host smart-ea88aa98-d89f-4565-8a98-29040e77735f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635343624 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_intg_err.2635343624
Directory /workspace/17.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.3614060489
Short name T62
Test name
Test status
Simulation time 43171399340 ps
CPU time 151.06 seconds
Started Jun 29 04:52:47 PM PDT 24
Finished Jun 29 04:55:19 PM PDT 24
Peak memory 216340 kb
Host smart-bfaee592-e78a-4a5e-95b4-ea09494217f5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614060489 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.hmac_csr_mem_rw_with_rand_reset.3614060489
Directory /workspace/18.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_rw.1134803603
Short name T813
Test name
Test status
Simulation time 60063904 ps
CPU time 0.68 seconds
Started Jun 29 04:52:47 PM PDT 24
Finished Jun 29 04:52:48 PM PDT 24
Peak memory 197680 kb
Host smart-ac46b528-50ca-4eba-a319-258f512753cf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134803603 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_rw.1134803603
Directory /workspace/18.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_intr_test.3335785997
Short name T914
Test name
Test status
Simulation time 18235515 ps
CPU time 0.58 seconds
Started Jun 29 04:52:40 PM PDT 24
Finished Jun 29 04:52:41 PM PDT 24
Peak memory 194728 kb
Host smart-945ef099-c76e-47f4-95ac-2234164faf9b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335785997 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_intr_test.3335785997
Directory /workspace/18.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.1741585549
Short name T837
Test name
Test status
Simulation time 229046566 ps
CPU time 1.23 seconds
Started Jun 29 04:52:50 PM PDT 24
Finished Jun 29 04:52:52 PM PDT 24
Peak memory 199848 kb
Host smart-e47ed6e5-268b-42c3-aa27-0fb2babd5aa8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741585549 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_same_cs
r_outstanding.1741585549
Directory /workspace/18.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_errors.3385471767
Short name T847
Test name
Test status
Simulation time 699875571 ps
CPU time 3.95 seconds
Started Jun 29 04:52:40 PM PDT 24
Finished Jun 29 04:52:45 PM PDT 24
Peak memory 199740 kb
Host smart-0788bd08-7478-4461-bc1e-9f309153dea2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385471767 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_errors.3385471767
Directory /workspace/18.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.1048033425
Short name T838
Test name
Test status
Simulation time 773620884 ps
CPU time 3.4 seconds
Started Jun 29 04:52:41 PM PDT 24
Finished Jun 29 04:52:45 PM PDT 24
Peak memory 199884 kb
Host smart-c6467855-b990-4d86-979b-aaa02e06e3c3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048033425 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_intg_err.1048033425
Directory /workspace/18.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.2136313056
Short name T900
Test name
Test status
Simulation time 28951561 ps
CPU time 1.74 seconds
Started Jun 29 04:52:49 PM PDT 24
Finished Jun 29 04:52:51 PM PDT 24
Peak memory 199892 kb
Host smart-e4e31592-c7cb-4bb0-9017-c60b34c7a250
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136313056 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.hmac_csr_mem_rw_with_rand_reset.2136313056
Directory /workspace/19.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_rw.2356504364
Short name T106
Test name
Test status
Simulation time 15949728 ps
CPU time 0.9 seconds
Started Jun 29 04:52:49 PM PDT 24
Finished Jun 29 04:52:50 PM PDT 24
Peak memory 199392 kb
Host smart-1b9e3785-ce21-4faa-914d-0e72e6cc10c0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356504364 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_rw.2356504364
Directory /workspace/19.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_intr_test.1995544111
Short name T821
Test name
Test status
Simulation time 40914293 ps
CPU time 0.58 seconds
Started Jun 29 04:52:50 PM PDT 24
Finished Jun 29 04:52:51 PM PDT 24
Peak memory 194632 kb
Host smart-2b895167-178b-4853-b088-88155b669c7d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995544111 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_intr_test.1995544111
Directory /workspace/19.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.745889146
Short name T833
Test name
Test status
Simulation time 44425951 ps
CPU time 1.13 seconds
Started Jun 29 04:52:50 PM PDT 24
Finished Jun 29 04:52:52 PM PDT 24
Peak memory 199816 kb
Host smart-6dbd6c44-1105-4523-8172-39adf5c0a232
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745889146 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_same_csr
_outstanding.745889146
Directory /workspace/19.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_errors.3211533364
Short name T860
Test name
Test status
Simulation time 50497500 ps
CPU time 1.39 seconds
Started Jun 29 04:52:50 PM PDT 24
Finished Jun 29 04:52:53 PM PDT 24
Peak memory 199772 kb
Host smart-553f2b7f-1343-4856-893e-b8f544c6a01b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211533364 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_errors.3211533364
Directory /workspace/19.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.1919229249
Short name T824
Test name
Test status
Simulation time 515267151 ps
CPU time 1.85 seconds
Started Jun 29 04:52:50 PM PDT 24
Finished Jun 29 04:52:53 PM PDT 24
Peak memory 199860 kb
Host smart-72fbec89-82b8-44ef-9544-8eb1e1e5b9f7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919229249 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_intg_err.1919229249
Directory /workspace/19.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.2712489342
Short name T97
Test name
Test status
Simulation time 59858690 ps
CPU time 3.17 seconds
Started Jun 29 04:52:14 PM PDT 24
Finished Jun 29 04:52:18 PM PDT 24
Peak memory 199504 kb
Host smart-a2899f96-e006-471b-9538-4137573ee1e6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712489342 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_aliasing.2712489342
Directory /workspace/2.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.2492627657
Short name T101
Test name
Test status
Simulation time 210148404 ps
CPU time 9.85 seconds
Started Jun 29 04:52:12 PM PDT 24
Finished Jun 29 04:52:23 PM PDT 24
Peak memory 198676 kb
Host smart-d2d32b49-a1cf-47e8-b0eb-e4d62481fcd9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492627657 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_bit_bash.2492627657
Directory /workspace/2.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.591502963
Short name T898
Test name
Test status
Simulation time 51698782 ps
CPU time 0.75 seconds
Started Jun 29 04:52:12 PM PDT 24
Finished Jun 29 04:52:13 PM PDT 24
Peak memory 197980 kb
Host smart-6d86bf5a-1edd-4f39-b5de-2c1f99cb9712
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591502963 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_hw_reset.591502963
Directory /workspace/2.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.1422046176
Short name T867
Test name
Test status
Simulation time 254888074344 ps
CPU time 656.89 seconds
Started Jun 29 04:52:11 PM PDT 24
Finished Jun 29 05:03:08 PM PDT 24
Peak memory 224388 kb
Host smart-17ea5237-41ad-43d0-a341-6808951b5cc6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422046176 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.hmac_csr_mem_rw_with_rand_reset.1422046176
Directory /workspace/2.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_rw.654194619
Short name T892
Test name
Test status
Simulation time 24247054 ps
CPU time 0.7 seconds
Started Jun 29 04:52:10 PM PDT 24
Finished Jun 29 04:52:12 PM PDT 24
Peak memory 197416 kb
Host smart-c773ddaa-8910-4e79-bf51-38e1035c2151
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654194619 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_rw.654194619
Directory /workspace/2.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_intr_test.694107501
Short name T875
Test name
Test status
Simulation time 54721072 ps
CPU time 0.63 seconds
Started Jun 29 04:52:13 PM PDT 24
Finished Jun 29 04:52:15 PM PDT 24
Peak memory 194864 kb
Host smart-5cfdd738-7398-4648-8e57-fcc57cf1cd5d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694107501 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_intr_test.694107501
Directory /workspace/2.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.249174284
Short name T112
Test name
Test status
Simulation time 1346929817 ps
CPU time 2.24 seconds
Started Jun 29 04:52:11 PM PDT 24
Finished Jun 29 04:52:14 PM PDT 24
Peak memory 199844 kb
Host smart-db1b8b10-895c-4866-8f02-1877c35c8670
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249174284 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_same_csr_
outstanding.249174284
Directory /workspace/2.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_errors.2216152718
Short name T58
Test name
Test status
Simulation time 196555583 ps
CPU time 2.8 seconds
Started Jun 29 04:52:11 PM PDT 24
Finished Jun 29 04:52:14 PM PDT 24
Peak memory 199720 kb
Host smart-58dbc6db-72b8-4b24-939d-785e7c509d5a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216152718 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_errors.2216152718
Directory /workspace/2.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.730159064
Short name T139
Test name
Test status
Simulation time 178950387 ps
CPU time 1.68 seconds
Started Jun 29 04:52:14 PM PDT 24
Finished Jun 29 04:52:16 PM PDT 24
Peak memory 199808 kb
Host smart-379f1fe8-cef0-42bc-bb26-2d57914dcdeb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730159064 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_intg_err.730159064
Directory /workspace/2.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.hmac_intr_test.3412793519
Short name T856
Test name
Test status
Simulation time 67142739 ps
CPU time 0.6 seconds
Started Jun 29 04:52:53 PM PDT 24
Finished Jun 29 04:52:54 PM PDT 24
Peak memory 194616 kb
Host smart-c32d2912-9dfe-4a5d-8d29-bf245d098f73
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412793519 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.hmac_intr_test.3412793519
Directory /workspace/20.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.hmac_intr_test.3154504138
Short name T78
Test name
Test status
Simulation time 35230247 ps
CPU time 0.58 seconds
Started Jun 29 04:52:51 PM PDT 24
Finished Jun 29 04:52:52 PM PDT 24
Peak memory 194644 kb
Host smart-9f217e46-27ac-413a-a73c-6d30a3ca9af0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154504138 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.hmac_intr_test.3154504138
Directory /workspace/21.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.hmac_intr_test.1941979829
Short name T894
Test name
Test status
Simulation time 39382271 ps
CPU time 0.58 seconds
Started Jun 29 04:52:58 PM PDT 24
Finished Jun 29 04:53:00 PM PDT 24
Peak memory 194580 kb
Host smart-9b4351ff-9502-4b3f-b3a7-54778c20e563
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941979829 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.hmac_intr_test.1941979829
Directory /workspace/22.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.hmac_intr_test.2834175047
Short name T897
Test name
Test status
Simulation time 14583866 ps
CPU time 0.59 seconds
Started Jun 29 04:52:59 PM PDT 24
Finished Jun 29 04:53:00 PM PDT 24
Peak memory 194464 kb
Host smart-f9d1b921-5899-43a3-9015-beb8024d70e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834175047 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.hmac_intr_test.2834175047
Directory /workspace/23.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.hmac_intr_test.1545681151
Short name T804
Test name
Test status
Simulation time 16958338 ps
CPU time 0.59 seconds
Started Jun 29 04:52:50 PM PDT 24
Finished Jun 29 04:52:51 PM PDT 24
Peak memory 194624 kb
Host smart-a6d5f659-decf-4cd4-8a64-78219532c548
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545681151 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.hmac_intr_test.1545681151
Directory /workspace/24.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.hmac_intr_test.723382324
Short name T848
Test name
Test status
Simulation time 29644717 ps
CPU time 0.64 seconds
Started Jun 29 04:52:49 PM PDT 24
Finished Jun 29 04:52:50 PM PDT 24
Peak memory 194624 kb
Host smart-19de7d53-f7b2-4945-b179-40cf2ff7b318
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723382324 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.hmac_intr_test.723382324
Directory /workspace/25.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.hmac_intr_test.3263736669
Short name T811
Test name
Test status
Simulation time 39661815 ps
CPU time 0.58 seconds
Started Jun 29 04:52:53 PM PDT 24
Finished Jun 29 04:52:54 PM PDT 24
Peak memory 194712 kb
Host smart-8ca97f29-ce94-4f9f-80ee-7883cc3a1e0d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263736669 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.hmac_intr_test.3263736669
Directory /workspace/26.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.hmac_intr_test.3570581784
Short name T877
Test name
Test status
Simulation time 43127189 ps
CPU time 0.66 seconds
Started Jun 29 04:52:48 PM PDT 24
Finished Jun 29 04:52:50 PM PDT 24
Peak memory 194716 kb
Host smart-00e840fa-4d30-4358-acb2-74fbf31f0ae2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570581784 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.hmac_intr_test.3570581784
Directory /workspace/27.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.hmac_intr_test.2730278858
Short name T803
Test name
Test status
Simulation time 24724885 ps
CPU time 0.62 seconds
Started Jun 29 04:52:51 PM PDT 24
Finished Jun 29 04:52:52 PM PDT 24
Peak memory 194788 kb
Host smart-08348649-4c82-47bb-b577-e19b778cec9b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730278858 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.hmac_intr_test.2730278858
Directory /workspace/28.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.hmac_intr_test.1462596970
Short name T851
Test name
Test status
Simulation time 54820190 ps
CPU time 0.63 seconds
Started Jun 29 04:52:49 PM PDT 24
Finished Jun 29 04:52:50 PM PDT 24
Peak memory 194632 kb
Host smart-5f2c163d-8f14-465f-82af-9a6f3c309cf5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462596970 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.hmac_intr_test.1462596970
Directory /workspace/29.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.803060838
Short name T100
Test name
Test status
Simulation time 60271725 ps
CPU time 3.12 seconds
Started Jun 29 04:52:11 PM PDT 24
Finished Jun 29 04:52:15 PM PDT 24
Peak memory 198728 kb
Host smart-8c81f59b-e8b8-43e1-ae69-393b5c524ce2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803060838 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_aliasing.803060838
Directory /workspace/3.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.1130283757
Short name T107
Test name
Test status
Simulation time 1540547721 ps
CPU time 16.01 seconds
Started Jun 29 04:52:11 PM PDT 24
Finished Jun 29 04:52:28 PM PDT 24
Peak memory 199708 kb
Host smart-571c3a62-6748-4044-8b4f-e4cd25db25c2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130283757 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_bit_bash.1130283757
Directory /workspace/3.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.3355918407
Short name T819
Test name
Test status
Simulation time 145938833 ps
CPU time 1 seconds
Started Jun 29 04:52:10 PM PDT 24
Finished Jun 29 04:52:12 PM PDT 24
Peak memory 199592 kb
Host smart-a2841046-6399-479e-9748-1f0d4d27bdd5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355918407 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_hw_reset.3355918407
Directory /workspace/3.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.508022260
Short name T889
Test name
Test status
Simulation time 164237230 ps
CPU time 1.18 seconds
Started Jun 29 04:52:11 PM PDT 24
Finished Jun 29 04:52:14 PM PDT 24
Peak memory 199644 kb
Host smart-24266921-9b10-478f-babe-2f1b650e34c2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508022260 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.hmac_csr_mem_rw_with_rand_reset.508022260
Directory /workspace/3.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_rw.3730161057
Short name T849
Test name
Test status
Simulation time 30173397 ps
CPU time 0.82 seconds
Started Jun 29 04:52:13 PM PDT 24
Finished Jun 29 04:52:14 PM PDT 24
Peak memory 198668 kb
Host smart-773cd1ed-5567-4a76-aae2-6daf4d19a468
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730161057 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_rw.3730161057
Directory /workspace/3.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_intr_test.2138915096
Short name T814
Test name
Test status
Simulation time 48399172 ps
CPU time 0.57 seconds
Started Jun 29 04:52:10 PM PDT 24
Finished Jun 29 04:52:11 PM PDT 24
Peak memory 194624 kb
Host smart-da71ac78-ef51-4b6e-a0ca-61329b80781d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138915096 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_intr_test.2138915096
Directory /workspace/3.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.1930274793
Short name T115
Test name
Test status
Simulation time 399401139 ps
CPU time 2.22 seconds
Started Jun 29 04:52:11 PM PDT 24
Finished Jun 29 04:52:14 PM PDT 24
Peak memory 199888 kb
Host smart-26dc1e3c-4352-4295-a9ab-bfcb9cbb9c8b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930274793 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_same_csr
_outstanding.1930274793
Directory /workspace/3.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_errors.2033507081
Short name T829
Test name
Test status
Simulation time 62862514 ps
CPU time 3.07 seconds
Started Jun 29 04:52:12 PM PDT 24
Finished Jun 29 04:52:16 PM PDT 24
Peak memory 199720 kb
Host smart-837ed76e-33b0-4eba-a8f2-e7c490e6aecc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033507081 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_errors.2033507081
Directory /workspace/3.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.3091109277
Short name T57
Test name
Test status
Simulation time 171048643 ps
CPU time 2.67 seconds
Started Jun 29 04:52:11 PM PDT 24
Finished Jun 29 04:52:15 PM PDT 24
Peak memory 199856 kb
Host smart-c3b5a9df-02b3-42ea-bb39-e19a21b75d08
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091109277 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_intg_err.3091109277
Directory /workspace/3.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.hmac_intr_test.1020433927
Short name T806
Test name
Test status
Simulation time 42124314 ps
CPU time 0.6 seconds
Started Jun 29 04:52:49 PM PDT 24
Finished Jun 29 04:52:50 PM PDT 24
Peak memory 194656 kb
Host smart-94e43d93-1534-44df-930d-6c5b362ee3e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020433927 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.hmac_intr_test.1020433927
Directory /workspace/30.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.hmac_intr_test.1543667822
Short name T885
Test name
Test status
Simulation time 18098311 ps
CPU time 0.59 seconds
Started Jun 29 04:52:51 PM PDT 24
Finished Jun 29 04:52:52 PM PDT 24
Peak memory 194596 kb
Host smart-235b1f6b-dfa5-4dfd-a49b-c46239fb692a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543667822 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.hmac_intr_test.1543667822
Directory /workspace/31.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.hmac_intr_test.948194883
Short name T901
Test name
Test status
Simulation time 38204036 ps
CPU time 0.61 seconds
Started Jun 29 04:52:50 PM PDT 24
Finished Jun 29 04:52:52 PM PDT 24
Peak memory 194700 kb
Host smart-d96c78f4-b40e-4bd7-92b8-4cd032787ff4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948194883 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.hmac_intr_test.948194883
Directory /workspace/32.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.hmac_intr_test.3522711915
Short name T913
Test name
Test status
Simulation time 12488282 ps
CPU time 0.59 seconds
Started Jun 29 04:52:48 PM PDT 24
Finished Jun 29 04:52:50 PM PDT 24
Peak memory 194620 kb
Host smart-a8174e51-0906-448a-9ae6-1142ceffe8d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522711915 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.hmac_intr_test.3522711915
Directory /workspace/33.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.hmac_intr_test.312584802
Short name T888
Test name
Test status
Simulation time 28340721 ps
CPU time 0.57 seconds
Started Jun 29 04:52:58 PM PDT 24
Finished Jun 29 04:52:59 PM PDT 24
Peak memory 194460 kb
Host smart-d42d2cbd-d730-4f4d-ae01-d2c5dfeb11f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312584802 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.hmac_intr_test.312584802
Directory /workspace/34.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.hmac_intr_test.1340594082
Short name T815
Test name
Test status
Simulation time 73367017 ps
CPU time 0.7 seconds
Started Jun 29 04:52:47 PM PDT 24
Finished Jun 29 04:52:48 PM PDT 24
Peak memory 194652 kb
Host smart-75e9c2db-c059-4df6-a49e-15c340a0a4dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340594082 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.hmac_intr_test.1340594082
Directory /workspace/35.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.hmac_intr_test.3766386899
Short name T842
Test name
Test status
Simulation time 56392560 ps
CPU time 0.59 seconds
Started Jun 29 04:52:48 PM PDT 24
Finished Jun 29 04:52:49 PM PDT 24
Peak memory 194572 kb
Host smart-6ffec636-a907-4586-a530-0a8246d60a54
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766386899 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.hmac_intr_test.3766386899
Directory /workspace/36.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.hmac_intr_test.3149445177
Short name T882
Test name
Test status
Simulation time 13075557 ps
CPU time 0.62 seconds
Started Jun 29 04:52:50 PM PDT 24
Finished Jun 29 04:52:52 PM PDT 24
Peak memory 194692 kb
Host smart-9eac3bb6-07e7-4105-bb09-4012dd467ff9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149445177 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.hmac_intr_test.3149445177
Directory /workspace/37.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.hmac_intr_test.551528193
Short name T891
Test name
Test status
Simulation time 39927478 ps
CPU time 0.63 seconds
Started Jun 29 04:52:48 PM PDT 24
Finished Jun 29 04:52:50 PM PDT 24
Peak memory 194752 kb
Host smart-ad30534c-41ba-4ca4-adbb-8de9821c9fd0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551528193 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.hmac_intr_test.551528193
Directory /workspace/38.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.hmac_intr_test.2535719686
Short name T911
Test name
Test status
Simulation time 27655250 ps
CPU time 0.64 seconds
Started Jun 29 04:52:59 PM PDT 24
Finished Jun 29 04:53:01 PM PDT 24
Peak memory 194556 kb
Host smart-039ee785-db66-4e6d-b4f2-0e63a87b6802
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535719686 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.hmac_intr_test.2535719686
Directory /workspace/39.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.1757645840
Short name T104
Test name
Test status
Simulation time 3304887498 ps
CPU time 6.19 seconds
Started Jun 29 04:52:26 PM PDT 24
Finished Jun 29 04:52:33 PM PDT 24
Peak memory 199440 kb
Host smart-99cd9726-6d05-49b3-96fe-bcf3a4687123
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757645840 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_aliasing.1757645840
Directory /workspace/4.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.1856609722
Short name T807
Test name
Test status
Simulation time 1857902981 ps
CPU time 16.52 seconds
Started Jun 29 04:52:25 PM PDT 24
Finished Jun 29 04:52:43 PM PDT 24
Peak memory 199668 kb
Host smart-cf38fead-1114-4bdc-bb33-27f0b3b7d1c2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856609722 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_bit_bash.1856609722
Directory /workspace/4.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.2107814956
Short name T105
Test name
Test status
Simulation time 36873426 ps
CPU time 0.84 seconds
Started Jun 29 04:52:12 PM PDT 24
Finished Jun 29 04:52:13 PM PDT 24
Peak memory 198868 kb
Host smart-cf7038c4-f228-4bbe-9fc5-93836968513b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107814956 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_hw_reset.2107814956
Directory /workspace/4.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.718093436
Short name T854
Test name
Test status
Simulation time 42938243 ps
CPU time 2.48 seconds
Started Jun 29 04:52:26 PM PDT 24
Finished Jun 29 04:52:29 PM PDT 24
Peak memory 199864 kb
Host smart-da024ddb-8827-4d19-a3e7-10634619c131
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718093436 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.hmac_csr_mem_rw_with_rand_reset.718093436
Directory /workspace/4.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_rw.2359010938
Short name T907
Test name
Test status
Simulation time 70268090 ps
CPU time 0.76 seconds
Started Jun 29 04:52:18 PM PDT 24
Finished Jun 29 04:52:19 PM PDT 24
Peak memory 197988 kb
Host smart-0ade12ad-5024-4089-b868-7fcfe3ab256c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359010938 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_rw.2359010938
Directory /workspace/4.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_intr_test.20862732
Short name T855
Test name
Test status
Simulation time 44974755 ps
CPU time 0.66 seconds
Started Jun 29 04:52:11 PM PDT 24
Finished Jun 29 04:52:12 PM PDT 24
Peak memory 194684 kb
Host smart-44ec6b9e-d6b8-4f64-b4e4-67eb73f92fd3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20862732 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_intr_test.20862732
Directory /workspace/4.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.338754674
Short name T863
Test name
Test status
Simulation time 42854732 ps
CPU time 1.14 seconds
Started Jun 29 04:52:21 PM PDT 24
Finished Jun 29 04:52:22 PM PDT 24
Peak memory 199712 kb
Host smart-c1abd301-660b-4619-8f6c-be9fb4c49c34
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338754674 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_same_csr_
outstanding.338754674
Directory /workspace/4.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_errors.661650802
Short name T872
Test name
Test status
Simulation time 266411448 ps
CPU time 2.86 seconds
Started Jun 29 04:52:11 PM PDT 24
Finished Jun 29 04:52:15 PM PDT 24
Peak memory 199768 kb
Host smart-57dd03ae-05b1-4ea1-a5e8-db7415dd59ce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661650802 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_errors.661650802
Directory /workspace/4.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.3429645428
Short name T91
Test name
Test status
Simulation time 1383002139 ps
CPU time 4.24 seconds
Started Jun 29 04:52:11 PM PDT 24
Finished Jun 29 04:52:15 PM PDT 24
Peak memory 199812 kb
Host smart-7d900aef-2c8c-4708-8d10-75b4a297849b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429645428 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_intg_err.3429645428
Directory /workspace/4.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.hmac_intr_test.993961766
Short name T866
Test name
Test status
Simulation time 18985996 ps
CPU time 0.59 seconds
Started Jun 29 04:52:50 PM PDT 24
Finished Jun 29 04:52:51 PM PDT 24
Peak memory 194544 kb
Host smart-1508edf0-b900-473a-9d5d-ab3269f67f82
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993961766 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.hmac_intr_test.993961766
Directory /workspace/40.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.hmac_intr_test.1725857136
Short name T831
Test name
Test status
Simulation time 41279903 ps
CPU time 0.62 seconds
Started Jun 29 04:52:48 PM PDT 24
Finished Jun 29 04:52:50 PM PDT 24
Peak memory 194760 kb
Host smart-17fb71a9-57a4-4fd5-aee1-398f98719073
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725857136 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.hmac_intr_test.1725857136
Directory /workspace/41.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.hmac_intr_test.2783100130
Short name T890
Test name
Test status
Simulation time 75686655 ps
CPU time 0.56 seconds
Started Jun 29 04:52:51 PM PDT 24
Finished Jun 29 04:52:52 PM PDT 24
Peak memory 194724 kb
Host smart-f069083c-1b62-43c0-b88f-d0856158bf84
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783100130 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.hmac_intr_test.2783100130
Directory /workspace/42.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.hmac_intr_test.2375057651
Short name T881
Test name
Test status
Simulation time 15857242 ps
CPU time 0.59 seconds
Started Jun 29 04:52:50 PM PDT 24
Finished Jun 29 04:52:51 PM PDT 24
Peak memory 194656 kb
Host smart-730d2724-f8d7-44fd-b516-5645977a2c45
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375057651 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.hmac_intr_test.2375057651
Directory /workspace/43.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.hmac_intr_test.4128484512
Short name T810
Test name
Test status
Simulation time 12561511 ps
CPU time 0.61 seconds
Started Jun 29 04:52:48 PM PDT 24
Finished Jun 29 04:52:50 PM PDT 24
Peak memory 194708 kb
Host smart-9f2c77da-a946-4a3a-b5da-b10754285e1b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128484512 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.hmac_intr_test.4128484512
Directory /workspace/44.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.hmac_intr_test.2877063296
Short name T836
Test name
Test status
Simulation time 10716680 ps
CPU time 0.58 seconds
Started Jun 29 04:52:53 PM PDT 24
Finished Jun 29 04:52:54 PM PDT 24
Peak memory 194688 kb
Host smart-6d284df3-dd8e-4b51-b5fd-b24d72e9f8c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877063296 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.hmac_intr_test.2877063296
Directory /workspace/45.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.hmac_intr_test.1472625826
Short name T827
Test name
Test status
Simulation time 45173170 ps
CPU time 0.62 seconds
Started Jun 29 04:52:53 PM PDT 24
Finished Jun 29 04:52:54 PM PDT 24
Peak memory 194644 kb
Host smart-9bb98ea2-32b7-4a21-9034-3efb1b32671b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472625826 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.hmac_intr_test.1472625826
Directory /workspace/46.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.hmac_intr_test.137878709
Short name T817
Test name
Test status
Simulation time 24326903 ps
CPU time 0.6 seconds
Started Jun 29 04:52:50 PM PDT 24
Finished Jun 29 04:52:51 PM PDT 24
Peak memory 194644 kb
Host smart-233b9476-faa8-49bf-83a3-822eef33526a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137878709 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.hmac_intr_test.137878709
Directory /workspace/47.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.hmac_intr_test.4020335554
Short name T865
Test name
Test status
Simulation time 52161045 ps
CPU time 0.61 seconds
Started Jun 29 04:52:50 PM PDT 24
Finished Jun 29 04:52:52 PM PDT 24
Peak memory 194704 kb
Host smart-c761a4fb-2b9d-4447-9a5a-7a64ff11ad0e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020335554 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.hmac_intr_test.4020335554
Directory /workspace/48.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.hmac_intr_test.1163071388
Short name T835
Test name
Test status
Simulation time 103996505 ps
CPU time 0.61 seconds
Started Jun 29 04:52:57 PM PDT 24
Finished Jun 29 04:52:59 PM PDT 24
Peak memory 194652 kb
Host smart-4206c584-f959-4958-a9c8-83a036d04a2f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163071388 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.hmac_intr_test.1163071388
Directory /workspace/49.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.3050166755
Short name T832
Test name
Test status
Simulation time 161668557 ps
CPU time 1.26 seconds
Started Jun 29 04:52:21 PM PDT 24
Finished Jun 29 04:52:23 PM PDT 24
Peak memory 199640 kb
Host smart-ed982622-6ab6-4a75-b263-7ec31b615f7a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050166755 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.hmac_csr_mem_rw_with_rand_reset.3050166755
Directory /workspace/5.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_rw.1517740638
Short name T868
Test name
Test status
Simulation time 24837696 ps
CPU time 0.85 seconds
Started Jun 29 04:52:19 PM PDT 24
Finished Jun 29 04:52:20 PM PDT 24
Peak memory 199564 kb
Host smart-be4784ef-8485-43b6-ae72-80386a0e8dcf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517740638 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_rw.1517740638
Directory /workspace/5.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_intr_test.1789278811
Short name T859
Test name
Test status
Simulation time 52704920 ps
CPU time 0.61 seconds
Started Jun 29 04:52:20 PM PDT 24
Finished Jun 29 04:52:21 PM PDT 24
Peak memory 194616 kb
Host smart-1dba85ee-430b-48b2-971c-2e14c045acea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789278811 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_intr_test.1789278811
Directory /workspace/5.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.2335494391
Short name T81
Test name
Test status
Simulation time 93614921 ps
CPU time 1.62 seconds
Started Jun 29 04:52:21 PM PDT 24
Finished Jun 29 04:52:23 PM PDT 24
Peak memory 199908 kb
Host smart-3a54991e-e61c-4367-9128-39a8cec744fb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335494391 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_same_csr
_outstanding.2335494391
Directory /workspace/5.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_errors.1160932022
Short name T60
Test name
Test status
Simulation time 129974934 ps
CPU time 1.89 seconds
Started Jun 29 04:52:20 PM PDT 24
Finished Jun 29 04:52:22 PM PDT 24
Peak memory 199692 kb
Host smart-3baa8c4b-eebc-48ca-acc9-43407358b055
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160932022 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_errors.1160932022
Directory /workspace/5.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.925710272
Short name T828
Test name
Test status
Simulation time 177506125 ps
CPU time 1.71 seconds
Started Jun 29 04:52:19 PM PDT 24
Finished Jun 29 04:52:21 PM PDT 24
Peak memory 199860 kb
Host smart-39cadb40-7a04-4a2b-a541-d9ae082d102c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925710272 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_intg_err.925710272
Directory /workspace/5.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.3563891430
Short name T905
Test name
Test status
Simulation time 206633680 ps
CPU time 3.14 seconds
Started Jun 29 04:52:20 PM PDT 24
Finished Jun 29 04:52:24 PM PDT 24
Peak memory 199812 kb
Host smart-86ffeb63-7153-4c5d-a187-cf302d26c6af
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563891430 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.hmac_csr_mem_rw_with_rand_reset.3563891430
Directory /workspace/6.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_rw.2296129618
Short name T110
Test name
Test status
Simulation time 17138630 ps
CPU time 0.91 seconds
Started Jun 29 04:52:25 PM PDT 24
Finished Jun 29 04:52:27 PM PDT 24
Peak memory 199532 kb
Host smart-e00ebd0f-818e-4427-8252-326b39d4d235
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296129618 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_rw.2296129618
Directory /workspace/6.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_intr_test.1420195490
Short name T879
Test name
Test status
Simulation time 43458335 ps
CPU time 0.6 seconds
Started Jun 29 04:52:21 PM PDT 24
Finished Jun 29 04:52:22 PM PDT 24
Peak memory 194596 kb
Host smart-ce2664f6-c0ca-47a2-9de8-c46505ebbe21
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420195490 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_intr_test.1420195490
Directory /workspace/6.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.645141363
Short name T834
Test name
Test status
Simulation time 223029848 ps
CPU time 2.29 seconds
Started Jun 29 04:52:22 PM PDT 24
Finished Jun 29 04:52:24 PM PDT 24
Peak memory 199832 kb
Host smart-b93590d7-9f52-48d3-b1f6-0c85fa520567
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645141363 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_same_csr_
outstanding.645141363
Directory /workspace/6.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_errors.819364014
Short name T871
Test name
Test status
Simulation time 27850064 ps
CPU time 1.26 seconds
Started Jun 29 04:52:26 PM PDT 24
Finished Jun 29 04:52:27 PM PDT 24
Peak memory 199724 kb
Host smart-333691a5-77e1-496f-9f4b-a64dbdfe2c51
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819364014 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_errors.819364014
Directory /workspace/6.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.1535478992
Short name T843
Test name
Test status
Simulation time 185782892 ps
CPU time 1.83 seconds
Started Jun 29 04:52:20 PM PDT 24
Finished Jun 29 04:52:22 PM PDT 24
Peak memory 199844 kb
Host smart-cd1c4c09-026d-4192-9106-d0e6d27f293e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535478992 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_intg_err.1535478992
Directory /workspace/6.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.710774500
Short name T874
Test name
Test status
Simulation time 46072572 ps
CPU time 2.93 seconds
Started Jun 29 04:52:26 PM PDT 24
Finished Jun 29 04:52:30 PM PDT 24
Peak memory 208088 kb
Host smart-93269651-d46c-4438-abc4-982cffaa781f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710774500 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.hmac_csr_mem_rw_with_rand_reset.710774500
Directory /workspace/7.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_rw.113980906
Short name T844
Test name
Test status
Simulation time 149736381 ps
CPU time 0.95 seconds
Started Jun 29 04:52:25 PM PDT 24
Finished Jun 29 04:52:26 PM PDT 24
Peak memory 199588 kb
Host smart-130f6640-b7a9-42df-aa53-bc11a453c50f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113980906 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_rw.113980906
Directory /workspace/7.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_intr_test.247537209
Short name T812
Test name
Test status
Simulation time 19369746 ps
CPU time 0.59 seconds
Started Jun 29 04:52:28 PM PDT 24
Finished Jun 29 04:52:29 PM PDT 24
Peak memory 194540 kb
Host smart-5fc42531-fc8b-4982-be16-fe8e4ce42e39
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247537209 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_intr_test.247537209
Directory /workspace/7.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.485616153
Short name T895
Test name
Test status
Simulation time 77925816 ps
CPU time 1.68 seconds
Started Jun 29 04:52:25 PM PDT 24
Finished Jun 29 04:52:27 PM PDT 24
Peak memory 199820 kb
Host smart-71014a13-a28e-40dc-b273-d3319d8009de
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485616153 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_same_csr_
outstanding.485616153
Directory /workspace/7.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_errors.1473600822
Short name T71
Test name
Test status
Simulation time 87215116 ps
CPU time 1.2 seconds
Started Jun 29 04:52:21 PM PDT 24
Finished Jun 29 04:52:22 PM PDT 24
Peak memory 199832 kb
Host smart-6cb74898-e9db-4ead-bdb8-6b70cfcf5833
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473600822 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_errors.1473600822
Directory /workspace/7.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.2130857831
Short name T870
Test name
Test status
Simulation time 164659217 ps
CPU time 3.1 seconds
Started Jun 29 04:52:19 PM PDT 24
Finished Jun 29 04:52:22 PM PDT 24
Peak memory 199912 kb
Host smart-549b8fab-09c3-4aa2-92f0-af2c1c1b521e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130857831 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_intg_err.2130857831
Directory /workspace/7.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.3000214927
Short name T906
Test name
Test status
Simulation time 298092801 ps
CPU time 1.84 seconds
Started Jun 29 04:52:26 PM PDT 24
Finished Jun 29 04:52:29 PM PDT 24
Peak memory 199896 kb
Host smart-7e3e2e10-7bc5-4673-b7c0-0f90f1ef5635
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000214927 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.hmac_csr_mem_rw_with_rand_reset.3000214927
Directory /workspace/8.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_rw.3715314517
Short name T117
Test name
Test status
Simulation time 50228632 ps
CPU time 0.68 seconds
Started Jun 29 04:52:26 PM PDT 24
Finished Jun 29 04:52:28 PM PDT 24
Peak memory 197576 kb
Host smart-16de2b67-a9c7-445b-9306-b3409488532c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715314517 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_rw.3715314517
Directory /workspace/8.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_intr_test.3559701389
Short name T79
Test name
Test status
Simulation time 14740991 ps
CPU time 0.64 seconds
Started Jun 29 04:52:26 PM PDT 24
Finished Jun 29 04:52:28 PM PDT 24
Peak memory 194592 kb
Host smart-cc14576b-1a28-4137-a800-ecc21c35cdf9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559701389 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_intr_test.3559701389
Directory /workspace/8.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.3454219126
Short name T820
Test name
Test status
Simulation time 19287478 ps
CPU time 1 seconds
Started Jun 29 04:52:27 PM PDT 24
Finished Jun 29 04:52:28 PM PDT 24
Peak memory 200124 kb
Host smart-f28f8e38-b7bc-4b2b-90de-cf221cf4ed03
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454219126 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_same_csr
_outstanding.3454219126
Directory /workspace/8.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_errors.4294348187
Short name T69
Test name
Test status
Simulation time 62968447 ps
CPU time 1.43 seconds
Started Jun 29 04:52:25 PM PDT 24
Finished Jun 29 04:52:26 PM PDT 24
Peak memory 199764 kb
Host smart-32f91593-d1b7-4b96-8f26-12efe365a495
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294348187 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_errors.4294348187
Directory /workspace/8.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.1371748041
Short name T861
Test name
Test status
Simulation time 190919284 ps
CPU time 1.72 seconds
Started Jun 29 04:52:26 PM PDT 24
Finished Jun 29 04:52:28 PM PDT 24
Peak memory 199748 kb
Host smart-58256a94-986a-41e7-91fe-bd88ead78ebd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371748041 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_intg_err.1371748041
Directory /workspace/8.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.834309467
Short name T884
Test name
Test status
Simulation time 31649634 ps
CPU time 1.09 seconds
Started Jun 29 04:52:25 PM PDT 24
Finished Jun 29 04:52:27 PM PDT 24
Peak memory 199556 kb
Host smart-0788e9c9-cc14-4826-b36c-39074766a0e0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834309467 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.hmac_csr_mem_rw_with_rand_reset.834309467
Directory /workspace/9.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_rw.1631145246
Short name T846
Test name
Test status
Simulation time 27247762 ps
CPU time 0.82 seconds
Started Jun 29 04:52:27 PM PDT 24
Finished Jun 29 04:52:29 PM PDT 24
Peak memory 199308 kb
Host smart-2136255c-2c17-4bbe-abb4-e4581a2c558a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631145246 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_rw.1631145246
Directory /workspace/9.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_intr_test.2947062872
Short name T902
Test name
Test status
Simulation time 132642529 ps
CPU time 0.59 seconds
Started Jun 29 04:52:27 PM PDT 24
Finished Jun 29 04:52:28 PM PDT 24
Peak memory 194672 kb
Host smart-59046b09-ad15-418f-b3ad-0fd69826e2de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947062872 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_intr_test.2947062872
Directory /workspace/9.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.603934933
Short name T873
Test name
Test status
Simulation time 223836919 ps
CPU time 1.2 seconds
Started Jun 29 04:52:25 PM PDT 24
Finished Jun 29 04:52:26 PM PDT 24
Peak memory 199800 kb
Host smart-334a01f4-9af8-4594-ad52-91707e9e74ad
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603934933 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_same_csr_
outstanding.603934933
Directory /workspace/9.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_errors.1895397303
Short name T70
Test name
Test status
Simulation time 137152684 ps
CPU time 1.72 seconds
Started Jun 29 04:52:28 PM PDT 24
Finished Jun 29 04:52:30 PM PDT 24
Peak memory 199732 kb
Host smart-ae00200e-2368-4115-a2a3-270c15b5880f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895397303 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_errors.1895397303
Directory /workspace/9.hmac_tl_errors/latest

Test location /workspace/coverage/default/0.hmac_alert_test.4074253541
Short name T775
Test name
Test status
Simulation time 67818213 ps
CPU time 0.58 seconds
Started Jun 29 05:08:05 PM PDT 24
Finished Jun 29 05:08:06 PM PDT 24
Peak memory 196268 kb
Host smart-1b66749a-f9df-47f8-a070-9ee44f12616d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074253541 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_alert_test.4074253541
Directory /workspace/0.hmac_alert_test/latest

Test location /workspace/coverage/default/0.hmac_back_pressure.2011180247
Short name T442
Test name
Test status
Simulation time 382157583 ps
CPU time 16.11 seconds
Started Jun 29 05:08:03 PM PDT 24
Finished Jun 29 05:08:20 PM PDT 24
Peak memory 200268 kb
Host smart-3bd7276f-6ca7-46c9-acd2-6acec71fc35a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2011180247 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_back_pressure.2011180247
Directory /workspace/0.hmac_back_pressure/latest

Test location /workspace/coverage/default/0.hmac_datapath_stress.4188399976
Short name T285
Test name
Test status
Simulation time 24466210764 ps
CPU time 942.49 seconds
Started Jun 29 05:08:03 PM PDT 24
Finished Jun 29 05:23:46 PM PDT 24
Peak memory 722768 kb
Host smart-3c269323-ff61-4710-944c-36d1d5a7299f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4188399976 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_datapath_stress.4188399976
Directory /workspace/0.hmac_datapath_stress/latest

Test location /workspace/coverage/default/0.hmac_error.3000484982
Short name T431
Test name
Test status
Simulation time 2257520552 ps
CPU time 41.81 seconds
Started Jun 29 05:08:06 PM PDT 24
Finished Jun 29 05:08:48 PM PDT 24
Peak memory 200240 kb
Host smart-b483981a-3a5d-4b68-91f2-58698202058e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000484982 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_error.3000484982
Directory /workspace/0.hmac_error/latest

Test location /workspace/coverage/default/0.hmac_long_msg.3333317340
Short name T577
Test name
Test status
Simulation time 6390232167 ps
CPU time 92.84 seconds
Started Jun 29 05:08:05 PM PDT 24
Finished Jun 29 05:09:38 PM PDT 24
Peak memory 208536 kb
Host smart-e3c303e5-6af6-4233-9bc1-154310fe0e45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333317340 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_long_msg.3333317340
Directory /workspace/0.hmac_long_msg/latest

Test location /workspace/coverage/default/0.hmac_smoke.766355628
Short name T714
Test name
Test status
Simulation time 3160239682 ps
CPU time 16.88 seconds
Started Jun 29 05:08:05 PM PDT 24
Finished Jun 29 05:08:23 PM PDT 24
Peak memory 200276 kb
Host smart-505f6000-d562-465f-adb0-89653861eaa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766355628 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_smoke.766355628
Directory /workspace/0.hmac_smoke/latest

Test location /workspace/coverage/default/0.hmac_stress_all.4283013273
Short name T799
Test name
Test status
Simulation time 243459360119 ps
CPU time 3419.41 seconds
Started Jun 29 05:08:06 PM PDT 24
Finished Jun 29 06:05:07 PM PDT 24
Peak memory 239496 kb
Host smart-c958eb4c-fe8b-4847-aa60-9efa41e44e7d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283013273 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all.4283013273
Directory /workspace/0.hmac_stress_all/latest

Test location /workspace/coverage/default/0.hmac_test_hmac256_vectors.3394638674
Short name T471
Test name
Test status
Simulation time 8024531450 ps
CPU time 57.77 seconds
Started Jun 29 05:08:06 PM PDT 24
Finished Jun 29 05:09:05 PM PDT 24
Peak memory 200368 kb
Host smart-e1d20762-f7d1-4842-9c26-568b590cf2ba
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3394638674 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac256_vectors.3394638674
Directory /workspace/0.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_hmac384_vectors.130782306
Short name T798
Test name
Test status
Simulation time 3075769904 ps
CPU time 83.08 seconds
Started Jun 29 05:08:06 PM PDT 24
Finished Jun 29 05:09:30 PM PDT 24
Peak memory 200356 kb
Host smart-2a073e4d-ec57-40e8-889d-5199ba02b959
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=130782306 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac384_vectors.130782306
Directory /workspace/0.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_hmac512_vectors.1861995111
Short name T162
Test name
Test status
Simulation time 30439895918 ps
CPU time 109.25 seconds
Started Jun 29 05:08:08 PM PDT 24
Finished Jun 29 05:09:58 PM PDT 24
Peak memory 200240 kb
Host smart-2b8b9477-3475-4808-bf1c-f59653801c1c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1861995111 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac512_vectors.1861995111
Directory /workspace/0.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha256_vectors.375390505
Short name T207
Test name
Test status
Simulation time 119254924679 ps
CPU time 523.27 seconds
Started Jun 29 05:08:06 PM PDT 24
Finished Jun 29 05:16:50 PM PDT 24
Peak memory 200264 kb
Host smart-91f84fed-4ff5-41a2-99fc-42b19493fec6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=375390505 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha256_vectors.375390505
Directory /workspace/0.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha384_vectors.403441311
Short name T300
Test name
Test status
Simulation time 603882806919 ps
CPU time 2038.39 seconds
Started Jun 29 05:08:06 PM PDT 24
Finished Jun 29 05:42:05 PM PDT 24
Peak memory 216644 kb
Host smart-3a902c27-c7a6-4d91-b660-c9b476240035
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=403441311 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha384_vectors.403441311
Directory /workspace/0.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha512_vectors.4256612849
Short name T480
Test name
Test status
Simulation time 29366063432 ps
CPU time 1742.54 seconds
Started Jun 29 05:08:07 PM PDT 24
Finished Jun 29 05:37:10 PM PDT 24
Peak memory 215640 kb
Host smart-96f9aef9-31aa-4b0e-9a23-632ed362687e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4256612849 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha512_vectors.4256612849
Directory /workspace/0.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/0.hmac_wipe_secret.1171765569
Short name T150
Test name
Test status
Simulation time 6353635447 ps
CPU time 29.77 seconds
Started Jun 29 05:08:06 PM PDT 24
Finished Jun 29 05:08:36 PM PDT 24
Peak memory 200336 kb
Host smart-53b72fd2-77e7-490f-a419-fedcf10f27da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171765569 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_wipe_secret.1171765569
Directory /workspace/0.hmac_wipe_secret/latest

Test location /workspace/coverage/default/1.hmac_alert_test.2836418166
Short name T678
Test name
Test status
Simulation time 42685314 ps
CPU time 0.57 seconds
Started Jun 29 05:08:12 PM PDT 24
Finished Jun 29 05:08:13 PM PDT 24
Peak memory 195868 kb
Host smart-3efda815-d356-4596-bfb8-930d79f23353
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836418166 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_alert_test.2836418166
Directory /workspace/1.hmac_alert_test/latest

Test location /workspace/coverage/default/1.hmac_back_pressure.3770400628
Short name T315
Test name
Test status
Simulation time 834516302 ps
CPU time 20.87 seconds
Started Jun 29 05:08:05 PM PDT 24
Finished Jun 29 05:08:26 PM PDT 24
Peak memory 200292 kb
Host smart-a63c6684-b2a4-47c8-9958-7f63859d9097
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3770400628 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_back_pressure.3770400628
Directory /workspace/1.hmac_back_pressure/latest

Test location /workspace/coverage/default/1.hmac_burst_wr.1851716790
Short name T474
Test name
Test status
Simulation time 1460860463 ps
CPU time 13.3 seconds
Started Jun 29 05:08:05 PM PDT 24
Finished Jun 29 05:08:19 PM PDT 24
Peak memory 200208 kb
Host smart-e0ec7f10-15f6-4a1b-bae2-5b1574c8a42b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851716790 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_burst_wr.1851716790
Directory /workspace/1.hmac_burst_wr/latest

Test location /workspace/coverage/default/1.hmac_error.1403730978
Short name T445
Test name
Test status
Simulation time 4576787047 ps
CPU time 134.88 seconds
Started Jun 29 05:08:04 PM PDT 24
Finished Jun 29 05:10:19 PM PDT 24
Peak memory 200328 kb
Host smart-31fbdfb0-5814-4bd0-af23-22c57ccab97f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403730978 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_error.1403730978
Directory /workspace/1.hmac_error/latest

Test location /workspace/coverage/default/1.hmac_long_msg.1576898961
Short name T178
Test name
Test status
Simulation time 31953887 ps
CPU time 1.1 seconds
Started Jun 29 05:08:05 PM PDT 24
Finished Jun 29 05:08:07 PM PDT 24
Peak memory 199976 kb
Host smart-f0e7b593-5e9b-433a-8f65-0a5a88ab14a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1576898961 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_long_msg.1576898961
Directory /workspace/1.hmac_long_msg/latest

Test location /workspace/coverage/default/1.hmac_sec_cm.3772363584
Short name T45
Test name
Test status
Simulation time 160874827 ps
CPU time 0.99 seconds
Started Jun 29 05:08:12 PM PDT 24
Finished Jun 29 05:08:13 PM PDT 24
Peak memory 219796 kb
Host smart-8c1a42fa-809a-4983-9226-3f56fe6178de
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772363584 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_sec_cm.3772363584
Directory /workspace/1.hmac_sec_cm/latest

Test location /workspace/coverage/default/1.hmac_smoke.3372026960
Short name T383
Test name
Test status
Simulation time 550911708 ps
CPU time 10.71 seconds
Started Jun 29 05:08:05 PM PDT 24
Finished Jun 29 05:08:17 PM PDT 24
Peak memory 200252 kb
Host smart-99bd5eeb-9e6c-4ffa-8b6a-0ae534c80721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372026960 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_smoke.3372026960
Directory /workspace/1.hmac_smoke/latest

Test location /workspace/coverage/default/1.hmac_stress_all.3407388176
Short name T597
Test name
Test status
Simulation time 188719137144 ps
CPU time 5299.02 seconds
Started Jun 29 05:08:11 PM PDT 24
Finished Jun 29 06:36:31 PM PDT 24
Peak memory 216700 kb
Host smart-1ea4aac7-31d9-41de-bc61-8d56c129e49f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407388176 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all.3407388176
Directory /workspace/1.hmac_stress_all/latest

Test location /workspace/coverage/default/1.hmac_test_hmac256_vectors.1714329211
Short name T24
Test name
Test status
Simulation time 6919755638 ps
CPU time 39.74 seconds
Started Jun 29 05:08:11 PM PDT 24
Finished Jun 29 05:08:51 PM PDT 24
Peak memory 200320 kb
Host smart-f62a9827-9dd4-4f63-afa6-064fe1b8dc7c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1714329211 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac256_vectors.1714329211
Directory /workspace/1.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_hmac384_vectors.1207608027
Short name T208
Test name
Test status
Simulation time 5860801564 ps
CPU time 92.96 seconds
Started Jun 29 05:08:15 PM PDT 24
Finished Jun 29 05:09:49 PM PDT 24
Peak memory 200332 kb
Host smart-9da4011e-ff28-4465-b89e-1e8c1c7defae
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1207608027 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac384_vectors.1207608027
Directory /workspace/1.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_hmac512_vectors.2281955691
Short name T188
Test name
Test status
Simulation time 11652734811 ps
CPU time 97.09 seconds
Started Jun 29 05:08:12 PM PDT 24
Finished Jun 29 05:09:49 PM PDT 24
Peak memory 200364 kb
Host smart-78f966d5-3e64-4b79-9e80-2fe41d1d8363
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2281955691 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac512_vectors.2281955691
Directory /workspace/1.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha256_vectors.1596868878
Short name T493
Test name
Test status
Simulation time 8636538761 ps
CPU time 482.71 seconds
Started Jun 29 05:08:05 PM PDT 24
Finished Jun 29 05:16:08 PM PDT 24
Peak memory 200264 kb
Host smart-b1a75a8f-438c-4ef4-aecd-0ce79fcb4940
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1596868878 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha256_vectors.1596868878
Directory /workspace/1.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha384_vectors.2894672403
Short name T683
Test name
Test status
Simulation time 247997595409 ps
CPU time 1831.57 seconds
Started Jun 29 05:08:12 PM PDT 24
Finished Jun 29 05:38:44 PM PDT 24
Peak memory 216460 kb
Host smart-5192e82a-8ff5-444a-b768-53ea3b31e100
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2894672403 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha384_vectors.2894672403
Directory /workspace/1.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha512_vectors.3000704352
Short name T576
Test name
Test status
Simulation time 33232286714 ps
CPU time 1884.92 seconds
Started Jun 29 05:08:11 PM PDT 24
Finished Jun 29 05:39:36 PM PDT 24
Peak memory 216684 kb
Host smart-e67b38cc-e49f-45a2-a11b-c01a070aa696
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3000704352 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha512_vectors.3000704352
Directory /workspace/1.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/1.hmac_wipe_secret.2983900194
Short name T252
Test name
Test status
Simulation time 12161179678 ps
CPU time 62.76 seconds
Started Jun 29 05:08:04 PM PDT 24
Finished Jun 29 05:09:08 PM PDT 24
Peak memory 200380 kb
Host smart-002f9645-6e00-4544-bb26-01eda085ffb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983900194 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_wipe_secret.2983900194
Directory /workspace/1.hmac_wipe_secret/latest

Test location /workspace/coverage/default/10.hmac_alert_test.2210192337
Short name T546
Test name
Test status
Simulation time 33770042 ps
CPU time 0.57 seconds
Started Jun 29 05:08:56 PM PDT 24
Finished Jun 29 05:08:57 PM PDT 24
Peak memory 195968 kb
Host smart-882307f6-ca47-43ec-8541-1894ef0f3bb5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210192337 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_alert_test.2210192337
Directory /workspace/10.hmac_alert_test/latest

Test location /workspace/coverage/default/10.hmac_back_pressure.3931703052
Short name T715
Test name
Test status
Simulation time 2807947364 ps
CPU time 34.11 seconds
Started Jun 29 05:08:48 PM PDT 24
Finished Jun 29 05:09:23 PM PDT 24
Peak memory 200560 kb
Host smart-6e5749a3-24a2-42a7-91a6-877b3d0ce458
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3931703052 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_back_pressure.3931703052
Directory /workspace/10.hmac_back_pressure/latest

Test location /workspace/coverage/default/10.hmac_burst_wr.4072528261
Short name T277
Test name
Test status
Simulation time 770896353 ps
CPU time 12.43 seconds
Started Jun 29 05:08:48 PM PDT 24
Finished Jun 29 05:09:01 PM PDT 24
Peak memory 200260 kb
Host smart-451dca51-1866-4f8b-ba80-b983f1ffd145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4072528261 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_burst_wr.4072528261
Directory /workspace/10.hmac_burst_wr/latest

Test location /workspace/coverage/default/10.hmac_datapath_stress.693163955
Short name T391
Test name
Test status
Simulation time 1367047738 ps
CPU time 264.71 seconds
Started Jun 29 05:08:49 PM PDT 24
Finished Jun 29 05:13:14 PM PDT 24
Peak memory 661268 kb
Host smart-1ce4787f-d07c-45b0-b7ca-bdb8c4d16253
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=693163955 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_datapath_stress.693163955
Directory /workspace/10.hmac_datapath_stress/latest

Test location /workspace/coverage/default/10.hmac_error.3236367292
Short name T636
Test name
Test status
Simulation time 2542875342 ps
CPU time 10.82 seconds
Started Jun 29 05:08:48 PM PDT 24
Finished Jun 29 05:08:59 PM PDT 24
Peak memory 200252 kb
Host smart-c8fb070c-0bb9-4e6e-8d77-4dae37f1b5fc
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236367292 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_error.3236367292
Directory /workspace/10.hmac_error/latest

Test location /workspace/coverage/default/10.hmac_smoke.3088436934
Short name T484
Test name
Test status
Simulation time 612456104 ps
CPU time 7.4 seconds
Started Jun 29 05:08:45 PM PDT 24
Finished Jun 29 05:08:52 PM PDT 24
Peak memory 200236 kb
Host smart-a9c2a79a-bfbc-4093-a7b9-a4e768ad3b5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088436934 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_smoke.3088436934
Directory /workspace/10.hmac_smoke/latest

Test location /workspace/coverage/default/10.hmac_stress_all.1740916886
Short name T75
Test name
Test status
Simulation time 1408522432970 ps
CPU time 3692.59 seconds
Started Jun 29 05:08:45 PM PDT 24
Finished Jun 29 06:10:19 PM PDT 24
Peak memory 683136 kb
Host smart-4420279e-0ba2-411f-9853-95764e68f52b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740916886 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.hmac_stress_all.1740916886
Directory /workspace/10.hmac_stress_all/latest

Test location /workspace/coverage/default/10.hmac_test_hmac256_vectors.1604868751
Short name T292
Test name
Test status
Simulation time 10497077598 ps
CPU time 36.92 seconds
Started Jun 29 05:08:47 PM PDT 24
Finished Jun 29 05:09:24 PM PDT 24
Peak memory 200360 kb
Host smart-d255207f-f37a-461d-8136-67df5424a08f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1604868751 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_test_hmac256_vectors.1604868751
Directory /workspace/10.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/10.hmac_test_hmac384_vectors.1776119705
Short name T265
Test name
Test status
Simulation time 38889669250 ps
CPU time 86.75 seconds
Started Jun 29 05:08:45 PM PDT 24
Finished Jun 29 05:10:13 PM PDT 24
Peak memory 200300 kb
Host smart-b55dc3d0-c53b-4096-98e2-a38e146d1352
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1776119705 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_test_hmac384_vectors.1776119705
Directory /workspace/10.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/10.hmac_test_hmac512_vectors.848666940
Short name T336
Test name
Test status
Simulation time 31757183133 ps
CPU time 112.13 seconds
Started Jun 29 05:08:49 PM PDT 24
Finished Jun 29 05:10:42 PM PDT 24
Peak memory 200312 kb
Host smart-68b35978-0af6-4e37-be57-17af98fe8219
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=848666940 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_test_hmac512_vectors.848666940
Directory /workspace/10.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/10.hmac_test_sha256_vectors.4092341887
Short name T346
Test name
Test status
Simulation time 58639564696 ps
CPU time 544.72 seconds
Started Jun 29 05:08:48 PM PDT 24
Finished Jun 29 05:17:53 PM PDT 24
Peak memory 200252 kb
Host smart-ee4572c5-27a9-4b5d-9917-ce990c64e408
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=4092341887 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_test_sha256_vectors.4092341887
Directory /workspace/10.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/10.hmac_test_sha384_vectors.1081495628
Short name T695
Test name
Test status
Simulation time 65979205772 ps
CPU time 1801.05 seconds
Started Jun 29 05:08:44 PM PDT 24
Finished Jun 29 05:38:46 PM PDT 24
Peak memory 215580 kb
Host smart-596e63d8-bb9e-473f-9fbe-768856e5dfb9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1081495628 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_test_sha384_vectors.1081495628
Directory /workspace/10.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/10.hmac_test_sha512_vectors.1134807699
Short name T795
Test name
Test status
Simulation time 128843779346 ps
CPU time 1716.43 seconds
Started Jun 29 05:08:47 PM PDT 24
Finished Jun 29 05:37:24 PM PDT 24
Peak memory 215740 kb
Host smart-85b55454-3e24-443b-ada2-c20a9bb7f0a1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1134807699 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_test_sha512_vectors.1134807699
Directory /workspace/10.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/10.hmac_wipe_secret.3406134740
Short name T564
Test name
Test status
Simulation time 2153486226 ps
CPU time 69.17 seconds
Started Jun 29 05:08:48 PM PDT 24
Finished Jun 29 05:09:58 PM PDT 24
Peak memory 200348 kb
Host smart-75bdfff5-b226-4f5e-ade7-42743b92272a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406134740 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_wipe_secret.3406134740
Directory /workspace/10.hmac_wipe_secret/latest

Test location /workspace/coverage/default/11.hmac_alert_test.2786253038
Short name T373
Test name
Test status
Simulation time 15402052 ps
CPU time 0.61 seconds
Started Jun 29 05:08:56 PM PDT 24
Finished Jun 29 05:08:57 PM PDT 24
Peak memory 196992 kb
Host smart-4881994c-1d69-4205-a67f-f4a0416f53fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786253038 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_alert_test.2786253038
Directory /workspace/11.hmac_alert_test/latest

Test location /workspace/coverage/default/11.hmac_back_pressure.3817038289
Short name T517
Test name
Test status
Simulation time 4563994608 ps
CPU time 41.13 seconds
Started Jun 29 05:08:54 PM PDT 24
Finished Jun 29 05:09:36 PM PDT 24
Peak memory 200356 kb
Host smart-98c53336-f041-464d-9049-eb89ff91a4a9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3817038289 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_back_pressure.3817038289
Directory /workspace/11.hmac_back_pressure/latest

Test location /workspace/coverage/default/11.hmac_burst_wr.1281323570
Short name T247
Test name
Test status
Simulation time 4960256885 ps
CPU time 21.02 seconds
Started Jun 29 05:08:58 PM PDT 24
Finished Jun 29 05:09:19 PM PDT 24
Peak memory 200340 kb
Host smart-192869d2-5456-405e-98f5-c013f319459a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281323570 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_burst_wr.1281323570
Directory /workspace/11.hmac_burst_wr/latest

Test location /workspace/coverage/default/11.hmac_datapath_stress.761188229
Short name T777
Test name
Test status
Simulation time 3799798089 ps
CPU time 161.01 seconds
Started Jun 29 05:08:58 PM PDT 24
Finished Jun 29 05:11:40 PM PDT 24
Peak memory 448948 kb
Host smart-481a3e46-0650-401e-b831-400626a44e24
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=761188229 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_datapath_stress.761188229
Directory /workspace/11.hmac_datapath_stress/latest

Test location /workspace/coverage/default/11.hmac_error.3013449041
Short name T653
Test name
Test status
Simulation time 518811154 ps
CPU time 29.05 seconds
Started Jun 29 05:08:55 PM PDT 24
Finished Jun 29 05:09:25 PM PDT 24
Peak memory 200140 kb
Host smart-777ab8ca-db87-4297-a0a3-730bca73ae31
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013449041 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_error.3013449041
Directory /workspace/11.hmac_error/latest

Test location /workspace/coverage/default/11.hmac_long_msg.710831014
Short name T726
Test name
Test status
Simulation time 4388132361 ps
CPU time 63.45 seconds
Started Jun 29 05:08:57 PM PDT 24
Finished Jun 29 05:10:01 PM PDT 24
Peak memory 200348 kb
Host smart-8e011eab-01f5-48f8-b676-ab98611b4ec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710831014 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_long_msg.710831014
Directory /workspace/11.hmac_long_msg/latest

Test location /workspace/coverage/default/11.hmac_smoke.3767689418
Short name T559
Test name
Test status
Simulation time 1932102387 ps
CPU time 15.34 seconds
Started Jun 29 05:08:56 PM PDT 24
Finished Jun 29 05:09:12 PM PDT 24
Peak memory 200272 kb
Host smart-cc970260-873f-456f-a330-27d4a9638446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767689418 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_smoke.3767689418
Directory /workspace/11.hmac_smoke/latest

Test location /workspace/coverage/default/11.hmac_test_hmac256_vectors.1206800512
Short name T190
Test name
Test status
Simulation time 2062056038 ps
CPU time 31.74 seconds
Started Jun 29 05:08:57 PM PDT 24
Finished Jun 29 05:09:30 PM PDT 24
Peak memory 200248 kb
Host smart-86130b54-cc12-450f-a5c1-3332722b511e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1206800512 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_test_hmac256_vectors.1206800512
Directory /workspace/11.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/11.hmac_test_hmac384_vectors.1576782906
Short name T637
Test name
Test status
Simulation time 7614389301 ps
CPU time 47.52 seconds
Started Jun 29 05:08:55 PM PDT 24
Finished Jun 29 05:09:43 PM PDT 24
Peak memory 200360 kb
Host smart-53121cb8-8cf3-4ca4-a1c3-fb950ab08e21
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1576782906 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_test_hmac384_vectors.1576782906
Directory /workspace/11.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/11.hmac_test_hmac512_vectors.1912652218
Short name T30
Test name
Test status
Simulation time 28989011063 ps
CPU time 58.67 seconds
Started Jun 29 05:08:57 PM PDT 24
Finished Jun 29 05:09:57 PM PDT 24
Peak memory 200552 kb
Host smart-df25d7b3-fd8e-4bc6-ae54-b0c3a5444b65
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1912652218 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_test_hmac512_vectors.1912652218
Directory /workspace/11.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/11.hmac_test_sha256_vectors.2696426715
Short name T374
Test name
Test status
Simulation time 41558541939 ps
CPU time 484.61 seconds
Started Jun 29 05:08:56 PM PDT 24
Finished Jun 29 05:17:01 PM PDT 24
Peak memory 200192 kb
Host smart-99fc1bc8-9d05-475f-b4ea-06b546537cb3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2696426715 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_test_sha256_vectors.2696426715
Directory /workspace/11.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/11.hmac_test_sha384_vectors.2535172576
Short name T425
Test name
Test status
Simulation time 226329601468 ps
CPU time 1862.55 seconds
Started Jun 29 05:08:57 PM PDT 24
Finished Jun 29 05:40:01 PM PDT 24
Peak memory 215680 kb
Host smart-fd927d3a-6a11-48a0-83a7-d3b535b717dc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2535172576 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_test_sha384_vectors.2535172576
Directory /workspace/11.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/11.hmac_test_sha512_vectors.3437088098
Short name T753
Test name
Test status
Simulation time 117150840576 ps
CPU time 1697.07 seconds
Started Jun 29 05:08:57 PM PDT 24
Finished Jun 29 05:37:16 PM PDT 24
Peak memory 216236 kb
Host smart-d9a581ee-05d6-439f-afd5-14f07644706a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3437088098 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_test_sha512_vectors.3437088098
Directory /workspace/11.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/11.hmac_wipe_secret.3586358352
Short name T157
Test name
Test status
Simulation time 1480011794 ps
CPU time 7.33 seconds
Started Jun 29 05:08:55 PM PDT 24
Finished Jun 29 05:09:03 PM PDT 24
Peak memory 200192 kb
Host smart-a718ef41-434a-4475-bcc2-46ff159f0431
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586358352 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_wipe_secret.3586358352
Directory /workspace/11.hmac_wipe_secret/latest

Test location /workspace/coverage/default/12.hmac_alert_test.846773662
Short name T491
Test name
Test status
Simulation time 22014210 ps
CPU time 0.56 seconds
Started Jun 29 05:08:55 PM PDT 24
Finished Jun 29 05:08:56 PM PDT 24
Peak memory 196256 kb
Host smart-8db4cf5c-ab46-43d2-95a0-48e2277af129
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846773662 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_alert_test.846773662
Directory /workspace/12.hmac_alert_test/latest

Test location /workspace/coverage/default/12.hmac_back_pressure.556536113
Short name T665
Test name
Test status
Simulation time 5461943597 ps
CPU time 36.42 seconds
Started Jun 29 05:08:54 PM PDT 24
Finished Jun 29 05:09:31 PM PDT 24
Peak memory 200324 kb
Host smart-cfd83856-3e41-4930-8b8f-6ad8964e9257
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=556536113 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_back_pressure.556536113
Directory /workspace/12.hmac_back_pressure/latest

Test location /workspace/coverage/default/12.hmac_burst_wr.4026438626
Short name T304
Test name
Test status
Simulation time 6371619256 ps
CPU time 44.16 seconds
Started Jun 29 05:08:53 PM PDT 24
Finished Jun 29 05:09:38 PM PDT 24
Peak memory 200356 kb
Host smart-d29cc7c9-934b-4c6c-a7a8-8afb7e21c1cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026438626 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_burst_wr.4026438626
Directory /workspace/12.hmac_burst_wr/latest

Test location /workspace/coverage/default/12.hmac_datapath_stress.3184960417
Short name T262
Test name
Test status
Simulation time 2220834407 ps
CPU time 532.82 seconds
Started Jun 29 05:08:55 PM PDT 24
Finished Jun 29 05:17:49 PM PDT 24
Peak memory 624340 kb
Host smart-21c937df-7a83-4631-a93e-e141a3624fa6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3184960417 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_datapath_stress.3184960417
Directory /workspace/12.hmac_datapath_stress/latest

Test location /workspace/coverage/default/12.hmac_error.230017698
Short name T553
Test name
Test status
Simulation time 7123189912 ps
CPU time 128.87 seconds
Started Jun 29 05:08:57 PM PDT 24
Finished Jun 29 05:11:07 PM PDT 24
Peak memory 200284 kb
Host smart-14c3dee1-eb74-484e-85c2-85c64b75cce0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230017698 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_error.230017698
Directory /workspace/12.hmac_error/latest

Test location /workspace/coverage/default/12.hmac_long_msg.1120763374
Short name T371
Test name
Test status
Simulation time 17505006027 ps
CPU time 128.45 seconds
Started Jun 29 05:08:57 PM PDT 24
Finished Jun 29 05:11:07 PM PDT 24
Peak memory 200352 kb
Host smart-f506c992-67d3-4882-9c08-c39c4dc858dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120763374 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_long_msg.1120763374
Directory /workspace/12.hmac_long_msg/latest

Test location /workspace/coverage/default/12.hmac_smoke.3897118761
Short name T757
Test name
Test status
Simulation time 55970392 ps
CPU time 2.76 seconds
Started Jun 29 05:08:55 PM PDT 24
Finished Jun 29 05:08:59 PM PDT 24
Peak memory 200252 kb
Host smart-03a7b944-5844-4c82-abb9-a3ae286d05f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897118761 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_smoke.3897118761
Directory /workspace/12.hmac_smoke/latest

Test location /workspace/coverage/default/12.hmac_stress_all.3453090306
Short name T55
Test name
Test status
Simulation time 11361897076 ps
CPU time 464.17 seconds
Started Jun 29 05:08:55 PM PDT 24
Finished Jun 29 05:16:40 PM PDT 24
Peak memory 200332 kb
Host smart-5a7799cb-31a5-4c61-8bd0-43f3e7431564
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453090306 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.hmac_stress_all.3453090306
Directory /workspace/12.hmac_stress_all/latest

Test location /workspace/coverage/default/12.hmac_test_hmac256_vectors.3892288379
Short name T557
Test name
Test status
Simulation time 1384497394 ps
CPU time 55.32 seconds
Started Jun 29 05:08:58 PM PDT 24
Finished Jun 29 05:09:54 PM PDT 24
Peak memory 200268 kb
Host smart-c58e42bc-c7f3-43f8-8a0e-b9d6742e951b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3892288379 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_test_hmac256_vectors.3892288379
Directory /workspace/12.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/12.hmac_test_hmac384_vectors.2240278299
Short name T768
Test name
Test status
Simulation time 14097007596 ps
CPU time 80.15 seconds
Started Jun 29 05:08:57 PM PDT 24
Finished Jun 29 05:10:18 PM PDT 24
Peak memory 200332 kb
Host smart-6a8b3765-54ee-4db0-8d8c-327b2e0a583a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2240278299 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_test_hmac384_vectors.2240278299
Directory /workspace/12.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/12.hmac_test_hmac512_vectors.1789601728
Short name T318
Test name
Test status
Simulation time 7927442174 ps
CPU time 53.16 seconds
Started Jun 29 05:08:57 PM PDT 24
Finished Jun 29 05:09:51 PM PDT 24
Peak memory 200296 kb
Host smart-92e72e84-2446-463e-81b6-6167043bc3af
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1789601728 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_test_hmac512_vectors.1789601728
Directory /workspace/12.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/12.hmac_test_sha256_vectors.176984636
Short name T800
Test name
Test status
Simulation time 35390782805 ps
CPU time 472.29 seconds
Started Jun 29 05:08:57 PM PDT 24
Finished Jun 29 05:16:50 PM PDT 24
Peak memory 200264 kb
Host smart-9ea21446-cbbb-4650-8a84-355ea19c35db
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=176984636 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_test_sha256_vectors.176984636
Directory /workspace/12.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/12.hmac_test_sha384_vectors.1797717248
Short name T163
Test name
Test status
Simulation time 319493644384 ps
CPU time 2053.5 seconds
Started Jun 29 05:08:55 PM PDT 24
Finished Jun 29 05:43:10 PM PDT 24
Peak memory 216684 kb
Host smart-bc45547a-15c2-4a74-b244-5042af32cd62
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1797717248 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_test_sha384_vectors.1797717248
Directory /workspace/12.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/12.hmac_test_sha512_vectors.2261898441
Short name T187
Test name
Test status
Simulation time 107566665394 ps
CPU time 1898.61 seconds
Started Jun 29 05:08:55 PM PDT 24
Finished Jun 29 05:40:35 PM PDT 24
Peak memory 215764 kb
Host smart-deb8fbdd-8ebb-4cd3-8f35-dc38844a4912
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2261898441 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_test_sha512_vectors.2261898441
Directory /workspace/12.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/12.hmac_wipe_secret.194560010
Short name T399
Test name
Test status
Simulation time 1710635154 ps
CPU time 82.01 seconds
Started Jun 29 05:08:57 PM PDT 24
Finished Jun 29 05:10:19 PM PDT 24
Peak memory 200320 kb
Host smart-7d1fa8fd-fec4-4e73-bd10-f7043d667066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=194560010 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_wipe_secret.194560010
Directory /workspace/12.hmac_wipe_secret/latest

Test location /workspace/coverage/default/13.hmac_alert_test.3679189513
Short name T353
Test name
Test status
Simulation time 39032181 ps
CPU time 0.58 seconds
Started Jun 29 05:09:06 PM PDT 24
Finished Jun 29 05:09:07 PM PDT 24
Peak memory 196252 kb
Host smart-182bcaae-1a2a-4071-93cc-17c4d92127fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679189513 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_alert_test.3679189513
Directory /workspace/13.hmac_alert_test/latest

Test location /workspace/coverage/default/13.hmac_burst_wr.2817034858
Short name T467
Test name
Test status
Simulation time 1039006288 ps
CPU time 55.85 seconds
Started Jun 29 05:08:57 PM PDT 24
Finished Jun 29 05:09:53 PM PDT 24
Peak memory 200300 kb
Host smart-17165860-4af5-4c35-9dc4-d4f22042884e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817034858 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_burst_wr.2817034858
Directory /workspace/13.hmac_burst_wr/latest

Test location /workspace/coverage/default/13.hmac_datapath_stress.2429812248
Short name T424
Test name
Test status
Simulation time 28646329204 ps
CPU time 1116.68 seconds
Started Jun 29 05:08:56 PM PDT 24
Finished Jun 29 05:27:33 PM PDT 24
Peak memory 772504 kb
Host smart-e7c0710e-e9a5-4017-991d-f181f733a0e0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2429812248 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_datapath_stress.2429812248
Directory /workspace/13.hmac_datapath_stress/latest

Test location /workspace/coverage/default/13.hmac_error.3084382806
Short name T769
Test name
Test status
Simulation time 6750257419 ps
CPU time 115.41 seconds
Started Jun 29 05:08:56 PM PDT 24
Finished Jun 29 05:10:52 PM PDT 24
Peak memory 200256 kb
Host smart-32449546-8c23-4107-a4e0-ae697b8f1504
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084382806 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_error.3084382806
Directory /workspace/13.hmac_error/latest

Test location /workspace/coverage/default/13.hmac_long_msg.836354906
Short name T376
Test name
Test status
Simulation time 18097397315 ps
CPU time 88.62 seconds
Started Jun 29 05:08:57 PM PDT 24
Finished Jun 29 05:10:27 PM PDT 24
Peak memory 200328 kb
Host smart-8fde5a95-38cc-4d56-91f5-a5952a6215a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836354906 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_long_msg.836354906
Directory /workspace/13.hmac_long_msg/latest

Test location /workspace/coverage/default/13.hmac_smoke.518069885
Short name T270
Test name
Test status
Simulation time 128739475 ps
CPU time 5.57 seconds
Started Jun 29 05:08:55 PM PDT 24
Finished Jun 29 05:09:02 PM PDT 24
Peak memory 200312 kb
Host smart-36445556-c039-4ef3-a700-100a40499df2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518069885 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_smoke.518069885
Directory /workspace/13.hmac_smoke/latest

Test location /workspace/coverage/default/13.hmac_stress_all.831824626
Short name T347
Test name
Test status
Simulation time 27891264357 ps
CPU time 1362.72 seconds
Started Jun 29 05:09:05 PM PDT 24
Finished Jun 29 05:31:48 PM PDT 24
Peak memory 664560 kb
Host smart-b8415f83-ff33-40f9-a37f-4d54199b39c7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831824626 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 13.hmac_stress_all.831824626
Directory /workspace/13.hmac_stress_all/latest

Test location /workspace/coverage/default/13.hmac_test_hmac256_vectors.1511973910
Short name T590
Test name
Test status
Simulation time 5275960236 ps
CPU time 62.34 seconds
Started Jun 29 05:09:04 PM PDT 24
Finished Jun 29 05:10:07 PM PDT 24
Peak memory 200320 kb
Host smart-661ca00e-e1ef-4519-af24-d6bd67dd1d54
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1511973910 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_test_hmac256_vectors.1511973910
Directory /workspace/13.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/13.hmac_test_hmac384_vectors.2727993575
Short name T412
Test name
Test status
Simulation time 6073274002 ps
CPU time 48.92 seconds
Started Jun 29 05:09:05 PM PDT 24
Finished Jun 29 05:09:55 PM PDT 24
Peak memory 200284 kb
Host smart-6fa7dba6-2d3f-4ff7-bc86-debc89b506aa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2727993575 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_test_hmac384_vectors.2727993575
Directory /workspace/13.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/13.hmac_test_hmac512_vectors.770887151
Short name T414
Test name
Test status
Simulation time 45752704955 ps
CPU time 128.15 seconds
Started Jun 29 05:09:04 PM PDT 24
Finished Jun 29 05:11:12 PM PDT 24
Peak memory 200264 kb
Host smart-1864716d-fe08-4968-8cd0-cd437437b32f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=770887151 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_test_hmac512_vectors.770887151
Directory /workspace/13.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/13.hmac_test_sha256_vectors.3761173781
Short name T599
Test name
Test status
Simulation time 34716835414 ps
CPU time 460.96 seconds
Started Jun 29 05:09:08 PM PDT 24
Finished Jun 29 05:16:49 PM PDT 24
Peak memory 200264 kb
Host smart-d34f250b-e4ea-4d22-8ee4-af5c5aff04d4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3761173781 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_test_sha256_vectors.3761173781
Directory /workspace/13.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/13.hmac_test_sha384_vectors.2943247786
Short name T92
Test name
Test status
Simulation time 29127966099 ps
CPU time 1782.17 seconds
Started Jun 29 05:09:05 PM PDT 24
Finished Jun 29 05:38:48 PM PDT 24
Peak memory 215776 kb
Host smart-a384f3eb-8944-4aa8-bd93-e937aafffe51
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2943247786 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_test_sha384_vectors.2943247786
Directory /workspace/13.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/13.hmac_test_sha512_vectors.3031956467
Short name T670
Test name
Test status
Simulation time 127346321500 ps
CPU time 1814.6 seconds
Started Jun 29 05:09:05 PM PDT 24
Finished Jun 29 05:39:21 PM PDT 24
Peak memory 216608 kb
Host smart-9eaba4f7-f4e5-4150-a5ca-4d30dcae99f1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3031956467 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_test_sha512_vectors.3031956467
Directory /workspace/13.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/13.hmac_wipe_secret.2443068217
Short name T619
Test name
Test status
Simulation time 6548591792 ps
CPU time 81.32 seconds
Started Jun 29 05:09:06 PM PDT 24
Finished Jun 29 05:10:28 PM PDT 24
Peak memory 200348 kb
Host smart-07faa1b7-2d5e-4fbd-a78f-fd9762770d6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2443068217 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_wipe_secret.2443068217
Directory /workspace/13.hmac_wipe_secret/latest

Test location /workspace/coverage/default/14.hmac_alert_test.789669598
Short name T369
Test name
Test status
Simulation time 18000324 ps
CPU time 0.63 seconds
Started Jun 29 05:09:05 PM PDT 24
Finished Jun 29 05:09:07 PM PDT 24
Peak memory 196252 kb
Host smart-48479784-b29e-4010-ac95-5191edcd1c8a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789669598 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_alert_test.789669598
Directory /workspace/14.hmac_alert_test/latest

Test location /workspace/coverage/default/14.hmac_back_pressure.3726787521
Short name T671
Test name
Test status
Simulation time 791185214 ps
CPU time 39.82 seconds
Started Jun 29 05:09:04 PM PDT 24
Finished Jun 29 05:09:45 PM PDT 24
Peak memory 200280 kb
Host smart-4a03c743-c460-4c0a-a09a-976a6a1058f9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3726787521 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_back_pressure.3726787521
Directory /workspace/14.hmac_back_pressure/latest

Test location /workspace/coverage/default/14.hmac_burst_wr.882968577
Short name T15
Test name
Test status
Simulation time 671445134 ps
CPU time 36.65 seconds
Started Jun 29 05:09:05 PM PDT 24
Finished Jun 29 05:09:43 PM PDT 24
Peak memory 200308 kb
Host smart-49a33bb0-702a-416f-971d-96dada980983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882968577 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_burst_wr.882968577
Directory /workspace/14.hmac_burst_wr/latest

Test location /workspace/coverage/default/14.hmac_datapath_stress.1668369990
Short name T567
Test name
Test status
Simulation time 12613926533 ps
CPU time 466.3 seconds
Started Jun 29 05:09:06 PM PDT 24
Finished Jun 29 05:16:53 PM PDT 24
Peak memory 708152 kb
Host smart-fcfb61ac-0c7f-43bb-a56d-bad8f64cead7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1668369990 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_datapath_stress.1668369990
Directory /workspace/14.hmac_datapath_stress/latest

Test location /workspace/coverage/default/14.hmac_error.647398192
Short name T674
Test name
Test status
Simulation time 5080804034 ps
CPU time 138.3 seconds
Started Jun 29 05:09:07 PM PDT 24
Finished Jun 29 05:11:26 PM PDT 24
Peak memory 200292 kb
Host smart-8bf6187d-90dc-4397-829c-7474a6f0d186
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647398192 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_error.647398192
Directory /workspace/14.hmac_error/latest

Test location /workspace/coverage/default/14.hmac_long_msg.1556011161
Short name T229
Test name
Test status
Simulation time 1062134433 ps
CPU time 65.13 seconds
Started Jun 29 05:09:07 PM PDT 24
Finished Jun 29 05:10:13 PM PDT 24
Peak memory 200276 kb
Host smart-bc74746d-2d38-4daa-a2b4-23d52012f088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556011161 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_long_msg.1556011161
Directory /workspace/14.hmac_long_msg/latest

Test location /workspace/coverage/default/14.hmac_smoke.1855394885
Short name T48
Test name
Test status
Simulation time 1046217470 ps
CPU time 4.89 seconds
Started Jun 29 05:09:06 PM PDT 24
Finished Jun 29 05:09:12 PM PDT 24
Peak memory 200268 kb
Host smart-9d05fab6-4f11-48a9-8826-59fbd2135836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855394885 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_smoke.1855394885
Directory /workspace/14.hmac_smoke/latest

Test location /workspace/coverage/default/14.hmac_test_hmac256_vectors.129018477
Short name T593
Test name
Test status
Simulation time 6013287977 ps
CPU time 72.37 seconds
Started Jun 29 05:09:04 PM PDT 24
Finished Jun 29 05:10:17 PM PDT 24
Peak memory 200320 kb
Host smart-99c155cd-2d1e-4d6c-a209-4176f0ef4002
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=129018477 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_test_hmac256_vectors.129018477
Directory /workspace/14.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/14.hmac_test_hmac384_vectors.3219388082
Short name T338
Test name
Test status
Simulation time 21271792323 ps
CPU time 79.36 seconds
Started Jun 29 05:09:04 PM PDT 24
Finished Jun 29 05:10:24 PM PDT 24
Peak memory 200332 kb
Host smart-e8f8026c-2720-4e54-b8e2-3e294ab9b26c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3219388082 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_test_hmac384_vectors.3219388082
Directory /workspace/14.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/14.hmac_test_hmac512_vectors.1139495199
Short name T221
Test name
Test status
Simulation time 8020610085 ps
CPU time 51.3 seconds
Started Jun 29 05:09:06 PM PDT 24
Finished Jun 29 05:09:58 PM PDT 24
Peak memory 200332 kb
Host smart-3d6c99bf-c000-42f0-953a-62216f76e44b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1139495199 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_test_hmac512_vectors.1139495199
Directory /workspace/14.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/14.hmac_test_sha256_vectors.2798988309
Short name T771
Test name
Test status
Simulation time 154475183354 ps
CPU time 503.23 seconds
Started Jun 29 05:09:05 PM PDT 24
Finished Jun 29 05:17:29 PM PDT 24
Peak memory 200280 kb
Host smart-a1817068-d502-4fc2-8cd3-2f64292b4204
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2798988309 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_test_sha256_vectors.2798988309
Directory /workspace/14.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/14.hmac_test_sha384_vectors.748237314
Short name T710
Test name
Test status
Simulation time 388845102852 ps
CPU time 1958.98 seconds
Started Jun 29 05:09:10 PM PDT 24
Finished Jun 29 05:41:50 PM PDT 24
Peak memory 215728 kb
Host smart-8ecfac46-13f5-4856-8d4d-1ba0d1fe9ea5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=748237314 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_test_sha384_vectors.748237314
Directory /workspace/14.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/14.hmac_test_sha512_vectors.3832524305
Short name T201
Test name
Test status
Simulation time 113554376579 ps
CPU time 2170.26 seconds
Started Jun 29 05:09:05 PM PDT 24
Finished Jun 29 05:45:16 PM PDT 24
Peak memory 215788 kb
Host smart-65922708-f47a-42a5-8a51-4911e85c43fe
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3832524305 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_test_sha512_vectors.3832524305
Directory /workspace/14.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/14.hmac_wipe_secret.2229727791
Short name T528
Test name
Test status
Simulation time 3935090868 ps
CPU time 18.82 seconds
Started Jun 29 05:09:05 PM PDT 24
Finished Jun 29 05:09:24 PM PDT 24
Peak memory 200336 kb
Host smart-0fe61bba-39db-46b2-b8eb-076540751ee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229727791 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_wipe_secret.2229727791
Directory /workspace/14.hmac_wipe_secret/latest

Test location /workspace/coverage/default/15.hmac_alert_test.2380936521
Short name T776
Test name
Test status
Simulation time 72117484 ps
CPU time 0.61 seconds
Started Jun 29 05:09:10 PM PDT 24
Finished Jun 29 05:09:11 PM PDT 24
Peak memory 196320 kb
Host smart-41a6f1f0-8bcf-4acf-adc0-1dbd809c8857
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380936521 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_alert_test.2380936521
Directory /workspace/15.hmac_alert_test/latest

Test location /workspace/coverage/default/15.hmac_back_pressure.1483019035
Short name T772
Test name
Test status
Simulation time 246862135 ps
CPU time 9.66 seconds
Started Jun 29 05:09:06 PM PDT 24
Finished Jun 29 05:09:17 PM PDT 24
Peak memory 200264 kb
Host smart-d237d8f7-a236-476b-8f1b-40117e2ba683
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1483019035 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_back_pressure.1483019035
Directory /workspace/15.hmac_back_pressure/latest

Test location /workspace/coverage/default/15.hmac_burst_wr.2051417513
Short name T145
Test name
Test status
Simulation time 2815303707 ps
CPU time 74.46 seconds
Started Jun 29 05:09:05 PM PDT 24
Finished Jun 29 05:10:20 PM PDT 24
Peak memory 200304 kb
Host smart-6eff61d6-6658-4b1c-b750-6b99a3ce9c02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051417513 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_burst_wr.2051417513
Directory /workspace/15.hmac_burst_wr/latest

Test location /workspace/coverage/default/15.hmac_datapath_stress.338059955
Short name T222
Test name
Test status
Simulation time 5503417620 ps
CPU time 443.42 seconds
Started Jun 29 05:09:04 PM PDT 24
Finished Jun 29 05:16:27 PM PDT 24
Peak memory 688440 kb
Host smart-b4ba53bd-97b2-4c9b-b526-9443dd441dc1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=338059955 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_datapath_stress.338059955
Directory /workspace/15.hmac_datapath_stress/latest

Test location /workspace/coverage/default/15.hmac_error.14106490
Short name T749
Test name
Test status
Simulation time 8142789013 ps
CPU time 18.15 seconds
Started Jun 29 05:09:06 PM PDT 24
Finished Jun 29 05:09:25 PM PDT 24
Peak memory 200324 kb
Host smart-bfb681d9-47e3-4a35-bcfd-683ad447b07a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14106490 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_error.14106490
Directory /workspace/15.hmac_error/latest

Test location /workspace/coverage/default/15.hmac_long_msg.2308707329
Short name T223
Test name
Test status
Simulation time 9813096837 ps
CPU time 47.39 seconds
Started Jun 29 05:09:05 PM PDT 24
Finished Jun 29 05:09:53 PM PDT 24
Peak memory 200384 kb
Host smart-beda3514-fdf1-4bbf-bea8-f28063ac7111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308707329 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_long_msg.2308707329
Directory /workspace/15.hmac_long_msg/latest

Test location /workspace/coverage/default/15.hmac_smoke.684152219
Short name T505
Test name
Test status
Simulation time 439162156 ps
CPU time 11.71 seconds
Started Jun 29 05:09:10 PM PDT 24
Finished Jun 29 05:09:22 PM PDT 24
Peak memory 200288 kb
Host smart-d5bc6408-c66e-47b1-aeda-013b128116c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684152219 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_smoke.684152219
Directory /workspace/15.hmac_smoke/latest

Test location /workspace/coverage/default/15.hmac_stress_all.1375345653
Short name T417
Test name
Test status
Simulation time 101822094640 ps
CPU time 6531.18 seconds
Started Jun 29 05:09:03 PM PDT 24
Finished Jun 29 06:57:55 PM PDT 24
Peak memory 696284 kb
Host smart-b6fb2961-b5ed-428d-88cb-964a7d8b0ee4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375345653 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.hmac_stress_all.1375345653
Directory /workspace/15.hmac_stress_all/latest

Test location /workspace/coverage/default/15.hmac_test_hmac256_vectors.2286794945
Short name T675
Test name
Test status
Simulation time 4763406281 ps
CPU time 34.61 seconds
Started Jun 29 05:09:06 PM PDT 24
Finished Jun 29 05:09:42 PM PDT 24
Peak memory 200292 kb
Host smart-83e8e65e-482b-46ee-a6c1-338dd5855784
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2286794945 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_test_hmac256_vectors.2286794945
Directory /workspace/15.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/15.hmac_test_hmac384_vectors.2897359480
Short name T706
Test name
Test status
Simulation time 1547478654 ps
CPU time 47.31 seconds
Started Jun 29 05:09:06 PM PDT 24
Finished Jun 29 05:09:54 PM PDT 24
Peak memory 200196 kb
Host smart-768fb73f-345d-4b93-be7d-ee9fee99e0a8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2897359480 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_test_hmac384_vectors.2897359480
Directory /workspace/15.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/15.hmac_test_hmac512_vectors.194456145
Short name T392
Test name
Test status
Simulation time 12827527953 ps
CPU time 129.9 seconds
Started Jun 29 05:09:06 PM PDT 24
Finished Jun 29 05:11:17 PM PDT 24
Peak memory 200296 kb
Host smart-f98b5f27-cce2-497f-b228-773db1475fa2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=194456145 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_test_hmac512_vectors.194456145
Directory /workspace/15.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/15.hmac_test_sha256_vectors.3399701224
Short name T754
Test name
Test status
Simulation time 44263073487 ps
CPU time 561.9 seconds
Started Jun 29 05:09:08 PM PDT 24
Finished Jun 29 05:18:30 PM PDT 24
Peak memory 200488 kb
Host smart-403db4a6-4bc8-4904-8b41-766ab9095bfe
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3399701224 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_test_sha256_vectors.3399701224
Directory /workspace/15.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/15.hmac_test_sha384_vectors.3041149743
Short name T3
Test name
Test status
Simulation time 119620868347 ps
CPU time 1811.16 seconds
Started Jun 29 05:09:04 PM PDT 24
Finished Jun 29 05:39:15 PM PDT 24
Peak memory 216264 kb
Host smart-3f780026-862c-4970-93cc-32673d6e10b4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3041149743 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_test_sha384_vectors.3041149743
Directory /workspace/15.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/15.hmac_test_sha512_vectors.1214169444
Short name T555
Test name
Test status
Simulation time 128055837521 ps
CPU time 1828.15 seconds
Started Jun 29 05:09:10 PM PDT 24
Finished Jun 29 05:39:39 PM PDT 24
Peak memory 216272 kb
Host smart-9160ea06-26e8-46fa-9e55-7c1857fd828f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1214169444 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_test_sha512_vectors.1214169444
Directory /workspace/15.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/15.hmac_wipe_secret.320526723
Short name T151
Test name
Test status
Simulation time 839982478 ps
CPU time 42.41 seconds
Started Jun 29 05:09:06 PM PDT 24
Finished Jun 29 05:09:50 PM PDT 24
Peak memory 200292 kb
Host smart-ef2ef0bf-7f93-4dc4-b1ec-5b0f44e4902e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320526723 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_wipe_secret.320526723
Directory /workspace/15.hmac_wipe_secret/latest

Test location /workspace/coverage/default/16.hmac_back_pressure.3220320972
Short name T96
Test name
Test status
Simulation time 2491489561 ps
CPU time 21.45 seconds
Started Jun 29 05:09:13 PM PDT 24
Finished Jun 29 05:09:34 PM PDT 24
Peak memory 200316 kb
Host smart-9d8c8c72-92de-4bf8-997d-1b83d6dde425
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3220320972 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_back_pressure.3220320972
Directory /workspace/16.hmac_back_pressure/latest

Test location /workspace/coverage/default/16.hmac_burst_wr.3787055506
Short name T568
Test name
Test status
Simulation time 12638444741 ps
CPU time 62.63 seconds
Started Jun 29 05:09:12 PM PDT 24
Finished Jun 29 05:10:15 PM PDT 24
Peak memory 200284 kb
Host smart-78052863-2f7b-4f23-8508-d69a4a634667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787055506 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_burst_wr.3787055506
Directory /workspace/16.hmac_burst_wr/latest

Test location /workspace/coverage/default/16.hmac_datapath_stress.2769598015
Short name T770
Test name
Test status
Simulation time 5062201091 ps
CPU time 272.54 seconds
Started Jun 29 05:09:12 PM PDT 24
Finished Jun 29 05:13:45 PM PDT 24
Peak memory 479544 kb
Host smart-6fdee555-b28c-4b79-8340-4096594d2a0e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2769598015 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_datapath_stress.2769598015
Directory /workspace/16.hmac_datapath_stress/latest

Test location /workspace/coverage/default/16.hmac_error.3671321976
Short name T760
Test name
Test status
Simulation time 4491103413 ps
CPU time 130.33 seconds
Started Jun 29 05:09:13 PM PDT 24
Finished Jun 29 05:11:24 PM PDT 24
Peak memory 200324 kb
Host smart-3105ecfd-ce62-4d2f-ba9b-e311418d99b3
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671321976 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_error.3671321976
Directory /workspace/16.hmac_error/latest

Test location /workspace/coverage/default/16.hmac_long_msg.1402700354
Short name T51
Test name
Test status
Simulation time 7823853123 ps
CPU time 41.28 seconds
Started Jun 29 05:09:14 PM PDT 24
Finished Jun 29 05:09:56 PM PDT 24
Peak memory 200352 kb
Host smart-876d50e1-be0e-4f06-90ef-1e43f73293d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402700354 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_long_msg.1402700354
Directory /workspace/16.hmac_long_msg/latest

Test location /workspace/coverage/default/16.hmac_smoke.300557718
Short name T27
Test name
Test status
Simulation time 534136034 ps
CPU time 3.28 seconds
Started Jun 29 05:09:12 PM PDT 24
Finished Jun 29 05:09:16 PM PDT 24
Peak memory 200312 kb
Host smart-67e19608-b58e-42ee-8dc7-48c31b99795e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300557718 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_smoke.300557718
Directory /workspace/16.hmac_smoke/latest

Test location /workspace/coverage/default/16.hmac_stress_all.4118598972
Short name T288
Test name
Test status
Simulation time 981116225 ps
CPU time 23.88 seconds
Started Jun 29 05:09:13 PM PDT 24
Finished Jun 29 05:09:37 PM PDT 24
Peak memory 200260 kb
Host smart-22fb30d2-9044-489b-b472-8c58d4f04294
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118598972 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.hmac_stress_all.4118598972
Directory /workspace/16.hmac_stress_all/latest

Test location /workspace/coverage/default/16.hmac_test_hmac256_vectors.3238373374
Short name T339
Test name
Test status
Simulation time 5974123105 ps
CPU time 38.49 seconds
Started Jun 29 05:09:11 PM PDT 24
Finished Jun 29 05:09:50 PM PDT 24
Peak memory 200224 kb
Host smart-e8e3f5f4-898e-4c3e-bdce-5003c02e732c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3238373374 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_test_hmac256_vectors.3238373374
Directory /workspace/16.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/16.hmac_test_hmac384_vectors.3421721416
Short name T747
Test name
Test status
Simulation time 5736598825 ps
CPU time 91.34 seconds
Started Jun 29 05:09:16 PM PDT 24
Finished Jun 29 05:10:48 PM PDT 24
Peak memory 200332 kb
Host smart-39b7126d-92c6-42ba-808a-8aa77925dbfa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3421721416 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_test_hmac384_vectors.3421721416
Directory /workspace/16.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/16.hmac_test_hmac512_vectors.1304314231
Short name T173
Test name
Test status
Simulation time 10644549529 ps
CPU time 109.72 seconds
Started Jun 29 05:09:16 PM PDT 24
Finished Jun 29 05:11:07 PM PDT 24
Peak memory 200368 kb
Host smart-238dc2f2-fd7a-4cd5-bbfa-febe703f89df
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1304314231 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_test_hmac512_vectors.1304314231
Directory /workspace/16.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/16.hmac_test_sha256_vectors.713911636
Short name T688
Test name
Test status
Simulation time 28888289637 ps
CPU time 529.26 seconds
Started Jun 29 05:09:14 PM PDT 24
Finished Jun 29 05:18:04 PM PDT 24
Peak memory 200484 kb
Host smart-6b434f20-303b-45e4-9bbf-ac1159418863
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=713911636 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_test_sha256_vectors.713911636
Directory /workspace/16.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/16.hmac_test_sha384_vectors.4124687799
Short name T433
Test name
Test status
Simulation time 115282062029 ps
CPU time 1631.83 seconds
Started Jun 29 05:09:11 PM PDT 24
Finished Jun 29 05:36:24 PM PDT 24
Peak memory 215752 kb
Host smart-4145a523-20af-4f70-8367-c3896e155d9d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4124687799 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_test_sha384_vectors.4124687799
Directory /workspace/16.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/16.hmac_test_sha512_vectors.4268309825
Short name T531
Test name
Test status
Simulation time 104615529173 ps
CPU time 1940.03 seconds
Started Jun 29 05:09:12 PM PDT 24
Finished Jun 29 05:41:32 PM PDT 24
Peak memory 216648 kb
Host smart-4104e8e1-b1fa-4be0-a20b-bc74a4fb7965
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4268309825 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_test_sha512_vectors.4268309825
Directory /workspace/16.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/16.hmac_wipe_secret.3320887230
Short name T540
Test name
Test status
Simulation time 258696114 ps
CPU time 4 seconds
Started Jun 29 05:09:11 PM PDT 24
Finished Jun 29 05:09:15 PM PDT 24
Peak memory 200312 kb
Host smart-f5de3bcd-d145-4d67-8e8a-c047b3313aaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320887230 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_wipe_secret.3320887230
Directory /workspace/16.hmac_wipe_secret/latest

Test location /workspace/coverage/default/17.hmac_alert_test.2860560206
Short name T676
Test name
Test status
Simulation time 26983871 ps
CPU time 0.62 seconds
Started Jun 29 05:09:21 PM PDT 24
Finished Jun 29 05:09:22 PM PDT 24
Peak memory 196252 kb
Host smart-dc13a0e1-e6a2-4040-bd85-70b0b6170c50
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860560206 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_alert_test.2860560206
Directory /workspace/17.hmac_alert_test/latest

Test location /workspace/coverage/default/17.hmac_back_pressure.3341281318
Short name T21
Test name
Test status
Simulation time 1580503891 ps
CPU time 20.36 seconds
Started Jun 29 05:09:12 PM PDT 24
Finished Jun 29 05:09:33 PM PDT 24
Peak memory 200288 kb
Host smart-95fef29b-4a8f-4cb3-a21a-9d6b4587a733
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3341281318 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_back_pressure.3341281318
Directory /workspace/17.hmac_back_pressure/latest

Test location /workspace/coverage/default/17.hmac_burst_wr.1849784711
Short name T430
Test name
Test status
Simulation time 18023238371 ps
CPU time 36.38 seconds
Started Jun 29 05:09:21 PM PDT 24
Finished Jun 29 05:09:58 PM PDT 24
Peak memory 200348 kb
Host smart-ef5c12ee-2b8c-451c-b8a9-bfe1e42f6bcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849784711 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_burst_wr.1849784711
Directory /workspace/17.hmac_burst_wr/latest

Test location /workspace/coverage/default/17.hmac_datapath_stress.1619606368
Short name T729
Test name
Test status
Simulation time 157974888 ps
CPU time 2.44 seconds
Started Jun 29 05:09:16 PM PDT 24
Finished Jun 29 05:09:19 PM PDT 24
Peak memory 200268 kb
Host smart-8cf3be5c-bed3-4b47-91d7-32d5fdb1dfd2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1619606368 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_datapath_stress.1619606368
Directory /workspace/17.hmac_datapath_stress/latest

Test location /workspace/coverage/default/17.hmac_error.2462422407
Short name T538
Test name
Test status
Simulation time 2155478042 ps
CPU time 120.57 seconds
Started Jun 29 05:09:23 PM PDT 24
Finished Jun 29 05:11:24 PM PDT 24
Peak memory 200284 kb
Host smart-7bcb8b76-043c-4489-afa5-148c279965c8
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462422407 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_error.2462422407
Directory /workspace/17.hmac_error/latest

Test location /workspace/coverage/default/17.hmac_long_msg.2551976365
Short name T464
Test name
Test status
Simulation time 2006125551 ps
CPU time 105.41 seconds
Started Jun 29 05:09:13 PM PDT 24
Finished Jun 29 05:10:59 PM PDT 24
Peak memory 200228 kb
Host smart-f61a0ec6-8079-4170-992a-9548ac3249fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2551976365 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_long_msg.2551976365
Directory /workspace/17.hmac_long_msg/latest

Test location /workspace/coverage/default/17.hmac_smoke.502721252
Short name T331
Test name
Test status
Simulation time 167800211 ps
CPU time 2.64 seconds
Started Jun 29 05:09:11 PM PDT 24
Finished Jun 29 05:09:14 PM PDT 24
Peak memory 200136 kb
Host smart-2359488e-8e19-438d-a495-f201a832cca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502721252 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_smoke.502721252
Directory /workspace/17.hmac_smoke/latest

Test location /workspace/coverage/default/17.hmac_stress_all.1080464549
Short name T333
Test name
Test status
Simulation time 572826818680 ps
CPU time 5301.62 seconds
Started Jun 29 05:09:22 PM PDT 24
Finished Jun 29 06:37:45 PM PDT 24
Peak memory 610096 kb
Host smart-638aadff-84e4-4d64-8766-288410515ea3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080464549 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.hmac_stress_all.1080464549
Directory /workspace/17.hmac_stress_all/latest

Test location /workspace/coverage/default/17.hmac_test_hmac256_vectors.3628127908
Short name T725
Test name
Test status
Simulation time 4151134234 ps
CPU time 37.5 seconds
Started Jun 29 05:09:24 PM PDT 24
Finished Jun 29 05:10:02 PM PDT 24
Peak memory 200328 kb
Host smart-9d338cbf-4e7a-4a2e-90f2-a689ad630428
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3628127908 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_test_hmac256_vectors.3628127908
Directory /workspace/17.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/17.hmac_test_hmac384_vectors.280645986
Short name T452
Test name
Test status
Simulation time 10083381754 ps
CPU time 52.99 seconds
Started Jun 29 05:09:22 PM PDT 24
Finished Jun 29 05:10:15 PM PDT 24
Peak memory 200344 kb
Host smart-9faae987-450a-496c-9a9a-96c64ce9d491
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=280645986 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_test_hmac384_vectors.280645986
Directory /workspace/17.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/17.hmac_test_hmac512_vectors.896027713
Short name T52
Test name
Test status
Simulation time 11882084163 ps
CPU time 57.9 seconds
Started Jun 29 05:09:23 PM PDT 24
Finished Jun 29 05:10:21 PM PDT 24
Peak memory 200300 kb
Host smart-ab75519d-53a9-4ea9-af12-e61a33de3c92
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=896027713 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_test_hmac512_vectors.896027713
Directory /workspace/17.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/17.hmac_test_sha256_vectors.982686239
Short name T724
Test name
Test status
Simulation time 191763971791 ps
CPU time 543.57 seconds
Started Jun 29 05:09:24 PM PDT 24
Finished Jun 29 05:18:28 PM PDT 24
Peak memory 200276 kb
Host smart-7e57b4c5-f4d1-4313-819b-475b6c638b35
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=982686239 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_test_sha256_vectors.982686239
Directory /workspace/17.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/17.hmac_test_sha384_vectors.2636287608
Short name T13
Test name
Test status
Simulation time 210914810739 ps
CPU time 2239.94 seconds
Started Jun 29 05:09:20 PM PDT 24
Finished Jun 29 05:46:41 PM PDT 24
Peak memory 216312 kb
Host smart-31455171-e07a-462a-be8f-9bf7556a88a8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2636287608 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_test_sha384_vectors.2636287608
Directory /workspace/17.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/17.hmac_test_sha512_vectors.484334729
Short name T634
Test name
Test status
Simulation time 131437662470 ps
CPU time 1785.48 seconds
Started Jun 29 05:09:27 PM PDT 24
Finished Jun 29 05:39:13 PM PDT 24
Peak memory 215916 kb
Host smart-fba6485f-9ee7-4f8f-b738-c0900833400d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=484334729 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_test_sha512_vectors.484334729
Directory /workspace/17.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/17.hmac_wipe_secret.3200212516
Short name T718
Test name
Test status
Simulation time 1962048925 ps
CPU time 16.71 seconds
Started Jun 29 05:09:21 PM PDT 24
Finished Jun 29 05:09:38 PM PDT 24
Peak memory 200228 kb
Host smart-f389a8f2-d894-45fe-99aa-0c9c2fefd59a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200212516 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_wipe_secret.3200212516
Directory /workspace/17.hmac_wipe_secret/latest

Test location /workspace/coverage/default/18.hmac_alert_test.1828076541
Short name T413
Test name
Test status
Simulation time 13163992 ps
CPU time 0.56 seconds
Started Jun 29 05:09:29 PM PDT 24
Finished Jun 29 05:09:30 PM PDT 24
Peak memory 197004 kb
Host smart-696b8baf-27b0-411b-9091-114cc3b09475
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828076541 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_alert_test.1828076541
Directory /workspace/18.hmac_alert_test/latest

Test location /workspace/coverage/default/18.hmac_back_pressure.1868564989
Short name T684
Test name
Test status
Simulation time 675325319 ps
CPU time 20.26 seconds
Started Jun 29 05:09:23 PM PDT 24
Finished Jun 29 05:09:44 PM PDT 24
Peak memory 200204 kb
Host smart-fed805e2-63e7-4d17-af61-3f0d5bf0ef19
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1868564989 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_back_pressure.1868564989
Directory /workspace/18.hmac_back_pressure/latest

Test location /workspace/coverage/default/18.hmac_burst_wr.3789246387
Short name T759
Test name
Test status
Simulation time 349701723 ps
CPU time 19.35 seconds
Started Jun 29 05:09:20 PM PDT 24
Finished Jun 29 05:09:40 PM PDT 24
Peak memory 200236 kb
Host smart-6d93e184-8863-494c-9697-696370ffde87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789246387 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_burst_wr.3789246387
Directory /workspace/18.hmac_burst_wr/latest

Test location /workspace/coverage/default/18.hmac_datapath_stress.4191584069
Short name T494
Test name
Test status
Simulation time 25068124175 ps
CPU time 364.91 seconds
Started Jun 29 05:09:22 PM PDT 24
Finished Jun 29 05:15:28 PM PDT 24
Peak memory 658316 kb
Host smart-f3d088a3-8400-4be5-9d2b-0d4b60ef3457
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4191584069 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_datapath_stress.4191584069
Directory /workspace/18.hmac_datapath_stress/latest

Test location /workspace/coverage/default/18.hmac_error.4038818262
Short name T283
Test name
Test status
Simulation time 2930033113 ps
CPU time 53.41 seconds
Started Jun 29 05:09:27 PM PDT 24
Finished Jun 29 05:10:21 PM PDT 24
Peak memory 200456 kb
Host smart-8cbfa33f-076b-4f46-a0cb-04642a65639c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038818262 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_error.4038818262
Directory /workspace/18.hmac_error/latest

Test location /workspace/coverage/default/18.hmac_long_msg.3745882306
Short name T219
Test name
Test status
Simulation time 24032280304 ps
CPU time 65.77 seconds
Started Jun 29 05:09:21 PM PDT 24
Finished Jun 29 05:10:27 PM PDT 24
Peak memory 200360 kb
Host smart-8edfd36c-fcc4-4479-8763-0e91bd49124c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745882306 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_long_msg.3745882306
Directory /workspace/18.hmac_long_msg/latest

Test location /workspace/coverage/default/18.hmac_smoke.57240219
Short name T529
Test name
Test status
Simulation time 276562302 ps
CPU time 6.67 seconds
Started Jun 29 05:09:21 PM PDT 24
Finished Jun 29 05:09:28 PM PDT 24
Peak memory 200196 kb
Host smart-82741024-5dd3-4b83-bf88-ac66f9093cf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57240219 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_smoke.57240219
Directory /workspace/18.hmac_smoke/latest

Test location /workspace/coverage/default/18.hmac_stress_all.737380112
Short name T232
Test name
Test status
Simulation time 7590127398 ps
CPU time 120.09 seconds
Started Jun 29 05:09:33 PM PDT 24
Finished Jun 29 05:11:34 PM PDT 24
Peak memory 208544 kb
Host smart-a42ba33c-9ce5-4450-932b-543ee49c204c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737380112 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 18.hmac_stress_all.737380112
Directory /workspace/18.hmac_stress_all/latest

Test location /workspace/coverage/default/18.hmac_test_hmac256_vectors.1078440862
Short name T787
Test name
Test status
Simulation time 7660242232 ps
CPU time 63.51 seconds
Started Jun 29 05:09:28 PM PDT 24
Finished Jun 29 05:10:32 PM PDT 24
Peak memory 200332 kb
Host smart-bb75d195-4a59-4097-903f-f1a9b06bd8bc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1078440862 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_test_hmac256_vectors.1078440862
Directory /workspace/18.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/18.hmac_test_hmac384_vectors.3597046396
Short name T640
Test name
Test status
Simulation time 7676224031 ps
CPU time 87.89 seconds
Started Jun 29 05:09:30 PM PDT 24
Finished Jun 29 05:10:59 PM PDT 24
Peak memory 200368 kb
Host smart-ec294e0b-6362-40b7-87f7-61daeb72de0f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3597046396 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_test_hmac384_vectors.3597046396
Directory /workspace/18.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/18.hmac_test_hmac512_vectors.3566851587
Short name T370
Test name
Test status
Simulation time 3451090192 ps
CPU time 108.65 seconds
Started Jun 29 05:09:30 PM PDT 24
Finished Jun 29 05:11:19 PM PDT 24
Peak memory 200368 kb
Host smart-adea44d2-5d84-4396-9ec7-351903833f4d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3566851587 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_test_hmac512_vectors.3566851587
Directory /workspace/18.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/18.hmac_test_sha256_vectors.4241118743
Short name T761
Test name
Test status
Simulation time 36272377186 ps
CPU time 536.59 seconds
Started Jun 29 05:09:21 PM PDT 24
Finished Jun 29 05:18:18 PM PDT 24
Peak memory 200228 kb
Host smart-2263eae7-9240-4ddb-ad4f-0e2077ec5def
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=4241118743 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_test_sha256_vectors.4241118743
Directory /workspace/18.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/18.hmac_test_sha384_vectors.2870272445
Short name T513
Test name
Test status
Simulation time 163935383949 ps
CPU time 2041.15 seconds
Started Jun 29 05:09:21 PM PDT 24
Finished Jun 29 05:43:23 PM PDT 24
Peak memory 216664 kb
Host smart-0695e8df-7cd2-4133-aefc-5fe5841136c9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2870272445 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_test_sha384_vectors.2870272445
Directory /workspace/18.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/18.hmac_test_sha512_vectors.2333712910
Short name T514
Test name
Test status
Simulation time 31506200730 ps
CPU time 1890.15 seconds
Started Jun 29 05:09:20 PM PDT 24
Finished Jun 29 05:40:51 PM PDT 24
Peak memory 215776 kb
Host smart-3b1fb779-20e6-4e2b-b714-f75ef74fdd97
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2333712910 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_test_sha512_vectors.2333712910
Directory /workspace/18.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/18.hmac_wipe_secret.3214390096
Short name T639
Test name
Test status
Simulation time 19836618168 ps
CPU time 81.98 seconds
Started Jun 29 05:09:22 PM PDT 24
Finished Jun 29 05:10:44 PM PDT 24
Peak memory 200272 kb
Host smart-78c45522-e0ba-4542-9332-2b72b1d97c0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214390096 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_wipe_secret.3214390096
Directory /workspace/18.hmac_wipe_secret/latest

Test location /workspace/coverage/default/19.hmac_alert_test.4065448750
Short name T302
Test name
Test status
Simulation time 23077174 ps
CPU time 0.57 seconds
Started Jun 29 05:09:32 PM PDT 24
Finished Jun 29 05:09:33 PM PDT 24
Peak memory 195228 kb
Host smart-f6997e94-944c-4718-90e5-90371164283b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065448750 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_alert_test.4065448750
Directory /workspace/19.hmac_alert_test/latest

Test location /workspace/coverage/default/19.hmac_burst_wr.3080815206
Short name T419
Test name
Test status
Simulation time 2605163336 ps
CPU time 40.26 seconds
Started Jun 29 05:09:31 PM PDT 24
Finished Jun 29 05:10:12 PM PDT 24
Peak memory 200296 kb
Host smart-8598f9d4-c942-432e-881b-903e0976f8e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3080815206 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_burst_wr.3080815206
Directory /workspace/19.hmac_burst_wr/latest

Test location /workspace/coverage/default/19.hmac_datapath_stress.3479150436
Short name T294
Test name
Test status
Simulation time 3890312568 ps
CPU time 508.47 seconds
Started Jun 29 05:09:31 PM PDT 24
Finished Jun 29 05:18:01 PM PDT 24
Peak memory 690320 kb
Host smart-0c7422f9-18d2-49f2-ab1f-a65d74de75ca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3479150436 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_datapath_stress.3479150436
Directory /workspace/19.hmac_datapath_stress/latest

Test location /workspace/coverage/default/19.hmac_error.2306710261
Short name T453
Test name
Test status
Simulation time 13259530024 ps
CPU time 79.72 seconds
Started Jun 29 05:09:30 PM PDT 24
Finished Jun 29 05:10:51 PM PDT 24
Peak memory 200260 kb
Host smart-9988cba2-687e-45e1-b964-d0dc18ecd181
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306710261 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_error.2306710261
Directory /workspace/19.hmac_error/latest

Test location /workspace/coverage/default/19.hmac_long_msg.777270741
Short name T583
Test name
Test status
Simulation time 44352069785 ps
CPU time 53.41 seconds
Started Jun 29 05:09:29 PM PDT 24
Finished Jun 29 05:10:22 PM PDT 24
Peak memory 200380 kb
Host smart-6d9c79ce-cb33-48ab-92f4-705f92b8b2d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777270741 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_long_msg.777270741
Directory /workspace/19.hmac_long_msg/latest

Test location /workspace/coverage/default/19.hmac_smoke.4029677468
Short name T629
Test name
Test status
Simulation time 302276227 ps
CPU time 10.98 seconds
Started Jun 29 05:09:29 PM PDT 24
Finished Jun 29 05:09:41 PM PDT 24
Peak memory 200284 kb
Host smart-2217f202-3da5-4e64-936d-5383acd4d41b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029677468 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_smoke.4029677468
Directory /workspace/19.hmac_smoke/latest

Test location /workspace/coverage/default/19.hmac_stress_all.1908883835
Short name T125
Test name
Test status
Simulation time 2346190201 ps
CPU time 71.04 seconds
Started Jun 29 05:09:29 PM PDT 24
Finished Jun 29 05:10:40 PM PDT 24
Peak memory 200340 kb
Host smart-21496a66-532d-444a-af91-53df7b4682b0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908883835 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.hmac_stress_all.1908883835
Directory /workspace/19.hmac_stress_all/latest

Test location /workspace/coverage/default/19.hmac_test_hmac256_vectors.2433222676
Short name T556
Test name
Test status
Simulation time 7702837264 ps
CPU time 34.23 seconds
Started Jun 29 05:09:30 PM PDT 24
Finished Jun 29 05:10:05 PM PDT 24
Peak memory 200248 kb
Host smart-03bce1af-8b3a-4795-84a0-e089d5b6dc4a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2433222676 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_test_hmac256_vectors.2433222676
Directory /workspace/19.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/19.hmac_test_hmac384_vectors.3996299323
Short name T337
Test name
Test status
Simulation time 8009124968 ps
CPU time 72.81 seconds
Started Jun 29 05:09:31 PM PDT 24
Finished Jun 29 05:10:45 PM PDT 24
Peak memory 200332 kb
Host smart-98a88c8d-bcda-4d2e-ad8b-dadfcfeaa168
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3996299323 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_test_hmac384_vectors.3996299323
Directory /workspace/19.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/19.hmac_test_hmac512_vectors.682316904
Short name T361
Test name
Test status
Simulation time 14033164054 ps
CPU time 58.96 seconds
Started Jun 29 05:09:31 PM PDT 24
Finished Jun 29 05:10:30 PM PDT 24
Peak memory 200340 kb
Host smart-d3a2d027-3a34-4caa-8bea-392bf2f26f6a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=682316904 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_test_hmac512_vectors.682316904
Directory /workspace/19.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/19.hmac_test_sha256_vectors.826058035
Short name T439
Test name
Test status
Simulation time 8166558418 ps
CPU time 460.17 seconds
Started Jun 29 05:09:31 PM PDT 24
Finished Jun 29 05:17:12 PM PDT 24
Peak memory 200252 kb
Host smart-ac767e8b-7657-4ac7-9a01-95a63a0acc1c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=826058035 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_test_sha256_vectors.826058035
Directory /workspace/19.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/19.hmac_test_sha384_vectors.2984840043
Short name T548
Test name
Test status
Simulation time 207420845559 ps
CPU time 1798.27 seconds
Started Jun 29 05:09:32 PM PDT 24
Finished Jun 29 05:39:31 PM PDT 24
Peak memory 215952 kb
Host smart-9d9167f8-07cd-4ea6-af5c-7d7febc738f3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2984840043 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_test_sha384_vectors.2984840043
Directory /workspace/19.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/19.hmac_test_sha512_vectors.658661519
Short name T463
Test name
Test status
Simulation time 62667841915 ps
CPU time 1810.62 seconds
Started Jun 29 05:09:31 PM PDT 24
Finished Jun 29 05:39:42 PM PDT 24
Peak memory 215872 kb
Host smart-120b5931-26c5-470f-89cc-91fc9897983a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=658661519 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_test_sha512_vectors.658661519
Directory /workspace/19.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/19.hmac_wipe_secret.205368036
Short name T90
Test name
Test status
Simulation time 2615155554 ps
CPU time 37.75 seconds
Started Jun 29 05:09:30 PM PDT 24
Finished Jun 29 05:10:08 PM PDT 24
Peak memory 200344 kb
Host smart-afc0d90c-540c-48e1-baee-015105d2f9b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205368036 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_wipe_secret.205368036
Directory /workspace/19.hmac_wipe_secret/latest

Test location /workspace/coverage/default/2.hmac_alert_test.2688500819
Short name T631
Test name
Test status
Simulation time 45161365 ps
CPU time 0.58 seconds
Started Jun 29 05:08:09 PM PDT 24
Finished Jun 29 05:08:10 PM PDT 24
Peak memory 195228 kb
Host smart-6226b2c4-93d9-443a-a4ac-db09da1cca0e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688500819 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_alert_test.2688500819
Directory /workspace/2.hmac_alert_test/latest

Test location /workspace/coverage/default/2.hmac_back_pressure.1990002750
Short name T243
Test name
Test status
Simulation time 132241871 ps
CPU time 1.77 seconds
Started Jun 29 05:08:13 PM PDT 24
Finished Jun 29 05:08:15 PM PDT 24
Peak memory 200112 kb
Host smart-d7150b94-3d33-458b-8be6-7e7852501b7f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1990002750 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_back_pressure.1990002750
Directory /workspace/2.hmac_back_pressure/latest

Test location /workspace/coverage/default/2.hmac_burst_wr.2031275720
Short name T563
Test name
Test status
Simulation time 11588508191 ps
CPU time 35.73 seconds
Started Jun 29 05:08:11 PM PDT 24
Finished Jun 29 05:08:48 PM PDT 24
Peak memory 200400 kb
Host smart-eecead09-275f-41a3-9aa2-b473e020dde2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031275720 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_burst_wr.2031275720
Directory /workspace/2.hmac_burst_wr/latest

Test location /workspace/coverage/default/2.hmac_datapath_stress.4014596092
Short name T403
Test name
Test status
Simulation time 3007790793 ps
CPU time 392.07 seconds
Started Jun 29 05:08:12 PM PDT 24
Finished Jun 29 05:14:44 PM PDT 24
Peak memory 710124 kb
Host smart-1db8fe54-8be3-46bb-96fa-92efc3e76432
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4014596092 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_datapath_stress.4014596092
Directory /workspace/2.hmac_datapath_stress/latest

Test location /workspace/coverage/default/2.hmac_error.3388449211
Short name T693
Test name
Test status
Simulation time 32918863635 ps
CPU time 101.4 seconds
Started Jun 29 05:08:11 PM PDT 24
Finished Jun 29 05:09:53 PM PDT 24
Peak memory 200264 kb
Host smart-453188a7-3238-4d72-ba49-fcc8a4af30c0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388449211 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_error.3388449211
Directory /workspace/2.hmac_error/latest

Test location /workspace/coverage/default/2.hmac_sec_cm.4231278200
Short name T43
Test name
Test status
Simulation time 92631586 ps
CPU time 1.02 seconds
Started Jun 29 05:08:12 PM PDT 24
Finished Jun 29 05:08:13 PM PDT 24
Peak memory 219716 kb
Host smart-9e6a33eb-cd2b-4194-a52f-c1c2121a489f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231278200 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_sec_cm.4231278200
Directory /workspace/2.hmac_sec_cm/latest

Test location /workspace/coverage/default/2.hmac_smoke.2108402654
Short name T260
Test name
Test status
Simulation time 3244532117 ps
CPU time 15.96 seconds
Started Jun 29 05:08:09 PM PDT 24
Finished Jun 29 05:08:26 PM PDT 24
Peak memory 200348 kb
Host smart-e2cbd0d3-ef63-4f6a-a5d3-6037917329c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108402654 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_smoke.2108402654
Directory /workspace/2.hmac_smoke/latest

Test location /workspace/coverage/default/2.hmac_stress_all.316686754
Short name T704
Test name
Test status
Simulation time 57994357652 ps
CPU time 5557.72 seconds
Started Jun 29 05:08:15 PM PDT 24
Finished Jun 29 06:40:53 PM PDT 24
Peak memory 812444 kb
Host smart-35549815-94ca-4f7f-823f-0f6ea08c5714
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316686754 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all.316686754
Directory /workspace/2.hmac_stress_all/latest

Test location /workspace/coverage/default/2.hmac_test_hmac256_vectors.2278519979
Short name T601
Test name
Test status
Simulation time 1555177271 ps
CPU time 63.82 seconds
Started Jun 29 05:08:18 PM PDT 24
Finished Jun 29 05:09:22 PM PDT 24
Peak memory 200308 kb
Host smart-09bfee05-b314-4aa5-9c23-3e4bd5bd85c8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2278519979 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac256_vectors.2278519979
Directory /workspace/2.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_hmac384_vectors.1941290105
Short name T506
Test name
Test status
Simulation time 19150758262 ps
CPU time 53.44 seconds
Started Jun 29 05:08:14 PM PDT 24
Finished Jun 29 05:09:08 PM PDT 24
Peak memory 200224 kb
Host smart-eec6f427-d6ef-44f0-becb-f9baccaf2872
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1941290105 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac384_vectors.1941290105
Directory /workspace/2.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_hmac512_vectors.3030264092
Short name T272
Test name
Test status
Simulation time 3806091460 ps
CPU time 62.11 seconds
Started Jun 29 05:08:16 PM PDT 24
Finished Jun 29 05:09:18 PM PDT 24
Peak memory 200332 kb
Host smart-b2b7e643-b37b-4a8d-9255-2cbb16428d67
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3030264092 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac512_vectors.3030264092
Directory /workspace/2.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha256_vectors.2130665917
Short name T250
Test name
Test status
Simulation time 8031197633 ps
CPU time 418.37 seconds
Started Jun 29 05:08:12 PM PDT 24
Finished Jun 29 05:15:11 PM PDT 24
Peak memory 200240 kb
Host smart-e5531b92-4502-4ca7-94b2-418a289143fb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2130665917 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha256_vectors.2130665917
Directory /workspace/2.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha384_vectors.1581169907
Short name T643
Test name
Test status
Simulation time 215409140755 ps
CPU time 1985.63 seconds
Started Jun 29 05:08:13 PM PDT 24
Finished Jun 29 05:41:19 PM PDT 24
Peak memory 215700 kb
Host smart-b0c9b7e9-0701-4cba-be90-83f24cb1f30f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1581169907 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha384_vectors.1581169907
Directory /workspace/2.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha512_vectors.490627885
Short name T359
Test name
Test status
Simulation time 549761398524 ps
CPU time 1956.81 seconds
Started Jun 29 05:08:11 PM PDT 24
Finished Jun 29 05:40:49 PM PDT 24
Peak memory 216576 kb
Host smart-c4f555ff-c1a5-4426-9654-307e29d8f2b9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=490627885 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha512_vectors.490627885
Directory /workspace/2.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/2.hmac_wipe_secret.938649641
Short name T700
Test name
Test status
Simulation time 3287680955 ps
CPU time 29.57 seconds
Started Jun 29 05:08:11 PM PDT 24
Finished Jun 29 05:08:41 PM PDT 24
Peak memory 200364 kb
Host smart-ff19be32-aa29-47da-bf50-5daa09012f70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938649641 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_wipe_secret.938649641
Directory /workspace/2.hmac_wipe_secret/latest

Test location /workspace/coverage/default/20.hmac_alert_test.1570820171
Short name T363
Test name
Test status
Simulation time 11848382 ps
CPU time 0.6 seconds
Started Jun 29 05:09:37 PM PDT 24
Finished Jun 29 05:09:38 PM PDT 24
Peak memory 196180 kb
Host smart-88dd8df8-c444-40cf-bebf-6e23deacc862
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570820171 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_alert_test.1570820171
Directory /workspace/20.hmac_alert_test/latest

Test location /workspace/coverage/default/20.hmac_back_pressure.1249816543
Short name T679
Test name
Test status
Simulation time 18750517546 ps
CPU time 48.93 seconds
Started Jun 29 05:09:30 PM PDT 24
Finished Jun 29 05:10:19 PM PDT 24
Peak memory 200288 kb
Host smart-c7f7b939-92df-4ff7-8bb0-c578b0dc8e52
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1249816543 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_back_pressure.1249816543
Directory /workspace/20.hmac_back_pressure/latest

Test location /workspace/coverage/default/20.hmac_burst_wr.3806081524
Short name T311
Test name
Test status
Simulation time 228222832 ps
CPU time 12.33 seconds
Started Jun 29 05:09:38 PM PDT 24
Finished Jun 29 05:09:50 PM PDT 24
Peak memory 200236 kb
Host smart-8e8919e9-068e-47eb-bcc6-e42aa4040938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806081524 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_burst_wr.3806081524
Directory /workspace/20.hmac_burst_wr/latest

Test location /workspace/coverage/default/20.hmac_datapath_stress.210142084
Short name T501
Test name
Test status
Simulation time 1084610347 ps
CPU time 149.28 seconds
Started Jun 29 05:09:38 PM PDT 24
Finished Jun 29 05:12:08 PM PDT 24
Peak memory 613728 kb
Host smart-289a9ff6-c7c1-439e-8692-ed5a4ff7eb58
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=210142084 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_datapath_stress.210142084
Directory /workspace/20.hmac_datapath_stress/latest

Test location /workspace/coverage/default/20.hmac_error.1395828200
Short name T782
Test name
Test status
Simulation time 10811489359 ps
CPU time 158.89 seconds
Started Jun 29 05:09:37 PM PDT 24
Finished Jun 29 05:12:17 PM PDT 24
Peak memory 200252 kb
Host smart-bcf5fa3f-3c80-4d84-b02c-a2e564a2a9d8
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395828200 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_error.1395828200
Directory /workspace/20.hmac_error/latest

Test location /workspace/coverage/default/20.hmac_long_msg.3667675048
Short name T366
Test name
Test status
Simulation time 38418562709 ps
CPU time 154.25 seconds
Started Jun 29 05:09:31 PM PDT 24
Finished Jun 29 05:12:06 PM PDT 24
Peak memory 216632 kb
Host smart-920314b6-b850-484c-8d9e-42c4762f1eaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667675048 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_long_msg.3667675048
Directory /workspace/20.hmac_long_msg/latest

Test location /workspace/coverage/default/20.hmac_smoke.1903730925
Short name T245
Test name
Test status
Simulation time 3126006283 ps
CPU time 17.55 seconds
Started Jun 29 05:09:31 PM PDT 24
Finished Jun 29 05:09:49 PM PDT 24
Peak memory 200288 kb
Host smart-b0dcbcca-88ec-4d98-ab9e-679e1d63e1f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1903730925 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_smoke.1903730925
Directory /workspace/20.hmac_smoke/latest

Test location /workspace/coverage/default/20.hmac_stress_all.489202536
Short name T530
Test name
Test status
Simulation time 320332232708 ps
CPU time 5846.12 seconds
Started Jun 29 05:09:38 PM PDT 24
Finished Jun 29 06:47:05 PM PDT 24
Peak memory 742276 kb
Host smart-4c4f9809-9f27-4b2f-887d-bead6d3fe719
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489202536 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 20.hmac_stress_all.489202536
Directory /workspace/20.hmac_stress_all/latest

Test location /workspace/coverage/default/20.hmac_test_hmac256_vectors.2295866569
Short name T594
Test name
Test status
Simulation time 6989568407 ps
CPU time 61.56 seconds
Started Jun 29 05:09:41 PM PDT 24
Finished Jun 29 05:10:43 PM PDT 24
Peak memory 200264 kb
Host smart-0e676eef-a784-442a-a883-4c263df4c561
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2295866569 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_test_hmac256_vectors.2295866569
Directory /workspace/20.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/20.hmac_test_hmac384_vectors.3742329632
Short name T573
Test name
Test status
Simulation time 2062344093 ps
CPU time 75.74 seconds
Started Jun 29 05:09:39 PM PDT 24
Finished Jun 29 05:10:55 PM PDT 24
Peak memory 200184 kb
Host smart-fdba31bf-3b10-4994-a576-755d45ca7015
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3742329632 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_test_hmac384_vectors.3742329632
Directory /workspace/20.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/20.hmac_test_hmac512_vectors.925529588
Short name T447
Test name
Test status
Simulation time 8151977840 ps
CPU time 65.53 seconds
Started Jun 29 05:09:38 PM PDT 24
Finished Jun 29 05:10:45 PM PDT 24
Peak memory 200332 kb
Host smart-8ffb1408-ac0e-43c0-90c8-f70f7411f01a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=925529588 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_test_hmac512_vectors.925529588
Directory /workspace/20.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/20.hmac_test_sha256_vectors.1226416592
Short name T341
Test name
Test status
Simulation time 39760713447 ps
CPU time 519.22 seconds
Started Jun 29 05:09:38 PM PDT 24
Finished Jun 29 05:18:18 PM PDT 24
Peak memory 200300 kb
Host smart-cb030954-ad39-4c91-8b10-3985c8e3736c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1226416592 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_test_sha256_vectors.1226416592
Directory /workspace/20.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/20.hmac_test_sha384_vectors.1545093717
Short name T781
Test name
Test status
Simulation time 281113386950 ps
CPU time 2128.31 seconds
Started Jun 29 05:09:38 PM PDT 24
Finished Jun 29 05:45:07 PM PDT 24
Peak memory 216640 kb
Host smart-af9e02e7-da59-468d-83a4-5fa78d8b33e2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1545093717 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_test_sha384_vectors.1545093717
Directory /workspace/20.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/20.hmac_test_sha512_vectors.2218914478
Short name T632
Test name
Test status
Simulation time 145684186213 ps
CPU time 1805.93 seconds
Started Jun 29 05:09:39 PM PDT 24
Finished Jun 29 05:39:46 PM PDT 24
Peak memory 216184 kb
Host smart-119b32a4-f1c8-43a3-b381-55eb79c35241
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2218914478 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_test_sha512_vectors.2218914478
Directory /workspace/20.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/20.hmac_wipe_secret.958805599
Short name T705
Test name
Test status
Simulation time 181019023 ps
CPU time 3.6 seconds
Started Jun 29 05:09:38 PM PDT 24
Finished Jun 29 05:09:43 PM PDT 24
Peak memory 200192 kb
Host smart-54e7562a-833d-4b7b-8156-d17c962eedec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958805599 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_wipe_secret.958805599
Directory /workspace/20.hmac_wipe_secret/latest

Test location /workspace/coverage/default/21.hmac_alert_test.2936014919
Short name T267
Test name
Test status
Simulation time 21963841 ps
CPU time 0.6 seconds
Started Jun 29 05:09:49 PM PDT 24
Finished Jun 29 05:09:50 PM PDT 24
Peak memory 196320 kb
Host smart-e751a970-65f9-41f9-a5ff-e1858b1f419a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936014919 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_alert_test.2936014919
Directory /workspace/21.hmac_alert_test/latest

Test location /workspace/coverage/default/21.hmac_back_pressure.2901655952
Short name T149
Test name
Test status
Simulation time 1072326700 ps
CPU time 49.92 seconds
Started Jun 29 05:09:38 PM PDT 24
Finished Jun 29 05:10:29 PM PDT 24
Peak memory 200280 kb
Host smart-db4fe7b8-87c5-405a-8558-b789397f066c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2901655952 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_back_pressure.2901655952
Directory /workspace/21.hmac_back_pressure/latest

Test location /workspace/coverage/default/21.hmac_burst_wr.4257389143
Short name T185
Test name
Test status
Simulation time 2269855893 ps
CPU time 31.31 seconds
Started Jun 29 05:09:38 PM PDT 24
Finished Jun 29 05:10:10 PM PDT 24
Peak memory 200312 kb
Host smart-b2937400-3392-46be-a640-5a7f0fba7150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257389143 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_burst_wr.4257389143
Directory /workspace/21.hmac_burst_wr/latest

Test location /workspace/coverage/default/21.hmac_datapath_stress.2046452904
Short name T627
Test name
Test status
Simulation time 3233209581 ps
CPU time 838.9 seconds
Started Jun 29 05:09:39 PM PDT 24
Finished Jun 29 05:23:39 PM PDT 24
Peak memory 694500 kb
Host smart-749d694b-7f2b-4ee3-9e43-d1e49e03d0ef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2046452904 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_datapath_stress.2046452904
Directory /workspace/21.hmac_datapath_stress/latest

Test location /workspace/coverage/default/21.hmac_error.2975042223
Short name T719
Test name
Test status
Simulation time 8111025506 ps
CPU time 133.53 seconds
Started Jun 29 05:09:40 PM PDT 24
Finished Jun 29 05:11:54 PM PDT 24
Peak memory 200260 kb
Host smart-653fcd77-5b95-40e4-87b5-d5bbba613c61
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975042223 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_error.2975042223
Directory /workspace/21.hmac_error/latest

Test location /workspace/coverage/default/21.hmac_long_msg.2458707202
Short name T733
Test name
Test status
Simulation time 1804119064 ps
CPU time 103.98 seconds
Started Jun 29 05:09:38 PM PDT 24
Finished Jun 29 05:11:23 PM PDT 24
Peak memory 200268 kb
Host smart-a85017e3-9376-4873-80f7-303296a515f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458707202 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_long_msg.2458707202
Directory /workspace/21.hmac_long_msg/latest

Test location /workspace/coverage/default/21.hmac_smoke.2437851721
Short name T536
Test name
Test status
Simulation time 746183904 ps
CPU time 5.49 seconds
Started Jun 29 05:09:37 PM PDT 24
Finished Jun 29 05:09:43 PM PDT 24
Peak memory 200220 kb
Host smart-6e66bffe-8e42-4071-a1ba-fb567b18a85f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437851721 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_smoke.2437851721
Directory /workspace/21.hmac_smoke/latest

Test location /workspace/coverage/default/21.hmac_stress_all.1139530421
Short name T488
Test name
Test status
Simulation time 30283378708 ps
CPU time 1323.64 seconds
Started Jun 29 05:09:48 PM PDT 24
Finished Jun 29 05:31:52 PM PDT 24
Peak memory 775616 kb
Host smart-2482fbd0-7a7d-418f-8877-28ae57ce7645
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139530421 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.hmac_stress_all.1139530421
Directory /workspace/21.hmac_stress_all/latest

Test location /workspace/coverage/default/21.hmac_test_hmac256_vectors.88836203
Short name T394
Test name
Test status
Simulation time 2572135584 ps
CPU time 31.36 seconds
Started Jun 29 05:09:38 PM PDT 24
Finished Jun 29 05:10:11 PM PDT 24
Peak memory 200328 kb
Host smart-57707963-a8ac-44ab-8aa8-42a5a532c9f0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=88836203 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_test_hmac256_vectors.88836203
Directory /workspace/21.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/21.hmac_test_hmac384_vectors.599655561
Short name T788
Test name
Test status
Simulation time 12652900303 ps
CPU time 46.42 seconds
Started Jun 29 05:09:37 PM PDT 24
Finished Jun 29 05:10:24 PM PDT 24
Peak memory 200304 kb
Host smart-34fdf9f7-4e15-4b55-972a-e8c6c6a6c592
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=599655561 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_test_hmac384_vectors.599655561
Directory /workspace/21.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/21.hmac_test_hmac512_vectors.645047876
Short name T264
Test name
Test status
Simulation time 6548941287 ps
CPU time 102.34 seconds
Started Jun 29 05:09:41 PM PDT 24
Finished Jun 29 05:11:24 PM PDT 24
Peak memory 200264 kb
Host smart-6e4190ce-78d8-43b1-9d99-c1fdcf731e9c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=645047876 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_test_hmac512_vectors.645047876
Directory /workspace/21.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/21.hmac_test_sha256_vectors.3560933050
Short name T380
Test name
Test status
Simulation time 30556105533 ps
CPU time 548.3 seconds
Started Jun 29 05:09:38 PM PDT 24
Finished Jun 29 05:18:47 PM PDT 24
Peak memory 200292 kb
Host smart-af889b05-79f2-4d43-9d82-061669979b08
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3560933050 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_test_sha256_vectors.3560933050
Directory /workspace/21.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/21.hmac_test_sha384_vectors.2241447763
Short name T581
Test name
Test status
Simulation time 110758549393 ps
CPU time 2019.54 seconds
Started Jun 29 05:09:39 PM PDT 24
Finished Jun 29 05:43:20 PM PDT 24
Peak memory 215868 kb
Host smart-648b2fc5-fb90-42dc-a554-3d8e79f77daa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2241447763 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_test_sha384_vectors.2241447763
Directory /workspace/21.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/21.hmac_wipe_secret.1261048984
Short name T355
Test name
Test status
Simulation time 15839785389 ps
CPU time 106.38 seconds
Started Jun 29 05:09:39 PM PDT 24
Finished Jun 29 05:11:26 PM PDT 24
Peak memory 200304 kb
Host smart-876f2783-a291-407c-beee-7f07706b1656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1261048984 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_wipe_secret.1261048984
Directory /workspace/21.hmac_wipe_secret/latest

Test location /workspace/coverage/default/22.hmac_alert_test.574503908
Short name T36
Test name
Test status
Simulation time 20333213 ps
CPU time 0.62 seconds
Started Jun 29 05:09:48 PM PDT 24
Finished Jun 29 05:09:50 PM PDT 24
Peak memory 196248 kb
Host smart-c35bf476-f35f-44da-8d85-adf8f0fdb09d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574503908 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_alert_test.574503908
Directory /workspace/22.hmac_alert_test/latest

Test location /workspace/coverage/default/22.hmac_back_pressure.2499348265
Short name T618
Test name
Test status
Simulation time 1754616546 ps
CPU time 17.84 seconds
Started Jun 29 05:09:52 PM PDT 24
Finished Jun 29 05:10:10 PM PDT 24
Peak memory 200264 kb
Host smart-ace41567-33b1-46bc-a89a-269d4e2c8b22
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2499348265 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_back_pressure.2499348265
Directory /workspace/22.hmac_back_pressure/latest

Test location /workspace/coverage/default/22.hmac_burst_wr.2938269549
Short name T404
Test name
Test status
Simulation time 15886696801 ps
CPU time 31.18 seconds
Started Jun 29 05:09:47 PM PDT 24
Finished Jun 29 05:10:18 PM PDT 24
Peak memory 200392 kb
Host smart-c27f6e21-651c-4ea6-a20f-92484eda89f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938269549 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_burst_wr.2938269549
Directory /workspace/22.hmac_burst_wr/latest

Test location /workspace/coverage/default/22.hmac_datapath_stress.3919120881
Short name T621
Test name
Test status
Simulation time 6989506531 ps
CPU time 914.43 seconds
Started Jun 29 05:09:48 PM PDT 24
Finished Jun 29 05:25:03 PM PDT 24
Peak memory 721312 kb
Host smart-e60941c9-ebbb-4d69-a645-78c41091f0a0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3919120881 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_datapath_stress.3919120881
Directory /workspace/22.hmac_datapath_stress/latest

Test location /workspace/coverage/default/22.hmac_error.4182072643
Short name T550
Test name
Test status
Simulation time 6705344451 ps
CPU time 80.96 seconds
Started Jun 29 05:09:48 PM PDT 24
Finished Jun 29 05:11:10 PM PDT 24
Peak memory 200324 kb
Host smart-41eae7ac-9557-449c-b880-22ebcbbc169b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182072643 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_error.4182072643
Directory /workspace/22.hmac_error/latest

Test location /workspace/coverage/default/22.hmac_long_msg.756474118
Short name T717
Test name
Test status
Simulation time 2680482145 ps
CPU time 49.05 seconds
Started Jun 29 05:09:47 PM PDT 24
Finished Jun 29 05:10:36 PM PDT 24
Peak memory 200328 kb
Host smart-18388ef3-16a0-421c-ad82-c38261f6f0ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756474118 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_long_msg.756474118
Directory /workspace/22.hmac_long_msg/latest

Test location /workspace/coverage/default/22.hmac_smoke.3712627745
Short name T205
Test name
Test status
Simulation time 65676173 ps
CPU time 1.62 seconds
Started Jun 29 05:09:48 PM PDT 24
Finished Jun 29 05:09:50 PM PDT 24
Peak memory 200268 kb
Host smart-dfeb5bfe-09d5-4601-9dd0-206855bbe6a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712627745 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_smoke.3712627745
Directory /workspace/22.hmac_smoke/latest

Test location /workspace/coverage/default/22.hmac_stress_all.3743606665
Short name T521
Test name
Test status
Simulation time 94761696 ps
CPU time 0.64 seconds
Started Jun 29 05:09:48 PM PDT 24
Finished Jun 29 05:09:50 PM PDT 24
Peak memory 195924 kb
Host smart-80ec061f-a6fe-49a7-8df7-791437b0645d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743606665 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.hmac_stress_all.3743606665
Directory /workspace/22.hmac_stress_all/latest

Test location /workspace/coverage/default/22.hmac_test_hmac256_vectors.1300740721
Short name T686
Test name
Test status
Simulation time 12572569789 ps
CPU time 41.91 seconds
Started Jun 29 05:09:48 PM PDT 24
Finished Jun 29 05:10:31 PM PDT 24
Peak memory 200364 kb
Host smart-417fbe03-8be8-4e56-90b1-462b754651ed
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1300740721 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_test_hmac256_vectors.1300740721
Directory /workspace/22.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/22.hmac_test_hmac384_vectors.3415360448
Short name T196
Test name
Test status
Simulation time 11515704628 ps
CPU time 41.37 seconds
Started Jun 29 05:09:46 PM PDT 24
Finished Jun 29 05:10:28 PM PDT 24
Peak memory 200320 kb
Host smart-24298914-49da-49a3-be30-bb3be2f398fc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3415360448 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_test_hmac384_vectors.3415360448
Directory /workspace/22.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/22.hmac_test_hmac512_vectors.3913320703
Short name T29
Test name
Test status
Simulation time 25450948281 ps
CPU time 56.71 seconds
Started Jun 29 05:09:49 PM PDT 24
Finished Jun 29 05:10:46 PM PDT 24
Peak memory 200284 kb
Host smart-1eb323a5-a46f-4230-9649-020ff5d5788f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3913320703 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_test_hmac512_vectors.3913320703
Directory /workspace/22.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/22.hmac_test_sha256_vectors.1518875848
Short name T603
Test name
Test status
Simulation time 9293492272 ps
CPU time 522.1 seconds
Started Jun 29 05:09:48 PM PDT 24
Finished Jun 29 05:18:30 PM PDT 24
Peak memory 200264 kb
Host smart-f8862df3-9b37-485a-858a-5faa8a688290
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1518875848 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_test_sha256_vectors.1518875848
Directory /workspace/22.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/22.hmac_test_sha384_vectors.4293243011
Short name T415
Test name
Test status
Simulation time 175562043710 ps
CPU time 1948.38 seconds
Started Jun 29 05:09:48 PM PDT 24
Finished Jun 29 05:42:18 PM PDT 24
Peak memory 216084 kb
Host smart-b949a56c-6e71-4d6a-ad9b-2729a505ac3f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4293243011 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_test_sha384_vectors.4293243011
Directory /workspace/22.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/22.hmac_test_sha512_vectors.3312115148
Short name T539
Test name
Test status
Simulation time 106914217791 ps
CPU time 1885.33 seconds
Started Jun 29 05:09:56 PM PDT 24
Finished Jun 29 05:41:21 PM PDT 24
Peak memory 215764 kb
Host smart-8de052e1-9a8b-4a3a-992f-95d095361ff5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3312115148 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_test_sha512_vectors.3312115148
Directory /workspace/22.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/22.hmac_wipe_secret.2263243531
Short name T2
Test name
Test status
Simulation time 1767490770 ps
CPU time 9.9 seconds
Started Jun 29 05:09:49 PM PDT 24
Finished Jun 29 05:10:00 PM PDT 24
Peak memory 200256 kb
Host smart-a2e97e88-caf3-428f-a059-354f116135a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263243531 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_wipe_secret.2263243531
Directory /workspace/22.hmac_wipe_secret/latest

Test location /workspace/coverage/default/23.hmac_alert_test.2096595510
Short name T549
Test name
Test status
Simulation time 21278708 ps
CPU time 0.61 seconds
Started Jun 29 05:10:00 PM PDT 24
Finished Jun 29 05:10:02 PM PDT 24
Peak memory 195228 kb
Host smart-2123ce7f-9918-46f2-8e85-46dbc51ef3dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096595510 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_alert_test.2096595510
Directory /workspace/23.hmac_alert_test/latest

Test location /workspace/coverage/default/23.hmac_back_pressure.2605504928
Short name T379
Test name
Test status
Simulation time 40165396 ps
CPU time 2.6 seconds
Started Jun 29 05:09:47 PM PDT 24
Finished Jun 29 05:09:50 PM PDT 24
Peak memory 200056 kb
Host smart-cc20a55d-3c73-43a0-b16f-e1c7af4790fc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2605504928 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_back_pressure.2605504928
Directory /workspace/23.hmac_back_pressure/latest

Test location /workspace/coverage/default/23.hmac_burst_wr.694202780
Short name T739
Test name
Test status
Simulation time 1862498600 ps
CPU time 55.88 seconds
Started Jun 29 05:09:47 PM PDT 24
Finished Jun 29 05:10:44 PM PDT 24
Peak memory 200304 kb
Host smart-33e32775-cd86-40e8-90cc-be34c53f9a0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694202780 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_burst_wr.694202780
Directory /workspace/23.hmac_burst_wr/latest

Test location /workspace/coverage/default/23.hmac_datapath_stress.2443300312
Short name T702
Test name
Test status
Simulation time 394658598 ps
CPU time 107.37 seconds
Started Jun 29 05:09:51 PM PDT 24
Finished Jun 29 05:11:39 PM PDT 24
Peak memory 607408 kb
Host smart-c818718c-041e-472f-9df1-7637dfbf98dd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2443300312 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_datapath_stress.2443300312
Directory /workspace/23.hmac_datapath_stress/latest

Test location /workspace/coverage/default/23.hmac_error.917103959
Short name T641
Test name
Test status
Simulation time 15157116369 ps
CPU time 109.61 seconds
Started Jun 29 05:09:46 PM PDT 24
Finished Jun 29 05:11:36 PM PDT 24
Peak memory 200236 kb
Host smart-5efaa971-967c-496e-b9a0-f2f0478eed05
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917103959 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_error.917103959
Directory /workspace/23.hmac_error/latest

Test location /workspace/coverage/default/23.hmac_long_msg.295240278
Short name T600
Test name
Test status
Simulation time 13229542561 ps
CPU time 105.43 seconds
Started Jun 29 05:09:47 PM PDT 24
Finished Jun 29 05:11:33 PM PDT 24
Peak memory 216612 kb
Host smart-63964a0e-6dc6-49ba-bf09-2a812b0cdb71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295240278 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_long_msg.295240278
Directory /workspace/23.hmac_long_msg/latest

Test location /workspace/coverage/default/23.hmac_smoke.4028996853
Short name T88
Test name
Test status
Simulation time 639641299 ps
CPU time 11.39 seconds
Started Jun 29 05:09:48 PM PDT 24
Finished Jun 29 05:10:01 PM PDT 24
Peak memory 200144 kb
Host smart-e8b10168-5505-44f8-be1e-34267310f3a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028996853 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_smoke.4028996853
Directory /workspace/23.hmac_smoke/latest

Test location /workspace/coverage/default/23.hmac_stress_all.2972369574
Short name T64
Test name
Test status
Simulation time 69823326997 ps
CPU time 1026.06 seconds
Started Jun 29 05:09:59 PM PDT 24
Finished Jun 29 05:27:06 PM PDT 24
Peak memory 216724 kb
Host smart-e7d7dcef-9d7e-4da0-b04b-c883ae174ffc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972369574 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.hmac_stress_all.2972369574
Directory /workspace/23.hmac_stress_all/latest

Test location /workspace/coverage/default/23.hmac_test_hmac256_vectors.709641971
Short name T215
Test name
Test status
Simulation time 21126336854 ps
CPU time 58.82 seconds
Started Jun 29 05:10:01 PM PDT 24
Finished Jun 29 05:11:01 PM PDT 24
Peak memory 200308 kb
Host smart-4cf093c2-1d11-4bf4-9f6c-2d3d8a82a918
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=709641971 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_test_hmac256_vectors.709641971
Directory /workspace/23.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/23.hmac_test_hmac384_vectors.1408583456
Short name T421
Test name
Test status
Simulation time 11651447170 ps
CPU time 97.18 seconds
Started Jun 29 05:10:00 PM PDT 24
Finished Jun 29 05:11:38 PM PDT 24
Peak memory 200332 kb
Host smart-59007d3b-633b-4acb-9ed2-8b6317c33760
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1408583456 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_test_hmac384_vectors.1408583456
Directory /workspace/23.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/23.hmac_test_hmac512_vectors.3646924073
Short name T764
Test name
Test status
Simulation time 10023096507 ps
CPU time 117.45 seconds
Started Jun 29 05:10:00 PM PDT 24
Finished Jun 29 05:11:58 PM PDT 24
Peak memory 200332 kb
Host smart-9cbcd26a-d6d4-484a-b3bb-611b6ff63957
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3646924073 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_test_hmac512_vectors.3646924073
Directory /workspace/23.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/23.hmac_test_sha256_vectors.1003429122
Short name T381
Test name
Test status
Simulation time 31138262450 ps
CPU time 474.75 seconds
Started Jun 29 05:10:01 PM PDT 24
Finished Jun 29 05:17:56 PM PDT 24
Peak memory 200272 kb
Host smart-898441d9-afd8-4af4-8c51-683f993db3bd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1003429122 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_test_sha256_vectors.1003429122
Directory /workspace/23.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/23.hmac_test_sha384_vectors.3212712034
Short name T648
Test name
Test status
Simulation time 32947770722 ps
CPU time 1749.76 seconds
Started Jun 29 05:09:59 PM PDT 24
Finished Jun 29 05:39:09 PM PDT 24
Peak memory 216608 kb
Host smart-85840d46-617f-4e9e-9008-eae41772bedf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3212712034 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_test_sha384_vectors.3212712034
Directory /workspace/23.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/23.hmac_test_sha512_vectors.1279207041
Short name T495
Test name
Test status
Simulation time 115152862064 ps
CPU time 1765.33 seconds
Started Jun 29 05:09:59 PM PDT 24
Finished Jun 29 05:39:25 PM PDT 24
Peak memory 215668 kb
Host smart-9471515b-26eb-40be-89ad-24790695d43b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1279207041 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_test_sha512_vectors.1279207041
Directory /workspace/23.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/23.hmac_wipe_secret.2322025185
Short name T420
Test name
Test status
Simulation time 1736239521 ps
CPU time 73.77 seconds
Started Jun 29 05:09:51 PM PDT 24
Finished Jun 29 05:11:06 PM PDT 24
Peak memory 200288 kb
Host smart-caa080ea-ae7b-4550-939a-3c588b71c0be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322025185 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_wipe_secret.2322025185
Directory /workspace/23.hmac_wipe_secret/latest

Test location /workspace/coverage/default/24.hmac_alert_test.1650592252
Short name T440
Test name
Test status
Simulation time 12133584 ps
CPU time 0.58 seconds
Started Jun 29 05:09:59 PM PDT 24
Finished Jun 29 05:10:00 PM PDT 24
Peak memory 195152 kb
Host smart-c4e49bac-0aa9-441a-9567-4f2415f79641
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650592252 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_alert_test.1650592252
Directory /workspace/24.hmac_alert_test/latest

Test location /workspace/coverage/default/24.hmac_back_pressure.242817827
Short name T656
Test name
Test status
Simulation time 427950007 ps
CPU time 11.07 seconds
Started Jun 29 05:09:59 PM PDT 24
Finished Jun 29 05:10:10 PM PDT 24
Peak memory 200148 kb
Host smart-cc4aebd0-8766-449e-9dad-157cf8d06567
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=242817827 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_back_pressure.242817827
Directory /workspace/24.hmac_back_pressure/latest

Test location /workspace/coverage/default/24.hmac_burst_wr.2540338296
Short name T499
Test name
Test status
Simulation time 889613323 ps
CPU time 5.12 seconds
Started Jun 29 05:09:59 PM PDT 24
Finished Jun 29 05:10:04 PM PDT 24
Peak memory 200216 kb
Host smart-8bddc43d-5a97-4711-aa20-ddda37fde61d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540338296 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_burst_wr.2540338296
Directory /workspace/24.hmac_burst_wr/latest

Test location /workspace/coverage/default/24.hmac_datapath_stress.522595433
Short name T202
Test name
Test status
Simulation time 663217604 ps
CPU time 106.42 seconds
Started Jun 29 05:10:01 PM PDT 24
Finished Jun 29 05:11:48 PM PDT 24
Peak memory 565852 kb
Host smart-60d233fc-8cf0-43a6-a299-d51534bdf490
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=522595433 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_datapath_stress.522595433
Directory /workspace/24.hmac_datapath_stress/latest

Test location /workspace/coverage/default/24.hmac_error.3262958007
Short name T592
Test name
Test status
Simulation time 2701972207 ps
CPU time 41.32 seconds
Started Jun 29 05:09:59 PM PDT 24
Finished Jun 29 05:10:41 PM PDT 24
Peak memory 200360 kb
Host smart-cc2a963a-fa68-48cf-8eeb-ad9dd349ff70
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262958007 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_error.3262958007
Directory /workspace/24.hmac_error/latest

Test location /workspace/coverage/default/24.hmac_long_msg.3840153397
Short name T743
Test name
Test status
Simulation time 9686581737 ps
CPU time 85.38 seconds
Started Jun 29 05:10:01 PM PDT 24
Finished Jun 29 05:11:27 PM PDT 24
Peak memory 200388 kb
Host smart-8ae75fdd-21fa-4eab-994c-bfeea364e63d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840153397 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_long_msg.3840153397
Directory /workspace/24.hmac_long_msg/latest

Test location /workspace/coverage/default/24.hmac_smoke.3965409826
Short name T561
Test name
Test status
Simulation time 3259260992 ps
CPU time 16.98 seconds
Started Jun 29 05:10:01 PM PDT 24
Finished Jun 29 05:10:18 PM PDT 24
Peak memory 200344 kb
Host smart-ad14d96b-a90c-47fc-9f07-2a295b208af2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965409826 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_smoke.3965409826
Directory /workspace/24.hmac_smoke/latest

Test location /workspace/coverage/default/24.hmac_stress_all.1682522726
Short name T663
Test name
Test status
Simulation time 195784937856 ps
CPU time 4619.42 seconds
Started Jun 29 05:09:59 PM PDT 24
Finished Jun 29 06:27:00 PM PDT 24
Peak memory 749944 kb
Host smart-b6d01d04-952b-4b62-99af-2cb5745cc18e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682522726 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.hmac_stress_all.1682522726
Directory /workspace/24.hmac_stress_all/latest

Test location /workspace/coverage/default/24.hmac_test_hmac256_vectors.29529504
Short name T195
Test name
Test status
Simulation time 2454952110 ps
CPU time 40.02 seconds
Started Jun 29 05:09:58 PM PDT 24
Finished Jun 29 05:10:39 PM PDT 24
Peak memory 200324 kb
Host smart-1f18d859-fb60-4593-9186-6d81c46c0e37
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=29529504 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_test_hmac256_vectors.29529504
Directory /workspace/24.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/24.hmac_test_hmac384_vectors.1993333845
Short name T721
Test name
Test status
Simulation time 5468272348 ps
CPU time 40.85 seconds
Started Jun 29 05:09:59 PM PDT 24
Finished Jun 29 05:10:40 PM PDT 24
Peak memory 200324 kb
Host smart-fb1a444e-79d6-4419-b91b-454de0da52d5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1993333845 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_test_hmac384_vectors.1993333845
Directory /workspace/24.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/24.hmac_test_hmac512_vectors.1560456740
Short name T83
Test name
Test status
Simulation time 2615672697 ps
CPU time 95.98 seconds
Started Jun 29 05:09:59 PM PDT 24
Finished Jun 29 05:11:36 PM PDT 24
Peak memory 200260 kb
Host smart-8540f89e-02af-4739-a345-a6d60c0e395b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1560456740 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_test_hmac512_vectors.1560456740
Directory /workspace/24.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/24.hmac_test_sha256_vectors.4193856812
Short name T622
Test name
Test status
Simulation time 46438703520 ps
CPU time 436.46 seconds
Started Jun 29 05:09:59 PM PDT 24
Finished Jun 29 05:17:16 PM PDT 24
Peak memory 200216 kb
Host smart-0137f9ef-bdb1-47aa-af4a-71c4c4ae1387
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=4193856812 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_test_sha256_vectors.4193856812
Directory /workspace/24.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/24.hmac_test_sha384_vectors.3078153394
Short name T186
Test name
Test status
Simulation time 49250700902 ps
CPU time 1953.89 seconds
Started Jun 29 05:10:00 PM PDT 24
Finished Jun 29 05:42:34 PM PDT 24
Peak memory 215796 kb
Host smart-b6a056e8-fc88-4599-911e-b772a8d4cd05
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3078153394 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_test_sha384_vectors.3078153394
Directory /workspace/24.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/24.hmac_test_sha512_vectors.1787216251
Short name T278
Test name
Test status
Simulation time 31368148906 ps
CPU time 1810.24 seconds
Started Jun 29 05:10:00 PM PDT 24
Finished Jun 29 05:40:11 PM PDT 24
Peak memory 216468 kb
Host smart-e5ea2b8e-e798-461d-801c-6807ecaa6e76
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1787216251 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_test_sha512_vectors.1787216251
Directory /workspace/24.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/24.hmac_wipe_secret.2887775261
Short name T261
Test name
Test status
Simulation time 2364342294 ps
CPU time 32.1 seconds
Started Jun 29 05:10:00 PM PDT 24
Finished Jun 29 05:10:33 PM PDT 24
Peak memory 200372 kb
Host smart-46b652bc-0ccc-45af-9014-1c01ce95e233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887775261 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_wipe_secret.2887775261
Directory /workspace/24.hmac_wipe_secret/latest

Test location /workspace/coverage/default/25.hmac_alert_test.218178910
Short name T580
Test name
Test status
Simulation time 13347280 ps
CPU time 0.63 seconds
Started Jun 29 05:10:08 PM PDT 24
Finished Jun 29 05:10:09 PM PDT 24
Peak memory 195808 kb
Host smart-23d38f05-0bbb-49cd-bb41-b42f974e0264
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218178910 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_alert_test.218178910
Directory /workspace/25.hmac_alert_test/latest

Test location /workspace/coverage/default/25.hmac_back_pressure.4283605982
Short name T18
Test name
Test status
Simulation time 1033847640 ps
CPU time 53.76 seconds
Started Jun 29 05:10:09 PM PDT 24
Finished Jun 29 05:11:03 PM PDT 24
Peak memory 200256 kb
Host smart-f2a3ae30-09cb-4389-aadc-586106fcb1bf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4283605982 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_back_pressure.4283605982
Directory /workspace/25.hmac_back_pressure/latest

Test location /workspace/coverage/default/25.hmac_burst_wr.957050923
Short name T652
Test name
Test status
Simulation time 4447754607 ps
CPU time 57.92 seconds
Started Jun 29 05:10:10 PM PDT 24
Finished Jun 29 05:11:09 PM PDT 24
Peak memory 200280 kb
Host smart-ed1b06c1-c355-4762-961e-ba4d04ab3dd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957050923 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_burst_wr.957050923
Directory /workspace/25.hmac_burst_wr/latest

Test location /workspace/coverage/default/25.hmac_datapath_stress.2545799058
Short name T329
Test name
Test status
Simulation time 7423516797 ps
CPU time 486.23 seconds
Started Jun 29 05:10:08 PM PDT 24
Finished Jun 29 05:18:14 PM PDT 24
Peak memory 649300 kb
Host smart-c340a49b-376a-4927-910c-81d9b8a7fc14
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2545799058 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_datapath_stress.2545799058
Directory /workspace/25.hmac_datapath_stress/latest

Test location /workspace/coverage/default/25.hmac_error.351558567
Short name T476
Test name
Test status
Simulation time 2559452013 ps
CPU time 132.63 seconds
Started Jun 29 05:10:13 PM PDT 24
Finished Jun 29 05:12:26 PM PDT 24
Peak memory 200356 kb
Host smart-a265d135-bd1b-4ec3-8de9-2966381ad251
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351558567 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_error.351558567
Directory /workspace/25.hmac_error/latest

Test location /workspace/coverage/default/25.hmac_long_msg.1703668029
Short name T763
Test name
Test status
Simulation time 6048226312 ps
CPU time 92.16 seconds
Started Jun 29 05:10:01 PM PDT 24
Finished Jun 29 05:11:34 PM PDT 24
Peak memory 200328 kb
Host smart-913e15dc-620a-4016-a484-d90ff50411c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1703668029 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_long_msg.1703668029
Directory /workspace/25.hmac_long_msg/latest

Test location /workspace/coverage/default/25.hmac_smoke.2099432555
Short name T282
Test name
Test status
Simulation time 1229690180 ps
CPU time 10.93 seconds
Started Jun 29 05:10:00 PM PDT 24
Finished Jun 29 05:10:11 PM PDT 24
Peak memory 200308 kb
Host smart-254d1e98-abd5-4533-9212-cab6b785419e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099432555 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_smoke.2099432555
Directory /workspace/25.hmac_smoke/latest

Test location /workspace/coverage/default/25.hmac_stress_all.618063997
Short name T17
Test name
Test status
Simulation time 100631708887 ps
CPU time 6330.96 seconds
Started Jun 29 05:10:08 PM PDT 24
Finished Jun 29 06:55:41 PM PDT 24
Peak memory 744540 kb
Host smart-f6e0d314-cc66-4668-ab24-53a26caa7973
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618063997 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 25.hmac_stress_all.618063997
Directory /workspace/25.hmac_stress_all/latest

Test location /workspace/coverage/default/25.hmac_test_hmac256_vectors.2998222679
Short name T175
Test name
Test status
Simulation time 33318928503 ps
CPU time 62.27 seconds
Started Jun 29 05:10:12 PM PDT 24
Finished Jun 29 05:11:15 PM PDT 24
Peak memory 200308 kb
Host smart-0773e10d-8528-40c4-8900-55ca16e3f3e9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2998222679 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_test_hmac256_vectors.2998222679
Directory /workspace/25.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/25.hmac_test_hmac384_vectors.2454408567
Short name T533
Test name
Test status
Simulation time 21482304291 ps
CPU time 84.38 seconds
Started Jun 29 05:10:10 PM PDT 24
Finished Jun 29 05:11:35 PM PDT 24
Peak memory 200360 kb
Host smart-98dcfee2-cd19-48b2-b838-134ad235fde0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2454408567 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_test_hmac384_vectors.2454408567
Directory /workspace/25.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/25.hmac_test_hmac512_vectors.404140231
Short name T231
Test name
Test status
Simulation time 9581348775 ps
CPU time 127.54 seconds
Started Jun 29 05:10:09 PM PDT 24
Finished Jun 29 05:12:17 PM PDT 24
Peak memory 200360 kb
Host smart-9625b418-68ff-4cc4-bb6f-85810ca809b6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=404140231 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_test_hmac512_vectors.404140231
Directory /workspace/25.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/25.hmac_test_sha256_vectors.3482636061
Short name T406
Test name
Test status
Simulation time 8025313967 ps
CPU time 455.15 seconds
Started Jun 29 05:10:09 PM PDT 24
Finished Jun 29 05:17:44 PM PDT 24
Peak memory 200300 kb
Host smart-21d49c1f-5999-454e-80f6-bc924f583b91
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3482636061 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_test_sha256_vectors.3482636061
Directory /workspace/25.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/25.hmac_test_sha384_vectors.3450324027
Short name T212
Test name
Test status
Simulation time 132285432572 ps
CPU time 1889.18 seconds
Started Jun 29 05:10:08 PM PDT 24
Finished Jun 29 05:41:38 PM PDT 24
Peak memory 215680 kb
Host smart-3a22c336-6a7a-485d-9a46-d33165b5deed
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3450324027 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_test_sha384_vectors.3450324027
Directory /workspace/25.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/25.hmac_test_sha512_vectors.2033972652
Short name T275
Test name
Test status
Simulation time 678155212823 ps
CPU time 1890.39 seconds
Started Jun 29 05:10:11 PM PDT 24
Finished Jun 29 05:41:42 PM PDT 24
Peak memory 215924 kb
Host smart-8caeeb62-fac9-47d3-b610-7f63d2baf0d4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2033972652 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_test_sha512_vectors.2033972652
Directory /workspace/25.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/25.hmac_wipe_secret.3436586402
Short name T728
Test name
Test status
Simulation time 1504689081 ps
CPU time 21.76 seconds
Started Jun 29 05:10:12 PM PDT 24
Finished Jun 29 05:10:35 PM PDT 24
Peak memory 200284 kb
Host smart-db352eb7-115c-420d-8dcc-73c20a981873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436586402 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_wipe_secret.3436586402
Directory /workspace/25.hmac_wipe_secret/latest

Test location /workspace/coverage/default/26.hmac_alert_test.2452092099
Short name T214
Test name
Test status
Simulation time 40286540 ps
CPU time 0.59 seconds
Started Jun 29 05:10:08 PM PDT 24
Finished Jun 29 05:10:10 PM PDT 24
Peak memory 197000 kb
Host smart-f03bc6e0-324e-4e7b-8793-6a1a362bf7d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452092099 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_alert_test.2452092099
Directory /workspace/26.hmac_alert_test/latest

Test location /workspace/coverage/default/26.hmac_back_pressure.442960988
Short name T22
Test name
Test status
Simulation time 2981988249 ps
CPU time 39.14 seconds
Started Jun 29 05:10:10 PM PDT 24
Finished Jun 29 05:10:49 PM PDT 24
Peak memory 200376 kb
Host smart-3a6b6223-01be-4ba6-aaa3-7268f4d62b52
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=442960988 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_back_pressure.442960988
Directory /workspace/26.hmac_back_pressure/latest

Test location /workspace/coverage/default/26.hmac_burst_wr.767610532
Short name T784
Test name
Test status
Simulation time 3790262043 ps
CPU time 52.91 seconds
Started Jun 29 05:10:10 PM PDT 24
Finished Jun 29 05:11:04 PM PDT 24
Peak memory 200336 kb
Host smart-43a92a86-7051-43e0-a9f3-85ce408d6e02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767610532 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_burst_wr.767610532
Directory /workspace/26.hmac_burst_wr/latest

Test location /workspace/coverage/default/26.hmac_datapath_stress.4286023441
Short name T170
Test name
Test status
Simulation time 6101173694 ps
CPU time 1188.35 seconds
Started Jun 29 05:10:09 PM PDT 24
Finished Jun 29 05:29:58 PM PDT 24
Peak memory 745808 kb
Host smart-e09bac64-dd21-419f-809e-ddbd8ffb6e77
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4286023441 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_datapath_stress.4286023441
Directory /workspace/26.hmac_datapath_stress/latest

Test location /workspace/coverage/default/26.hmac_error.305292186
Short name T122
Test name
Test status
Simulation time 37387925023 ps
CPU time 176.96 seconds
Started Jun 29 05:10:13 PM PDT 24
Finished Jun 29 05:13:10 PM PDT 24
Peak memory 200320 kb
Host smart-24eaf90f-08bd-4f99-b45d-a3d555c91509
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305292186 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_error.305292186
Directory /workspace/26.hmac_error/latest

Test location /workspace/coverage/default/26.hmac_long_msg.1467794883
Short name T489
Test name
Test status
Simulation time 15608988505 ps
CPU time 82.03 seconds
Started Jun 29 05:10:12 PM PDT 24
Finished Jun 29 05:11:34 PM PDT 24
Peak memory 200336 kb
Host smart-7aff34f6-80cb-4b99-9a86-0601a86c6efe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467794883 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_long_msg.1467794883
Directory /workspace/26.hmac_long_msg/latest

Test location /workspace/coverage/default/26.hmac_smoke.1839892175
Short name T708
Test name
Test status
Simulation time 52921675 ps
CPU time 1.32 seconds
Started Jun 29 05:10:12 PM PDT 24
Finished Jun 29 05:10:14 PM PDT 24
Peak memory 200284 kb
Host smart-85fed0d0-a13f-4029-bef0-7fb56ae4e2a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839892175 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_smoke.1839892175
Directory /workspace/26.hmac_smoke/latest

Test location /workspace/coverage/default/26.hmac_test_hmac256_vectors.340575734
Short name T238
Test name
Test status
Simulation time 1055812158 ps
CPU time 35.72 seconds
Started Jun 29 05:10:13 PM PDT 24
Finished Jun 29 05:10:49 PM PDT 24
Peak memory 200272 kb
Host smart-7b215078-04c1-4f3c-91ec-75ba1ee7b6fc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=340575734 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_test_hmac256_vectors.340575734
Directory /workspace/26.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/26.hmac_test_hmac384_vectors.3661856719
Short name T154
Test name
Test status
Simulation time 3549878658 ps
CPU time 43.52 seconds
Started Jun 29 05:10:10 PM PDT 24
Finished Jun 29 05:10:54 PM PDT 24
Peak memory 200368 kb
Host smart-6a381ce8-4604-4852-be0d-1ab9b82033bf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3661856719 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_test_hmac384_vectors.3661856719
Directory /workspace/26.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/26.hmac_test_hmac512_vectors.3451823965
Short name T758
Test name
Test status
Simulation time 5211017379 ps
CPU time 93.35 seconds
Started Jun 29 05:10:08 PM PDT 24
Finished Jun 29 05:11:42 PM PDT 24
Peak memory 200308 kb
Host smart-e577af33-8974-4cad-aa83-e2028dc43fa7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3451823965 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_test_hmac512_vectors.3451823965
Directory /workspace/26.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/26.hmac_test_sha256_vectors.2919484411
Short name T384
Test name
Test status
Simulation time 36894852626 ps
CPU time 494.23 seconds
Started Jun 29 05:10:09 PM PDT 24
Finished Jun 29 05:18:23 PM PDT 24
Peak memory 200300 kb
Host smart-dc2ea735-bfae-4204-adac-4e1e1e858003
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2919484411 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_test_sha256_vectors.2919484411
Directory /workspace/26.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/26.hmac_test_sha384_vectors.654573046
Short name T435
Test name
Test status
Simulation time 102517181532 ps
CPU time 1779.6 seconds
Started Jun 29 05:10:08 PM PDT 24
Finished Jun 29 05:39:48 PM PDT 24
Peak memory 216592 kb
Host smart-6616e53b-44e2-4a17-9119-e1b571771054
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=654573046 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_test_sha384_vectors.654573046
Directory /workspace/26.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/26.hmac_test_sha512_vectors.823279278
Short name T167
Test name
Test status
Simulation time 555385030532 ps
CPU time 1993.57 seconds
Started Jun 29 05:10:10 PM PDT 24
Finished Jun 29 05:43:24 PM PDT 24
Peak memory 216044 kb
Host smart-5e7f8cb1-f851-471e-ad11-cc535c1ea27f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=823279278 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_test_sha512_vectors.823279278
Directory /workspace/26.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/26.hmac_wipe_secret.1679008704
Short name T93
Test name
Test status
Simulation time 66963311411 ps
CPU time 83.54 seconds
Started Jun 29 05:10:08 PM PDT 24
Finished Jun 29 05:11:33 PM PDT 24
Peak memory 200384 kb
Host smart-107d11c2-18e9-4bea-ac25-2426966df832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679008704 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_wipe_secret.1679008704
Directory /workspace/26.hmac_wipe_secret/latest

Test location /workspace/coverage/default/27.hmac_alert_test.546745859
Short name T785
Test name
Test status
Simulation time 15454485 ps
CPU time 0.6 seconds
Started Jun 29 05:10:26 PM PDT 24
Finished Jun 29 05:10:28 PM PDT 24
Peak memory 196252 kb
Host smart-01ee5a21-fb28-4997-974f-93a04eadff5c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546745859 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_alert_test.546745859
Directory /workspace/27.hmac_alert_test/latest

Test location /workspace/coverage/default/27.hmac_back_pressure.3229444540
Short name T23
Test name
Test status
Simulation time 400237329 ps
CPU time 15.74 seconds
Started Jun 29 05:10:26 PM PDT 24
Finished Jun 29 05:10:43 PM PDT 24
Peak memory 200240 kb
Host smart-dee97ec6-57bf-42c7-b4f5-afdbce8739d6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3229444540 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_back_pressure.3229444540
Directory /workspace/27.hmac_back_pressure/latest

Test location /workspace/coverage/default/27.hmac_burst_wr.1164555709
Short name T460
Test name
Test status
Simulation time 10789758342 ps
CPU time 39.69 seconds
Started Jun 29 05:10:25 PM PDT 24
Finished Jun 29 05:11:06 PM PDT 24
Peak memory 200368 kb
Host smart-5123d6af-9723-4c82-a798-327f516307b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164555709 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_burst_wr.1164555709
Directory /workspace/27.hmac_burst_wr/latest

Test location /workspace/coverage/default/27.hmac_datapath_stress.1853748006
Short name T734
Test name
Test status
Simulation time 789325340 ps
CPU time 187.73 seconds
Started Jun 29 05:10:28 PM PDT 24
Finished Jun 29 05:13:37 PM PDT 24
Peak memory 641128 kb
Host smart-256929bd-a4a5-45a4-8dc3-cc3d3bc7e912
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1853748006 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_datapath_stress.1853748006
Directory /workspace/27.hmac_datapath_stress/latest

Test location /workspace/coverage/default/27.hmac_error.902735422
Short name T591
Test name
Test status
Simulation time 10819782296 ps
CPU time 210.25 seconds
Started Jun 29 05:10:26 PM PDT 24
Finished Jun 29 05:13:58 PM PDT 24
Peak memory 200324 kb
Host smart-d646e663-c02d-412c-b49a-66b7e719cca0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902735422 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_error.902735422
Directory /workspace/27.hmac_error/latest

Test location /workspace/coverage/default/27.hmac_long_msg.732900280
Short name T751
Test name
Test status
Simulation time 92510475 ps
CPU time 2.52 seconds
Started Jun 29 05:10:13 PM PDT 24
Finished Jun 29 05:10:16 PM PDT 24
Peak memory 200156 kb
Host smart-ac867bf1-25f7-4f0d-80c7-995536a5a9c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732900280 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_long_msg.732900280
Directory /workspace/27.hmac_long_msg/latest

Test location /workspace/coverage/default/27.hmac_smoke.3154763812
Short name T497
Test name
Test status
Simulation time 201545063 ps
CPU time 4.44 seconds
Started Jun 29 05:10:12 PM PDT 24
Finished Jun 29 05:10:17 PM PDT 24
Peak memory 200252 kb
Host smart-509bc635-010d-4f54-9ca8-272c2467ccb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154763812 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_smoke.3154763812
Directory /workspace/27.hmac_smoke/latest

Test location /workspace/coverage/default/27.hmac_test_hmac256_vectors.3586345213
Short name T183
Test name
Test status
Simulation time 10714741607 ps
CPU time 68.68 seconds
Started Jun 29 05:10:26 PM PDT 24
Finished Jun 29 05:11:36 PM PDT 24
Peak memory 200368 kb
Host smart-4c080f02-e50b-43fb-a81e-5e39f21e0718
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3586345213 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_test_hmac256_vectors.3586345213
Directory /workspace/27.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/27.hmac_test_hmac384_vectors.2242205717
Short name T740
Test name
Test status
Simulation time 1559442215 ps
CPU time 51.27 seconds
Started Jun 29 05:10:25 PM PDT 24
Finished Jun 29 05:11:17 PM PDT 24
Peak memory 200204 kb
Host smart-4fa82ec6-c2b2-45a1-b7ac-3c02c1920d1e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2242205717 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_test_hmac384_vectors.2242205717
Directory /workspace/27.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/27.hmac_test_hmac512_vectors.1442072090
Short name T699
Test name
Test status
Simulation time 61823410622 ps
CPU time 131.43 seconds
Started Jun 29 05:10:28 PM PDT 24
Finished Jun 29 05:12:40 PM PDT 24
Peak memory 200308 kb
Host smart-0074fb16-57bd-43d8-8a8a-095f96999d89
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1442072090 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_test_hmac512_vectors.1442072090
Directory /workspace/27.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/27.hmac_test_sha256_vectors.2137089392
Short name T200
Test name
Test status
Simulation time 42906251475 ps
CPU time 516.52 seconds
Started Jun 29 05:10:24 PM PDT 24
Finished Jun 29 05:19:01 PM PDT 24
Peak memory 200320 kb
Host smart-311baf37-8ef8-4731-ab3e-037d59175764
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2137089392 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_test_sha256_vectors.2137089392
Directory /workspace/27.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/27.hmac_test_sha384_vectors.808100577
Short name T566
Test name
Test status
Simulation time 265836853259 ps
CPU time 1924.99 seconds
Started Jun 29 05:10:26 PM PDT 24
Finished Jun 29 05:42:33 PM PDT 24
Peak memory 215852 kb
Host smart-9abe6ed7-7bc4-4958-9e2e-18c9ec3b9df2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=808100577 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_test_sha384_vectors.808100577
Directory /workspace/27.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/27.hmac_test_sha512_vectors.2381660100
Short name T248
Test name
Test status
Simulation time 287180307056 ps
CPU time 2098.78 seconds
Started Jun 29 05:10:25 PM PDT 24
Finished Jun 29 05:45:26 PM PDT 24
Peak memory 216516 kb
Host smart-65b2059f-81d7-4f4c-8ef6-a8da11ba3349
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2381660100 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_test_sha512_vectors.2381660100
Directory /workspace/27.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/27.hmac_wipe_secret.3110762229
Short name T565
Test name
Test status
Simulation time 15276802135 ps
CPU time 76.31 seconds
Started Jun 29 05:10:28 PM PDT 24
Finished Jun 29 05:11:45 PM PDT 24
Peak memory 200304 kb
Host smart-80dc2e56-baad-4028-b02a-3c65c8a634a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3110762229 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_wipe_secret.3110762229
Directory /workspace/27.hmac_wipe_secret/latest

Test location /workspace/coverage/default/28.hmac_alert_test.1007513376
Short name T659
Test name
Test status
Simulation time 22892826 ps
CPU time 0.61 seconds
Started Jun 29 05:10:28 PM PDT 24
Finished Jun 29 05:10:29 PM PDT 24
Peak memory 196264 kb
Host smart-910a5d13-c0ae-45f1-9fd0-fa274d7f41c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007513376 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_alert_test.1007513376
Directory /workspace/28.hmac_alert_test/latest

Test location /workspace/coverage/default/28.hmac_back_pressure.1890790304
Short name T562
Test name
Test status
Simulation time 3598682267 ps
CPU time 41.4 seconds
Started Jun 29 05:10:25 PM PDT 24
Finished Jun 29 05:11:08 PM PDT 24
Peak memory 200304 kb
Host smart-d089ddfa-bcf9-40b0-b327-d292d921c581
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1890790304 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_back_pressure.1890790304
Directory /workspace/28.hmac_back_pressure/latest

Test location /workspace/coverage/default/28.hmac_burst_wr.2581635440
Short name T742
Test name
Test status
Simulation time 7078588836 ps
CPU time 36.14 seconds
Started Jun 29 05:10:25 PM PDT 24
Finished Jun 29 05:11:01 PM PDT 24
Peak memory 200332 kb
Host smart-816d01ed-c43a-4c42-8793-0a9934fa7437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581635440 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_burst_wr.2581635440
Directory /workspace/28.hmac_burst_wr/latest

Test location /workspace/coverage/default/28.hmac_datapath_stress.3831167948
Short name T456
Test name
Test status
Simulation time 62600311688 ps
CPU time 1304.37 seconds
Started Jun 29 05:10:26 PM PDT 24
Finished Jun 29 05:32:12 PM PDT 24
Peak memory 770712 kb
Host smart-37c4eab1-7405-4938-b09e-ca7e707ff3cc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3831167948 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_datapath_stress.3831167948
Directory /workspace/28.hmac_datapath_stress/latest

Test location /workspace/coverage/default/28.hmac_error.1386258543
Short name T570
Test name
Test status
Simulation time 6927426159 ps
CPU time 38.54 seconds
Started Jun 29 05:10:26 PM PDT 24
Finished Jun 29 05:11:05 PM PDT 24
Peak memory 200236 kb
Host smart-ba932ef7-a3b9-4b15-a3b1-e8d06be6167d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386258543 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_error.1386258543
Directory /workspace/28.hmac_error/latest

Test location /workspace/coverage/default/28.hmac_long_msg.3149460897
Short name T644
Test name
Test status
Simulation time 103287488588 ps
CPU time 125.48 seconds
Started Jun 29 05:10:26 PM PDT 24
Finished Jun 29 05:12:32 PM PDT 24
Peak memory 200452 kb
Host smart-b5008fd0-7e87-426e-951c-34221cbdf692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149460897 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_long_msg.3149460897
Directory /workspace/28.hmac_long_msg/latest

Test location /workspace/coverage/default/28.hmac_smoke.993061201
Short name T642
Test name
Test status
Simulation time 178038729 ps
CPU time 8.32 seconds
Started Jun 29 05:10:26 PM PDT 24
Finished Jun 29 05:10:36 PM PDT 24
Peak memory 200252 kb
Host smart-609177dc-790b-4179-afd7-f63d08f9a6c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993061201 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_smoke.993061201
Directory /workspace/28.hmac_smoke/latest

Test location /workspace/coverage/default/28.hmac_test_hmac256_vectors.1445559666
Short name T153
Test name
Test status
Simulation time 3098955955 ps
CPU time 61.51 seconds
Started Jun 29 05:10:27 PM PDT 24
Finished Jun 29 05:11:29 PM PDT 24
Peak memory 200336 kb
Host smart-6f7cb021-bed1-4c0d-9636-813d9e214b08
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1445559666 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_test_hmac256_vectors.1445559666
Directory /workspace/28.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/28.hmac_test_hmac384_vectors.748258418
Short name T287
Test name
Test status
Simulation time 15030647267 ps
CPU time 51 seconds
Started Jun 29 05:10:25 PM PDT 24
Finished Jun 29 05:11:17 PM PDT 24
Peak memory 200260 kb
Host smart-d08fa59a-3e4e-48d7-8d28-f043ea3f6fd5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=748258418 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_test_hmac384_vectors.748258418
Directory /workspace/28.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/28.hmac_test_hmac512_vectors.2736623857
Short name T398
Test name
Test status
Simulation time 12603493756 ps
CPU time 52.75 seconds
Started Jun 29 05:10:26 PM PDT 24
Finished Jun 29 05:11:20 PM PDT 24
Peak memory 200332 kb
Host smart-6bb547b0-61a0-4ca3-9ade-d510d135ea3b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2736623857 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_test_hmac512_vectors.2736623857
Directory /workspace/28.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/28.hmac_test_sha256_vectors.3908112339
Short name T681
Test name
Test status
Simulation time 30139438181 ps
CPU time 404.08 seconds
Started Jun 29 05:10:29 PM PDT 24
Finished Jun 29 05:17:13 PM PDT 24
Peak memory 200272 kb
Host smart-646b1cd7-32ec-4f15-96cf-110c02699c5b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3908112339 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_test_sha256_vectors.3908112339
Directory /workspace/28.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/28.hmac_test_sha384_vectors.2153955340
Short name T244
Test name
Test status
Simulation time 436441470444 ps
CPU time 1912.46 seconds
Started Jun 29 05:10:26 PM PDT 24
Finished Jun 29 05:42:20 PM PDT 24
Peak memory 215744 kb
Host smart-7a032e39-9834-490c-9b32-e93f02e4ecdb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2153955340 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_test_sha384_vectors.2153955340
Directory /workspace/28.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/28.hmac_test_sha512_vectors.2240901466
Short name T614
Test name
Test status
Simulation time 59879264920 ps
CPU time 1709.6 seconds
Started Jun 29 05:10:27 PM PDT 24
Finished Jun 29 05:38:57 PM PDT 24
Peak memory 216272 kb
Host smart-ee2e9490-694e-4ff9-8072-3ad6f87bfa52
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2240901466 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_test_sha512_vectors.2240901466
Directory /workspace/28.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/28.hmac_wipe_secret.3903659593
Short name T180
Test name
Test status
Simulation time 761541983 ps
CPU time 13.13 seconds
Started Jun 29 05:10:25 PM PDT 24
Finished Jun 29 05:10:39 PM PDT 24
Peak memory 200208 kb
Host smart-45f4aa5a-4f88-42eb-8774-89b49609f871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903659593 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_wipe_secret.3903659593
Directory /workspace/28.hmac_wipe_secret/latest

Test location /workspace/coverage/default/29.hmac_alert_test.877419688
Short name T750
Test name
Test status
Simulation time 15631295 ps
CPU time 0.6 seconds
Started Jun 29 05:10:35 PM PDT 24
Finished Jun 29 05:10:36 PM PDT 24
Peak memory 196244 kb
Host smart-b4fccfac-7506-4aa2-bf0c-16f4c9cd60b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877419688 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_alert_test.877419688
Directory /workspace/29.hmac_alert_test/latest

Test location /workspace/coverage/default/29.hmac_back_pressure.1857465545
Short name T323
Test name
Test status
Simulation time 977329430 ps
CPU time 47.63 seconds
Started Jun 29 05:10:26 PM PDT 24
Finished Jun 29 05:11:15 PM PDT 24
Peak memory 200280 kb
Host smart-04e52cce-7687-4f39-8275-7f2bf8cfa677
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1857465545 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_back_pressure.1857465545
Directory /workspace/29.hmac_back_pressure/latest

Test location /workspace/coverage/default/29.hmac_burst_wr.3547084992
Short name T596
Test name
Test status
Simulation time 3987390796 ps
CPU time 50.8 seconds
Started Jun 29 05:10:25 PM PDT 24
Finished Jun 29 05:11:16 PM PDT 24
Peak memory 200328 kb
Host smart-5224e4db-1b47-48e8-8f01-2237dd7e6d71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547084992 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_burst_wr.3547084992
Directory /workspace/29.hmac_burst_wr/latest

Test location /workspace/coverage/default/29.hmac_datapath_stress.4077359059
Short name T256
Test name
Test status
Simulation time 430594969 ps
CPU time 35.13 seconds
Started Jun 29 05:10:26 PM PDT 24
Finished Jun 29 05:11:02 PM PDT 24
Peak memory 306892 kb
Host smart-9f0ded0a-987b-4d07-941e-c2b9eb48aee2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4077359059 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_datapath_stress.4077359059
Directory /workspace/29.hmac_datapath_stress/latest

Test location /workspace/coverage/default/29.hmac_error.2131235779
Short name T486
Test name
Test status
Simulation time 2845143531 ps
CPU time 15.64 seconds
Started Jun 29 05:10:27 PM PDT 24
Finished Jun 29 05:10:43 PM PDT 24
Peak memory 200164 kb
Host smart-a780bb97-7d2f-4b6e-a462-b02092d09300
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131235779 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_error.2131235779
Directory /workspace/29.hmac_error/latest

Test location /workspace/coverage/default/29.hmac_long_msg.3565924972
Short name T696
Test name
Test status
Simulation time 2955921333 ps
CPU time 44.81 seconds
Started Jun 29 05:10:25 PM PDT 24
Finished Jun 29 05:11:11 PM PDT 24
Peak memory 200352 kb
Host smart-b689062b-127f-4b72-adb4-0d70256a8bb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565924972 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_long_msg.3565924972
Directory /workspace/29.hmac_long_msg/latest

Test location /workspace/coverage/default/29.hmac_smoke.4163879826
Short name T335
Test name
Test status
Simulation time 187907277 ps
CPU time 5.07 seconds
Started Jun 29 05:10:26 PM PDT 24
Finished Jun 29 05:10:32 PM PDT 24
Peak memory 200272 kb
Host smart-b7c06b3b-64fc-43aa-8af0-132f57bac690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4163879826 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_smoke.4163879826
Directory /workspace/29.hmac_smoke/latest

Test location /workspace/coverage/default/29.hmac_test_hmac256_vectors.2511007400
Short name T209
Test name
Test status
Simulation time 16703107804 ps
CPU time 36.57 seconds
Started Jun 29 05:10:29 PM PDT 24
Finished Jun 29 05:11:06 PM PDT 24
Peak memory 200320 kb
Host smart-449e6b18-0d37-4a7f-8ff0-1fffc098c466
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2511007400 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_test_hmac256_vectors.2511007400
Directory /workspace/29.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/29.hmac_test_hmac384_vectors.2506576907
Short name T780
Test name
Test status
Simulation time 23355653975 ps
CPU time 80.69 seconds
Started Jun 29 05:10:26 PM PDT 24
Finished Jun 29 05:11:48 PM PDT 24
Peak memory 200324 kb
Host smart-203ad522-cbcb-4351-91ea-9eaf963d12a4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2506576907 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_test_hmac384_vectors.2506576907
Directory /workspace/29.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/29.hmac_test_hmac512_vectors.125718796
Short name T169
Test name
Test status
Simulation time 9884850309 ps
CPU time 111.24 seconds
Started Jun 29 05:10:25 PM PDT 24
Finished Jun 29 05:12:17 PM PDT 24
Peak memory 200332 kb
Host smart-37e85c09-0b48-4dc0-934d-701e42076f37
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=125718796 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_test_hmac512_vectors.125718796
Directory /workspace/29.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/29.hmac_test_sha256_vectors.2136126122
Short name T401
Test name
Test status
Simulation time 8020761398 ps
CPU time 462.5 seconds
Started Jun 29 05:10:26 PM PDT 24
Finished Jun 29 05:18:10 PM PDT 24
Peak memory 200264 kb
Host smart-2fb1fd5d-edf4-4dd8-ad6b-c7cf2e163fba
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2136126122 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_test_sha256_vectors.2136126122
Directory /workspace/29.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/29.hmac_test_sha384_vectors.3447913965
Short name T457
Test name
Test status
Simulation time 98706939016 ps
CPU time 1745.85 seconds
Started Jun 29 05:10:27 PM PDT 24
Finished Jun 29 05:39:34 PM PDT 24
Peak memory 215784 kb
Host smart-69338d18-588d-4629-aa23-7dbdb9b57ce8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3447913965 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_test_sha384_vectors.3447913965
Directory /workspace/29.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/29.hmac_test_sha512_vectors.3715740155
Short name T746
Test name
Test status
Simulation time 237647929832 ps
CPU time 1676.83 seconds
Started Jun 29 05:10:25 PM PDT 24
Finished Jun 29 05:38:22 PM PDT 24
Peak memory 215792 kb
Host smart-2be01229-216d-4423-81b3-065a5cbfb792
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3715740155 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_test_sha512_vectors.3715740155
Directory /workspace/29.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/29.hmac_wipe_secret.2288667601
Short name T767
Test name
Test status
Simulation time 4954680922 ps
CPU time 6.46 seconds
Started Jun 29 05:10:26 PM PDT 24
Finished Jun 29 05:10:33 PM PDT 24
Peak memory 200304 kb
Host smart-b70ec5c2-bccb-4033-9a2b-c638eb24f37f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288667601 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_wipe_secret.2288667601
Directory /workspace/29.hmac_wipe_secret/latest

Test location /workspace/coverage/default/3.hmac_alert_test.2272979778
Short name T515
Test name
Test status
Simulation time 52266372 ps
CPU time 0.6 seconds
Started Jun 29 05:08:22 PM PDT 24
Finished Jun 29 05:08:23 PM PDT 24
Peak memory 196320 kb
Host smart-dda58173-b6d5-49f6-a852-b29acb073926
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272979778 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_alert_test.2272979778
Directory /workspace/3.hmac_alert_test/latest

Test location /workspace/coverage/default/3.hmac_back_pressure.2621090582
Short name T441
Test name
Test status
Simulation time 34538657 ps
CPU time 1.16 seconds
Started Jun 29 05:08:11 PM PDT 24
Finished Jun 29 05:08:13 PM PDT 24
Peak memory 199952 kb
Host smart-f59f3b86-0aa3-420e-918e-bb258eb73984
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2621090582 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_back_pressure.2621090582
Directory /workspace/3.hmac_back_pressure/latest

Test location /workspace/coverage/default/3.hmac_burst_wr.1221330379
Short name T571
Test name
Test status
Simulation time 3916340829 ps
CPU time 54.05 seconds
Started Jun 29 05:08:21 PM PDT 24
Finished Jun 29 05:09:16 PM PDT 24
Peak memory 200364 kb
Host smart-24f6cdae-d382-4882-b1cc-7a2c7893b42e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221330379 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_burst_wr.1221330379
Directory /workspace/3.hmac_burst_wr/latest

Test location /workspace/coverage/default/3.hmac_datapath_stress.1628865422
Short name T502
Test name
Test status
Simulation time 549501714 ps
CPU time 163.16 seconds
Started Jun 29 05:08:21 PM PDT 24
Finished Jun 29 05:11:05 PM PDT 24
Peak memory 459772 kb
Host smart-641f4795-993a-408b-9c6e-d90cef8e0941
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1628865422 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_datapath_stress.1628865422
Directory /workspace/3.hmac_datapath_stress/latest

Test location /workspace/coverage/default/3.hmac_error.1207859081
Short name T16
Test name
Test status
Simulation time 1788006367 ps
CPU time 30.3 seconds
Started Jun 29 05:08:22 PM PDT 24
Finished Jun 29 05:08:53 PM PDT 24
Peak memory 200268 kb
Host smart-d50d9151-0329-4338-be4d-259ee0f9d033
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207859081 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_error.1207859081
Directory /workspace/3.hmac_error/latest

Test location /workspace/coverage/default/3.hmac_sec_cm.183360019
Short name T42
Test name
Test status
Simulation time 71732751 ps
CPU time 0.89 seconds
Started Jun 29 05:08:23 PM PDT 24
Finished Jun 29 05:08:24 PM PDT 24
Peak memory 218740 kb
Host smart-12d91f8f-3fa5-47ac-bc7f-f423018c9363
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183360019 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_sec_cm.183360019
Directory /workspace/3.hmac_sec_cm/latest

Test location /workspace/coverage/default/3.hmac_smoke.416867844
Short name T429
Test name
Test status
Simulation time 517576533 ps
CPU time 8.02 seconds
Started Jun 29 05:08:15 PM PDT 24
Finished Jun 29 05:08:23 PM PDT 24
Peak memory 200284 kb
Host smart-a9f49a54-6032-4c0b-9eda-6f2bf1264886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416867844 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_smoke.416867844
Directory /workspace/3.hmac_smoke/latest

Test location /workspace/coverage/default/3.hmac_stress_all.1354707179
Short name T120
Test name
Test status
Simulation time 710700485112 ps
CPU time 3033.51 seconds
Started Jun 29 05:08:20 PM PDT 24
Finished Jun 29 05:58:54 PM PDT 24
Peak memory 216048 kb
Host smart-9812ba9e-4ada-4c46-8ce8-ac093f9bd01d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354707179 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all.1354707179
Directory /workspace/3.hmac_stress_all/latest

Test location /workspace/coverage/default/3.hmac_test_hmac256_vectors.3399184329
Short name T645
Test name
Test status
Simulation time 2876906392 ps
CPU time 31.81 seconds
Started Jun 29 05:08:25 PM PDT 24
Finished Jun 29 05:08:57 PM PDT 24
Peak memory 200300 kb
Host smart-fc28b454-1e3c-4807-a436-c8a5b75518d1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3399184329 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac256_vectors.3399184329
Directory /workspace/3.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_hmac384_vectors.1265076713
Short name T218
Test name
Test status
Simulation time 2483019690 ps
CPU time 41.96 seconds
Started Jun 29 05:08:22 PM PDT 24
Finished Jun 29 05:09:05 PM PDT 24
Peak memory 200356 kb
Host smart-dbf8ecd4-7a6f-469a-99ce-d815287a985a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1265076713 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac384_vectors.1265076713
Directory /workspace/3.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_hmac512_vectors.1894846693
Short name T547
Test name
Test status
Simulation time 9915045268 ps
CPU time 113.59 seconds
Started Jun 29 05:08:20 PM PDT 24
Finished Jun 29 05:10:15 PM PDT 24
Peak memory 200364 kb
Host smart-a94a3636-b540-4230-8180-6913323e39bd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1894846693 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac512_vectors.1894846693
Directory /workspace/3.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha256_vectors.4173606414
Short name T411
Test name
Test status
Simulation time 10134565217 ps
CPU time 436.65 seconds
Started Jun 29 05:08:22 PM PDT 24
Finished Jun 29 05:15:39 PM PDT 24
Peak memory 200300 kb
Host smart-85e1b646-efd3-4ccc-bc0e-5662cdb6d4d6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=4173606414 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha256_vectors.4173606414
Directory /workspace/3.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha384_vectors.3259563972
Short name T543
Test name
Test status
Simulation time 138742915036 ps
CPU time 2000.52 seconds
Started Jun 29 05:08:21 PM PDT 24
Finished Jun 29 05:41:42 PM PDT 24
Peak memory 215748 kb
Host smart-b35943b9-94a1-466a-9975-c6aae84c7914
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3259563972 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha384_vectors.3259563972
Directory /workspace/3.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha512_vectors.2513911824
Short name T234
Test name
Test status
Simulation time 309433955920 ps
CPU time 2180.34 seconds
Started Jun 29 05:08:20 PM PDT 24
Finished Jun 29 05:44:41 PM PDT 24
Peak memory 216284 kb
Host smart-103bf3b9-ea7f-4d09-b747-877440c94a7b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2513911824 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha512_vectors.2513911824
Directory /workspace/3.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/3.hmac_wipe_secret.2395810917
Short name T12
Test name
Test status
Simulation time 8760536624 ps
CPU time 82.94 seconds
Started Jun 29 05:08:20 PM PDT 24
Finished Jun 29 05:09:44 PM PDT 24
Peak memory 200380 kb
Host smart-e2fc31c3-fb4b-444e-a0e2-dd4a66d35a83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395810917 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_wipe_secret.2395810917
Directory /workspace/3.hmac_wipe_secret/latest

Test location /workspace/coverage/default/30.hmac_alert_test.3543834851
Short name T348
Test name
Test status
Simulation time 11806726 ps
CPU time 0.58 seconds
Started Jun 29 05:10:33 PM PDT 24
Finished Jun 29 05:10:34 PM PDT 24
Peak memory 196180 kb
Host smart-b83643e3-9ee2-4c1b-93c4-d519f60ad2bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543834851 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_alert_test.3543834851
Directory /workspace/30.hmac_alert_test/latest

Test location /workspace/coverage/default/30.hmac_back_pressure.1396544035
Short name T745
Test name
Test status
Simulation time 1882044123 ps
CPU time 45.14 seconds
Started Jun 29 05:10:35 PM PDT 24
Finished Jun 29 05:11:21 PM PDT 24
Peak memory 200320 kb
Host smart-642ec354-ce76-46b8-9d87-dff617873f48
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1396544035 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_back_pressure.1396544035
Directory /workspace/30.hmac_back_pressure/latest

Test location /workspace/coverage/default/30.hmac_burst_wr.3831488949
Short name T133
Test name
Test status
Simulation time 11310110079 ps
CPU time 46.31 seconds
Started Jun 29 05:10:40 PM PDT 24
Finished Jun 29 05:11:26 PM PDT 24
Peak memory 199956 kb
Host smart-0527e150-2844-4868-a992-6f17ecf7ce9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831488949 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_burst_wr.3831488949
Directory /workspace/30.hmac_burst_wr/latest

Test location /workspace/coverage/default/30.hmac_datapath_stress.3202638807
Short name T646
Test name
Test status
Simulation time 15144268085 ps
CPU time 1150.94 seconds
Started Jun 29 05:10:39 PM PDT 24
Finished Jun 29 05:29:50 PM PDT 24
Peak memory 781212 kb
Host smart-359aeab5-2d83-4ea2-a6d9-b1de46608b10
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3202638807 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_datapath_stress.3202638807
Directory /workspace/30.hmac_datapath_stress/latest

Test location /workspace/coverage/default/30.hmac_error.1923078987
Short name T612
Test name
Test status
Simulation time 148858494442 ps
CPU time 139.61 seconds
Started Jun 29 05:10:39 PM PDT 24
Finished Jun 29 05:12:59 PM PDT 24
Peak memory 200324 kb
Host smart-28d5bcee-f0d8-4baf-ac87-0df6b92dbda8
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923078987 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_error.1923078987
Directory /workspace/30.hmac_error/latest

Test location /workspace/coverage/default/30.hmac_long_msg.139686135
Short name T276
Test name
Test status
Simulation time 6606180404 ps
CPU time 67.92 seconds
Started Jun 29 05:10:36 PM PDT 24
Finished Jun 29 05:11:44 PM PDT 24
Peak memory 200364 kb
Host smart-838576fa-7bf5-4168-9748-4e4a99b06555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139686135 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_long_msg.139686135
Directory /workspace/30.hmac_long_msg/latest

Test location /workspace/coverage/default/30.hmac_smoke.2848208242
Short name T504
Test name
Test status
Simulation time 696329393 ps
CPU time 9.39 seconds
Started Jun 29 05:10:34 PM PDT 24
Finished Jun 29 05:10:44 PM PDT 24
Peak memory 200216 kb
Host smart-709e12cc-b303-4bc5-b556-47a23bdc4e4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848208242 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_smoke.2848208242
Directory /workspace/30.hmac_smoke/latest

Test location /workspace/coverage/default/30.hmac_stress_all.742033699
Short name T297
Test name
Test status
Simulation time 1492384210307 ps
CPU time 4360.91 seconds
Started Jun 29 05:10:39 PM PDT 24
Finished Jun 29 06:23:21 PM PDT 24
Peak memory 673588 kb
Host smart-50e1db67-fb93-4622-84e8-91f70b0506e7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742033699 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 30.hmac_stress_all.742033699
Directory /workspace/30.hmac_stress_all/latest

Test location /workspace/coverage/default/30.hmac_test_hmac256_vectors.1111112400
Short name T350
Test name
Test status
Simulation time 3001135309 ps
CPU time 61.47 seconds
Started Jun 29 05:10:38 PM PDT 24
Finished Jun 29 05:11:40 PM PDT 24
Peak memory 200332 kb
Host smart-4c1bdbe7-4171-45aa-aab4-af8171fe10e9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1111112400 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_test_hmac256_vectors.1111112400
Directory /workspace/30.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/30.hmac_test_hmac384_vectors.3104196199
Short name T396
Test name
Test status
Simulation time 3598015595 ps
CPU time 54.06 seconds
Started Jun 29 05:10:37 PM PDT 24
Finished Jun 29 05:11:31 PM PDT 24
Peak memory 200552 kb
Host smart-8ab3b2a7-ace6-48e0-8afa-fa5f364aa311
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3104196199 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_test_hmac384_vectors.3104196199
Directory /workspace/30.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/30.hmac_test_hmac512_vectors.3462548467
Short name T322
Test name
Test status
Simulation time 3442373879 ps
CPU time 101.83 seconds
Started Jun 29 05:10:33 PM PDT 24
Finished Jun 29 05:12:16 PM PDT 24
Peak memory 200312 kb
Host smart-aca329ca-81cd-4907-8cc8-a44596de4c89
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3462548467 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_test_hmac512_vectors.3462548467
Directory /workspace/30.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/30.hmac_test_sha256_vectors.2360195613
Short name T378
Test name
Test status
Simulation time 137935488494 ps
CPU time 448.99 seconds
Started Jun 29 05:10:35 PM PDT 24
Finished Jun 29 05:18:05 PM PDT 24
Peak memory 200232 kb
Host smart-a9bfb726-8297-4a72-90d6-1b14694e0d8e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2360195613 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_test_sha256_vectors.2360195613
Directory /workspace/30.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/30.hmac_test_sha384_vectors.833699021
Short name T730
Test name
Test status
Simulation time 585625859444 ps
CPU time 2131.65 seconds
Started Jun 29 05:10:40 PM PDT 24
Finished Jun 29 05:46:12 PM PDT 24
Peak memory 215260 kb
Host smart-523df216-d61e-48b9-9a01-909a79a8116c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=833699021 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_test_sha384_vectors.833699021
Directory /workspace/30.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/30.hmac_test_sha512_vectors.1201049963
Short name T239
Test name
Test status
Simulation time 236191894108 ps
CPU time 2135.59 seconds
Started Jun 29 05:10:33 PM PDT 24
Finished Jun 29 05:46:09 PM PDT 24
Peak memory 216176 kb
Host smart-4e6725fa-0106-4b96-bd52-0d1efda82224
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1201049963 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_test_sha512_vectors.1201049963
Directory /workspace/30.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/30.hmac_wipe_secret.1212924712
Short name T801
Test name
Test status
Simulation time 1601056866 ps
CPU time 73.43 seconds
Started Jun 29 05:10:33 PM PDT 24
Finished Jun 29 05:11:47 PM PDT 24
Peak memory 200204 kb
Host smart-864cb01e-28d2-459b-bd3e-d4c4788a7584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212924712 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_wipe_secret.1212924712
Directory /workspace/30.hmac_wipe_secret/latest

Test location /workspace/coverage/default/31.hmac_alert_test.2060082616
Short name T588
Test name
Test status
Simulation time 11335984 ps
CPU time 0.59 seconds
Started Jun 29 05:10:43 PM PDT 24
Finished Jun 29 05:10:45 PM PDT 24
Peak memory 195228 kb
Host smart-d82cfbc9-6911-4ee2-9722-2057f5b3342a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060082616 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_alert_test.2060082616
Directory /workspace/31.hmac_alert_test/latest

Test location /workspace/coverage/default/31.hmac_back_pressure.3667986032
Short name T351
Test name
Test status
Simulation time 2281231465 ps
CPU time 29.15 seconds
Started Jun 29 05:10:34 PM PDT 24
Finished Jun 29 05:11:04 PM PDT 24
Peak memory 200220 kb
Host smart-d458af82-2fc5-486c-89fd-9a5ae9ce3b78
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3667986032 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_back_pressure.3667986032
Directory /workspace/31.hmac_back_pressure/latest

Test location /workspace/coverage/default/31.hmac_burst_wr.78197428
Short name T735
Test name
Test status
Simulation time 672458849 ps
CPU time 36.36 seconds
Started Jun 29 05:10:35 PM PDT 24
Finished Jun 29 05:11:11 PM PDT 24
Peak memory 200264 kb
Host smart-87c71832-6639-4fb5-8230-267d5f765c60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78197428 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_burst_wr.78197428
Directory /workspace/31.hmac_burst_wr/latest

Test location /workspace/coverage/default/31.hmac_datapath_stress.4246668619
Short name T134
Test name
Test status
Simulation time 1046784730 ps
CPU time 174.21 seconds
Started Jun 29 05:10:34 PM PDT 24
Finished Jun 29 05:13:28 PM PDT 24
Peak memory 455716 kb
Host smart-e636a6b8-6048-4fb1-86a3-24ab1a52c04a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4246668619 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_datapath_stress.4246668619
Directory /workspace/31.hmac_datapath_stress/latest

Test location /workspace/coverage/default/31.hmac_error.2403700217
Short name T293
Test name
Test status
Simulation time 6092107075 ps
CPU time 86.13 seconds
Started Jun 29 05:10:33 PM PDT 24
Finished Jun 29 05:12:00 PM PDT 24
Peak memory 200328 kb
Host smart-77428740-3151-442b-a45b-b4f7959975b6
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403700217 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_error.2403700217
Directory /workspace/31.hmac_error/latest

Test location /workspace/coverage/default/31.hmac_long_msg.53220771
Short name T334
Test name
Test status
Simulation time 5791256743 ps
CPU time 90.88 seconds
Started Jun 29 05:10:34 PM PDT 24
Finished Jun 29 05:12:05 PM PDT 24
Peak memory 216540 kb
Host smart-4396ccfb-d21b-40ed-82e4-73dad9199600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53220771 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_long_msg.53220771
Directory /workspace/31.hmac_long_msg/latest

Test location /workspace/coverage/default/31.hmac_smoke.3544556495
Short name T535
Test name
Test status
Simulation time 288909623 ps
CPU time 5.76 seconds
Started Jun 29 05:10:34 PM PDT 24
Finished Jun 29 05:10:40 PM PDT 24
Peak memory 200284 kb
Host smart-dbf04815-9817-4bf2-963c-2883e72920c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544556495 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_smoke.3544556495
Directory /workspace/31.hmac_smoke/latest

Test location /workspace/coverage/default/31.hmac_stress_all.717097533
Short name T790
Test name
Test status
Simulation time 6404395230 ps
CPU time 101.05 seconds
Started Jun 29 05:10:33 PM PDT 24
Finished Jun 29 05:12:15 PM PDT 24
Peak memory 200328 kb
Host smart-8c5bb9e6-aac0-40fc-96d0-5d7c192c3488
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717097533 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 31.hmac_stress_all.717097533
Directory /workspace/31.hmac_stress_all/latest

Test location /workspace/coverage/default/31.hmac_test_hmac256_vectors.1575462639
Short name T181
Test name
Test status
Simulation time 2828783121 ps
CPU time 60.33 seconds
Started Jun 29 05:10:39 PM PDT 24
Finished Jun 29 05:11:40 PM PDT 24
Peak memory 200332 kb
Host smart-39615904-4ab5-44e2-a17d-f663f48d4b78
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1575462639 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_test_hmac256_vectors.1575462639
Directory /workspace/31.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/31.hmac_test_hmac384_vectors.1528809893
Short name T737
Test name
Test status
Simulation time 19486085198 ps
CPU time 53.89 seconds
Started Jun 29 05:10:36 PM PDT 24
Finished Jun 29 05:11:30 PM PDT 24
Peak memory 200332 kb
Host smart-0fd1e69e-0096-44d9-bedd-490963b5c5ac
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1528809893 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_test_hmac384_vectors.1528809893
Directory /workspace/31.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/31.hmac_test_hmac512_vectors.3118279287
Short name T85
Test name
Test status
Simulation time 26457535735 ps
CPU time 105.88 seconds
Started Jun 29 05:10:33 PM PDT 24
Finished Jun 29 05:12:19 PM PDT 24
Peak memory 200284 kb
Host smart-558e26bc-84cc-4ec3-aed3-6fcbd29d7a74
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3118279287 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_test_hmac512_vectors.3118279287
Directory /workspace/31.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/31.hmac_test_sha256_vectors.3534841509
Short name T613
Test name
Test status
Simulation time 103354332792 ps
CPU time 485.13 seconds
Started Jun 29 05:10:34 PM PDT 24
Finished Jun 29 05:18:40 PM PDT 24
Peak memory 200228 kb
Host smart-f055fed0-dbef-4661-b5f2-f1ded2c454b8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3534841509 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_test_sha256_vectors.3534841509
Directory /workspace/31.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/31.hmac_test_sha384_vectors.1413050572
Short name T281
Test name
Test status
Simulation time 408624429960 ps
CPU time 1677.64 seconds
Started Jun 29 05:10:36 PM PDT 24
Finished Jun 29 05:38:34 PM PDT 24
Peak memory 216480 kb
Host smart-ea47acd4-919a-458d-b706-6b270e053ace
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1413050572 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_test_sha384_vectors.1413050572
Directory /workspace/31.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/31.hmac_test_sha512_vectors.689273630
Short name T791
Test name
Test status
Simulation time 115585332141 ps
CPU time 2028.11 seconds
Started Jun 29 05:10:39 PM PDT 24
Finished Jun 29 05:44:27 PM PDT 24
Peak memory 216508 kb
Host smart-dd88225c-a0fa-4e90-8fd6-16c72fe3ec26
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=689273630 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_test_sha512_vectors.689273630
Directory /workspace/31.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/31.hmac_wipe_secret.1979771512
Short name T478
Test name
Test status
Simulation time 2672886531 ps
CPU time 19.59 seconds
Started Jun 29 05:10:40 PM PDT 24
Finished Jun 29 05:11:00 PM PDT 24
Peak memory 200348 kb
Host smart-dcadc68a-e9fd-4ee3-aa3e-dce82ec732a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1979771512 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_wipe_secret.1979771512
Directory /workspace/31.hmac_wipe_secret/latest

Test location /workspace/coverage/default/32.hmac_alert_test.2497332415
Short name T438
Test name
Test status
Simulation time 37706880 ps
CPU time 0.59 seconds
Started Jun 29 05:10:44 PM PDT 24
Finished Jun 29 05:10:46 PM PDT 24
Peak memory 195228 kb
Host smart-48933eb5-52d9-496b-a4d6-8a6a9b91a12a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497332415 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_alert_test.2497332415
Directory /workspace/32.hmac_alert_test/latest

Test location /workspace/coverage/default/32.hmac_back_pressure.1789836247
Short name T427
Test name
Test status
Simulation time 972738259 ps
CPU time 47.07 seconds
Started Jun 29 05:10:42 PM PDT 24
Finished Jun 29 05:11:30 PM PDT 24
Peak memory 200312 kb
Host smart-d5bb749b-0e66-4f8a-8a27-ced4787d1e12
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1789836247 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_back_pressure.1789836247
Directory /workspace/32.hmac_back_pressure/latest

Test location /workspace/coverage/default/32.hmac_burst_wr.1838612725
Short name T485
Test name
Test status
Simulation time 1309247047 ps
CPU time 19.53 seconds
Started Jun 29 05:10:43 PM PDT 24
Finished Jun 29 05:11:04 PM PDT 24
Peak memory 200300 kb
Host smart-d280a11b-b331-4ce1-bdd0-a722d83ed57d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838612725 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_burst_wr.1838612725
Directory /workspace/32.hmac_burst_wr/latest

Test location /workspace/coverage/default/32.hmac_datapath_stress.3612198529
Short name T194
Test name
Test status
Simulation time 33216336756 ps
CPU time 1210.13 seconds
Started Jun 29 05:10:44 PM PDT 24
Finished Jun 29 05:30:55 PM PDT 24
Peak memory 770496 kb
Host smart-35744d22-a2d8-43a1-934d-8601e40f253a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3612198529 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_datapath_stress.3612198529
Directory /workspace/32.hmac_datapath_stress/latest

Test location /workspace/coverage/default/32.hmac_error.3832198644
Short name T123
Test name
Test status
Simulation time 1626901175 ps
CPU time 24.77 seconds
Started Jun 29 05:10:44 PM PDT 24
Finished Jun 29 05:11:10 PM PDT 24
Peak memory 200184 kb
Host smart-5818c971-eb54-41ad-b1aa-63a1c9abfda6
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832198644 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_error.3832198644
Directory /workspace/32.hmac_error/latest

Test location /workspace/coverage/default/32.hmac_long_msg.2287213591
Short name T537
Test name
Test status
Simulation time 15504853225 ps
CPU time 118.81 seconds
Started Jun 29 05:10:44 PM PDT 24
Finished Jun 29 05:12:44 PM PDT 24
Peak memory 200348 kb
Host smart-3554fa28-0952-4ddc-9f0c-6c5ed8b2ef94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287213591 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_long_msg.2287213591
Directory /workspace/32.hmac_long_msg/latest

Test location /workspace/coverage/default/32.hmac_smoke.1349792204
Short name T4
Test name
Test status
Simulation time 2975887077 ps
CPU time 16.24 seconds
Started Jun 29 05:10:43 PM PDT 24
Finished Jun 29 05:11:01 PM PDT 24
Peak memory 200344 kb
Host smart-75c7acc2-0570-46fe-af78-b7b2bb70bdca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349792204 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_smoke.1349792204
Directory /workspace/32.hmac_smoke/latest

Test location /workspace/coverage/default/32.hmac_stress_all.974135610
Short name T664
Test name
Test status
Simulation time 35590696962 ps
CPU time 499.73 seconds
Started Jun 29 05:10:43 PM PDT 24
Finished Jun 29 05:19:05 PM PDT 24
Peak memory 200356 kb
Host smart-5a4a42b6-e4cf-453e-8169-0b9c6c3755eb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974135610 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 32.hmac_stress_all.974135610
Directory /workspace/32.hmac_stress_all/latest

Test location /workspace/coverage/default/32.hmac_test_hmac256_vectors.248399924
Short name T732
Test name
Test status
Simulation time 2881049608 ps
CPU time 35.3 seconds
Started Jun 29 05:10:44 PM PDT 24
Finished Jun 29 05:11:21 PM PDT 24
Peak memory 200328 kb
Host smart-378ef276-cc85-4bda-a8d1-6cd3b0f6830f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=248399924 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_test_hmac256_vectors.248399924
Directory /workspace/32.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/32.hmac_test_hmac384_vectors.3736061753
Short name T608
Test name
Test status
Simulation time 14507928945 ps
CPU time 51.77 seconds
Started Jun 29 05:10:44 PM PDT 24
Finished Jun 29 05:11:37 PM PDT 24
Peak memory 200260 kb
Host smart-bdd472fb-b4a1-4ea7-83b3-f46072d94d81
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3736061753 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_test_hmac384_vectors.3736061753
Directory /workspace/32.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/32.hmac_test_hmac512_vectors.3635449871
Short name T461
Test name
Test status
Simulation time 5227217537 ps
CPU time 95.61 seconds
Started Jun 29 05:10:46 PM PDT 24
Finished Jun 29 05:12:23 PM PDT 24
Peak memory 200332 kb
Host smart-271848a3-2063-425a-a737-cd915064f40f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3635449871 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_test_hmac512_vectors.3635449871
Directory /workspace/32.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/32.hmac_test_sha256_vectors.187573570
Short name T606
Test name
Test status
Simulation time 72553919432 ps
CPU time 483.03 seconds
Started Jun 29 05:10:43 PM PDT 24
Finished Jun 29 05:18:48 PM PDT 24
Peak memory 200264 kb
Host smart-c4a0c7ef-94fe-4bb7-96d8-973929d0fa01
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=187573570 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_test_sha256_vectors.187573570
Directory /workspace/32.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/32.hmac_test_sha384_vectors.1502576420
Short name T313
Test name
Test status
Simulation time 587579352692 ps
CPU time 1981.68 seconds
Started Jun 29 05:10:47 PM PDT 24
Finished Jun 29 05:43:49 PM PDT 24
Peak memory 215704 kb
Host smart-a0b4dfc6-39cc-4ac6-b6dc-95e7e29dceba
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1502576420 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_test_sha384_vectors.1502576420
Directory /workspace/32.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/32.hmac_test_sha512_vectors.2560006748
Short name T669
Test name
Test status
Simulation time 57668698592 ps
CPU time 1729.16 seconds
Started Jun 29 05:10:43 PM PDT 24
Finished Jun 29 05:39:34 PM PDT 24
Peak memory 215788 kb
Host smart-8150ff0e-5775-40b3-815b-e98844d204bf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2560006748 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_test_sha512_vectors.2560006748
Directory /workspace/32.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/32.hmac_wipe_secret.1404701309
Short name T473
Test name
Test status
Simulation time 1819103664 ps
CPU time 83.29 seconds
Started Jun 29 05:10:43 PM PDT 24
Finished Jun 29 05:12:08 PM PDT 24
Peak memory 200212 kb
Host smart-1d0a71b6-1f8d-47f1-acb5-e57731a44c96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404701309 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_wipe_secret.1404701309
Directory /workspace/32.hmac_wipe_secret/latest

Test location /workspace/coverage/default/33.hmac_alert_test.1572602622
Short name T35
Test name
Test status
Simulation time 30373536 ps
CPU time 0.56 seconds
Started Jun 29 05:10:52 PM PDT 24
Finished Jun 29 05:10:53 PM PDT 24
Peak memory 195196 kb
Host smart-f294521c-2700-4245-81e8-f2d6e5b25ac4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572602622 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_alert_test.1572602622
Directory /workspace/33.hmac_alert_test/latest

Test location /workspace/coverage/default/33.hmac_back_pressure.2876179914
Short name T95
Test name
Test status
Simulation time 3026614231 ps
CPU time 37.23 seconds
Started Jun 29 05:10:44 PM PDT 24
Finished Jun 29 05:11:23 PM PDT 24
Peak memory 200312 kb
Host smart-d0a36750-8abf-4fbc-809a-98cc8367cdcf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2876179914 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_back_pressure.2876179914
Directory /workspace/33.hmac_back_pressure/latest

Test location /workspace/coverage/default/33.hmac_burst_wr.3257474114
Short name T305
Test name
Test status
Simulation time 2324744184 ps
CPU time 33.67 seconds
Started Jun 29 05:10:48 PM PDT 24
Finished Jun 29 05:11:22 PM PDT 24
Peak memory 200328 kb
Host smart-dab644bd-86cf-4e5f-b0d9-81dcf71b6067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257474114 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_burst_wr.3257474114
Directory /workspace/33.hmac_burst_wr/latest

Test location /workspace/coverage/default/33.hmac_datapath_stress.4016209080
Short name T405
Test name
Test status
Simulation time 14450980813 ps
CPU time 996.94 seconds
Started Jun 29 05:10:44 PM PDT 24
Finished Jun 29 05:27:22 PM PDT 24
Peak memory 697112 kb
Host smart-abdf40f2-9177-493d-bfeb-63e04ea5b94e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4016209080 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_datapath_stress.4016209080
Directory /workspace/33.hmac_datapath_stress/latest

Test location /workspace/coverage/default/33.hmac_error.2268493197
Short name T199
Test name
Test status
Simulation time 1563818744 ps
CPU time 27.97 seconds
Started Jun 29 05:10:48 PM PDT 24
Finished Jun 29 05:11:16 PM PDT 24
Peak memory 200104 kb
Host smart-52eea2e2-02af-4f44-b7dd-b145f18b234d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268493197 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_error.2268493197
Directory /workspace/33.hmac_error/latest

Test location /workspace/coverage/default/33.hmac_long_msg.3454416657
Short name T387
Test name
Test status
Simulation time 2451239034 ps
CPU time 13.01 seconds
Started Jun 29 05:10:43 PM PDT 24
Finished Jun 29 05:10:58 PM PDT 24
Peak memory 200200 kb
Host smart-b37e8dc9-0ad4-4359-9ffc-7ac7ab6330d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454416657 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_long_msg.3454416657
Directory /workspace/33.hmac_long_msg/latest

Test location /workspace/coverage/default/33.hmac_smoke.210261552
Short name T357
Test name
Test status
Simulation time 145719892 ps
CPU time 6.78 seconds
Started Jun 29 05:10:44 PM PDT 24
Finished Jun 29 05:10:52 PM PDT 24
Peak memory 200276 kb
Host smart-b3cf19fe-ed76-4a69-b368-dd5d61b8c48e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210261552 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_smoke.210261552
Directory /workspace/33.hmac_smoke/latest

Test location /workspace/coverage/default/33.hmac_stress_all.4235874741
Short name T144
Test name
Test status
Simulation time 38648758307 ps
CPU time 491.84 seconds
Started Jun 29 05:10:52 PM PDT 24
Finished Jun 29 05:19:04 PM PDT 24
Peak memory 200300 kb
Host smart-099cf72b-9838-4960-879a-473d457187e2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235874741 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.hmac_stress_all.4235874741
Directory /workspace/33.hmac_stress_all/latest

Test location /workspace/coverage/default/33.hmac_test_hmac256_vectors.751112280
Short name T436
Test name
Test status
Simulation time 25343284815 ps
CPU time 66.05 seconds
Started Jun 29 05:10:52 PM PDT 24
Finished Jun 29 05:11:59 PM PDT 24
Peak memory 200332 kb
Host smart-45f1ec98-56b1-4b12-bf6b-5fb7726b6b71
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=751112280 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_test_hmac256_vectors.751112280
Directory /workspace/33.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/33.hmac_test_hmac384_vectors.1219199370
Short name T397
Test name
Test status
Simulation time 1560885564 ps
CPU time 50.33 seconds
Started Jun 29 05:10:52 PM PDT 24
Finished Jun 29 05:11:43 PM PDT 24
Peak memory 200304 kb
Host smart-687e35ef-176b-4a66-b1b3-b276f8d2e7d6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1219199370 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_test_hmac384_vectors.1219199370
Directory /workspace/33.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/33.hmac_test_hmac512_vectors.64043559
Short name T682
Test name
Test status
Simulation time 12736130283 ps
CPU time 94.99 seconds
Started Jun 29 05:10:53 PM PDT 24
Finished Jun 29 05:12:28 PM PDT 24
Peak memory 200368 kb
Host smart-4ed2e2ce-9266-4b96-a49f-b34631a66c97
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=64043559 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_test_hmac512_vectors.64043559
Directory /workspace/33.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/33.hmac_test_sha256_vectors.2726714831
Short name T255
Test name
Test status
Simulation time 41309920102 ps
CPU time 521.07 seconds
Started Jun 29 05:10:55 PM PDT 24
Finished Jun 29 05:19:37 PM PDT 24
Peak memory 200288 kb
Host smart-7a8a1dde-62f6-42e8-9488-e31c51f9dac8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2726714831 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_test_sha256_vectors.2726714831
Directory /workspace/33.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/33.hmac_test_sha384_vectors.1408152178
Short name T360
Test name
Test status
Simulation time 110450524527 ps
CPU time 2132.76 seconds
Started Jun 29 05:10:53 PM PDT 24
Finished Jun 29 05:46:26 PM PDT 24
Peak memory 215680 kb
Host smart-3e049289-6b04-4a2f-a18a-60fbc22de7ca
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1408152178 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_test_sha384_vectors.1408152178
Directory /workspace/33.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/33.hmac_test_sha512_vectors.2123021907
Short name T286
Test name
Test status
Simulation time 33402572531 ps
CPU time 1874.69 seconds
Started Jun 29 05:10:51 PM PDT 24
Finished Jun 29 05:42:06 PM PDT 24
Peak memory 215740 kb
Host smart-8ba6e731-b7b4-4940-b0d7-35fa88321066
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2123021907 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_test_sha512_vectors.2123021907
Directory /workspace/33.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/33.hmac_wipe_secret.943972073
Short name T654
Test name
Test status
Simulation time 5414906188 ps
CPU time 53.11 seconds
Started Jun 29 05:10:56 PM PDT 24
Finished Jun 29 05:11:50 PM PDT 24
Peak memory 200380 kb
Host smart-458025fa-63d6-4d47-9e36-d84957014268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943972073 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_wipe_secret.943972073
Directory /workspace/33.hmac_wipe_secret/latest

Test location /workspace/coverage/default/34.hmac_alert_test.3768250000
Short name T37
Test name
Test status
Simulation time 24474004 ps
CPU time 0.58 seconds
Started Jun 29 05:10:53 PM PDT 24
Finished Jun 29 05:10:54 PM PDT 24
Peak memory 195996 kb
Host smart-5538c20f-ff5f-466b-9b66-edf0b577c2e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768250000 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_alert_test.3768250000
Directory /workspace/34.hmac_alert_test/latest

Test location /workspace/coverage/default/34.hmac_back_pressure.2858414609
Short name T317
Test name
Test status
Simulation time 4585536560 ps
CPU time 55.1 seconds
Started Jun 29 05:10:53 PM PDT 24
Finished Jun 29 05:11:48 PM PDT 24
Peak memory 216480 kb
Host smart-9551592e-4cbf-47c2-8bf3-e5dd3409e621
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2858414609 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_back_pressure.2858414609
Directory /workspace/34.hmac_back_pressure/latest

Test location /workspace/coverage/default/34.hmac_burst_wr.1123104452
Short name T624
Test name
Test status
Simulation time 1009492240 ps
CPU time 55.26 seconds
Started Jun 29 05:10:57 PM PDT 24
Finished Jun 29 05:11:52 PM PDT 24
Peak memory 200328 kb
Host smart-bf7fac14-a011-4559-a164-c627ac0d481f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123104452 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_burst_wr.1123104452
Directory /workspace/34.hmac_burst_wr/latest

Test location /workspace/coverage/default/34.hmac_datapath_stress.3602640339
Short name T227
Test name
Test status
Simulation time 1884331365 ps
CPU time 589.15 seconds
Started Jun 29 05:10:54 PM PDT 24
Finished Jun 29 05:20:43 PM PDT 24
Peak memory 682356 kb
Host smart-355faa2d-3ed4-4cb9-a62d-1d43bbb94563
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3602640339 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_datapath_stress.3602640339
Directory /workspace/34.hmac_datapath_stress/latest

Test location /workspace/coverage/default/34.hmac_error.2843590315
Short name T802
Test name
Test status
Simulation time 693232972 ps
CPU time 37.23 seconds
Started Jun 29 05:10:55 PM PDT 24
Finished Jun 29 05:11:33 PM PDT 24
Peak memory 200188 kb
Host smart-ad01ab7f-f7ec-4a8f-81e0-32d145e8325a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843590315 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_error.2843590315
Directory /workspace/34.hmac_error/latest

Test location /workspace/coverage/default/34.hmac_long_msg.141362503
Short name T748
Test name
Test status
Simulation time 56470506522 ps
CPU time 134.08 seconds
Started Jun 29 05:10:52 PM PDT 24
Finished Jun 29 05:13:06 PM PDT 24
Peak memory 200360 kb
Host smart-2cefffba-ba12-4460-a724-2bb594517f22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141362503 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_long_msg.141362503
Directory /workspace/34.hmac_long_msg/latest

Test location /workspace/coverage/default/34.hmac_smoke.910645873
Short name T279
Test name
Test status
Simulation time 801589584 ps
CPU time 7.85 seconds
Started Jun 29 05:10:54 PM PDT 24
Finished Jun 29 05:11:03 PM PDT 24
Peak memory 200288 kb
Host smart-1976ea40-a31f-443e-bf05-e2b25c8b872e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=910645873 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_smoke.910645873
Directory /workspace/34.hmac_smoke/latest

Test location /workspace/coverage/default/34.hmac_stress_all.309149483
Short name T124
Test name
Test status
Simulation time 38244641966 ps
CPU time 271.02 seconds
Started Jun 29 05:10:57 PM PDT 24
Finished Jun 29 05:15:28 PM PDT 24
Peak memory 200368 kb
Host smart-8076b9fe-562c-4234-9e56-9036b0f1a0b2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309149483 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 34.hmac_stress_all.309149483
Directory /workspace/34.hmac_stress_all/latest

Test location /workspace/coverage/default/34.hmac_test_hmac256_vectors.3406321928
Short name T249
Test name
Test status
Simulation time 2082653471 ps
CPU time 35.54 seconds
Started Jun 29 05:10:56 PM PDT 24
Finished Jun 29 05:11:32 PM PDT 24
Peak memory 200276 kb
Host smart-42d980cf-9f97-40f3-8861-3c91b3ad11ff
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3406321928 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_test_hmac256_vectors.3406321928
Directory /workspace/34.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/34.hmac_test_hmac384_vectors.2216909630
Short name T697
Test name
Test status
Simulation time 14710224559 ps
CPU time 88.22 seconds
Started Jun 29 05:10:57 PM PDT 24
Finished Jun 29 05:12:26 PM PDT 24
Peak memory 200308 kb
Host smart-38b5bf28-51e3-4a9f-bdce-353d0e0350b5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2216909630 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_test_hmac384_vectors.2216909630
Directory /workspace/34.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/34.hmac_test_hmac512_vectors.153636187
Short name T184
Test name
Test status
Simulation time 24179642046 ps
CPU time 67.92 seconds
Started Jun 29 05:10:51 PM PDT 24
Finished Jun 29 05:11:59 PM PDT 24
Peak memory 200300 kb
Host smart-68f61c7f-b7a0-4f5e-a45a-2e7b23ab58de
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=153636187 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_test_hmac512_vectors.153636187
Directory /workspace/34.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/34.hmac_test_sha256_vectors.3826895003
Short name T161
Test name
Test status
Simulation time 222225257940 ps
CPU time 533.73 seconds
Started Jun 29 05:10:52 PM PDT 24
Finished Jun 29 05:19:46 PM PDT 24
Peak memory 200300 kb
Host smart-b290b940-b545-4cca-a1e2-0fe7912b1254
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3826895003 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_test_sha256_vectors.3826895003
Directory /workspace/34.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/34.hmac_test_sha384_vectors.1116827969
Short name T628
Test name
Test status
Simulation time 109811980885 ps
CPU time 1983.55 seconds
Started Jun 29 05:10:54 PM PDT 24
Finished Jun 29 05:43:58 PM PDT 24
Peak memory 216716 kb
Host smart-eb5cf815-2ef9-454c-9d71-11d84edf0d4a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1116827969 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_test_sha384_vectors.1116827969
Directory /workspace/34.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/34.hmac_wipe_secret.1151364240
Short name T709
Test name
Test status
Simulation time 8473926183 ps
CPU time 84.27 seconds
Started Jun 29 05:10:54 PM PDT 24
Finished Jun 29 05:12:19 PM PDT 24
Peak memory 200348 kb
Host smart-34a3d022-a5b4-48ab-9e39-b38fd84e93cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151364240 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_wipe_secret.1151364240
Directory /workspace/34.hmac_wipe_secret/latest

Test location /workspace/coverage/default/35.hmac_alert_test.2291255254
Short name T301
Test name
Test status
Simulation time 43318415 ps
CPU time 0.59 seconds
Started Jun 29 05:11:03 PM PDT 24
Finished Jun 29 05:11:04 PM PDT 24
Peak memory 195980 kb
Host smart-1570b64a-bc15-42ed-b478-6e7d0cb89f22
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291255254 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_alert_test.2291255254
Directory /workspace/35.hmac_alert_test/latest

Test location /workspace/coverage/default/35.hmac_back_pressure.3701856089
Short name T299
Test name
Test status
Simulation time 661084117 ps
CPU time 30.85 seconds
Started Jun 29 05:10:52 PM PDT 24
Finished Jun 29 05:11:24 PM PDT 24
Peak memory 200160 kb
Host smart-bd6ffd44-f2cb-4d2e-a240-18ff8b469eeb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3701856089 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_back_pressure.3701856089
Directory /workspace/35.hmac_back_pressure/latest

Test location /workspace/coverage/default/35.hmac_burst_wr.3053261308
Short name T172
Test name
Test status
Simulation time 4168499349 ps
CPU time 62.71 seconds
Started Jun 29 05:10:54 PM PDT 24
Finished Jun 29 05:11:57 PM PDT 24
Peak memory 200380 kb
Host smart-79878a51-b1f1-4b35-ba45-ec0411255f41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3053261308 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_burst_wr.3053261308
Directory /workspace/35.hmac_burst_wr/latest

Test location /workspace/coverage/default/35.hmac_datapath_stress.1435202348
Short name T28
Test name
Test status
Simulation time 11109486397 ps
CPU time 800.96 seconds
Started Jun 29 05:10:53 PM PDT 24
Finished Jun 29 05:24:14 PM PDT 24
Peak memory 696768 kb
Host smart-b4b5689d-de6e-4167-a0c7-fb420144cdcb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1435202348 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_datapath_stress.1435202348
Directory /workspace/35.hmac_datapath_stress/latest

Test location /workspace/coverage/default/35.hmac_error.2601347238
Short name T498
Test name
Test status
Simulation time 38993910391 ps
CPU time 58.6 seconds
Started Jun 29 05:10:52 PM PDT 24
Finished Jun 29 05:11:51 PM PDT 24
Peak memory 200244 kb
Host smart-7fe474af-c0a3-4de4-a549-e0dd1c6ad4ec
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601347238 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_error.2601347238
Directory /workspace/35.hmac_error/latest

Test location /workspace/coverage/default/35.hmac_long_msg.3094433025
Short name T365
Test name
Test status
Simulation time 19899788898 ps
CPU time 107.45 seconds
Started Jun 29 05:10:52 PM PDT 24
Finished Jun 29 05:12:40 PM PDT 24
Peak memory 216724 kb
Host smart-5974c5c1-8d8f-4a00-b09c-7abefb07253d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094433025 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_long_msg.3094433025
Directory /workspace/35.hmac_long_msg/latest

Test location /workspace/coverage/default/35.hmac_smoke.2962530267
Short name T356
Test name
Test status
Simulation time 446854189 ps
CPU time 9.23 seconds
Started Jun 29 05:10:55 PM PDT 24
Finished Jun 29 05:11:05 PM PDT 24
Peak memory 200272 kb
Host smart-af444cd1-592e-4278-a2e0-0f63ab350fe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962530267 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_smoke.2962530267
Directory /workspace/35.hmac_smoke/latest

Test location /workspace/coverage/default/35.hmac_stress_all.1768835849
Short name T73
Test name
Test status
Simulation time 986969062021 ps
CPU time 3534.79 seconds
Started Jun 29 05:11:01 PM PDT 24
Finished Jun 29 06:09:57 PM PDT 24
Peak memory 768048 kb
Host smart-1351b1fb-894c-4180-b4ec-604120cf1f09
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768835849 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.hmac_stress_all.1768835849
Directory /workspace/35.hmac_stress_all/latest

Test location /workspace/coverage/default/35.hmac_test_hmac256_vectors.278284763
Short name T496
Test name
Test status
Simulation time 2525492286 ps
CPU time 43.13 seconds
Started Jun 29 05:11:01 PM PDT 24
Finished Jun 29 05:11:45 PM PDT 24
Peak memory 200324 kb
Host smart-74350cd3-1a85-4d65-8586-04db109eb9ff
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=278284763 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_test_hmac256_vectors.278284763
Directory /workspace/35.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/35.hmac_test_hmac384_vectors.1495599142
Short name T203
Test name
Test status
Simulation time 2018556718 ps
CPU time 79.28 seconds
Started Jun 29 05:11:06 PM PDT 24
Finished Jun 29 05:12:25 PM PDT 24
Peak memory 200308 kb
Host smart-315f6528-a41c-4b86-b69e-b05a8acabb46
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1495599142 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_test_hmac384_vectors.1495599142
Directory /workspace/35.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/35.hmac_test_hmac512_vectors.3203509894
Short name T314
Test name
Test status
Simulation time 31656390953 ps
CPU time 117.87 seconds
Started Jun 29 05:11:01 PM PDT 24
Finished Jun 29 05:13:00 PM PDT 24
Peak memory 200368 kb
Host smart-25b8921c-f539-4e43-89f4-45b089228e1e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3203509894 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_test_hmac512_vectors.3203509894
Directory /workspace/35.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/35.hmac_test_sha256_vectors.3733413902
Short name T786
Test name
Test status
Simulation time 8901445672 ps
CPU time 547.98 seconds
Started Jun 29 05:11:05 PM PDT 24
Finished Jun 29 05:20:14 PM PDT 24
Peak memory 200264 kb
Host smart-ad554fcd-dd76-4906-bd9c-237c8cafb1c8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3733413902 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_test_sha256_vectors.3733413902
Directory /workspace/35.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/35.hmac_test_sha384_vectors.1812253823
Short name T236
Test name
Test status
Simulation time 157276772014 ps
CPU time 1728.13 seconds
Started Jun 29 05:11:04 PM PDT 24
Finished Jun 29 05:39:53 PM PDT 24
Peak memory 216504 kb
Host smart-8cb64f3e-1243-4ac0-ab87-00bc32a19feb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1812253823 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_test_sha384_vectors.1812253823
Directory /workspace/35.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/35.hmac_test_sha512_vectors.2361583460
Short name T455
Test name
Test status
Simulation time 34275853222 ps
CPU time 1785.64 seconds
Started Jun 29 05:11:02 PM PDT 24
Finished Jun 29 05:40:48 PM PDT 24
Peak memory 215780 kb
Host smart-00b645ca-0613-45fa-87ff-f53a99b0483d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2361583460 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_test_sha512_vectors.2361583460
Directory /workspace/35.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/35.hmac_wipe_secret.3619158323
Short name T545
Test name
Test status
Simulation time 440624944 ps
CPU time 6.74 seconds
Started Jun 29 05:10:52 PM PDT 24
Finished Jun 29 05:11:00 PM PDT 24
Peak memory 200132 kb
Host smart-26516966-e35a-46a4-83b5-45cce6b43421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3619158323 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_wipe_secret.3619158323
Directory /workspace/35.hmac_wipe_secret/latest

Test location /workspace/coverage/default/36.hmac_alert_test.4208484528
Short name T720
Test name
Test status
Simulation time 23745553 ps
CPU time 0.6 seconds
Started Jun 29 05:11:06 PM PDT 24
Finished Jun 29 05:11:07 PM PDT 24
Peak memory 197004 kb
Host smart-7a2827ed-4d2b-4c67-9f9d-e7f496560bbf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208484528 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_alert_test.4208484528
Directory /workspace/36.hmac_alert_test/latest

Test location /workspace/coverage/default/36.hmac_back_pressure.600433287
Short name T617
Test name
Test status
Simulation time 1214563031 ps
CPU time 32.61 seconds
Started Jun 29 05:11:02 PM PDT 24
Finished Jun 29 05:11:35 PM PDT 24
Peak memory 200448 kb
Host smart-5d38ded3-7d45-4939-ad51-91e479526a44
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=600433287 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_back_pressure.600433287
Directory /workspace/36.hmac_back_pressure/latest

Test location /workspace/coverage/default/36.hmac_burst_wr.2112566281
Short name T712
Test name
Test status
Simulation time 7483682772 ps
CPU time 27.72 seconds
Started Jun 29 05:11:02 PM PDT 24
Finished Jun 29 05:11:31 PM PDT 24
Peak memory 200532 kb
Host smart-8b7aecc6-b545-4199-8cf1-902009b3ca70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112566281 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_burst_wr.2112566281
Directory /workspace/36.hmac_burst_wr/latest

Test location /workspace/coverage/default/36.hmac_datapath_stress.3387374592
Short name T225
Test name
Test status
Simulation time 11349664724 ps
CPU time 707.28 seconds
Started Jun 29 05:11:01 PM PDT 24
Finished Jun 29 05:22:50 PM PDT 24
Peak memory 695664 kb
Host smart-c5f3d4d9-05c2-450c-aee7-b26826f550ff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3387374592 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_datapath_stress.3387374592
Directory /workspace/36.hmac_datapath_stress/latest

Test location /workspace/coverage/default/36.hmac_error.3930711144
Short name T198
Test name
Test status
Simulation time 15198511491 ps
CPU time 66.79 seconds
Started Jun 29 05:11:03 PM PDT 24
Finished Jun 29 05:12:10 PM PDT 24
Peak memory 200260 kb
Host smart-9909a02c-f432-49dd-bfb2-121f0c8f4bc6
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930711144 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_error.3930711144
Directory /workspace/36.hmac_error/latest

Test location /workspace/coverage/default/36.hmac_long_msg.376486872
Short name T492
Test name
Test status
Simulation time 8452161642 ps
CPU time 87.9 seconds
Started Jun 29 05:11:01 PM PDT 24
Finished Jun 29 05:12:30 PM PDT 24
Peak memory 208588 kb
Host smart-de1382f4-8915-416e-bdfd-c59b0696fc19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376486872 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_long_msg.376486872
Directory /workspace/36.hmac_long_msg/latest

Test location /workspace/coverage/default/36.hmac_smoke.82761468
Short name T579
Test name
Test status
Simulation time 2032523242 ps
CPU time 8.73 seconds
Started Jun 29 05:11:01 PM PDT 24
Finished Jun 29 05:11:10 PM PDT 24
Peak memory 200288 kb
Host smart-39aac2d9-b6f7-4314-87b0-70af8faf4212
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82761468 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_smoke.82761468
Directory /workspace/36.hmac_smoke/latest

Test location /workspace/coverage/default/36.hmac_stress_all.3204536364
Short name T469
Test name
Test status
Simulation time 255714016283 ps
CPU time 1154.56 seconds
Started Jun 29 05:11:01 PM PDT 24
Finished Jun 29 05:30:17 PM PDT 24
Peak memory 200336 kb
Host smart-7428193d-8c90-4763-857d-7e62914ee806
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204536364 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.hmac_stress_all.3204536364
Directory /workspace/36.hmac_stress_all/latest

Test location /workspace/coverage/default/36.hmac_test_hmac256_vectors.1197762773
Short name T382
Test name
Test status
Simulation time 5879325074 ps
CPU time 58.16 seconds
Started Jun 29 05:11:03 PM PDT 24
Finished Jun 29 05:12:01 PM PDT 24
Peak memory 200260 kb
Host smart-738131ea-94d1-4a7b-87c4-211f10750fcb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1197762773 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_test_hmac256_vectors.1197762773
Directory /workspace/36.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/36.hmac_test_hmac384_vectors.3610140779
Short name T326
Test name
Test status
Simulation time 12052839842 ps
CPU time 45.42 seconds
Started Jun 29 05:11:06 PM PDT 24
Finished Jun 29 05:11:51 PM PDT 24
Peak memory 200332 kb
Host smart-a855f750-bd84-4b48-b357-a87527dd5221
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3610140779 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_test_hmac384_vectors.3610140779
Directory /workspace/36.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/36.hmac_test_hmac512_vectors.2214167069
Short name T189
Test name
Test status
Simulation time 7590368137 ps
CPU time 118.33 seconds
Started Jun 29 05:11:04 PM PDT 24
Finished Jun 29 05:13:03 PM PDT 24
Peak memory 200220 kb
Host smart-2bda5e3a-f81a-475d-ace4-1ee9506ae943
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2214167069 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_test_hmac512_vectors.2214167069
Directory /workspace/36.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/36.hmac_test_sha256_vectors.2454264462
Short name T520
Test name
Test status
Simulation time 87096997693 ps
CPU time 542.96 seconds
Started Jun 29 05:11:01 PM PDT 24
Finished Jun 29 05:20:04 PM PDT 24
Peak memory 200252 kb
Host smart-9a758fec-800c-42f3-a296-d246bbd49ffc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2454264462 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_test_sha256_vectors.2454264462
Directory /workspace/36.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/36.hmac_test_sha384_vectors.187765234
Short name T89
Test name
Test status
Simulation time 161535314536 ps
CPU time 2059.72 seconds
Started Jun 29 05:11:04 PM PDT 24
Finished Jun 29 05:45:24 PM PDT 24
Peak memory 216684 kb
Host smart-3c0df534-2871-42cc-b40b-24a2e486c34a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=187765234 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_test_sha384_vectors.187765234
Directory /workspace/36.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/36.hmac_wipe_secret.785502940
Short name T633
Test name
Test status
Simulation time 8050784552 ps
CPU time 76.1 seconds
Started Jun 29 05:11:03 PM PDT 24
Finished Jun 29 05:12:19 PM PDT 24
Peak memory 200344 kb
Host smart-f52d25fc-4359-4376-a571-d14d47d6380b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785502940 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_wipe_secret.785502940
Directory /workspace/36.hmac_wipe_secret/latest

Test location /workspace/coverage/default/37.hmac_alert_test.860142019
Short name T509
Test name
Test status
Simulation time 12981777 ps
CPU time 0.61 seconds
Started Jun 29 05:11:13 PM PDT 24
Finished Jun 29 05:11:14 PM PDT 24
Peak memory 197004 kb
Host smart-709b1038-6d88-46f9-8eef-8e9c880df222
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860142019 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_alert_test.860142019
Directory /workspace/37.hmac_alert_test/latest

Test location /workspace/coverage/default/37.hmac_back_pressure.2638524513
Short name T532
Test name
Test status
Simulation time 306238623 ps
CPU time 6.72 seconds
Started Jun 29 05:11:10 PM PDT 24
Finished Jun 29 05:11:17 PM PDT 24
Peak memory 200232 kb
Host smart-a7dfc6be-71ae-4778-bdd0-e303729f1254
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2638524513 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_back_pressure.2638524513
Directory /workspace/37.hmac_back_pressure/latest

Test location /workspace/coverage/default/37.hmac_burst_wr.3885481043
Short name T254
Test name
Test status
Simulation time 823602481 ps
CPU time 4.09 seconds
Started Jun 29 05:11:12 PM PDT 24
Finished Jun 29 05:11:17 PM PDT 24
Peak memory 200224 kb
Host smart-01c1e46a-27f9-4666-a7e6-93190dcacc4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885481043 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_burst_wr.3885481043
Directory /workspace/37.hmac_burst_wr/latest

Test location /workspace/coverage/default/37.hmac_datapath_stress.3298911869
Short name T11
Test name
Test status
Simulation time 2709208720 ps
CPU time 657.78 seconds
Started Jun 29 05:11:11 PM PDT 24
Finished Jun 29 05:22:09 PM PDT 24
Peak memory 618672 kb
Host smart-4714b5b7-5c4e-40bc-8955-2a16e2ff219a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3298911869 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_datapath_stress.3298911869
Directory /workspace/37.hmac_datapath_stress/latest

Test location /workspace/coverage/default/37.hmac_error.1726947688
Short name T306
Test name
Test status
Simulation time 7004069000 ps
CPU time 60.23 seconds
Started Jun 29 05:11:11 PM PDT 24
Finished Jun 29 05:12:12 PM PDT 24
Peak memory 200324 kb
Host smart-bb8cf79a-0efa-467a-9871-b712e64a168b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726947688 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_error.1726947688
Directory /workspace/37.hmac_error/latest

Test location /workspace/coverage/default/37.hmac_long_msg.2419765680
Short name T449
Test name
Test status
Simulation time 14292743312 ps
CPU time 68.23 seconds
Started Jun 29 05:11:04 PM PDT 24
Finished Jun 29 05:12:12 PM PDT 24
Peak memory 200548 kb
Host smart-37586d88-0134-4c8c-958b-01ebb02cfd99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419765680 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_long_msg.2419765680
Directory /workspace/37.hmac_long_msg/latest

Test location /workspace/coverage/default/37.hmac_smoke.3145845494
Short name T437
Test name
Test status
Simulation time 788269394 ps
CPU time 9.71 seconds
Started Jun 29 05:11:04 PM PDT 24
Finished Jun 29 05:11:14 PM PDT 24
Peak memory 200172 kb
Host smart-ef96b684-ddbd-4b82-a45a-23f381846039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145845494 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_smoke.3145845494
Directory /workspace/37.hmac_smoke/latest

Test location /workspace/coverage/default/37.hmac_test_hmac256_vectors.737748201
Short name T422
Test name
Test status
Simulation time 3552373700 ps
CPU time 40.63 seconds
Started Jun 29 05:11:11 PM PDT 24
Finished Jun 29 05:11:52 PM PDT 24
Peak memory 200332 kb
Host smart-b3b2f4a3-6802-4fd3-8d54-c4ec1bad6dc7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=737748201 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_test_hmac256_vectors.737748201
Directory /workspace/37.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/37.hmac_test_hmac384_vectors.364401890
Short name T192
Test name
Test status
Simulation time 1552279019 ps
CPU time 47.77 seconds
Started Jun 29 05:11:10 PM PDT 24
Finished Jun 29 05:11:58 PM PDT 24
Peak memory 200232 kb
Host smart-2e4ebb33-a238-4b74-8fb0-0b5a34e5cf1c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=364401890 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_test_hmac384_vectors.364401890
Directory /workspace/37.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/37.hmac_test_hmac512_vectors.2012542896
Short name T692
Test name
Test status
Simulation time 23131994370 ps
CPU time 74.1 seconds
Started Jun 29 05:11:12 PM PDT 24
Finished Jun 29 05:12:26 PM PDT 24
Peak memory 200332 kb
Host smart-a50c57b1-6979-4ae0-9e2f-d55499f38e6d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2012542896 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_test_hmac512_vectors.2012542896
Directory /workspace/37.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/37.hmac_test_sha256_vectors.818179612
Short name T156
Test name
Test status
Simulation time 35510819012 ps
CPU time 475.94 seconds
Started Jun 29 05:11:12 PM PDT 24
Finished Jun 29 05:19:09 PM PDT 24
Peak memory 200216 kb
Host smart-ec860ec4-7147-46b7-b27b-199fb68a418c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=818179612 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_test_sha256_vectors.818179612
Directory /workspace/37.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/37.hmac_test_sha384_vectors.714504528
Short name T472
Test name
Test status
Simulation time 476301080482 ps
CPU time 1868.71 seconds
Started Jun 29 05:11:10 PM PDT 24
Finished Jun 29 05:42:19 PM PDT 24
Peak memory 215816 kb
Host smart-b5a75e82-e8b6-4fd7-8da0-927794634bc3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=714504528 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_test_sha384_vectors.714504528
Directory /workspace/37.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/37.hmac_test_sha512_vectors.1007769655
Short name T630
Test name
Test status
Simulation time 155838057756 ps
CPU time 1826.84 seconds
Started Jun 29 05:11:10 PM PDT 24
Finished Jun 29 05:41:38 PM PDT 24
Peak memory 216676 kb
Host smart-b8800f63-b685-42a7-8a99-a4f3f6ee22d7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1007769655 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_test_sha512_vectors.1007769655
Directory /workspace/37.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/37.hmac_wipe_secret.1691096302
Short name T10
Test name
Test status
Simulation time 2663283451 ps
CPU time 47.17 seconds
Started Jun 29 05:11:12 PM PDT 24
Finished Jun 29 05:12:00 PM PDT 24
Peak memory 200296 kb
Host smart-8ea66b61-0b6c-48bc-9aa5-6713d320719f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691096302 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_wipe_secret.1691096302
Directory /workspace/37.hmac_wipe_secret/latest

Test location /workspace/coverage/default/38.hmac_alert_test.2980372142
Short name T554
Test name
Test status
Simulation time 114622888 ps
CPU time 0.61 seconds
Started Jun 29 05:11:27 PM PDT 24
Finished Jun 29 05:11:28 PM PDT 24
Peak memory 196972 kb
Host smart-5384df93-a258-4b6d-b321-2bca1bfe52c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980372142 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_alert_test.2980372142
Directory /workspace/38.hmac_alert_test/latest

Test location /workspace/coverage/default/38.hmac_back_pressure.2883512992
Short name T585
Test name
Test status
Simulation time 1004506110 ps
CPU time 12.44 seconds
Started Jun 29 05:11:11 PM PDT 24
Finished Jun 29 05:11:24 PM PDT 24
Peak memory 200208 kb
Host smart-1bf87a13-6c8a-4556-8fad-980629dfda84
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2883512992 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_back_pressure.2883512992
Directory /workspace/38.hmac_back_pressure/latest

Test location /workspace/coverage/default/38.hmac_burst_wr.1476128267
Short name T291
Test name
Test status
Simulation time 6656190689 ps
CPU time 27.88 seconds
Started Jun 29 05:11:12 PM PDT 24
Finished Jun 29 05:11:41 PM PDT 24
Peak memory 200356 kb
Host smart-726e4e07-95fb-454b-a713-abee16c1702c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476128267 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_burst_wr.1476128267
Directory /workspace/38.hmac_burst_wr/latest

Test location /workspace/coverage/default/38.hmac_datapath_stress.82413413
Short name T204
Test name
Test status
Simulation time 37652935132 ps
CPU time 1593.77 seconds
Started Jun 29 05:11:14 PM PDT 24
Finished Jun 29 05:37:49 PM PDT 24
Peak memory 763180 kb
Host smart-fa24f556-20ca-4553-b429-e6af10ef65d0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=82413413 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_datapath_stress.82413413
Directory /workspace/38.hmac_datapath_stress/latest

Test location /workspace/coverage/default/38.hmac_error.558723997
Short name T273
Test name
Test status
Simulation time 22331874653 ps
CPU time 103.3 seconds
Started Jun 29 05:11:12 PM PDT 24
Finished Jun 29 05:12:56 PM PDT 24
Peak memory 200308 kb
Host smart-613057e4-e9b7-498b-9fbd-a0aeecc8fa5a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558723997 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_error.558723997
Directory /workspace/38.hmac_error/latest

Test location /workspace/coverage/default/38.hmac_long_msg.1417529415
Short name T512
Test name
Test status
Simulation time 15408650314 ps
CPU time 64.44 seconds
Started Jun 29 05:11:12 PM PDT 24
Finished Jun 29 05:12:16 PM PDT 24
Peak memory 200340 kb
Host smart-583f8840-d891-4251-b939-5c181d040f96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417529415 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_long_msg.1417529415
Directory /workspace/38.hmac_long_msg/latest

Test location /workspace/coverage/default/38.hmac_smoke.4085999603
Short name T280
Test name
Test status
Simulation time 372374319 ps
CPU time 5.81 seconds
Started Jun 29 05:11:12 PM PDT 24
Finished Jun 29 05:11:18 PM PDT 24
Peak memory 200272 kb
Host smart-6de6c0f0-40c1-4246-90cc-165941c06375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085999603 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_smoke.4085999603
Directory /workspace/38.hmac_smoke/latest

Test location /workspace/coverage/default/38.hmac_stress_all.3266165103
Short name T251
Test name
Test status
Simulation time 787678363553 ps
CPU time 2663.66 seconds
Started Jun 29 05:11:20 PM PDT 24
Finished Jun 29 05:55:44 PM PDT 24
Peak memory 216752 kb
Host smart-bd572718-779a-47ac-8200-1bf7fb822333
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266165103 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.hmac_stress_all.3266165103
Directory /workspace/38.hmac_stress_all/latest

Test location /workspace/coverage/default/38.hmac_test_hmac256_vectors.900116122
Short name T206
Test name
Test status
Simulation time 8287367741 ps
CPU time 32.37 seconds
Started Jun 29 05:11:20 PM PDT 24
Finished Jun 29 05:11:53 PM PDT 24
Peak memory 200372 kb
Host smart-9aad03b5-be3c-4549-9709-795e20ef88f6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=900116122 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_test_hmac256_vectors.900116122
Directory /workspace/38.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/38.hmac_test_hmac384_vectors.963750552
Short name T310
Test name
Test status
Simulation time 4387457594 ps
CPU time 79.08 seconds
Started Jun 29 05:11:18 PM PDT 24
Finished Jun 29 05:12:38 PM PDT 24
Peak memory 200332 kb
Host smart-b1edfb51-d4c7-4627-bb07-b27cedee3182
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=963750552 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_test_hmac384_vectors.963750552
Directory /workspace/38.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/38.hmac_test_hmac512_vectors.3173691137
Short name T604
Test name
Test status
Simulation time 11280566640 ps
CPU time 60.85 seconds
Started Jun 29 05:11:20 PM PDT 24
Finished Jun 29 05:12:22 PM PDT 24
Peak memory 200360 kb
Host smart-4ce0c194-d1d0-411b-9ce4-440d7902b1ca
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3173691137 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_test_hmac512_vectors.3173691137
Directory /workspace/38.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/38.hmac_test_sha256_vectors.3980678632
Short name T332
Test name
Test status
Simulation time 8708011530 ps
CPU time 419.3 seconds
Started Jun 29 05:11:12 PM PDT 24
Finished Jun 29 05:18:12 PM PDT 24
Peak memory 200264 kb
Host smart-b0c5a67d-0a8e-4276-8089-6e4cabd323a6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3980678632 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_test_sha256_vectors.3980678632
Directory /workspace/38.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/38.hmac_test_sha384_vectors.2238144189
Short name T176
Test name
Test status
Simulation time 109723363178 ps
CPU time 2000.26 seconds
Started Jun 29 05:11:18 PM PDT 24
Finished Jun 29 05:44:39 PM PDT 24
Peak memory 215688 kb
Host smart-26d7b806-8b0c-4cad-a2bd-72f4eeec1ac2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2238144189 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_test_sha384_vectors.2238144189
Directory /workspace/38.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/38.hmac_test_sha512_vectors.2044086755
Short name T54
Test name
Test status
Simulation time 248395575166 ps
CPU time 1785.19 seconds
Started Jun 29 05:11:18 PM PDT 24
Finished Jun 29 05:41:04 PM PDT 24
Peak memory 216044 kb
Host smart-7752d3c5-73b4-4d76-b8f0-3329659550e7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2044086755 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_test_sha512_vectors.2044086755
Directory /workspace/38.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/38.hmac_wipe_secret.984264925
Short name T616
Test name
Test status
Simulation time 1813592729 ps
CPU time 25.61 seconds
Started Jun 29 05:11:15 PM PDT 24
Finished Jun 29 05:11:41 PM PDT 24
Peak memory 200296 kb
Host smart-51460316-4ed7-43e6-abcc-306d7b96fbb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984264925 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_wipe_secret.984264925
Directory /workspace/38.hmac_wipe_secret/latest

Test location /workspace/coverage/default/39.hmac_alert_test.1651524777
Short name T544
Test name
Test status
Simulation time 14344739 ps
CPU time 0.6 seconds
Started Jun 29 05:11:20 PM PDT 24
Finished Jun 29 05:11:21 PM PDT 24
Peak memory 196260 kb
Host smart-0194b992-03c1-4c81-9e66-dba9a0ebb2af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651524777 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_alert_test.1651524777
Directory /workspace/39.hmac_alert_test/latest

Test location /workspace/coverage/default/39.hmac_back_pressure.3626885488
Short name T662
Test name
Test status
Simulation time 2471366971 ps
CPU time 29.92 seconds
Started Jun 29 05:11:18 PM PDT 24
Finished Jun 29 05:11:48 PM PDT 24
Peak memory 200328 kb
Host smart-9c41c9ed-cc20-4c8c-8d5a-59ce4141aa8e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3626885488 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_back_pressure.3626885488
Directory /workspace/39.hmac_back_pressure/latest

Test location /workspace/coverage/default/39.hmac_burst_wr.2648330182
Short name T660
Test name
Test status
Simulation time 242411093 ps
CPU time 13.75 seconds
Started Jun 29 05:11:20 PM PDT 24
Finished Jun 29 05:11:34 PM PDT 24
Peak memory 200248 kb
Host smart-dfcd55e1-e823-432f-bf59-cb112d120cbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648330182 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_burst_wr.2648330182
Directory /workspace/39.hmac_burst_wr/latest

Test location /workspace/coverage/default/39.hmac_datapath_stress.4249258057
Short name T481
Test name
Test status
Simulation time 5439797614 ps
CPU time 323.17 seconds
Started Jun 29 05:11:18 PM PDT 24
Finished Jun 29 05:16:42 PM PDT 24
Peak memory 658656 kb
Host smart-6409ac5d-6013-498a-99b0-720badf86ef1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4249258057 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_datapath_stress.4249258057
Directory /workspace/39.hmac_datapath_stress/latest

Test location /workspace/coverage/default/39.hmac_error.3656559419
Short name T511
Test name
Test status
Simulation time 12078102445 ps
CPU time 176.44 seconds
Started Jun 29 05:11:21 PM PDT 24
Finished Jun 29 05:14:18 PM PDT 24
Peak memory 200352 kb
Host smart-d5dbdd47-b9eb-4ced-8305-dfa329610cf7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656559419 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_error.3656559419
Directory /workspace/39.hmac_error/latest

Test location /workspace/coverage/default/39.hmac_long_msg.285688487
Short name T146
Test name
Test status
Simulation time 12686129979 ps
CPU time 64.95 seconds
Started Jun 29 05:11:19 PM PDT 24
Finished Jun 29 05:12:24 PM PDT 24
Peak memory 200344 kb
Host smart-75c2ef0d-c10d-451f-9113-55b358e729de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285688487 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_long_msg.285688487
Directory /workspace/39.hmac_long_msg/latest

Test location /workspace/coverage/default/39.hmac_smoke.1643529844
Short name T450
Test name
Test status
Simulation time 1741094634 ps
CPU time 9.96 seconds
Started Jun 29 05:11:19 PM PDT 24
Finished Jun 29 05:11:30 PM PDT 24
Peak memory 200292 kb
Host smart-bedcbf33-7fbd-4a27-bc02-d8d440be4320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643529844 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_smoke.1643529844
Directory /workspace/39.hmac_smoke/latest

Test location /workspace/coverage/default/39.hmac_stress_all.3469133558
Short name T87
Test name
Test status
Simulation time 1157823895015 ps
CPU time 3116.27 seconds
Started Jun 29 05:11:20 PM PDT 24
Finished Jun 29 06:03:17 PM PDT 24
Peak memory 216396 kb
Host smart-b8f2ea01-a647-45b7-8a50-bbb42a00d254
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469133558 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.hmac_stress_all.3469133558
Directory /workspace/39.hmac_stress_all/latest

Test location /workspace/coverage/default/39.hmac_test_hmac256_vectors.2798115561
Short name T191
Test name
Test status
Simulation time 885362388 ps
CPU time 28.56 seconds
Started Jun 29 05:11:19 PM PDT 24
Finished Jun 29 05:11:48 PM PDT 24
Peak memory 200200 kb
Host smart-d57c16bd-b3bf-4ef1-887c-5ad9b001abb4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2798115561 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_test_hmac256_vectors.2798115561
Directory /workspace/39.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/39.hmac_test_hmac384_vectors.3675404815
Short name T736
Test name
Test status
Simulation time 10191128112 ps
CPU time 78.17 seconds
Started Jun 29 05:11:21 PM PDT 24
Finished Jun 29 05:12:39 PM PDT 24
Peak memory 200336 kb
Host smart-e4a5e1cc-c25f-4c7b-bca5-4ce18dd79ba6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3675404815 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_test_hmac384_vectors.3675404815
Directory /workspace/39.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/39.hmac_test_hmac512_vectors.2798841998
Short name T390
Test name
Test status
Simulation time 3949245528 ps
CPU time 59.83 seconds
Started Jun 29 05:11:21 PM PDT 24
Finished Jun 29 05:12:21 PM PDT 24
Peak memory 200332 kb
Host smart-d869bf31-cc75-4db2-9a40-40f874c9b395
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2798841998 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_test_hmac512_vectors.2798841998
Directory /workspace/39.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/39.hmac_test_sha256_vectors.531305309
Short name T263
Test name
Test status
Simulation time 72865108445 ps
CPU time 489.52 seconds
Started Jun 29 05:11:20 PM PDT 24
Finished Jun 29 05:19:30 PM PDT 24
Peak memory 200300 kb
Host smart-685bff33-7d4f-4ed8-a78c-779cbf5ed0af
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=531305309 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_test_sha256_vectors.531305309
Directory /workspace/39.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/39.hmac_test_sha384_vectors.2928345089
Short name T432
Test name
Test status
Simulation time 29678960904 ps
CPU time 1735.89 seconds
Started Jun 29 05:11:30 PM PDT 24
Finished Jun 29 05:40:26 PM PDT 24
Peak memory 208400 kb
Host smart-3d6c3b78-624b-47c0-ac6e-c1a2acdb261f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2928345089 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_test_sha384_vectors.2928345089
Directory /workspace/39.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/39.hmac_test_sha512_vectors.2154478256
Short name T166
Test name
Test status
Simulation time 50487474005 ps
CPU time 1716.65 seconds
Started Jun 29 05:11:20 PM PDT 24
Finished Jun 29 05:39:57 PM PDT 24
Peak memory 216584 kb
Host smart-262e43aa-90c9-44f9-a6d7-700cace14794
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2154478256 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_test_sha512_vectors.2154478256
Directory /workspace/39.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/39.hmac_wipe_secret.3530243474
Short name T325
Test name
Test status
Simulation time 139190838 ps
CPU time 8.01 seconds
Started Jun 29 05:11:19 PM PDT 24
Finished Jun 29 05:11:27 PM PDT 24
Peak memory 200316 kb
Host smart-c378474e-6532-48b8-a5b3-6f33b63b07df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530243474 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_wipe_secret.3530243474
Directory /workspace/39.hmac_wipe_secret/latest

Test location /workspace/coverage/default/4.hmac_alert_test.2143196621
Short name T752
Test name
Test status
Simulation time 11137185 ps
CPU time 0.57 seconds
Started Jun 29 05:08:22 PM PDT 24
Finished Jun 29 05:08:24 PM PDT 24
Peak memory 195924 kb
Host smart-6c80b216-6352-43b6-8f08-962a57e47b24
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143196621 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_alert_test.2143196621
Directory /workspace/4.hmac_alert_test/latest

Test location /workspace/coverage/default/4.hmac_back_pressure.3566690148
Short name T458
Test name
Test status
Simulation time 3437614200 ps
CPU time 39.31 seconds
Started Jun 29 05:08:23 PM PDT 24
Finished Jun 29 05:09:03 PM PDT 24
Peak memory 200284 kb
Host smart-73d86f55-6550-496a-bbc4-1656c10e51c9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3566690148 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_back_pressure.3566690148
Directory /workspace/4.hmac_back_pressure/latest

Test location /workspace/coverage/default/4.hmac_burst_wr.1153740214
Short name T372
Test name
Test status
Simulation time 5457329565 ps
CPU time 39.04 seconds
Started Jun 29 05:08:23 PM PDT 24
Finished Jun 29 05:09:03 PM PDT 24
Peak memory 200320 kb
Host smart-9056cb09-e083-4001-8024-faa0d0398143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1153740214 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_burst_wr.1153740214
Directory /workspace/4.hmac_burst_wr/latest

Test location /workspace/coverage/default/4.hmac_datapath_stress.1522613925
Short name T651
Test name
Test status
Simulation time 3111140486 ps
CPU time 947.69 seconds
Started Jun 29 05:08:21 PM PDT 24
Finished Jun 29 05:24:10 PM PDT 24
Peak memory 748808 kb
Host smart-5e7fd7af-abe7-4391-a749-f15491cf860b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1522613925 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_datapath_stress.1522613925
Directory /workspace/4.hmac_datapath_stress/latest

Test location /workspace/coverage/default/4.hmac_error.3544492345
Short name T542
Test name
Test status
Simulation time 20805600020 ps
CPU time 67.95 seconds
Started Jun 29 05:08:22 PM PDT 24
Finished Jun 29 05:09:30 PM PDT 24
Peak memory 200328 kb
Host smart-4595d964-aee2-4b3c-9b35-c810dbb0bce6
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544492345 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_error.3544492345
Directory /workspace/4.hmac_error/latest

Test location /workspace/coverage/default/4.hmac_long_msg.4059270771
Short name T797
Test name
Test status
Simulation time 1459277072 ps
CPU time 94.11 seconds
Started Jun 29 05:08:21 PM PDT 24
Finished Jun 29 05:09:55 PM PDT 24
Peak memory 200184 kb
Host smart-a9f765d8-0a93-454e-98b7-9ca854817538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059270771 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_long_msg.4059270771
Directory /workspace/4.hmac_long_msg/latest

Test location /workspace/coverage/default/4.hmac_sec_cm.3778765299
Short name T44
Test name
Test status
Simulation time 168703492 ps
CPU time 1.1 seconds
Started Jun 29 05:08:21 PM PDT 24
Finished Jun 29 05:08:23 PM PDT 24
Peak memory 219864 kb
Host smart-3a2bb13e-8ebb-4070-a890-4f6d9ac501eb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778765299 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_sec_cm.3778765299
Directory /workspace/4.hmac_sec_cm/latest

Test location /workspace/coverage/default/4.hmac_smoke.3740968557
Short name T466
Test name
Test status
Simulation time 457247936 ps
CPU time 5.98 seconds
Started Jun 29 05:08:21 PM PDT 24
Finished Jun 29 05:08:28 PM PDT 24
Peak memory 200248 kb
Host smart-2ad164ff-472f-4a00-bf96-5d029008c578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740968557 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_smoke.3740968557
Directory /workspace/4.hmac_smoke/latest

Test location /workspace/coverage/default/4.hmac_stress_all.2479597798
Short name T649
Test name
Test status
Simulation time 279740799600 ps
CPU time 2108.46 seconds
Started Jun 29 05:08:22 PM PDT 24
Finished Jun 29 05:43:31 PM PDT 24
Peak memory 729608 kb
Host smart-878b053d-4da0-41d1-9957-9e8dc896c73a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479597798 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all.2479597798
Directory /workspace/4.hmac_stress_all/latest

Test location /workspace/coverage/default/4.hmac_test_hmac256_vectors.1151337380
Short name T500
Test name
Test status
Simulation time 1727893069 ps
CPU time 36.69 seconds
Started Jun 29 05:08:20 PM PDT 24
Finished Jun 29 05:08:57 PM PDT 24
Peak memory 200304 kb
Host smart-a75b1994-90db-4600-bcce-7b36c8e42e67
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1151337380 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac256_vectors.1151337380
Directory /workspace/4.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_hmac384_vectors.4044338650
Short name T569
Test name
Test status
Simulation time 2833932302 ps
CPU time 41.05 seconds
Started Jun 29 05:08:24 PM PDT 24
Finished Jun 29 05:09:06 PM PDT 24
Peak memory 200336 kb
Host smart-f8caa1d2-c687-422a-918f-5cb10024aab1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4044338650 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac384_vectors.4044338650
Directory /workspace/4.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_hmac512_vectors.594098770
Short name T773
Test name
Test status
Simulation time 29769705376 ps
CPU time 71.84 seconds
Started Jun 29 05:08:22 PM PDT 24
Finished Jun 29 05:09:35 PM PDT 24
Peak memory 200260 kb
Host smart-d5fc8c5c-17c9-4206-a872-378f8b758a0e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=594098770 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac512_vectors.594098770
Directory /workspace/4.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha256_vectors.3744590918
Short name T216
Test name
Test status
Simulation time 26987400249 ps
CPU time 465.25 seconds
Started Jun 29 05:08:20 PM PDT 24
Finished Jun 29 05:16:06 PM PDT 24
Peak memory 200216 kb
Host smart-4224989b-0451-4b47-9a66-5091c36652f3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3744590918 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha256_vectors.3744590918
Directory /workspace/4.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha384_vectors.89957526
Short name T159
Test name
Test status
Simulation time 290918968841 ps
CPU time 2088.38 seconds
Started Jun 29 05:08:23 PM PDT 24
Finished Jun 29 05:43:12 PM PDT 24
Peak memory 216452 kb
Host smart-a313125f-a870-4467-9f41-bc0d8680ff90
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=89957526 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha384_vectors.89957526
Directory /workspace/4.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha512_vectors.309291548
Short name T756
Test name
Test status
Simulation time 665780307115 ps
CPU time 2086.78 seconds
Started Jun 29 05:08:20 PM PDT 24
Finished Jun 29 05:43:08 PM PDT 24
Peak memory 208468 kb
Host smart-320cbafc-d10c-4b5e-814d-28f86eee5778
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=309291548 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha512_vectors.309291548
Directory /workspace/4.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/40.hmac_alert_test.3404964202
Short name T344
Test name
Test status
Simulation time 14344466 ps
CPU time 0.61 seconds
Started Jun 29 05:11:32 PM PDT 24
Finished Jun 29 05:11:33 PM PDT 24
Peak memory 196976 kb
Host smart-da528075-4b1b-4b5f-b07d-fd39b5644cd0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404964202 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_alert_test.3404964202
Directory /workspace/40.hmac_alert_test/latest

Test location /workspace/coverage/default/40.hmac_back_pressure.1456646798
Short name T343
Test name
Test status
Simulation time 961924096 ps
CPU time 46.32 seconds
Started Jun 29 05:11:20 PM PDT 24
Finished Jun 29 05:12:07 PM PDT 24
Peak memory 200208 kb
Host smart-f7165fbc-0763-46ea-9271-31ded9ece915
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1456646798 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_back_pressure.1456646798
Directory /workspace/40.hmac_back_pressure/latest

Test location /workspace/coverage/default/40.hmac_burst_wr.2140834852
Short name T352
Test name
Test status
Simulation time 2898266666 ps
CPU time 39.08 seconds
Started Jun 29 05:11:28 PM PDT 24
Finished Jun 29 05:12:08 PM PDT 24
Peak memory 200388 kb
Host smart-0e51bfb5-2946-43f2-a45e-05bcb6919089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140834852 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_burst_wr.2140834852
Directory /workspace/40.hmac_burst_wr/latest

Test location /workspace/coverage/default/40.hmac_datapath_stress.1749788033
Short name T416
Test name
Test status
Simulation time 4286796932 ps
CPU time 615.55 seconds
Started Jun 29 05:11:21 PM PDT 24
Finished Jun 29 05:21:37 PM PDT 24
Peak memory 730540 kb
Host smart-281f5dce-4231-41b7-b528-ee09e5b62a56
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1749788033 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_datapath_stress.1749788033
Directory /workspace/40.hmac_datapath_stress/latest

Test location /workspace/coverage/default/40.hmac_error.391822754
Short name T47
Test name
Test status
Simulation time 55742100436 ps
CPU time 129.91 seconds
Started Jun 29 05:11:27 PM PDT 24
Finished Jun 29 05:13:38 PM PDT 24
Peak memory 200284 kb
Host smart-1051b95f-646f-4b70-bfb9-01c2dfae8796
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391822754 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_error.391822754
Directory /workspace/40.hmac_error/latest

Test location /workspace/coverage/default/40.hmac_long_msg.2728338731
Short name T451
Test name
Test status
Simulation time 1300524411 ps
CPU time 36.19 seconds
Started Jun 29 05:11:30 PM PDT 24
Finished Jun 29 05:12:06 PM PDT 24
Peak memory 200056 kb
Host smart-7329c1a9-8368-4688-ace9-427929a46ae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728338731 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_long_msg.2728338731
Directory /workspace/40.hmac_long_msg/latest

Test location /workspace/coverage/default/40.hmac_smoke.3483667679
Short name T158
Test name
Test status
Simulation time 761166878 ps
CPU time 4.15 seconds
Started Jun 29 05:11:18 PM PDT 24
Finished Jun 29 05:11:23 PM PDT 24
Peak memory 200244 kb
Host smart-88790eae-dcaf-403f-9caa-ff86a9abcaab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483667679 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_smoke.3483667679
Directory /workspace/40.hmac_smoke/latest

Test location /workspace/coverage/default/40.hmac_stress_all.3123347216
Short name T340
Test name
Test status
Simulation time 299861822451 ps
CPU time 453.45 seconds
Started Jun 29 05:11:28 PM PDT 24
Finished Jun 29 05:19:02 PM PDT 24
Peak memory 200332 kb
Host smart-057a176f-ca1f-4d89-a1fd-c92be0b05793
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123347216 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.hmac_stress_all.3123347216
Directory /workspace/40.hmac_stress_all/latest

Test location /workspace/coverage/default/40.hmac_test_hmac256_vectors.909972762
Short name T49
Test name
Test status
Simulation time 5946541537 ps
CPU time 69.74 seconds
Started Jun 29 05:11:28 PM PDT 24
Finished Jun 29 05:12:38 PM PDT 24
Peak memory 200296 kb
Host smart-3e4128af-bbf1-4954-aab8-0b9d7fdb1bc6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=909972762 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_test_hmac256_vectors.909972762
Directory /workspace/40.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/40.hmac_test_hmac384_vectors.1746237641
Short name T762
Test name
Test status
Simulation time 4276330945 ps
CPU time 57.88 seconds
Started Jun 29 05:11:30 PM PDT 24
Finished Jun 29 05:12:28 PM PDT 24
Peak memory 200300 kb
Host smart-07316897-9752-4027-a8b5-e8284f90104c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1746237641 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_test_hmac384_vectors.1746237641
Directory /workspace/40.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/40.hmac_test_hmac512_vectors.903363929
Short name T25
Test name
Test status
Simulation time 22798311655 ps
CPU time 106.2 seconds
Started Jun 29 05:11:27 PM PDT 24
Finished Jun 29 05:13:14 PM PDT 24
Peak memory 200332 kb
Host smart-89774d30-8d16-4322-b09f-5671917c066b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=903363929 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_test_hmac512_vectors.903363929
Directory /workspace/40.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/40.hmac_test_sha256_vectors.2108058152
Short name T741
Test name
Test status
Simulation time 297731740981 ps
CPU time 488.54 seconds
Started Jun 29 05:11:31 PM PDT 24
Finished Jun 29 05:19:40 PM PDT 24
Peak memory 200264 kb
Host smart-3454842a-b0d1-49c8-b5c0-573dce6f229f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2108058152 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_test_sha256_vectors.2108058152
Directory /workspace/40.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/40.hmac_test_sha384_vectors.2804782590
Short name T794
Test name
Test status
Simulation time 28969632177 ps
CPU time 1697.05 seconds
Started Jun 29 05:11:30 PM PDT 24
Finished Jun 29 05:39:47 PM PDT 24
Peak memory 215804 kb
Host smart-c46fa457-f1d3-4ba8-bea9-25c6d93edbf8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2804782590 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_test_sha384_vectors.2804782590
Directory /workspace/40.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/40.hmac_test_sha512_vectors.1198381085
Short name T171
Test name
Test status
Simulation time 52129529247 ps
CPU time 1481.49 seconds
Started Jun 29 05:11:30 PM PDT 24
Finished Jun 29 05:36:12 PM PDT 24
Peak memory 216684 kb
Host smart-c20cdcb2-b841-4668-bed2-75867b527b36
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1198381085 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_test_sha512_vectors.1198381085
Directory /workspace/40.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/40.hmac_wipe_secret.4003293359
Short name T82
Test name
Test status
Simulation time 1739853981 ps
CPU time 78.38 seconds
Started Jun 29 05:11:28 PM PDT 24
Finished Jun 29 05:12:46 PM PDT 24
Peak memory 200216 kb
Host smart-74ede5fe-2bca-495d-99b0-2cebc089a764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003293359 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_wipe_secret.4003293359
Directory /workspace/40.hmac_wipe_secret/latest

Test location /workspace/coverage/default/41.hmac_alert_test.2862789798
Short name T598
Test name
Test status
Simulation time 44346947 ps
CPU time 0.59 seconds
Started Jun 29 05:11:41 PM PDT 24
Finished Jun 29 05:11:42 PM PDT 24
Peak memory 196288 kb
Host smart-5c1d0951-6dd3-41ef-b0a7-a2b0de3fcbbf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862789798 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_alert_test.2862789798
Directory /workspace/41.hmac_alert_test/latest

Test location /workspace/coverage/default/41.hmac_back_pressure.1905680566
Short name T448
Test name
Test status
Simulation time 4921181310 ps
CPU time 49.41 seconds
Started Jun 29 05:11:27 PM PDT 24
Finished Jun 29 05:12:17 PM PDT 24
Peak memory 200344 kb
Host smart-701bbabd-8435-4dc4-885b-f67710fc290c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1905680566 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_back_pressure.1905680566
Directory /workspace/41.hmac_back_pressure/latest

Test location /workspace/coverage/default/41.hmac_burst_wr.2759465351
Short name T454
Test name
Test status
Simulation time 1706308579 ps
CPU time 43.29 seconds
Started Jun 29 05:11:33 PM PDT 24
Finished Jun 29 05:12:16 PM PDT 24
Peak memory 200308 kb
Host smart-b4972cdb-d3b1-4963-a037-a59e4fe70c1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759465351 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_burst_wr.2759465351
Directory /workspace/41.hmac_burst_wr/latest

Test location /workspace/coverage/default/41.hmac_datapath_stress.2519341346
Short name T551
Test name
Test status
Simulation time 7656155026 ps
CPU time 1294.17 seconds
Started Jun 29 05:11:27 PM PDT 24
Finished Jun 29 05:33:01 PM PDT 24
Peak memory 745576 kb
Host smart-61dd4d10-e4e9-4b4f-9c8a-539c75b3c727
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2519341346 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_datapath_stress.2519341346
Directory /workspace/41.hmac_datapath_stress/latest

Test location /workspace/coverage/default/41.hmac_error.948912811
Short name T33
Test name
Test status
Simulation time 2222668004 ps
CPU time 65.8 seconds
Started Jun 29 05:11:25 PM PDT 24
Finished Jun 29 05:12:31 PM PDT 24
Peak memory 200256 kb
Host smart-3a9ee06c-6afe-4160-8cf6-80f76c56989b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948912811 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_error.948912811
Directory /workspace/41.hmac_error/latest

Test location /workspace/coverage/default/41.hmac_long_msg.3230083350
Short name T503
Test name
Test status
Simulation time 950260357 ps
CPU time 58.42 seconds
Started Jun 29 05:11:32 PM PDT 24
Finished Jun 29 05:12:31 PM PDT 24
Peak memory 200260 kb
Host smart-041234fd-9bac-40fd-a1b3-c65571bb989a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3230083350 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_long_msg.3230083350
Directory /workspace/41.hmac_long_msg/latest

Test location /workspace/coverage/default/41.hmac_smoke.2123102839
Short name T148
Test name
Test status
Simulation time 314815519 ps
CPU time 3.38 seconds
Started Jun 29 05:11:31 PM PDT 24
Finished Jun 29 05:11:35 PM PDT 24
Peak memory 200208 kb
Host smart-45d2dcd4-5c27-40de-931c-aa7f5fcde0ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123102839 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_smoke.2123102839
Directory /workspace/41.hmac_smoke/latest

Test location /workspace/coverage/default/41.hmac_stress_all.463805063
Short name T595
Test name
Test status
Simulation time 390750004378 ps
CPU time 3059.38 seconds
Started Jun 29 05:11:37 PM PDT 24
Finished Jun 29 06:02:37 PM PDT 24
Peak memory 795328 kb
Host smart-0f7fc093-0412-42c6-aad0-23a7e71cea21
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463805063 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 41.hmac_stress_all.463805063
Directory /workspace/41.hmac_stress_all/latest

Test location /workspace/coverage/default/41.hmac_test_hmac256_vectors.4252509604
Short name T711
Test name
Test status
Simulation time 9014353285 ps
CPU time 30.31 seconds
Started Jun 29 05:11:37 PM PDT 24
Finished Jun 29 05:12:08 PM PDT 24
Peak memory 200332 kb
Host smart-256a6079-16f3-4fbe-9499-d6d9e6640704
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4252509604 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_test_hmac256_vectors.4252509604
Directory /workspace/41.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/41.hmac_test_hmac384_vectors.62278366
Short name T193
Test name
Test status
Simulation time 5488614984 ps
CPU time 83.17 seconds
Started Jun 29 05:11:40 PM PDT 24
Finished Jun 29 05:13:03 PM PDT 24
Peak memory 200332 kb
Host smart-21966d22-7920-400d-a37f-5fc8f1f04d50
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=62278366 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_test_hmac384_vectors.62278366
Directory /workspace/41.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/41.hmac_test_hmac512_vectors.3169085791
Short name T53
Test name
Test status
Simulation time 3351008590 ps
CPU time 98.31 seconds
Started Jun 29 05:11:37 PM PDT 24
Finished Jun 29 05:13:16 PM PDT 24
Peak memory 200264 kb
Host smart-cfa9dc39-b9f8-4981-8853-059324ed20c9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3169085791 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_test_hmac512_vectors.3169085791
Directory /workspace/41.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/41.hmac_test_sha256_vectors.3578349935
Short name T268
Test name
Test status
Simulation time 85346926961 ps
CPU time 591.44 seconds
Started Jun 29 05:11:31 PM PDT 24
Finished Jun 29 05:21:23 PM PDT 24
Peak memory 200192 kb
Host smart-bfdff344-b254-4ba0-a28d-4965e8d87e5e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3578349935 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_test_sha256_vectors.3578349935
Directory /workspace/41.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/41.hmac_test_sha384_vectors.561051804
Short name T386
Test name
Test status
Simulation time 432741359244 ps
CPU time 1910.79 seconds
Started Jun 29 05:11:30 PM PDT 24
Finished Jun 29 05:43:22 PM PDT 24
Peak memory 216176 kb
Host smart-c2e87756-809d-4398-be06-7c3378f78a58
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=561051804 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_test_sha384_vectors.561051804
Directory /workspace/41.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/41.hmac_test_sha512_vectors.1162431200
Short name T635
Test name
Test status
Simulation time 159231625509 ps
CPU time 2033.42 seconds
Started Jun 29 05:11:28 PM PDT 24
Finished Jun 29 05:45:22 PM PDT 24
Peak memory 216612 kb
Host smart-56964bff-ff64-4ca4-9b4c-0fca370f1308
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1162431200 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_test_sha512_vectors.1162431200
Directory /workspace/41.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/41.hmac_wipe_secret.2866108548
Short name T755
Test name
Test status
Simulation time 5260286315 ps
CPU time 79.36 seconds
Started Jun 29 05:11:27 PM PDT 24
Finished Jun 29 05:12:47 PM PDT 24
Peak memory 200324 kb
Host smart-e29a2a02-935c-4bd6-9939-3896de38bac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2866108548 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_wipe_secret.2866108548
Directory /workspace/41.hmac_wipe_secret/latest

Test location /workspace/coverage/default/42.hmac_alert_test.3764914855
Short name T364
Test name
Test status
Simulation time 60322479 ps
CPU time 0.6 seconds
Started Jun 29 05:11:47 PM PDT 24
Finished Jun 29 05:11:49 PM PDT 24
Peak memory 196260 kb
Host smart-aecc3d60-3d4e-4d14-8e44-f1c13c5ca369
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764914855 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_alert_test.3764914855
Directory /workspace/42.hmac_alert_test/latest

Test location /workspace/coverage/default/42.hmac_back_pressure.488136805
Short name T778
Test name
Test status
Simulation time 4936306261 ps
CPU time 36.41 seconds
Started Jun 29 05:11:36 PM PDT 24
Finished Jun 29 05:12:13 PM PDT 24
Peak memory 200340 kb
Host smart-edfc6e84-e2a4-4893-b14f-0196f1a4dcaf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=488136805 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_back_pressure.488136805
Directory /workspace/42.hmac_back_pressure/latest

Test location /workspace/coverage/default/42.hmac_burst_wr.2974753642
Short name T765
Test name
Test status
Simulation time 10702281064 ps
CPU time 46.62 seconds
Started Jun 29 05:11:40 PM PDT 24
Finished Jun 29 05:12:27 PM PDT 24
Peak memory 200300 kb
Host smart-782197e3-7522-40e3-a972-47cc0f4de3a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2974753642 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_burst_wr.2974753642
Directory /workspace/42.hmac_burst_wr/latest

Test location /workspace/coverage/default/42.hmac_datapath_stress.3237426621
Short name T358
Test name
Test status
Simulation time 10220864696 ps
CPU time 811.68 seconds
Started Jun 29 05:11:38 PM PDT 24
Finished Jun 29 05:25:11 PM PDT 24
Peak memory 761776 kb
Host smart-d80e9517-ecd3-41a6-af1e-6ebf26e5fa39
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3237426621 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_datapath_stress.3237426621
Directory /workspace/42.hmac_datapath_stress/latest

Test location /workspace/coverage/default/42.hmac_error.31021415
Short name T490
Test name
Test status
Simulation time 232118593 ps
CPU time 13.02 seconds
Started Jun 29 05:11:39 PM PDT 24
Finished Jun 29 05:11:52 PM PDT 24
Peak memory 200212 kb
Host smart-9a9167c5-4bc1-43c0-9d28-c40a98109d99
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31021415 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_error.31021415
Directory /workspace/42.hmac_error/latest

Test location /workspace/coverage/default/42.hmac_long_msg.589677918
Short name T147
Test name
Test status
Simulation time 15605705097 ps
CPU time 113.89 seconds
Started Jun 29 05:11:37 PM PDT 24
Finished Jun 29 05:13:31 PM PDT 24
Peak memory 216640 kb
Host smart-cfc0e218-6745-49fc-b951-2792d442cfc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589677918 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_long_msg.589677918
Directory /workspace/42.hmac_long_msg/latest

Test location /workspace/coverage/default/42.hmac_smoke.3097017333
Short name T56
Test name
Test status
Simulation time 422491252 ps
CPU time 3.07 seconds
Started Jun 29 05:11:40 PM PDT 24
Finished Jun 29 05:11:44 PM PDT 24
Peak memory 200288 kb
Host smart-bc65c589-d848-46ea-9eab-eb8cd758d408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3097017333 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_smoke.3097017333
Directory /workspace/42.hmac_smoke/latest

Test location /workspace/coverage/default/42.hmac_test_hmac256_vectors.973249239
Short name T253
Test name
Test status
Simulation time 6060081214 ps
CPU time 40.91 seconds
Started Jun 29 05:11:37 PM PDT 24
Finished Jun 29 05:12:18 PM PDT 24
Peak memory 200360 kb
Host smart-2ba2b362-9760-4e4c-8ade-b87eb3bcd1fa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=973249239 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_test_hmac256_vectors.973249239
Directory /workspace/42.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/42.hmac_test_hmac384_vectors.4151325744
Short name T524
Test name
Test status
Simulation time 34028614771 ps
CPU time 97.88 seconds
Started Jun 29 05:11:40 PM PDT 24
Finished Jun 29 05:13:18 PM PDT 24
Peak memory 200368 kb
Host smart-a0b69095-6add-461c-bc89-6d86a4c15523
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4151325744 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_test_hmac384_vectors.4151325744
Directory /workspace/42.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/42.hmac_test_hmac512_vectors.3209376753
Short name T673
Test name
Test status
Simulation time 10291760439 ps
CPU time 63.67 seconds
Started Jun 29 05:11:38 PM PDT 24
Finished Jun 29 05:12:42 PM PDT 24
Peak memory 200588 kb
Host smart-0052da5f-10fc-4a6e-9bf5-6baa6966b56f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3209376753 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_test_hmac512_vectors.3209376753
Directory /workspace/42.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/42.hmac_test_sha256_vectors.2058841358
Short name T5
Test name
Test status
Simulation time 156943602391 ps
CPU time 523.22 seconds
Started Jun 29 05:11:36 PM PDT 24
Finished Jun 29 05:20:20 PM PDT 24
Peak memory 200224 kb
Host smart-729d81bf-a02c-480e-98f6-521c506682f7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2058841358 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_test_sha256_vectors.2058841358
Directory /workspace/42.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/42.hmac_test_sha384_vectors.3672310259
Short name T779
Test name
Test status
Simulation time 138113393392 ps
CPU time 1835.79 seconds
Started Jun 29 05:11:37 PM PDT 24
Finished Jun 29 05:42:14 PM PDT 24
Peak memory 216300 kb
Host smart-f4791cf0-002b-4fce-9a7e-93a903ece083
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3672310259 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_test_sha384_vectors.3672310259
Directory /workspace/42.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/42.hmac_wipe_secret.3212251012
Short name T560
Test name
Test status
Simulation time 1498465498 ps
CPU time 68.27 seconds
Started Jun 29 05:11:37 PM PDT 24
Finished Jun 29 05:12:45 PM PDT 24
Peak memory 200288 kb
Host smart-0ae7aa50-c72d-4584-9515-b25702956f08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212251012 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_wipe_secret.3212251012
Directory /workspace/42.hmac_wipe_secret/latest

Test location /workspace/coverage/default/43.hmac_alert_test.2215521045
Short name T233
Test name
Test status
Simulation time 30794002 ps
CPU time 0.59 seconds
Started Jun 29 05:11:47 PM PDT 24
Finished Jun 29 05:11:48 PM PDT 24
Peak memory 196996 kb
Host smart-1418e8cc-ef68-4895-96f7-e712730ae6fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215521045 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_alert_test.2215521045
Directory /workspace/43.hmac_alert_test/latest

Test location /workspace/coverage/default/43.hmac_back_pressure.537931513
Short name T284
Test name
Test status
Simulation time 2096886954 ps
CPU time 29.14 seconds
Started Jun 29 05:11:45 PM PDT 24
Finished Jun 29 05:12:15 PM PDT 24
Peak memory 200200 kb
Host smart-648948d6-2258-42d0-a1cb-5862f8fb04f5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=537931513 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_back_pressure.537931513
Directory /workspace/43.hmac_back_pressure/latest

Test location /workspace/coverage/default/43.hmac_burst_wr.4255689759
Short name T426
Test name
Test status
Simulation time 9224283262 ps
CPU time 57.31 seconds
Started Jun 29 05:11:45 PM PDT 24
Finished Jun 29 05:12:43 PM PDT 24
Peak memory 200336 kb
Host smart-fc66d94b-68ab-401e-b78d-10a6fd7ab750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255689759 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_burst_wr.4255689759
Directory /workspace/43.hmac_burst_wr/latest

Test location /workspace/coverage/default/43.hmac_datapath_stress.814433763
Short name T367
Test name
Test status
Simulation time 332606979 ps
CPU time 68.37 seconds
Started Jun 29 05:11:46 PM PDT 24
Finished Jun 29 05:12:54 PM PDT 24
Peak memory 402468 kb
Host smart-d942ad14-45d9-46a2-a2f5-3ab1f8eadc9d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=814433763 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_datapath_stress.814433763
Directory /workspace/43.hmac_datapath_stress/latest

Test location /workspace/coverage/default/43.hmac_error.1231967872
Short name T308
Test name
Test status
Simulation time 3290021447 ps
CPU time 202.65 seconds
Started Jun 29 05:11:45 PM PDT 24
Finished Jun 29 05:15:08 PM PDT 24
Peak memory 200296 kb
Host smart-6400bd49-3bf2-4f9f-89cb-090fd0f364f1
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231967872 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_error.1231967872
Directory /workspace/43.hmac_error/latest

Test location /workspace/coverage/default/43.hmac_long_msg.1984454103
Short name T237
Test name
Test status
Simulation time 16733460288 ps
CPU time 109.78 seconds
Started Jun 29 05:11:47 PM PDT 24
Finished Jun 29 05:13:37 PM PDT 24
Peak memory 216656 kb
Host smart-d02b661c-65b7-4b73-b286-8de651702389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984454103 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_long_msg.1984454103
Directory /workspace/43.hmac_long_msg/latest

Test location /workspace/coverage/default/43.hmac_smoke.1569247221
Short name T680
Test name
Test status
Simulation time 388553425 ps
CPU time 6.69 seconds
Started Jun 29 05:11:45 PM PDT 24
Finished Jun 29 05:11:52 PM PDT 24
Peak memory 200272 kb
Host smart-a03298ac-0e02-4c5b-9726-59c2864d8a76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569247221 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_smoke.1569247221
Directory /workspace/43.hmac_smoke/latest

Test location /workspace/coverage/default/43.hmac_stress_all.299388062
Short name T522
Test name
Test status
Simulation time 51041136584 ps
CPU time 207.72 seconds
Started Jun 29 05:11:47 PM PDT 24
Finished Jun 29 05:15:15 PM PDT 24
Peak memory 337228 kb
Host smart-e9a023b5-d8ed-4515-8415-f6e12d6d3117
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299388062 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 43.hmac_stress_all.299388062
Directory /workspace/43.hmac_stress_all/latest

Test location /workspace/coverage/default/43.hmac_test_hmac256_vectors.133700283
Short name T703
Test name
Test status
Simulation time 5246042780 ps
CPU time 37.9 seconds
Started Jun 29 05:11:47 PM PDT 24
Finished Jun 29 05:12:26 PM PDT 24
Peak memory 200332 kb
Host smart-a7aca9c0-1a0a-4ca9-8f1f-e5faecd38418
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=133700283 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_test_hmac256_vectors.133700283
Directory /workspace/43.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/43.hmac_test_hmac384_vectors.3552182489
Short name T541
Test name
Test status
Simulation time 1523654680 ps
CPU time 52.11 seconds
Started Jun 29 05:11:47 PM PDT 24
Finished Jun 29 05:12:40 PM PDT 24
Peak memory 200188 kb
Host smart-5bca0ca7-f74b-4ca5-9b98-5aa01f860264
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3552182489 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_test_hmac384_vectors.3552182489
Directory /workspace/43.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/43.hmac_test_hmac512_vectors.536156579
Short name T610
Test name
Test status
Simulation time 34669677516 ps
CPU time 107.65 seconds
Started Jun 29 05:11:46 PM PDT 24
Finished Jun 29 05:13:35 PM PDT 24
Peak memory 200324 kb
Host smart-391a7aa3-71d1-449a-97e7-b8e3ee7ed4c1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=536156579 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_test_hmac512_vectors.536156579
Directory /workspace/43.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/43.hmac_test_sha256_vectors.2655446750
Short name T6
Test name
Test status
Simulation time 45589915776 ps
CPU time 481.17 seconds
Started Jun 29 05:11:46 PM PDT 24
Finished Jun 29 05:19:48 PM PDT 24
Peak memory 200216 kb
Host smart-970959e8-b70e-4d39-8cf2-c136027b5f5b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2655446750 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_test_sha256_vectors.2655446750
Directory /workspace/43.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/43.hmac_test_sha384_vectors.1645273628
Short name T443
Test name
Test status
Simulation time 317463491070 ps
CPU time 1953.95 seconds
Started Jun 29 05:11:46 PM PDT 24
Finished Jun 29 05:44:21 PM PDT 24
Peak memory 216304 kb
Host smart-a849c7df-cbed-4b68-baec-be8ac44a2b50
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1645273628 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_test_sha384_vectors.1645273628
Directory /workspace/43.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/43.hmac_test_sha512_vectors.3587127784
Short name T368
Test name
Test status
Simulation time 146864563412 ps
CPU time 1717.03 seconds
Started Jun 29 05:11:45 PM PDT 24
Finished Jun 29 05:40:23 PM PDT 24
Peak memory 216684 kb
Host smart-86710162-866b-47c8-af69-a15098db0554
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3587127784 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_test_sha512_vectors.3587127784
Directory /workspace/43.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/43.hmac_wipe_secret.385459634
Short name T230
Test name
Test status
Simulation time 935043380 ps
CPU time 38.26 seconds
Started Jun 29 05:11:46 PM PDT 24
Finished Jun 29 05:12:25 PM PDT 24
Peak memory 200176 kb
Host smart-34b0c089-efd7-4b2b-a8e4-4dfe795a3153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385459634 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_wipe_secret.385459634
Directory /workspace/43.hmac_wipe_secret/latest

Test location /workspace/coverage/default/44.hmac_alert_test.1792023871
Short name T316
Test name
Test status
Simulation time 23936100 ps
CPU time 0.59 seconds
Started Jun 29 05:11:56 PM PDT 24
Finished Jun 29 05:11:57 PM PDT 24
Peak memory 196232 kb
Host smart-2681fea9-e0ce-4e87-85e6-904c696f1423
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792023871 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_alert_test.1792023871
Directory /workspace/44.hmac_alert_test/latest

Test location /workspace/coverage/default/44.hmac_back_pressure.653907862
Short name T19
Test name
Test status
Simulation time 236507379 ps
CPU time 11.01 seconds
Started Jun 29 05:11:46 PM PDT 24
Finished Jun 29 05:11:57 PM PDT 24
Peak memory 200200 kb
Host smart-d73b9c3d-a9f7-4dce-b1f8-a95992689163
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=653907862 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_back_pressure.653907862
Directory /workspace/44.hmac_back_pressure/latest

Test location /workspace/coverage/default/44.hmac_burst_wr.2741159053
Short name T516
Test name
Test status
Simulation time 1086077025 ps
CPU time 60.66 seconds
Started Jun 29 05:11:46 PM PDT 24
Finished Jun 29 05:12:48 PM PDT 24
Peak memory 200328 kb
Host smart-2b3aac89-9b6b-49b4-b780-344368ceed9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741159053 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_burst_wr.2741159053
Directory /workspace/44.hmac_burst_wr/latest

Test location /workspace/coverage/default/44.hmac_datapath_stress.2148630004
Short name T128
Test name
Test status
Simulation time 2444201585 ps
CPU time 313.98 seconds
Started Jun 29 05:11:48 PM PDT 24
Finished Jun 29 05:17:02 PM PDT 24
Peak memory 665900 kb
Host smart-fe2819e8-faa1-46f0-b666-3746c9d96ce9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2148630004 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_datapath_stress.2148630004
Directory /workspace/44.hmac_datapath_stress/latest

Test location /workspace/coverage/default/44.hmac_error.3260317600
Short name T290
Test name
Test status
Simulation time 3598172780 ps
CPU time 200.18 seconds
Started Jun 29 05:11:46 PM PDT 24
Finished Jun 29 05:15:07 PM PDT 24
Peak memory 200260 kb
Host smart-417058f6-e97f-4310-a4c5-b763b49a0659
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260317600 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_error.3260317600
Directory /workspace/44.hmac_error/latest

Test location /workspace/coverage/default/44.hmac_long_msg.3351331493
Short name T723
Test name
Test status
Simulation time 19527689458 ps
CPU time 76.78 seconds
Started Jun 29 05:11:45 PM PDT 24
Finished Jun 29 05:13:03 PM PDT 24
Peak memory 200340 kb
Host smart-00110757-9149-42d3-a4e3-014547281cf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351331493 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_long_msg.3351331493
Directory /workspace/44.hmac_long_msg/latest

Test location /workspace/coverage/default/44.hmac_smoke.3421377494
Short name T575
Test name
Test status
Simulation time 196094986 ps
CPU time 2.72 seconds
Started Jun 29 05:11:46 PM PDT 24
Finished Jun 29 05:11:49 PM PDT 24
Peak memory 200264 kb
Host smart-1d7bd099-482d-4a48-b341-e82c10e43618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421377494 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_smoke.3421377494
Directory /workspace/44.hmac_smoke/latest

Test location /workspace/coverage/default/44.hmac_stress_all.3230273680
Short name T38
Test name
Test status
Simulation time 10327110577 ps
CPU time 72.42 seconds
Started Jun 29 05:11:55 PM PDT 24
Finished Jun 29 05:13:08 PM PDT 24
Peak memory 200340 kb
Host smart-ec6f5412-eb16-46cd-baad-1461a532bbbd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230273680 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.hmac_stress_all.3230273680
Directory /workspace/44.hmac_stress_all/latest

Test location /workspace/coverage/default/44.hmac_test_hmac256_vectors.367593491
Short name T197
Test name
Test status
Simulation time 1843868815 ps
CPU time 30.59 seconds
Started Jun 29 05:11:46 PM PDT 24
Finished Jun 29 05:12:17 PM PDT 24
Peak memory 200236 kb
Host smart-092dbb2b-1a2e-4b82-b547-6fdf422ecb13
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=367593491 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_test_hmac256_vectors.367593491
Directory /workspace/44.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/44.hmac_test_hmac384_vectors.3440617809
Short name T615
Test name
Test status
Simulation time 1367704265 ps
CPU time 39.53 seconds
Started Jun 29 05:11:56 PM PDT 24
Finished Jun 29 05:12:36 PM PDT 24
Peak memory 200200 kb
Host smart-91a5ca9b-dd75-4060-8da6-3ef69b8c97fe
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3440617809 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_test_hmac384_vectors.3440617809
Directory /workspace/44.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/44.hmac_test_hmac512_vectors.3524216034
Short name T362
Test name
Test status
Simulation time 11525603459 ps
CPU time 61.43 seconds
Started Jun 29 05:11:56 PM PDT 24
Finished Jun 29 05:12:58 PM PDT 24
Peak memory 200332 kb
Host smart-664b62e7-3dae-4dd8-9ab9-24a10a2f2f19
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3524216034 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_test_hmac512_vectors.3524216034
Directory /workspace/44.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/44.hmac_test_sha256_vectors.4292259763
Short name T164
Test name
Test status
Simulation time 102268037745 ps
CPU time 433.8 seconds
Started Jun 29 05:11:45 PM PDT 24
Finished Jun 29 05:19:00 PM PDT 24
Peak memory 200264 kb
Host smart-8e89d5d3-32dd-48a9-b5ca-7461e4f62b98
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=4292259763 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_test_sha256_vectors.4292259763
Directory /workspace/44.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/44.hmac_test_sha384_vectors.3251335100
Short name T423
Test name
Test status
Simulation time 152652578858 ps
CPU time 2036.94 seconds
Started Jun 29 05:11:46 PM PDT 24
Finished Jun 29 05:45:44 PM PDT 24
Peak memory 216184 kb
Host smart-c2b704a2-6831-429d-bbba-ed4cee4b5917
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3251335100 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_test_sha384_vectors.3251335100
Directory /workspace/44.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/44.hmac_test_sha512_vectors.3851413257
Short name T309
Test name
Test status
Simulation time 294321404325 ps
CPU time 1988.39 seconds
Started Jun 29 05:11:46 PM PDT 24
Finished Jun 29 05:44:56 PM PDT 24
Peak memory 216452 kb
Host smart-6e8d39c9-4c01-45d8-b10b-43751c26c19f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3851413257 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_test_sha512_vectors.3851413257
Directory /workspace/44.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/44.hmac_wipe_secret.2977556846
Short name T324
Test name
Test status
Simulation time 8805123426 ps
CPU time 88.62 seconds
Started Jun 29 05:11:47 PM PDT 24
Finished Jun 29 05:13:17 PM PDT 24
Peak memory 200348 kb
Host smart-74e41f70-fc84-43bd-940f-abf9ea449668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977556846 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_wipe_secret.2977556846
Directory /workspace/44.hmac_wipe_secret/latest

Test location /workspace/coverage/default/45.hmac_alert_test.2587042764
Short name T602
Test name
Test status
Simulation time 25079928 ps
CPU time 0.6 seconds
Started Jun 29 05:11:57 PM PDT 24
Finished Jun 29 05:11:58 PM PDT 24
Peak memory 196996 kb
Host smart-8cd0b99f-f732-4817-8d2d-f72cb441c6a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587042764 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_alert_test.2587042764
Directory /workspace/45.hmac_alert_test/latest

Test location /workspace/coverage/default/45.hmac_back_pressure.1607863835
Short name T7
Test name
Test status
Simulation time 640388390 ps
CPU time 31.46 seconds
Started Jun 29 05:11:56 PM PDT 24
Finished Jun 29 05:12:28 PM PDT 24
Peak memory 200276 kb
Host smart-76aeebbd-8bcb-4e37-905f-dd3e8b6ab243
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1607863835 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_back_pressure.1607863835
Directory /workspace/45.hmac_back_pressure/latest

Test location /workspace/coverage/default/45.hmac_burst_wr.1330146429
Short name T527
Test name
Test status
Simulation time 3369445099 ps
CPU time 48.3 seconds
Started Jun 29 05:11:55 PM PDT 24
Finished Jun 29 05:12:44 PM PDT 24
Peak memory 200332 kb
Host smart-419348db-a079-4dd8-95be-4a8a53b91e64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330146429 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_burst_wr.1330146429
Directory /workspace/45.hmac_burst_wr/latest

Test location /workspace/coverage/default/45.hmac_datapath_stress.3559538217
Short name T182
Test name
Test status
Simulation time 201160138 ps
CPU time 35.01 seconds
Started Jun 29 05:11:56 PM PDT 24
Finished Jun 29 05:12:31 PM PDT 24
Peak memory 307916 kb
Host smart-6acf485a-5e5e-4226-bd50-850d990002ad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3559538217 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_datapath_stress.3559538217
Directory /workspace/45.hmac_datapath_stress/latest

Test location /workspace/coverage/default/45.hmac_error.254447353
Short name T121
Test name
Test status
Simulation time 7572452830 ps
CPU time 111.71 seconds
Started Jun 29 05:11:57 PM PDT 24
Finished Jun 29 05:13:49 PM PDT 24
Peak memory 200320 kb
Host smart-41399752-3cfa-42c9-988c-8e1961dfb35d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254447353 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_error.254447353
Directory /workspace/45.hmac_error/latest

Test location /workspace/coverage/default/45.hmac_long_msg.3650827083
Short name T672
Test name
Test status
Simulation time 1749327056 ps
CPU time 24.57 seconds
Started Jun 29 05:11:56 PM PDT 24
Finished Jun 29 05:12:21 PM PDT 24
Peak memory 200304 kb
Host smart-4c9f9ebb-0288-48d9-bf90-deefb7cd2169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650827083 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_long_msg.3650827083
Directory /workspace/45.hmac_long_msg/latest

Test location /workspace/coverage/default/45.hmac_smoke.1149239635
Short name T168
Test name
Test status
Simulation time 209677236 ps
CPU time 10.19 seconds
Started Jun 29 05:12:00 PM PDT 24
Finished Jun 29 05:12:10 PM PDT 24
Peak memory 200292 kb
Host smart-cbc4a52f-b7ae-47af-ac84-ac2f9fd65583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149239635 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_smoke.1149239635
Directory /workspace/45.hmac_smoke/latest

Test location /workspace/coverage/default/45.hmac_stress_all.3535103565
Short name T483
Test name
Test status
Simulation time 15840824821 ps
CPU time 78.7 seconds
Started Jun 29 05:12:00 PM PDT 24
Finished Jun 29 05:13:19 PM PDT 24
Peak memory 200328 kb
Host smart-77b194e1-81b8-4751-931a-113a959343c0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535103565 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.hmac_stress_all.3535103565
Directory /workspace/45.hmac_stress_all/latest

Test location /workspace/coverage/default/45.hmac_test_hmac256_vectors.3823249787
Short name T587
Test name
Test status
Simulation time 40296195998 ps
CPU time 71.43 seconds
Started Jun 29 05:11:55 PM PDT 24
Finished Jun 29 05:13:07 PM PDT 24
Peak memory 200368 kb
Host smart-21364d6d-e61a-45ce-b4a7-f30997a3b1f1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3823249787 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_test_hmac256_vectors.3823249787
Directory /workspace/45.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/45.hmac_test_hmac384_vectors.1403678089
Short name T86
Test name
Test status
Simulation time 3510096979 ps
CPU time 54.08 seconds
Started Jun 29 05:11:57 PM PDT 24
Finished Jun 29 05:12:52 PM PDT 24
Peak memory 200248 kb
Host smart-dc3792dd-6d5a-4436-a4d9-d736c325304f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1403678089 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_test_hmac384_vectors.1403678089
Directory /workspace/45.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/45.hmac_test_hmac512_vectors.3287720744
Short name T400
Test name
Test status
Simulation time 3919909038 ps
CPU time 65.21 seconds
Started Jun 29 05:11:58 PM PDT 24
Finished Jun 29 05:13:04 PM PDT 24
Peak memory 200368 kb
Host smart-ad4055ef-f094-4f29-92a5-dd79736eb43d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3287720744 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_test_hmac512_vectors.3287720744
Directory /workspace/45.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/45.hmac_test_sha256_vectors.1230842355
Short name T523
Test name
Test status
Simulation time 276255444642 ps
CPU time 468.03 seconds
Started Jun 29 05:11:56 PM PDT 24
Finished Jun 29 05:19:45 PM PDT 24
Peak memory 200264 kb
Host smart-7ac05440-cdcc-4a8e-8c57-14c79e08cca3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1230842355 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_test_sha256_vectors.1230842355
Directory /workspace/45.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/45.hmac_test_sha384_vectors.2368281078
Short name T319
Test name
Test status
Simulation time 627691922499 ps
CPU time 1949.98 seconds
Started Jun 29 05:11:58 PM PDT 24
Finished Jun 29 05:44:29 PM PDT 24
Peak memory 215876 kb
Host smart-74f736f0-06fd-406c-9c10-5281ea00779e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2368281078 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_test_sha384_vectors.2368281078
Directory /workspace/45.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/45.hmac_test_sha512_vectors.2726018185
Short name T507
Test name
Test status
Simulation time 115289737716 ps
CPU time 1758.31 seconds
Started Jun 29 05:11:56 PM PDT 24
Finished Jun 29 05:41:15 PM PDT 24
Peak memory 215928 kb
Host smart-77576aee-3e48-427f-84f4-0f2fa9716d95
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2726018185 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_test_sha512_vectors.2726018185
Directory /workspace/45.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/45.hmac_wipe_secret.3093335767
Short name T605
Test name
Test status
Simulation time 25407276916 ps
CPU time 88.24 seconds
Started Jun 29 05:11:57 PM PDT 24
Finished Jun 29 05:13:25 PM PDT 24
Peak memory 200280 kb
Host smart-8f64e7f3-bd19-4746-90e5-a63b43760596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093335767 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_wipe_secret.3093335767
Directory /workspace/45.hmac_wipe_secret/latest

Test location /workspace/coverage/default/46.hmac_alert_test.3303642313
Short name T783
Test name
Test status
Simulation time 35956819 ps
CPU time 0.58 seconds
Started Jun 29 05:12:08 PM PDT 24
Finished Jun 29 05:12:08 PM PDT 24
Peak memory 196252 kb
Host smart-560b4629-b237-4ba2-87d8-f52bc2fd9984
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303642313 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_alert_test.3303642313
Directory /workspace/46.hmac_alert_test/latest

Test location /workspace/coverage/default/46.hmac_back_pressure.457111226
Short name T388
Test name
Test status
Simulation time 411502757 ps
CPU time 20.61 seconds
Started Jun 29 05:12:00 PM PDT 24
Finished Jun 29 05:12:21 PM PDT 24
Peak memory 200252 kb
Host smart-c190388c-a8c6-48b2-ab6d-e9adc386ea4b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=457111226 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_back_pressure.457111226
Directory /workspace/46.hmac_back_pressure/latest

Test location /workspace/coverage/default/46.hmac_burst_wr.4217523274
Short name T407
Test name
Test status
Simulation time 2522239894 ps
CPU time 13.03 seconds
Started Jun 29 05:12:08 PM PDT 24
Finished Jun 29 05:12:21 PM PDT 24
Peak memory 200232 kb
Host smart-91792e9f-e65e-411c-8033-4957bf151e39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217523274 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_burst_wr.4217523274
Directory /workspace/46.hmac_burst_wr/latest

Test location /workspace/coverage/default/46.hmac_datapath_stress.3774792914
Short name T465
Test name
Test status
Simulation time 1524907365 ps
CPU time 373 seconds
Started Jun 29 05:11:54 PM PDT 24
Finished Jun 29 05:18:08 PM PDT 24
Peak memory 651192 kb
Host smart-f45f1173-2702-4b79-97b5-abdba978ceb7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3774792914 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_datapath_stress.3774792914
Directory /workspace/46.hmac_datapath_stress/latest

Test location /workspace/coverage/default/46.hmac_error.2821161815
Short name T375
Test name
Test status
Simulation time 8807884681 ps
CPU time 108.39 seconds
Started Jun 29 05:12:04 PM PDT 24
Finished Jun 29 05:13:53 PM PDT 24
Peak memory 200324 kb
Host smart-d2268bef-f683-4682-89b1-3ca869160890
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821161815 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_error.2821161815
Directory /workspace/46.hmac_error/latest

Test location /workspace/coverage/default/46.hmac_long_msg.3612002904
Short name T582
Test name
Test status
Simulation time 294397405 ps
CPU time 12.44 seconds
Started Jun 29 05:11:56 PM PDT 24
Finished Jun 29 05:12:09 PM PDT 24
Peak memory 200260 kb
Host smart-23537e25-19f5-40ad-b926-bd3220e42784
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612002904 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_long_msg.3612002904
Directory /workspace/46.hmac_long_msg/latest

Test location /workspace/coverage/default/46.hmac_smoke.3370667566
Short name T650
Test name
Test status
Simulation time 488242629 ps
CPU time 5.7 seconds
Started Jun 29 05:11:55 PM PDT 24
Finished Jun 29 05:12:02 PM PDT 24
Peak memory 200272 kb
Host smart-945f5175-9bf9-459d-95a9-81fe63e66644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370667566 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_smoke.3370667566
Directory /workspace/46.hmac_smoke/latest

Test location /workspace/coverage/default/46.hmac_stress_all.3899980289
Short name T143
Test name
Test status
Simulation time 8496780651 ps
CPU time 795.5 seconds
Started Jun 29 05:12:04 PM PDT 24
Finished Jun 29 05:25:20 PM PDT 24
Peak memory 674184 kb
Host smart-dfd9868e-e46f-4f25-8f1c-755b9bba8b70
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899980289 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.hmac_stress_all.3899980289
Directory /workspace/46.hmac_stress_all/latest

Test location /workspace/coverage/default/46.hmac_test_hmac256_vectors.1619807551
Short name T241
Test name
Test status
Simulation time 1620107524 ps
CPU time 66.75 seconds
Started Jun 29 05:12:04 PM PDT 24
Finished Jun 29 05:13:11 PM PDT 24
Peak memory 200272 kb
Host smart-c4f041af-17d1-468f-9694-baa30a4abc0e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1619807551 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_test_hmac256_vectors.1619807551
Directory /workspace/46.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/46.hmac_test_hmac384_vectors.727912491
Short name T774
Test name
Test status
Simulation time 1365160824 ps
CPU time 38.79 seconds
Started Jun 29 05:12:08 PM PDT 24
Finished Jun 29 05:12:47 PM PDT 24
Peak memory 200308 kb
Host smart-5e6e54f1-9ce7-4e2b-9c4e-17fd735d9172
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=727912491 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_test_hmac384_vectors.727912491
Directory /workspace/46.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/46.hmac_test_hmac512_vectors.1492333231
Short name T620
Test name
Test status
Simulation time 5605786566 ps
CPU time 105.5 seconds
Started Jun 29 05:12:04 PM PDT 24
Finished Jun 29 05:13:50 PM PDT 24
Peak memory 200332 kb
Host smart-f1a6a9ed-85f1-4b19-ae0b-bdfcc4e1ac50
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1492333231 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_test_hmac512_vectors.1492333231
Directory /workspace/46.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/46.hmac_test_sha256_vectors.3933932853
Short name T349
Test name
Test status
Simulation time 112270445954 ps
CPU time 498.49 seconds
Started Jun 29 05:12:11 PM PDT 24
Finished Jun 29 05:20:30 PM PDT 24
Peak memory 200224 kb
Host smart-bf507bac-6859-4eba-aafc-eda2b558b0f9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3933932853 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_test_sha256_vectors.3933932853
Directory /workspace/46.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/46.hmac_test_sha384_vectors.2815461182
Short name T330
Test name
Test status
Simulation time 63817147042 ps
CPU time 1846.2 seconds
Started Jun 29 05:12:04 PM PDT 24
Finished Jun 29 05:42:50 PM PDT 24
Peak memory 215688 kb
Host smart-6f77d298-23c6-4a86-b88d-fefd6071c187
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2815461182 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_test_sha384_vectors.2815461182
Directory /workspace/46.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/46.hmac_test_sha512_vectors.278794113
Short name T716
Test name
Test status
Simulation time 30186743266 ps
CPU time 1726.12 seconds
Started Jun 29 05:12:07 PM PDT 24
Finished Jun 29 05:40:53 PM PDT 24
Peak memory 216296 kb
Host smart-f38b1d86-e369-402a-9557-96f13a76a49f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=278794113 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_test_sha512_vectors.278794113
Directory /workspace/46.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/46.hmac_wipe_secret.628594400
Short name T558
Test name
Test status
Simulation time 766633548 ps
CPU time 20.46 seconds
Started Jun 29 05:12:05 PM PDT 24
Finished Jun 29 05:12:26 PM PDT 24
Peak memory 200268 kb
Host smart-59ed8664-73cb-4aaf-9b5f-dbb7b1eda434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628594400 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_wipe_secret.628594400
Directory /workspace/46.hmac_wipe_secret/latest

Test location /workspace/coverage/default/47.hmac_alert_test.2063866431
Short name T626
Test name
Test status
Simulation time 13142612 ps
CPU time 0.59 seconds
Started Jun 29 05:12:12 PM PDT 24
Finished Jun 29 05:12:13 PM PDT 24
Peak memory 196252 kb
Host smart-ea21bf44-3671-4094-953a-f76bf623150a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063866431 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_alert_test.2063866431
Directory /workspace/47.hmac_alert_test/latest

Test location /workspace/coverage/default/47.hmac_back_pressure.663409420
Short name T327
Test name
Test status
Simulation time 1330220579 ps
CPU time 14.48 seconds
Started Jun 29 05:12:12 PM PDT 24
Finished Jun 29 05:12:26 PM PDT 24
Peak memory 200264 kb
Host smart-ae32d530-afc9-4f9b-aedc-0c9a89972cf8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=663409420 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_back_pressure.663409420
Directory /workspace/47.hmac_back_pressure/latest

Test location /workspace/coverage/default/47.hmac_burst_wr.1188893934
Short name T611
Test name
Test status
Simulation time 1408618118 ps
CPU time 10.76 seconds
Started Jun 29 05:12:11 PM PDT 24
Finished Jun 29 05:12:23 PM PDT 24
Peak memory 200144 kb
Host smart-ad0fd7c0-c364-47cc-bfa1-cbd0ca4fb72f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188893934 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_burst_wr.1188893934
Directory /workspace/47.hmac_burst_wr/latest

Test location /workspace/coverage/default/47.hmac_datapath_stress.1851079409
Short name T377
Test name
Test status
Simulation time 2649696825 ps
CPU time 598.76 seconds
Started Jun 29 05:12:11 PM PDT 24
Finished Jun 29 05:22:10 PM PDT 24
Peak memory 627024 kb
Host smart-07ce3a71-d977-4da9-ba83-ca9be7d842d8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1851079409 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_datapath_stress.1851079409
Directory /workspace/47.hmac_datapath_stress/latest

Test location /workspace/coverage/default/47.hmac_error.1790097017
Short name T722
Test name
Test status
Simulation time 5949155672 ps
CPU time 106.32 seconds
Started Jun 29 05:12:04 PM PDT 24
Finished Jun 29 05:13:51 PM PDT 24
Peak memory 200324 kb
Host smart-95ccab04-c21c-46ca-bf54-4d5eadedb289
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790097017 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_error.1790097017
Directory /workspace/47.hmac_error/latest

Test location /workspace/coverage/default/47.hmac_long_msg.3534014108
Short name T526
Test name
Test status
Simulation time 885446146 ps
CPU time 3.45 seconds
Started Jun 29 05:12:06 PM PDT 24
Finished Jun 29 05:12:10 PM PDT 24
Peak memory 200224 kb
Host smart-73e6b687-cfa5-447b-b5c6-91673db1e633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534014108 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_long_msg.3534014108
Directory /workspace/47.hmac_long_msg/latest

Test location /workspace/coverage/default/47.hmac_smoke.101911609
Short name T518
Test name
Test status
Simulation time 2085601735 ps
CPU time 12.68 seconds
Started Jun 29 05:12:11 PM PDT 24
Finished Jun 29 05:12:24 PM PDT 24
Peak memory 200216 kb
Host smart-be381d29-126f-4ca5-a13d-60b487be0cb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101911609 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_smoke.101911609
Directory /workspace/47.hmac_smoke/latest

Test location /workspace/coverage/default/47.hmac_stress_all.613305269
Short name T258
Test name
Test status
Simulation time 22145578262 ps
CPU time 1146.21 seconds
Started Jun 29 05:12:14 PM PDT 24
Finished Jun 29 05:31:22 PM PDT 24
Peak memory 691544 kb
Host smart-53b58a70-830b-45a8-913d-43cc66da17dd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613305269 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 47.hmac_stress_all.613305269
Directory /workspace/47.hmac_stress_all/latest

Test location /workspace/coverage/default/47.hmac_test_hmac256_vectors.3736282264
Short name T155
Test name
Test status
Simulation time 3830361308 ps
CPU time 29.62 seconds
Started Jun 29 05:12:04 PM PDT 24
Finished Jun 29 05:12:34 PM PDT 24
Peak memory 200332 kb
Host smart-6466f247-75ff-4cac-bcbf-ea7ed722907e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3736282264 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_test_hmac256_vectors.3736282264
Directory /workspace/47.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/47.hmac_test_hmac384_vectors.2193209728
Short name T271
Test name
Test status
Simulation time 2838226626 ps
CPU time 43.32 seconds
Started Jun 29 05:12:04 PM PDT 24
Finished Jun 29 05:12:48 PM PDT 24
Peak memory 200336 kb
Host smart-7f9945fe-ae34-4072-9059-4097f3e5cf0a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2193209728 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_test_hmac384_vectors.2193209728
Directory /workspace/47.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/47.hmac_test_hmac512_vectors.1326862573
Short name T179
Test name
Test status
Simulation time 3522679212 ps
CPU time 50.17 seconds
Started Jun 29 05:12:15 PM PDT 24
Finished Jun 29 05:13:06 PM PDT 24
Peak memory 200368 kb
Host smart-781f984f-d4fc-44c5-bcd4-ad3980d7ab10
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1326862573 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_test_hmac512_vectors.1326862573
Directory /workspace/47.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/47.hmac_test_sha256_vectors.279937172
Short name T393
Test name
Test status
Simulation time 152215370625 ps
CPU time 521.16 seconds
Started Jun 29 05:12:04 PM PDT 24
Finished Jun 29 05:20:46 PM PDT 24
Peak memory 200260 kb
Host smart-8538a187-59b5-41cc-b90f-fc9330617634
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=279937172 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_test_sha256_vectors.279937172
Directory /workspace/47.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/47.hmac_test_sha384_vectors.3902759618
Short name T572
Test name
Test status
Simulation time 140261686409 ps
CPU time 1981.34 seconds
Started Jun 29 05:12:05 PM PDT 24
Finished Jun 29 05:45:07 PM PDT 24
Peak memory 216088 kb
Host smart-a4866560-bd5c-48c3-801a-b5420520d2f5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3902759618 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_test_sha384_vectors.3902759618
Directory /workspace/47.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/47.hmac_test_sha512_vectors.1477229807
Short name T534
Test name
Test status
Simulation time 28519072282 ps
CPU time 1701.59 seconds
Started Jun 29 05:12:06 PM PDT 24
Finished Jun 29 05:40:28 PM PDT 24
Peak memory 215676 kb
Host smart-17ef9788-c4f6-4fd8-bfb2-6db8a68a8973
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1477229807 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_test_sha512_vectors.1477229807
Directory /workspace/47.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/47.hmac_wipe_secret.3874253798
Short name T385
Test name
Test status
Simulation time 265077451 ps
CPU time 10.17 seconds
Started Jun 29 05:12:03 PM PDT 24
Finished Jun 29 05:12:14 PM PDT 24
Peak memory 200144 kb
Host smart-c91629b8-bb36-46ad-92c3-03abec30aceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874253798 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_wipe_secret.3874253798
Directory /workspace/47.hmac_wipe_secret/latest

Test location /workspace/coverage/default/48.hmac_alert_test.487469327
Short name T217
Test name
Test status
Simulation time 12185980 ps
CPU time 0.59 seconds
Started Jun 29 05:12:12 PM PDT 24
Finished Jun 29 05:12:14 PM PDT 24
Peak memory 195228 kb
Host smart-1e691d7a-ab60-4ce8-8e85-7e744efb21f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487469327 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_alert_test.487469327
Directory /workspace/48.hmac_alert_test/latest

Test location /workspace/coverage/default/48.hmac_back_pressure.2064092131
Short name T20
Test name
Test status
Simulation time 940986843 ps
CPU time 19.2 seconds
Started Jun 29 05:12:13 PM PDT 24
Finished Jun 29 05:12:33 PM PDT 24
Peak memory 200304 kb
Host smart-aea9c8ca-fb17-409f-9db9-66bdcec27aba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2064092131 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_back_pressure.2064092131
Directory /workspace/48.hmac_back_pressure/latest

Test location /workspace/coverage/default/48.hmac_burst_wr.4269330018
Short name T689
Test name
Test status
Simulation time 2776051906 ps
CPU time 11.86 seconds
Started Jun 29 05:12:15 PM PDT 24
Finished Jun 29 05:12:27 PM PDT 24
Peak memory 200304 kb
Host smart-0da37b40-125b-459a-98dc-84c70878e400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4269330018 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_burst_wr.4269330018
Directory /workspace/48.hmac_burst_wr/latest

Test location /workspace/coverage/default/48.hmac_datapath_stress.3181972742
Short name T667
Test name
Test status
Simulation time 11745641012 ps
CPU time 263.71 seconds
Started Jun 29 05:12:15 PM PDT 24
Finished Jun 29 05:16:39 PM PDT 24
Peak memory 642544 kb
Host smart-0fe5893b-0108-494c-9eb9-e922e06fd7f6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3181972742 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_datapath_stress.3181972742
Directory /workspace/48.hmac_datapath_stress/latest

Test location /workspace/coverage/default/48.hmac_error.2385060224
Short name T418
Test name
Test status
Simulation time 3717669387 ps
CPU time 81.7 seconds
Started Jun 29 05:12:13 PM PDT 24
Finished Jun 29 05:13:36 PM PDT 24
Peak memory 200252 kb
Host smart-21cfdc35-aaa0-4d45-a80e-ea109c8b2cdf
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385060224 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_error.2385060224
Directory /workspace/48.hmac_error/latest

Test location /workspace/coverage/default/48.hmac_long_msg.807807915
Short name T354
Test name
Test status
Simulation time 503791819 ps
CPU time 21.43 seconds
Started Jun 29 05:12:13 PM PDT 24
Finished Jun 29 05:12:35 PM PDT 24
Peak memory 200280 kb
Host smart-597e9487-7dcf-4f31-9526-048b6247ab5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807807915 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_long_msg.807807915
Directory /workspace/48.hmac_long_msg/latest

Test location /workspace/coverage/default/48.hmac_stress_all.636291991
Short name T402
Test name
Test status
Simulation time 7364626027 ps
CPU time 56.26 seconds
Started Jun 29 05:12:13 PM PDT 24
Finished Jun 29 05:13:10 PM PDT 24
Peak memory 200300 kb
Host smart-4088b8ca-0004-4e5d-aa6a-666830080b77
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636291991 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 48.hmac_stress_all.636291991
Directory /workspace/48.hmac_stress_all/latest

Test location /workspace/coverage/default/48.hmac_test_hmac256_vectors.2493436671
Short name T257
Test name
Test status
Simulation time 9590945789 ps
CPU time 40.58 seconds
Started Jun 29 05:12:13 PM PDT 24
Finished Jun 29 05:12:55 PM PDT 24
Peak memory 200292 kb
Host smart-b80a770b-5423-4710-95d4-39b88d2c150a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2493436671 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_test_hmac256_vectors.2493436671
Directory /workspace/48.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/48.hmac_test_hmac384_vectors.3774843796
Short name T589
Test name
Test status
Simulation time 32842941323 ps
CPU time 94.56 seconds
Started Jun 29 05:12:13 PM PDT 24
Finished Jun 29 05:13:48 PM PDT 24
Peak memory 200332 kb
Host smart-2eca418c-c88a-4b07-b9ee-44ed5af8b7e5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3774843796 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_test_hmac384_vectors.3774843796
Directory /workspace/48.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/48.hmac_test_hmac512_vectors.4108196193
Short name T242
Test name
Test status
Simulation time 11007055469 ps
CPU time 108.17 seconds
Started Jun 29 05:12:14 PM PDT 24
Finished Jun 29 05:14:03 PM PDT 24
Peak memory 200336 kb
Host smart-f33796ba-c6cd-4524-8373-31c8cac93ec4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4108196193 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_test_hmac512_vectors.4108196193
Directory /workspace/48.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/48.hmac_test_sha256_vectors.556113362
Short name T638
Test name
Test status
Simulation time 57294268699 ps
CPU time 440.24 seconds
Started Jun 29 05:12:15 PM PDT 24
Finished Jun 29 05:19:36 PM PDT 24
Peak memory 200252 kb
Host smart-ad3afc47-3caa-4471-9c10-27ebf0a85b2b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=556113362 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_test_sha256_vectors.556113362
Directory /workspace/48.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/48.hmac_test_sha384_vectors.2359230391
Short name T623
Test name
Test status
Simulation time 129480728694 ps
CPU time 1787.42 seconds
Started Jun 29 05:12:14 PM PDT 24
Finished Jun 29 05:42:03 PM PDT 24
Peak memory 216264 kb
Host smart-859f3625-8785-4647-a2ab-b54adda7d40c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2359230391 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_test_sha384_vectors.2359230391
Directory /workspace/48.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/48.hmac_test_sha512_vectors.374143711
Short name T727
Test name
Test status
Simulation time 114420390003 ps
CPU time 1929.34 seconds
Started Jun 29 05:12:14 PM PDT 24
Finished Jun 29 05:44:24 PM PDT 24
Peak memory 215908 kb
Host smart-ecfc2334-0dc6-4e90-a050-0cde4cec4e72
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=374143711 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_test_sha512_vectors.374143711
Directory /workspace/48.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/48.hmac_wipe_secret.529049829
Short name T444
Test name
Test status
Simulation time 3299671498 ps
CPU time 45.26 seconds
Started Jun 29 05:12:14 PM PDT 24
Finished Jun 29 05:13:00 PM PDT 24
Peak memory 200308 kb
Host smart-a3d05889-0da5-4248-b2ba-3f147265b87d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=529049829 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_wipe_secret.529049829
Directory /workspace/48.hmac_wipe_secret/latest

Test location /workspace/coverage/default/49.hmac_alert_test.2884997698
Short name T687
Test name
Test status
Simulation time 13342351 ps
CPU time 0.62 seconds
Started Jun 29 05:12:24 PM PDT 24
Finished Jun 29 05:12:25 PM PDT 24
Peak memory 196972 kb
Host smart-7562120f-b8d2-4375-8cc8-ef48ef67c1a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884997698 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_alert_test.2884997698
Directory /workspace/49.hmac_alert_test/latest

Test location /workspace/coverage/default/49.hmac_back_pressure.1422957467
Short name T796
Test name
Test status
Simulation time 364606483 ps
CPU time 16.14 seconds
Started Jun 29 05:12:13 PM PDT 24
Finished Jun 29 05:12:30 PM PDT 24
Peak memory 200172 kb
Host smart-d449a83b-d46e-4b54-a252-7d4e35075d37
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1422957467 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_back_pressure.1422957467
Directory /workspace/49.hmac_back_pressure/latest

Test location /workspace/coverage/default/49.hmac_burst_wr.649508485
Short name T246
Test name
Test status
Simulation time 2272726966 ps
CPU time 32.88 seconds
Started Jun 29 05:12:15 PM PDT 24
Finished Jun 29 05:12:49 PM PDT 24
Peak memory 200292 kb
Host smart-be83055b-b92d-43f4-ae47-928b386bbe1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649508485 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_burst_wr.649508485
Directory /workspace/49.hmac_burst_wr/latest

Test location /workspace/coverage/default/49.hmac_datapath_stress.2982430174
Short name T707
Test name
Test status
Simulation time 303841568 ps
CPU time 87.26 seconds
Started Jun 29 05:12:13 PM PDT 24
Finished Jun 29 05:13:42 PM PDT 24
Peak memory 549364 kb
Host smart-2bcc12ca-14d1-4c66-95c9-13dd74eaf819
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2982430174 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_datapath_stress.2982430174
Directory /workspace/49.hmac_datapath_stress/latest

Test location /workspace/coverage/default/49.hmac_error.2745256246
Short name T307
Test name
Test status
Simulation time 1702101545 ps
CPU time 82.39 seconds
Started Jun 29 05:12:15 PM PDT 24
Finished Jun 29 05:13:38 PM PDT 24
Peak memory 200288 kb
Host smart-1f679a6f-44d5-4b0f-8bb0-86df474dafeb
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745256246 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_error.2745256246
Directory /workspace/49.hmac_error/latest

Test location /workspace/coverage/default/49.hmac_long_msg.2229668549
Short name T459
Test name
Test status
Simulation time 721039548 ps
CPU time 38.29 seconds
Started Jun 29 05:12:13 PM PDT 24
Finished Jun 29 05:12:53 PM PDT 24
Peak memory 200248 kb
Host smart-81f299a7-df25-41b9-b3dc-e1e10ebc07e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229668549 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_long_msg.2229668549
Directory /workspace/49.hmac_long_msg/latest

Test location /workspace/coverage/default/49.hmac_smoke.3324956182
Short name T789
Test name
Test status
Simulation time 1386153633 ps
CPU time 7.81 seconds
Started Jun 29 05:12:14 PM PDT 24
Finished Jun 29 05:12:23 PM PDT 24
Peak memory 200252 kb
Host smart-8d19476f-ba30-4133-977e-629e2818d99f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324956182 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_smoke.3324956182
Directory /workspace/49.hmac_smoke/latest

Test location /workspace/coverage/default/49.hmac_stress_all.610393197
Short name T574
Test name
Test status
Simulation time 72088832915 ps
CPU time 4325.23 seconds
Started Jun 29 05:12:22 PM PDT 24
Finished Jun 29 06:24:28 PM PDT 24
Peak memory 257480 kb
Host smart-a8404c96-2def-40aa-9a61-5598fec7f693
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610393197 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 49.hmac_stress_all.610393197
Directory /workspace/49.hmac_stress_all/latest

Test location /workspace/coverage/default/49.hmac_test_hmac256_vectors.1693084562
Short name T321
Test name
Test status
Simulation time 2740913338 ps
CPU time 34.1 seconds
Started Jun 29 05:12:22 PM PDT 24
Finished Jun 29 05:12:56 PM PDT 24
Peak memory 200368 kb
Host smart-1343e386-e631-4d47-b580-a884b45e3240
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1693084562 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_test_hmac256_vectors.1693084562
Directory /workspace/49.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/49.hmac_test_hmac384_vectors.3638684308
Short name T235
Test name
Test status
Simulation time 8944747512 ps
CPU time 88.06 seconds
Started Jun 29 05:12:24 PM PDT 24
Finished Jun 29 05:13:53 PM PDT 24
Peak memory 200228 kb
Host smart-65b13025-fe96-418e-a91b-3c39de338e80
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3638684308 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_test_hmac384_vectors.3638684308
Directory /workspace/49.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/49.hmac_test_hmac512_vectors.1481026170
Short name T487
Test name
Test status
Simulation time 9338132200 ps
CPU time 111.65 seconds
Started Jun 29 05:12:31 PM PDT 24
Finished Jun 29 05:14:23 PM PDT 24
Peak memory 200328 kb
Host smart-b4fa9fcd-349f-4a50-9cef-5cfb2884fcc7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1481026170 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_test_hmac512_vectors.1481026170
Directory /workspace/49.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/49.hmac_test_sha256_vectors.4201094963
Short name T658
Test name
Test status
Simulation time 29306050773 ps
CPU time 511 seconds
Started Jun 29 05:12:13 PM PDT 24
Finished Jun 29 05:20:45 PM PDT 24
Peak memory 200300 kb
Host smart-a5751d9b-e8b7-4dd8-a1d5-0257e91adbc4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=4201094963 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_test_sha256_vectors.4201094963
Directory /workspace/49.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/49.hmac_test_sha512_vectors.1720787309
Short name T228
Test name
Test status
Simulation time 442630187920 ps
CPU time 2113.63 seconds
Started Jun 29 05:12:23 PM PDT 24
Finished Jun 29 05:47:37 PM PDT 24
Peak memory 216108 kb
Host smart-8a93bf13-188f-4048-b254-86059af2de17
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1720787309 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_test_sha512_vectors.1720787309
Directory /workspace/49.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/49.hmac_wipe_secret.3538092738
Short name T31
Test name
Test status
Simulation time 186398655 ps
CPU time 4.09 seconds
Started Jun 29 05:12:13 PM PDT 24
Finished Jun 29 05:12:18 PM PDT 24
Peak memory 200088 kb
Host smart-d6ad7ca3-593f-4612-94e1-4bd26effb553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538092738 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_wipe_secret.3538092738
Directory /workspace/49.hmac_wipe_secret/latest

Test location /workspace/coverage/default/5.hmac_alert_test.1906382220
Short name T213
Test name
Test status
Simulation time 16601660 ps
CPU time 0.59 seconds
Started Jun 29 05:08:29 PM PDT 24
Finished Jun 29 05:08:31 PM PDT 24
Peak memory 195800 kb
Host smart-6944bdd3-e045-4003-92fa-48dd3c3119ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906382220 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_alert_test.1906382220
Directory /workspace/5.hmac_alert_test/latest

Test location /workspace/coverage/default/5.hmac_back_pressure.2159661659
Short name T295
Test name
Test status
Simulation time 2203467912 ps
CPU time 26.13 seconds
Started Jun 29 05:08:29 PM PDT 24
Finished Jun 29 05:08:56 PM PDT 24
Peak memory 200272 kb
Host smart-62bf7832-aefa-4eee-9403-c44b55a14eee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2159661659 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_back_pressure.2159661659
Directory /workspace/5.hmac_back_pressure/latest

Test location /workspace/coverage/default/5.hmac_burst_wr.756006036
Short name T510
Test name
Test status
Simulation time 7088511241 ps
CPU time 32.73 seconds
Started Jun 29 05:08:29 PM PDT 24
Finished Jun 29 05:09:02 PM PDT 24
Peak memory 200396 kb
Host smart-88f0d663-1425-4c32-9a2d-5b2ce94b1dad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756006036 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_burst_wr.756006036
Directory /workspace/5.hmac_burst_wr/latest

Test location /workspace/coverage/default/5.hmac_datapath_stress.3205458400
Short name T668
Test name
Test status
Simulation time 6769259084 ps
CPU time 925.69 seconds
Started Jun 29 05:08:28 PM PDT 24
Finished Jun 29 05:23:54 PM PDT 24
Peak memory 766568 kb
Host smart-5b0992ee-2e31-430d-a8a1-a6df193c002c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3205458400 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_datapath_stress.3205458400
Directory /workspace/5.hmac_datapath_stress/latest

Test location /workspace/coverage/default/5.hmac_error.2379502478
Short name T625
Test name
Test status
Simulation time 3007606876 ps
CPU time 38.06 seconds
Started Jun 29 05:08:31 PM PDT 24
Finished Jun 29 05:09:10 PM PDT 24
Peak memory 200260 kb
Host smart-e1319152-e606-410c-a505-b5c43a64e313
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379502478 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_error.2379502478
Directory /workspace/5.hmac_error/latest

Test location /workspace/coverage/default/5.hmac_long_msg.3732933100
Short name T475
Test name
Test status
Simulation time 6662329406 ps
CPU time 37.1 seconds
Started Jun 29 05:08:31 PM PDT 24
Finished Jun 29 05:09:09 PM PDT 24
Peak memory 200324 kb
Host smart-47c9ac47-45c7-4513-a27c-6d1e30348949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732933100 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_long_msg.3732933100
Directory /workspace/5.hmac_long_msg/latest

Test location /workspace/coverage/default/5.hmac_smoke.2326056943
Short name T328
Test name
Test status
Simulation time 847312775 ps
CPU time 11.16 seconds
Started Jun 29 05:08:22 PM PDT 24
Finished Jun 29 05:08:34 PM PDT 24
Peak memory 200272 kb
Host smart-af93c3c5-414c-4ab2-9d60-9e0ce3ab38ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2326056943 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_smoke.2326056943
Directory /workspace/5.hmac_smoke/latest

Test location /workspace/coverage/default/5.hmac_stress_all.767641039
Short name T525
Test name
Test status
Simulation time 88724732255 ps
CPU time 2285.8 seconds
Started Jun 29 05:08:29 PM PDT 24
Finished Jun 29 05:46:36 PM PDT 24
Peak memory 216296 kb
Host smart-777e6632-98e7-41a9-a055-190a7cc2da41
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767641039 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all.767641039
Directory /workspace/5.hmac_stress_all/latest

Test location /workspace/coverage/default/5.hmac_test_hmac256_vectors.2712299879
Short name T409
Test name
Test status
Simulation time 3849311133 ps
CPU time 58.63 seconds
Started Jun 29 05:08:29 PM PDT 24
Finished Jun 29 05:09:29 PM PDT 24
Peak memory 200320 kb
Host smart-4f7565c2-3294-4ef0-bcd4-3b18c27db25a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2712299879 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_test_hmac256_vectors.2712299879
Directory /workspace/5.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/5.hmac_test_hmac384_vectors.2796385736
Short name T647
Test name
Test status
Simulation time 2150315081 ps
CPU time 80.45 seconds
Started Jun 29 05:08:32 PM PDT 24
Finished Jun 29 05:09:53 PM PDT 24
Peak memory 200280 kb
Host smart-b3e43985-c62e-4d2a-b921-3ee18d97ff26
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2796385736 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_test_hmac384_vectors.2796385736
Directory /workspace/5.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/5.hmac_test_hmac512_vectors.4149383063
Short name T298
Test name
Test status
Simulation time 2689560105 ps
CPU time 95.49 seconds
Started Jun 29 05:08:31 PM PDT 24
Finished Jun 29 05:10:07 PM PDT 24
Peak memory 200296 kb
Host smart-f2e72951-95b4-41e6-a047-e21ed643dfc8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4149383063 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_test_hmac512_vectors.4149383063
Directory /workspace/5.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/5.hmac_test_sha256_vectors.3416823449
Short name T552
Test name
Test status
Simulation time 24815960395 ps
CPU time 447.15 seconds
Started Jun 29 05:08:30 PM PDT 24
Finished Jun 29 05:15:58 PM PDT 24
Peak memory 200260 kb
Host smart-e664353f-2c78-43f5-b9ad-444be7ba48f6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3416823449 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_test_sha256_vectors.3416823449
Directory /workspace/5.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/5.hmac_test_sha384_vectors.2733976545
Short name T296
Test name
Test status
Simulation time 172205074233 ps
CPU time 2263.54 seconds
Started Jun 29 05:08:31 PM PDT 24
Finished Jun 29 05:46:15 PM PDT 24
Peak memory 216576 kb
Host smart-70423ec4-c351-409e-bd64-0438deb6efd3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2733976545 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_test_sha384_vectors.2733976545
Directory /workspace/5.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/5.hmac_wipe_secret.1931812281
Short name T691
Test name
Test status
Simulation time 4574639728 ps
CPU time 17.74 seconds
Started Jun 29 05:08:29 PM PDT 24
Finished Jun 29 05:08:48 PM PDT 24
Peak memory 200340 kb
Host smart-c8590884-eee0-4ece-b2e7-abcbead1a3d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931812281 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_wipe_secret.1931812281
Directory /workspace/5.hmac_wipe_secret/latest

Test location /workspace/coverage/default/6.hmac_alert_test.2732875758
Short name T607
Test name
Test status
Simulation time 13782600 ps
CPU time 0.59 seconds
Started Jun 29 05:08:33 PM PDT 24
Finished Jun 29 05:08:34 PM PDT 24
Peak memory 196240 kb
Host smart-90123f41-83d4-48ab-8c96-2e78389764ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732875758 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_alert_test.2732875758
Directory /workspace/6.hmac_alert_test/latest

Test location /workspace/coverage/default/6.hmac_back_pressure.2647061489
Short name T434
Test name
Test status
Simulation time 1026834670 ps
CPU time 44.39 seconds
Started Jun 29 05:08:31 PM PDT 24
Finished Jun 29 05:09:16 PM PDT 24
Peak memory 200272 kb
Host smart-bee9ea84-f762-429f-bb80-7dbfc546bf8c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2647061489 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_back_pressure.2647061489
Directory /workspace/6.hmac_back_pressure/latest

Test location /workspace/coverage/default/6.hmac_burst_wr.1487315930
Short name T289
Test name
Test status
Simulation time 1314174713 ps
CPU time 9.11 seconds
Started Jun 29 05:08:29 PM PDT 24
Finished Jun 29 05:08:39 PM PDT 24
Peak memory 200324 kb
Host smart-8151dfa7-7ee6-43c2-bd97-77714c120378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487315930 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_burst_wr.1487315930
Directory /workspace/6.hmac_burst_wr/latest

Test location /workspace/coverage/default/6.hmac_datapath_stress.2488658952
Short name T274
Test name
Test status
Simulation time 7729355112 ps
CPU time 1074.87 seconds
Started Jun 29 05:08:30 PM PDT 24
Finished Jun 29 05:26:25 PM PDT 24
Peak memory 731232 kb
Host smart-9c7a36ad-60a4-478d-bc75-a239f1103a3b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2488658952 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_datapath_stress.2488658952
Directory /workspace/6.hmac_datapath_stress/latest

Test location /workspace/coverage/default/6.hmac_error.476296072
Short name T446
Test name
Test status
Simulation time 8180407421 ps
CPU time 31.26 seconds
Started Jun 29 05:08:32 PM PDT 24
Finished Jun 29 05:09:03 PM PDT 24
Peak memory 200268 kb
Host smart-bd002411-43c9-46b0-87af-aa87b13e0c83
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476296072 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_error.476296072
Directory /workspace/6.hmac_error/latest

Test location /workspace/coverage/default/6.hmac_long_msg.1896394542
Short name T793
Test name
Test status
Simulation time 7556703033 ps
CPU time 117.13 seconds
Started Jun 29 05:08:30 PM PDT 24
Finished Jun 29 05:10:28 PM PDT 24
Peak memory 200476 kb
Host smart-a76415d4-a166-4d71-89d3-3247f30373fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896394542 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_long_msg.1896394542
Directory /workspace/6.hmac_long_msg/latest

Test location /workspace/coverage/default/6.hmac_smoke.2548660592
Short name T666
Test name
Test status
Simulation time 1685631605 ps
CPU time 6.84 seconds
Started Jun 29 05:08:33 PM PDT 24
Finished Jun 29 05:08:40 PM PDT 24
Peak memory 200220 kb
Host smart-b7b9272e-8e11-4ff5-acef-b046af70e236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548660592 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_smoke.2548660592
Directory /workspace/6.hmac_smoke/latest

Test location /workspace/coverage/default/6.hmac_stress_all.1234662617
Short name T690
Test name
Test status
Simulation time 161229385874 ps
CPU time 2365.86 seconds
Started Jun 29 05:08:28 PM PDT 24
Finished Jun 29 05:47:54 PM PDT 24
Peak memory 480980 kb
Host smart-9295066c-4d74-4d24-a7cf-17664970a6b4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234662617 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all.1234662617
Directory /workspace/6.hmac_stress_all/latest

Test location /workspace/coverage/default/6.hmac_test_hmac256_vectors.624084335
Short name T744
Test name
Test status
Simulation time 16694316446 ps
CPU time 35.85 seconds
Started Jun 29 05:08:30 PM PDT 24
Finished Jun 29 05:09:07 PM PDT 24
Peak memory 200368 kb
Host smart-1f892153-5b2c-4a7a-96b8-224057d872a3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=624084335 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_test_hmac256_vectors.624084335
Directory /workspace/6.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/6.hmac_test_hmac384_vectors.1756586608
Short name T428
Test name
Test status
Simulation time 14703329058 ps
CPU time 88.75 seconds
Started Jun 29 05:08:32 PM PDT 24
Finished Jun 29 05:10:01 PM PDT 24
Peak memory 200236 kb
Host smart-df6d9e2a-d0b5-4410-841c-6c45c3f63e95
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1756586608 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_test_hmac384_vectors.1756586608
Directory /workspace/6.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/6.hmac_test_hmac512_vectors.3094554924
Short name T479
Test name
Test status
Simulation time 5612920263 ps
CPU time 103.5 seconds
Started Jun 29 05:08:29 PM PDT 24
Finished Jun 29 05:10:13 PM PDT 24
Peak memory 200360 kb
Host smart-968d665f-bf92-40fc-a43c-a21ae6b4de06
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3094554924 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_test_hmac512_vectors.3094554924
Directory /workspace/6.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/6.hmac_test_sha256_vectors.2376422718
Short name T165
Test name
Test status
Simulation time 293173853656 ps
CPU time 532.99 seconds
Started Jun 29 05:08:32 PM PDT 24
Finished Jun 29 05:17:25 PM PDT 24
Peak memory 200272 kb
Host smart-a850bf82-c277-4e6f-8dd3-00da20fda6a9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2376422718 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_test_sha256_vectors.2376422718
Directory /workspace/6.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/6.hmac_test_sha384_vectors.3519804111
Short name T508
Test name
Test status
Simulation time 234975403152 ps
CPU time 2086.21 seconds
Started Jun 29 05:08:31 PM PDT 24
Finished Jun 29 05:43:18 PM PDT 24
Peak memory 215696 kb
Host smart-33a0d8b5-b22c-4f24-a3dd-22d781182cd8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3519804111 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_test_sha384_vectors.3519804111
Directory /workspace/6.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/6.hmac_test_sha512_vectors.3591280544
Short name T713
Test name
Test status
Simulation time 650568156013 ps
CPU time 1907.87 seconds
Started Jun 29 05:08:32 PM PDT 24
Finished Jun 29 05:40:21 PM PDT 24
Peak memory 215616 kb
Host smart-a3f9408e-f45f-4568-8ec4-c8f8f875ce83
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3591280544 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_test_sha512_vectors.3591280544
Directory /workspace/6.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/6.hmac_wipe_secret.1629313768
Short name T395
Test name
Test status
Simulation time 4674199847 ps
CPU time 84.36 seconds
Started Jun 29 05:08:31 PM PDT 24
Finished Jun 29 05:09:56 PM PDT 24
Peak memory 200208 kb
Host smart-5a8b11ff-9957-4060-90f0-1ac074756256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629313768 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_wipe_secret.1629313768
Directory /workspace/6.hmac_wipe_secret/latest

Test location /workspace/coverage/default/7.hmac_alert_test.3778021593
Short name T303
Test name
Test status
Simulation time 36287294 ps
CPU time 0.58 seconds
Started Jun 29 05:08:40 PM PDT 24
Finished Jun 29 05:08:41 PM PDT 24
Peak memory 195228 kb
Host smart-589d6172-796c-4313-a92b-30b1140fe94d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778021593 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_alert_test.3778021593
Directory /workspace/7.hmac_alert_test/latest

Test location /workspace/coverage/default/7.hmac_back_pressure.3820525921
Short name T345
Test name
Test status
Simulation time 2240248100 ps
CPU time 27.55 seconds
Started Jun 29 05:08:44 PM PDT 24
Finished Jun 29 05:09:12 PM PDT 24
Peak memory 200244 kb
Host smart-c61ea823-e495-47b4-96e0-7e56989657cb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3820525921 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_back_pressure.3820525921
Directory /workspace/7.hmac_back_pressure/latest

Test location /workspace/coverage/default/7.hmac_burst_wr.2928077489
Short name T584
Test name
Test status
Simulation time 5005649195 ps
CPU time 46.45 seconds
Started Jun 29 05:08:37 PM PDT 24
Finished Jun 29 05:09:23 PM PDT 24
Peak memory 200308 kb
Host smart-c3f70f1a-04af-49a0-91ba-6e815efc7af6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928077489 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_burst_wr.2928077489
Directory /workspace/7.hmac_burst_wr/latest

Test location /workspace/coverage/default/7.hmac_datapath_stress.216414693
Short name T224
Test name
Test status
Simulation time 3014430215 ps
CPU time 412.07 seconds
Started Jun 29 05:08:40 PM PDT 24
Finished Jun 29 05:15:33 PM PDT 24
Peak memory 653924 kb
Host smart-516916b1-6741-45b9-a63c-f3d8ae2f5260
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=216414693 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_datapath_stress.216414693
Directory /workspace/7.hmac_datapath_stress/latest

Test location /workspace/coverage/default/7.hmac_error.4094712783
Short name T34
Test name
Test status
Simulation time 3215296762 ps
CPU time 55.25 seconds
Started Jun 29 05:08:43 PM PDT 24
Finished Jun 29 05:09:39 PM PDT 24
Peak memory 200172 kb
Host smart-0ad428bf-d70a-4724-b22e-b5366e3cf2ba
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094712783 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_error.4094712783
Directory /workspace/7.hmac_error/latest

Test location /workspace/coverage/default/7.hmac_long_msg.3354209591
Short name T342
Test name
Test status
Simulation time 1871084792 ps
CPU time 28.23 seconds
Started Jun 29 05:08:37 PM PDT 24
Finished Jun 29 05:09:05 PM PDT 24
Peak memory 200264 kb
Host smart-88d507c9-d4b9-422d-8282-12c58698cc0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354209591 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_long_msg.3354209591
Directory /workspace/7.hmac_long_msg/latest

Test location /workspace/coverage/default/7.hmac_smoke.3708339868
Short name T519
Test name
Test status
Simulation time 637916164 ps
CPU time 3.71 seconds
Started Jun 29 05:08:32 PM PDT 24
Finished Jun 29 05:08:36 PM PDT 24
Peak memory 200288 kb
Host smart-b26b3c17-9a61-439e-a76d-52fff63b592b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708339868 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_smoke.3708339868
Directory /workspace/7.hmac_smoke/latest

Test location /workspace/coverage/default/7.hmac_stress_all.771821142
Short name T76
Test name
Test status
Simulation time 201172834948 ps
CPU time 2834.02 seconds
Started Jun 29 05:08:45 PM PDT 24
Finished Jun 29 05:55:59 PM PDT 24
Peak memory 216736 kb
Host smart-5518c47c-8271-4c7e-93cf-3692523a5d5d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771821142 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all.771821142
Directory /workspace/7.hmac_stress_all/latest

Test location /workspace/coverage/default/7.hmac_test_hmac256_vectors.2135455530
Short name T677
Test name
Test status
Simulation time 4004328418 ps
CPU time 28.86 seconds
Started Jun 29 05:08:35 PM PDT 24
Finished Jun 29 05:09:05 PM PDT 24
Peak memory 200332 kb
Host smart-d18cc722-0c26-41a0-a0d4-754009d6ad07
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2135455530 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_test_hmac256_vectors.2135455530
Directory /workspace/7.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/7.hmac_test_hmac384_vectors.853744184
Short name T738
Test name
Test status
Simulation time 3324722302 ps
CPU time 50.35 seconds
Started Jun 29 05:08:43 PM PDT 24
Finished Jun 29 05:09:34 PM PDT 24
Peak memory 200332 kb
Host smart-88dd1eca-f307-4b31-b145-11a9b6e31a63
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=853744184 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_test_hmac384_vectors.853744184
Directory /workspace/7.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/7.hmac_test_hmac512_vectors.2874976605
Short name T470
Test name
Test status
Simulation time 7377605842 ps
CPU time 120.48 seconds
Started Jun 29 05:08:36 PM PDT 24
Finished Jun 29 05:10:37 PM PDT 24
Peak memory 200332 kb
Host smart-b80bf3ba-c32f-4ea4-8242-9715982ef993
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2874976605 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_test_hmac512_vectors.2874976605
Directory /workspace/7.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/7.hmac_test_sha256_vectors.1870654078
Short name T152
Test name
Test status
Simulation time 7492208768 ps
CPU time 434.06 seconds
Started Jun 29 05:08:39 PM PDT 24
Finished Jun 29 05:15:54 PM PDT 24
Peak memory 200260 kb
Host smart-ee057ae3-e227-4af9-9905-39fb51144db5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1870654078 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_test_sha256_vectors.1870654078
Directory /workspace/7.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/7.hmac_test_sha384_vectors.2227720867
Short name T482
Test name
Test status
Simulation time 93970731938 ps
CPU time 1601.56 seconds
Started Jun 29 05:08:36 PM PDT 24
Finished Jun 29 05:35:19 PM PDT 24
Peak memory 215780 kb
Host smart-7638b36e-48b7-475d-9ab7-3eb47208db12
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2227720867 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_test_sha384_vectors.2227720867
Directory /workspace/7.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/7.hmac_test_sha512_vectors.1646972894
Short name T685
Test name
Test status
Simulation time 113710815940 ps
CPU time 1669.1 seconds
Started Jun 29 05:08:44 PM PDT 24
Finished Jun 29 05:36:34 PM PDT 24
Peak memory 216684 kb
Host smart-1f70ba2a-39fc-4bc4-a493-b45e3b9a39ae
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1646972894 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_test_sha512_vectors.1646972894
Directory /workspace/7.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/7.hmac_wipe_secret.2404655325
Short name T731
Test name
Test status
Simulation time 1727470178 ps
CPU time 30.81 seconds
Started Jun 29 05:08:37 PM PDT 24
Finished Jun 29 05:09:08 PM PDT 24
Peak memory 200200 kb
Host smart-fd076f3d-47db-432f-8589-bfa9ccf955ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404655325 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_wipe_secret.2404655325
Directory /workspace/7.hmac_wipe_secret/latest

Test location /workspace/coverage/default/8.hmac_alert_test.10655856
Short name T211
Test name
Test status
Simulation time 33963457 ps
CPU time 0.55 seconds
Started Jun 29 05:08:45 PM PDT 24
Finished Jun 29 05:08:46 PM PDT 24
Peak memory 195228 kb
Host smart-37a55e5f-adf4-475f-8323-c4327b3d2b91
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10655856 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_alert_test.10655856
Directory /workspace/8.hmac_alert_test/latest

Test location /workspace/coverage/default/8.hmac_back_pressure.1731051347
Short name T266
Test name
Test status
Simulation time 140994612 ps
CPU time 6.82 seconds
Started Jun 29 05:08:44 PM PDT 24
Finished Jun 29 05:08:51 PM PDT 24
Peak memory 200268 kb
Host smart-8729572c-a8db-4d87-9ade-8a4c3c9de68e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1731051347 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_back_pressure.1731051347
Directory /workspace/8.hmac_back_pressure/latest

Test location /workspace/coverage/default/8.hmac_burst_wr.310715470
Short name T766
Test name
Test status
Simulation time 341898423 ps
CPU time 5.17 seconds
Started Jun 29 05:08:37 PM PDT 24
Finished Jun 29 05:08:43 PM PDT 24
Peak memory 200184 kb
Host smart-1730806e-c7f4-474f-b85d-1957ff277a61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310715470 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_burst_wr.310715470
Directory /workspace/8.hmac_burst_wr/latest

Test location /workspace/coverage/default/8.hmac_datapath_stress.4188413979
Short name T609
Test name
Test status
Simulation time 14433440190 ps
CPU time 1361.82 seconds
Started Jun 29 05:08:36 PM PDT 24
Finished Jun 29 05:31:18 PM PDT 24
Peak memory 768036 kb
Host smart-67edfaac-18e5-4f48-b7cc-d9cf193c5d6a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4188413979 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_datapath_stress.4188413979
Directory /workspace/8.hmac_datapath_stress/latest

Test location /workspace/coverage/default/8.hmac_error.2584931569
Short name T32
Test name
Test status
Simulation time 3674526421 ps
CPU time 210.36 seconds
Started Jun 29 05:08:43 PM PDT 24
Finished Jun 29 05:12:13 PM PDT 24
Peak memory 200232 kb
Host smart-750241b0-346b-462e-8bed-1b5126dc979b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584931569 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_error.2584931569
Directory /workspace/8.hmac_error/latest

Test location /workspace/coverage/default/8.hmac_long_msg.2469724742
Short name T701
Test name
Test status
Simulation time 2532644979 ps
CPU time 74.72 seconds
Started Jun 29 05:08:47 PM PDT 24
Finished Jun 29 05:10:02 PM PDT 24
Peak memory 200332 kb
Host smart-be748ccc-55d3-4ead-a8d2-27be009b3cb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469724742 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_long_msg.2469724742
Directory /workspace/8.hmac_long_msg/latest

Test location /workspace/coverage/default/8.hmac_smoke.412016307
Short name T269
Test name
Test status
Simulation time 3420834561 ps
CPU time 14.24 seconds
Started Jun 29 05:08:37 PM PDT 24
Finished Jun 29 05:08:51 PM PDT 24
Peak memory 200344 kb
Host smart-72b91d75-b950-4cf9-bca9-eed39dc9a593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412016307 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_smoke.412016307
Directory /workspace/8.hmac_smoke/latest

Test location /workspace/coverage/default/8.hmac_stress_all.2966545797
Short name T94
Test name
Test status
Simulation time 1336535324310 ps
CPU time 5025.5 seconds
Started Jun 29 05:08:38 PM PDT 24
Finished Jun 29 06:32:24 PM PDT 24
Peak memory 571968 kb
Host smart-8080826d-ee55-4dbb-861a-925979fcc240
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966545797 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all.2966545797
Directory /workspace/8.hmac_stress_all/latest

Test location /workspace/coverage/default/8.hmac_test_hmac256_vectors.38224391
Short name T468
Test name
Test status
Simulation time 37383904415 ps
CPU time 72.74 seconds
Started Jun 29 05:08:39 PM PDT 24
Finished Jun 29 05:09:52 PM PDT 24
Peak memory 200300 kb
Host smart-bc5275f4-afbc-4ecd-9409-d24460799af6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=38224391 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_test_hmac256_vectors.38224391
Directory /workspace/8.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/8.hmac_test_hmac384_vectors.311105138
Short name T320
Test name
Test status
Simulation time 23316938689 ps
CPU time 79.34 seconds
Started Jun 29 05:08:44 PM PDT 24
Finished Jun 29 05:10:04 PM PDT 24
Peak memory 200332 kb
Host smart-96022fad-21ef-419d-9f62-f19008bbbf14
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=311105138 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_test_hmac384_vectors.311105138
Directory /workspace/8.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/8.hmac_test_hmac512_vectors.2208769823
Short name T655
Test name
Test status
Simulation time 7346642561 ps
CPU time 50.48 seconds
Started Jun 29 05:08:37 PM PDT 24
Finished Jun 29 05:09:28 PM PDT 24
Peak memory 200332 kb
Host smart-79e6fa35-9042-44ca-9135-39da8d911292
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2208769823 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_test_hmac512_vectors.2208769823
Directory /workspace/8.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/8.hmac_test_sha256_vectors.2081989211
Short name T174
Test name
Test status
Simulation time 73079223635 ps
CPU time 500.74 seconds
Started Jun 29 05:08:43 PM PDT 24
Finished Jun 29 05:17:05 PM PDT 24
Peak memory 200224 kb
Host smart-6fc93905-8edb-4535-8036-f3ee2f7ee43c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2081989211 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_test_sha256_vectors.2081989211
Directory /workspace/8.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/8.hmac_test_sha384_vectors.1942321423
Short name T586
Test name
Test status
Simulation time 30172943127 ps
CPU time 1633.91 seconds
Started Jun 29 05:08:39 PM PDT 24
Finished Jun 29 05:35:53 PM PDT 24
Peak memory 215800 kb
Host smart-5b7bd72c-00ce-4241-ba32-5bd553fbb1ae
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1942321423 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_test_sha384_vectors.1942321423
Directory /workspace/8.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/8.hmac_test_sha512_vectors.4060173018
Short name T694
Test name
Test status
Simulation time 120739838762 ps
CPU time 2089.49 seconds
Started Jun 29 05:08:43 PM PDT 24
Finished Jun 29 05:43:34 PM PDT 24
Peak memory 216480 kb
Host smart-1dfba47e-6d4a-4d3b-8f17-59dd91f49349
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4060173018 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_test_sha512_vectors.4060173018
Directory /workspace/8.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/8.hmac_wipe_secret.892558213
Short name T657
Test name
Test status
Simulation time 5400834962 ps
CPU time 77.9 seconds
Started Jun 29 05:08:37 PM PDT 24
Finished Jun 29 05:09:55 PM PDT 24
Peak memory 200324 kb
Host smart-779a3d83-44d5-4824-a792-ce92bff2a3c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=892558213 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_wipe_secret.892558213
Directory /workspace/8.hmac_wipe_secret/latest

Test location /workspace/coverage/default/9.hmac_alert_test.1220004427
Short name T220
Test name
Test status
Simulation time 18805643 ps
CPU time 0.58 seconds
Started Jun 29 05:08:47 PM PDT 24
Finished Jun 29 05:08:48 PM PDT 24
Peak memory 196996 kb
Host smart-8eb9d01d-d613-4e3e-b417-f8a084a07ae8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220004427 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_alert_test.1220004427
Directory /workspace/9.hmac_alert_test/latest

Test location /workspace/coverage/default/9.hmac_back_pressure.3171719252
Short name T410
Test name
Test status
Simulation time 2861489776 ps
CPU time 36.4 seconds
Started Jun 29 05:08:47 PM PDT 24
Finished Jun 29 05:09:23 PM PDT 24
Peak memory 200348 kb
Host smart-eef000cd-954d-4f06-91ac-a67561152188
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3171719252 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_back_pressure.3171719252
Directory /workspace/9.hmac_back_pressure/latest

Test location /workspace/coverage/default/9.hmac_burst_wr.3068209119
Short name T135
Test name
Test status
Simulation time 4957837861 ps
CPU time 72.04 seconds
Started Jun 29 05:08:48 PM PDT 24
Finished Jun 29 05:10:01 PM PDT 24
Peak memory 208520 kb
Host smart-5137a172-d491-4426-bd6e-0b5c4e182118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068209119 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_burst_wr.3068209119
Directory /workspace/9.hmac_burst_wr/latest

Test location /workspace/coverage/default/9.hmac_datapath_stress.729845570
Short name T312
Test name
Test status
Simulation time 10933005748 ps
CPU time 702.84 seconds
Started Jun 29 05:08:50 PM PDT 24
Finished Jun 29 05:20:33 PM PDT 24
Peak memory 726928 kb
Host smart-ee956e9d-7768-4bcb-9eca-fc6940a56c93
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=729845570 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_datapath_stress.729845570
Directory /workspace/9.hmac_datapath_stress/latest

Test location /workspace/coverage/default/9.hmac_error.917925312
Short name T792
Test name
Test status
Simulation time 35314782970 ps
CPU time 160.54 seconds
Started Jun 29 05:08:50 PM PDT 24
Finished Jun 29 05:11:31 PM PDT 24
Peak memory 200316 kb
Host smart-346ae057-ddca-42ae-a93f-7073150cce72
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917925312 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_error.917925312
Directory /workspace/9.hmac_error/latest

Test location /workspace/coverage/default/9.hmac_long_msg.825940622
Short name T698
Test name
Test status
Simulation time 21240161232 ps
CPU time 69.08 seconds
Started Jun 29 05:08:49 PM PDT 24
Finished Jun 29 05:09:58 PM PDT 24
Peak memory 200348 kb
Host smart-fa2fc53b-d25c-4f42-8474-c14ea2776bac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825940622 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_long_msg.825940622
Directory /workspace/9.hmac_long_msg/latest

Test location /workspace/coverage/default/9.hmac_smoke.1279503716
Short name T226
Test name
Test status
Simulation time 406201028 ps
CPU time 9.74 seconds
Started Jun 29 05:08:48 PM PDT 24
Finished Jun 29 05:08:59 PM PDT 24
Peak memory 200248 kb
Host smart-00dc2466-8a90-4d90-a69a-d652fddca3da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279503716 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_smoke.1279503716
Directory /workspace/9.hmac_smoke/latest

Test location /workspace/coverage/default/9.hmac_stress_all.3456523304
Short name T408
Test name
Test status
Simulation time 198962097719 ps
CPU time 2777.77 seconds
Started Jun 29 05:08:48 PM PDT 24
Finished Jun 29 05:55:06 PM PDT 24
Peak memory 438132 kb
Host smart-519e194b-07cd-4725-83ff-64f3e082b279
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456523304 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all.3456523304
Directory /workspace/9.hmac_stress_all/latest

Test location /workspace/coverage/default/9.hmac_test_hmac256_vectors.3621477892
Short name T477
Test name
Test status
Simulation time 1785211656 ps
CPU time 28.88 seconds
Started Jun 29 05:08:48 PM PDT 24
Finished Jun 29 05:09:17 PM PDT 24
Peak memory 200304 kb
Host smart-397ad743-4b90-42cb-a365-256b00af88b7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3621477892 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_test_hmac256_vectors.3621477892
Directory /workspace/9.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/9.hmac_test_hmac384_vectors.724225057
Short name T177
Test name
Test status
Simulation time 2011912980 ps
CPU time 48.65 seconds
Started Jun 29 05:08:47 PM PDT 24
Finished Jun 29 05:09:36 PM PDT 24
Peak memory 200272 kb
Host smart-4fa545f3-3d6c-4a00-9ab1-640b9606d62c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=724225057 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_test_hmac384_vectors.724225057
Directory /workspace/9.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/9.hmac_test_hmac512_vectors.2098934205
Short name T160
Test name
Test status
Simulation time 2265554271 ps
CPU time 52.4 seconds
Started Jun 29 05:08:47 PM PDT 24
Finished Jun 29 05:09:40 PM PDT 24
Peak memory 200332 kb
Host smart-f8817be2-6d53-43fa-ab0b-a2d8a09c6b99
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2098934205 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_test_hmac512_vectors.2098934205
Directory /workspace/9.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/9.hmac_test_sha256_vectors.239438995
Short name T50
Test name
Test status
Simulation time 28338575183 ps
CPU time 425.85 seconds
Started Jun 29 05:08:50 PM PDT 24
Finished Jun 29 05:15:56 PM PDT 24
Peak memory 200252 kb
Host smart-f2c1a044-c2d7-4962-bfba-335993d1c388
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=239438995 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_test_sha256_vectors.239438995
Directory /workspace/9.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/9.hmac_test_sha384_vectors.3259804250
Short name T389
Test name
Test status
Simulation time 428086075914 ps
CPU time 2014.94 seconds
Started Jun 29 05:08:48 PM PDT 24
Finished Jun 29 05:42:23 PM PDT 24
Peak memory 216164 kb
Host smart-0c67baaf-6a9a-4d4b-aeed-7ca129936a3c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3259804250 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_test_sha384_vectors.3259804250
Directory /workspace/9.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/9.hmac_test_sha512_vectors.1659900823
Short name T210
Test name
Test status
Simulation time 174974051053 ps
CPU time 1979.4 seconds
Started Jun 29 05:08:48 PM PDT 24
Finished Jun 29 05:41:48 PM PDT 24
Peak memory 216640 kb
Host smart-0060645a-9785-46e5-bd9e-5926852db9ba
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1659900823 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_test_sha512_vectors.1659900823
Directory /workspace/9.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/9.hmac_wipe_secret.1381190644
Short name T661
Test name
Test status
Simulation time 9218729049 ps
CPU time 44.1 seconds
Started Jun 29 05:08:48 PM PDT 24
Finished Jun 29 05:09:33 PM PDT 24
Peak memory 200272 kb
Host smart-9e57c1c3-72ff-4d0e-933f-11928b4cc8da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381190644 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_wipe_secret.1381190644
Directory /workspace/9.hmac_wipe_secret/latest
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