Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	46007913	1			T2	277758		T3	9681		T4	13102
all_values[1]	46007913	1			T2	277758		T3	9681		T4	13102
all_values[2]	46007913	1			T2	277758		T3	9681		T4	13102

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

116711

1

T7

1270

T9

51

T5

93

auto[1]

137907028

1

T2

833274

T3

29043

T4

39306

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

114480128

1

T2

703587

T3

19878

T4

34104

auto[1]

23543611

1

T2

129687

T3

9165

T4

5202

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	41314	1			T7	1214		T9	49		T84	882
all_values[0]	auto[0]	auto[1]	279	1			T7	8		T9	2		T33	2
all_values[0]	auto[1]	auto[0]	45861910	1			T2	277372		T3	9677		T4	13071
all_values[0]	auto[1]	auto[1]	104410	1			T2	386		T3	4		T4	31
all_values[1]	auto[0]	auto[0]	32024	1			T7	15		T5	93		T83	21
all_values[1]	auto[0]	auto[1]	139	1			T7	4		T48	2		T49	2
all_values[1]	auto[1]	auto[0]	45971588	1			T2	277758		T3	9681		T4	13102
all_values[1]	auto[1]	auto[1]	4162	1			T7	9		T6	76		T80	5
all_values[2]	auto[0]	auto[0]	11856	1			T7	9		T33	18		T119	512
all_values[2]	auto[0]	auto[1]	31099	1			T7	20		T119	15		T48	5
all_values[2]	auto[1]	auto[0]	22561436	1			T2	148457		T3	520		T4	7931
all_values[2]	auto[1]	auto[1]	23403522	1			T2	129301		T3	9161		T4	5171