Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::msg_len_cg

Group : hmac_env_pkg::hmac_env_cov::msg_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
78.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	3	15	83.33
Crosses	32	8	24	75.00

Variables for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
hmac_en	2	0	2	100.00	100	1	1	2
msg_len_lower_cp	15	2	13	86.67	100	1	1	0
msg_len_upper_cp	1	1	0	0.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
msg_len_lower_cross	30	6	24	80.00	100	1	1	0
msg_len_upper_cross	2	2	0	0.00	100	1	1	0

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

150796

1

T2

384

T3

16

T4

32

auto[1]

137184

1

T3

14

T4

24

T11

222

---

Summary for Variable msg_len_lower_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	2	13	86.67

User Defined Bins for msg_len_lower_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
len_2047	0	1	1
len_511	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_2050_plus	41478	1			T2	52		T4	9		T7	282
len_1026_2046	29100	1			T2	3		T3	9		T4	7
len_514_1022	9428	1			T2	3		T4	1		T7	186
len_2_510	52249	1			T2	133		T4	10		T11	111
len_2049	13	1			T125	3		T126	4		T127	2
len_2048	58	1			T48	1		T18	3		T57	3
len_1025	23	1			T128	4		T129	4		T130	13
len_1024	116	1			T7	4		T5	1		T80	5
len_1023	1	1			T131	1		-	-		-	-
len_513	2	1			T132	2		-	-		-	-
len_512	119	1			T7	2		T80	4		T48	3
len_1	980	1			T2	1		T7	2		T10	2
len_0	10423	1			T3	6		T4	1		T7	61

---

Summary for Variable msg_len_upper_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	1	0	0.00

User Defined Bins for msg_len_upper_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
len_upper	0	1	1

---

Summary for Cross msg_len_lower_cross

Samples crossed: hmac_en msg_len_lower_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	6	24	80.00	6

Automatically Generated Cross Bins for msg_len_lower_cross

Uncovered bins

hmac_en	msg_len_lower_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[len_2047]	0	1	1
[auto[0]]	[len_1023 , len_513]	--	--	2
[auto[0]]	[len_511]	0	1	1
[auto[1]]	[len_2047]	0	1	1
[auto[1]]	[len_511]	0	1	1

Covered bins

hmac_en	msg_len_lower_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	len_2050_plus	23778	1			T2	52		T4	5		T7	203
auto[0]	len_1026_2046	14321	1			T2	3		T3	6		T4	3
auto[0]	len_514_1022	6084	1			T2	3		T4	1		T7	138
auto[0]	len_2_510	27238	1			T2	133		T4	6		T7	290
auto[0]	len_2049	5	1			T126	3		T127	2		-	-
auto[0]	len_2048	34	1			T57	2		T133	2		T134	1
auto[0]	len_1025	3	1			T128	2		T130	1		-	-
auto[0]	len_1024	63	1			T7	2		T5	1		T80	4
auto[0]	len_512	68	1			T7	1		T80	3		T48	2
auto[0]	len_1	245	1			T2	1		T7	1		T10	2
auto[0]	len_0	3559	1			T3	2		T4	1		T7	9
auto[1]	len_2050_plus	17700	1			T4	4		T7	79		T5	59
auto[1]	len_1026_2046	14779	1			T3	3		T4	4		T7	189
auto[1]	len_514_1022	3344	1			T7	48		T5	10		T80	19
auto[1]	len_2_510	25011	1			T4	4		T11	111		T7	297
auto[1]	len_2049	8	1			T125	3		T126	1		T135	4
auto[1]	len_2048	24	1			T48	1		T18	3		T57	1
auto[1]	len_1025	20	1			T128	2		T129	4		T130	12
auto[1]	len_1024	53	1			T7	2		T80	1		T81	1
auto[1]	len_1023	1	1			T131	1		-	-		-	-
auto[1]	len_513	2	1			T132	2		-	-		-	-
auto[1]	len_512	51	1			T7	1		T80	1		T48	1
auto[1]	len_1	735	1			T7	1		T30	10		T33	8
auto[1]	len_0	6864	1			T3	4		T7	52		T9	9

---

Summary for Cross msg_len_upper_cross

Samples crossed: hmac_en msg_len_upper_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	2	2	0	0.00	2

Automatically Generated Cross Bins for msg_len_upper_cross

Uncovered bins

hmac_en	msg_len_upper_cp	COUNT	AT LEAST	NUMBER	STATUS
*	*	--	--	2