Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::status_cg

Group : hmac_env_pkg::hmac_env_cov::status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	96	0	96	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	2
sta_fifo_depth	8	0	8	100.00	100	1	1	0
sta_fifo_empty	2	0	2	100.00	100	1	1	2
sta_fifo_full	2	0	2	100.00	100	1	1	2

Crosses for Group hmac_env_pkg::hmac_env_cov::status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
fifo_empty_cross	16	0	16	100.00	100	1	1	0
fifo_full_cross	16	0	16	100.00	100	1	1	0
fifo_depth_cross	64	0	64	100.00	100	1	1	0

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22656146

1

T2

148070

T3

705

T4

6066

auto[1]

2164641

1

T3

509

T4

6921

T7

17046

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2051821

1

T3

211

T4

5654

T7

25089

auto[1]

22768966

1

T2

148070

T3

1003

T4

7333

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20976601

1

T2

148070

T3

860

T4

6582

auto[1]

3844186

1

T3

354

T4

6405

T11

5206

---

Summary for Variable sta_fifo_depth

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for sta_fifo_depth

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	21486391	1			T2	141293		T3	1125		T4	12512
fifo_depth[1]	659225	1			T2	3555		T3	14		T4	235
fifo_depth[2]	504772	1			T2	1813		T3	11		T4	146
fifo_depth[3]	402318	1			T2	896		T3	17		T4	65
fifo_depth[4]	317876	1			T2	359		T3	9		T4	23
fifo_depth[5]	249694	1			T2	123		T3	9		T4	5
fifo_depth[6]	219136	1			T2	22		T3	11		T4	1
fifo_depth[7]	194530	1			T2	7		T3	5		T7	3254

---

Summary for Variable sta_fifo_empty

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_empty

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3334396

1

T2

6777

T3

89

T4

475

auto[1]

21486391

1

T2

141293

T3

1125

T4

12512

---

Summary for Variable sta_fifo_full

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_full

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24808533

1

T2

148070

T3

1214

T4

12987

auto[1]

12254

1

T7

132

T5

106

T80

343

---

Summary for Cross fifo_empty_cross

Samples crossed: sta_fifo_empty hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for fifo_empty_cross

Bins

sta_fifo_empty

hmac_en

endian_swap

digest_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

66672

1

T4

49

T7

2672

T16

44

auto[0]

auto[0]

auto[0]

auto[1]

58096

1

T3

15

T4

75

T7

2281

auto[0]

auto[0]

auto[1]

auto[0]

2511637

1

T2

6777

T4

17

T7

32350

auto[0]

auto[0]

auto[1]

auto[1]

76709

1

T3

74

T4

115

T7

1692

auto[0]

auto[1]

auto[0]

auto[0]

111335

1

T4

78

T7

2855

T5

421

auto[0]

auto[1]

auto[0]

auto[1]

126016

1

T4

37

T7

1175

T16

32

auto[0]

auto[1]

auto[1]

auto[0]

272769

1

T4

54

T11

196

T7

5476

auto[0]

auto[1]

auto[1]

auto[1]

111162

1

T4

50

T7

528

T5

2120

auto[1]

auto[0]

auto[0]

auto[0]

239414

1

T4

1696

T7

2845

T9

20

auto[1]

auto[0]

auto[0]

auto[1]

228269

1

T3

193

T4

1019

T7

2126

auto[1]

auto[0]

auto[1]

auto[0]

17539758

1

T2

141293

T3

356

T4

275

auto[1]

auto[0]

auto[1]

auto[1]

256046

1

T3

222

T4

3336

T7

4469

auto[1]

auto[1]

auto[0]

auto[0]

580505

1

T3

2

T4

1345

T7

9106

auto[1]

auto[1]

auto[0]

auto[1]

641514

1

T3

1

T4

1355

T7

2029

auto[1]

auto[1]

auto[1]

auto[0]

1334056

1

T3

347

T4

2552

T11

5010

auto[1]

auto[1]

auto[1]

auto[1]

666829

1

T3

4

T4

934

T7

2746

---

Summary for Cross fifo_full_cross

Samples crossed: sta_fifo_full hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for fifo_full_cross

Bins

sta_fifo_full

hmac_en

endian_swap

digest_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

303618

1

T4

1745

T7

5430

T9

20

auto[0]

auto[0]

auto[0]

auto[1]

283945

1

T3

208

T4

1094

T7

4379

auto[0]

auto[0]

auto[1]

auto[0]

20050921

1

T2

148070

T3

356

T4

292

auto[0]

auto[0]

auto[1]

auto[1]

331441

1

T3

296

T4

3451

T7

6146

auto[0]

auto[1]

auto[0]

auto[0]

690367

1

T3

2

T4

1423

T7

11959

auto[0]

auto[1]

auto[0]

auto[1]

765432

1

T3

1

T4

1392

T7

3204

auto[0]

auto[1]

auto[1]

auto[0]

1606181

1

T3

347

T4

2606

T11

5206

auto[0]

auto[1]

auto[1]

auto[1]

776628

1

T3

4

T4

984

T7

3274

auto[1]

auto[0]

auto[0]

auto[0]

2468

1

T7

87

T80

107

T18

284

auto[1]

auto[0]

auto[0]

auto[1]

2420

1

T7

28

T80

52

T18

179

auto[1]

auto[0]

auto[1]

auto[0]

474

1

T5

56

T80

53

T18

69

auto[1]

auto[0]

auto[1]

auto[1]

1314

1

T7

15

T80

54

T13

1

auto[1]

auto[1]

auto[0]

auto[0]

1473

1

T7

2

T5

3

T13

1

auto[1]

auto[1]

auto[0]

auto[1]

2098

1

T18

210

T25

1

T144

14

auto[1]

auto[1]

auto[1]

auto[0]

644

1

T18

54

T144

22

T145

5

auto[1]

auto[1]

auto[1]

auto[1]

1363

1

T5

47

T80

77

T18

27

---

Summary for Cross fifo_depth_cross

Samples crossed: sta_fifo_depth hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for fifo_depth_cross

Bins

sta_fifo_depth	hmac_en	endian_swap	digest_swap	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	auto[0]	auto[0]	auto[0]	239414	1			T4	1696		T7	2845		T9	20
fifo_depth[0]	auto[0]	auto[0]	auto[1]	228269	1			T3	193		T4	1019		T7	2126
fifo_depth[0]	auto[0]	auto[1]	auto[0]	17539758	1			T2	141293		T3	356		T4	275
fifo_depth[0]	auto[0]	auto[1]	auto[1]	256046	1			T3	222		T4	3336		T7	4469
fifo_depth[0]	auto[1]	auto[0]	auto[0]	580505	1			T3	2		T4	1345		T7	9106
fifo_depth[0]	auto[1]	auto[0]	auto[1]	641514	1			T3	1		T4	1355		T7	2029
fifo_depth[0]	auto[1]	auto[1]	auto[0]	1334056	1			T3	347		T4	2552		T11	5010
fifo_depth[0]	auto[1]	auto[1]	auto[1]	666829	1			T3	4		T4	934		T7	2746
fifo_depth[1]	auto[0]	auto[0]	auto[0]	6943	1			T4	28		T7	160		T16	14
fifo_depth[1]	auto[0]	auto[0]	auto[1]	5809	1			T3	4		T4	36		T7	93
fifo_depth[1]	auto[0]	auto[1]	auto[0]	565036	1			T2	3555		T4	11		T7	5102
fifo_depth[1]	auto[0]	auto[1]	auto[1]	6817	1			T3	10		T4	55		T7	127
fifo_depth[1]	auto[1]	auto[0]	auto[0]	9762	1			T4	39		T7	166		T5	1
fifo_depth[1]	auto[1]	auto[0]	auto[1]	11874	1			T4	23		T7	118		T16	4
fifo_depth[1]	auto[1]	auto[1]	auto[0]	41910	1			T4	20		T11	148		T7	753
fifo_depth[1]	auto[1]	auto[1]	auto[1]	11074	1			T4	23		T7	26		T16	32
fifo_depth[2]	auto[0]	auto[0]	auto[0]	6040	1			T4	14		T7	238		T16	12
fifo_depth[2]	auto[0]	auto[0]	auto[1]	5406	1			T3	1		T4	27		T7	112
fifo_depth[2]	auto[0]	auto[1]	auto[0]	422633	1			T2	1813		T4	5		T7	5005
fifo_depth[2]	auto[0]	auto[1]	auto[1]	6003	1			T3	10		T4	32		T7	151
fifo_depth[2]	auto[1]	auto[0]	auto[0]	9519	1			T4	25		T7	148		T5	4
fifo_depth[2]	auto[1]	auto[0]	auto[1]	11115	1			T4	8		T7	96		T16	15
fifo_depth[2]	auto[1]	auto[1]	auto[0]	33487	1			T4	22		T11	47		T7	739
fifo_depth[2]	auto[1]	auto[1]	auto[1]	10569	1			T4	13		T7	25		T5	3
fifo_depth[3]	auto[0]	auto[0]	auto[0]	4563	1			T4	5		T7	162		T16	6
fifo_depth[3]	auto[0]	auto[0]	auto[1]	4135	1			T3	9		T4	8		T7	111
fifo_depth[3]	auto[0]	auto[1]	auto[0]	333752	1			T2	896		T7	4600		T10	4622
fifo_depth[3]	auto[0]	auto[1]	auto[1]	4739	1			T3	8		T4	20		T7	136
fifo_depth[3]	auto[1]	auto[0]	auto[0]	8477	1			T4	11		T7	160		T14	38
fifo_depth[3]	auto[1]	auto[0]	auto[1]	9891	1			T4	4		T7	127		T16	7
fifo_depth[3]	auto[1]	auto[1]	auto[0]	27458	1			T4	8		T11	1		T7	659
fifo_depth[3]	auto[1]	auto[1]	auto[1]	9303	1			T4	9		T7	31		T5	40
fifo_depth[4]	auto[0]	auto[0]	auto[0]	4231	1			T4	2		T7	239		T16	6
fifo_depth[4]	auto[0]	auto[0]	auto[1]	3856	1			T3	1		T4	3		T7	98
fifo_depth[4]	auto[0]	auto[1]	auto[0]	253593	1			T2	359		T4	1		T7	3768
fifo_depth[4]	auto[0]	auto[1]	auto[1]	4711	1			T3	8		T4	6		T7	148
fifo_depth[4]	auto[1]	auto[0]	auto[0]	8791	1			T4	1		T7	223		T5	5
fifo_depth[4]	auto[1]	auto[0]	auto[1]	9454	1			T4	2		T7	110		T16	3
fifo_depth[4]	auto[1]	auto[1]	auto[0]	24022	1			T4	3		T7	649		T8	194
fifo_depth[4]	auto[1]	auto[1]	auto[1]	9218	1			T4	5		T7	24		T5	34
fifo_depth[5]	auto[0]	auto[0]	auto[0]	3151	1			T7	127		T16	4		T14	39
fifo_depth[5]	auto[0]	auto[0]	auto[1]	3178	1			T4	1		T7	89		T5	1
fifo_depth[5]	auto[0]	auto[1]	auto[0]	193557	1			T2	123		T7	2800		T10	3370
fifo_depth[5]	auto[0]	auto[1]	auto[1]	3664	1			T3	9		T4	1		T7	137
fifo_depth[5]	auto[1]	auto[0]	auto[0]	7951	1			T4	2		T7	190		T5	1
fifo_depth[5]	auto[1]	auto[0]	auto[1]	8879	1			T7	117		T16	3		T14	16
fifo_depth[5]	auto[1]	auto[1]	auto[0]	21001	1			T4	1		T7	571		T8	195
fifo_depth[5]	auto[1]	auto[1]	auto[1]	8313	1			T7	29		T5	41		T16	2
fifo_depth[6]	auto[0]	auto[0]	auto[0]	3090	1			T7	219		T16	2		T14	41
fifo_depth[6]	auto[0]	auto[0]	auto[1]	3112	1			T7	123		T16	1		T14	11
fifo_depth[6]	auto[0]	auto[1]	auto[0]	165343	1			T2	22		T7	2348		T10	3049
fifo_depth[6]	auto[0]	auto[1]	auto[1]	3628	1			T3	11		T4	1		T7	143
fifo_depth[6]	auto[1]	auto[0]	auto[0]	8267	1			T7	210		T5	6		T14	42
fifo_depth[6]	auto[1]	auto[0]	auto[1]	8913	1			T7	102		T14	15		T15	5
fifo_depth[6]	auto[1]	auto[1]	auto[0]	18622	1			T7	490		T8	159		T22	1
fifo_depth[6]	auto[1]	auto[1]	auto[1]	8161	1			T7	32		T5	9		T14	21
fifo_depth[7]	auto[0]	auto[0]	auto[0]	2952	1			T7	146		T14	39		T15	1
fifo_depth[7]	auto[0]	auto[0]	auto[1]	2825	1			T7	130		T14	15		T15	2
fifo_depth[7]	auto[0]	auto[1]	auto[0]	145219	1			T2	7		T7	2101		T10	2731
fifo_depth[7]	auto[0]	auto[1]	auto[1]	3216	1			T3	5		T7	113		T15	5
fifo_depth[7]	auto[1]	auto[0]	auto[0]	7817	1			T7	219		T14	36		T17	76
fifo_depth[7]	auto[1]	auto[0]	auto[1]	8531	1			T7	117		T14	20		T15	2
fifo_depth[7]	auto[1]	auto[1]	auto[0]	16324	1			T7	399		T8	139		T14	10
fifo_depth[7]	auto[1]	auto[1]	auto[1]	7646	1			T7	29		T5	41		T14	18