Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	46007913	1			T2	277758		T3	9681		T4	13102
all_pins[1]	46007913	1			T2	277758		T3	9681		T4	13102
all_pins[2]	46007913	1			T2	277758		T3	9681		T4	13102

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	114510848	1			T2	703587		T3	19878		T4	34103
values[0x1]	23512891	1			T2	129687		T3	9165		T4	5203
transitions[0x0=>0x1]	23512654	1			T2	129687		T3	9165		T4	5203
transitions[0x1=>0x0]	23512666	1			T2	129687		T3	9165		T4	5203

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	45902824	1			T2	277372		T3	9677		T4	13070
all_pins[0]	values[0x1]	105089	1			T2	386		T3	4		T4	32
all_pins[0]	transitions[0x0=>0x1]	105039	1			T2	386		T3	4		T4	32
all_pins[0]	transitions[0x1=>0x0]	23403484	1			T2	129301		T3	9161		T4	5171
all_pins[1]	values[0x0]	46003633	1			T2	277758		T3	9681		T4	13102
all_pins[1]	values[0x1]	4280	1			T7	9		T6	78		T80	7
all_pins[1]	transitions[0x0=>0x1]	4127	1			T7	8		T6	75		T80	7
all_pins[1]	transitions[0x1=>0x0]	104936	1			T2	386		T3	4		T4	32
all_pins[2]	values[0x0]	22604391	1			T2	148457		T3	520		T4	7931
all_pins[2]	values[0x1]	23403522	1			T2	129301		T3	9161		T4	5171
all_pins[2]	transitions[0x0=>0x1]	23403488	1			T2	129301		T3	9161		T4	5171
all_pins[2]	transitions[0x1=>0x0]	4246	1			T7	7		T6	78		T80	7