Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 0 18 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 0 18 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 623 1 T7 31 T48 7 T49 7
all_values[1] 623 1 T7 31 T48 7 T49 7
all_values[2] 623 1 T7 31 T48 7 T49 7


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 987 1 T7 43 T48 12 T49 10
auto[1] 882 1 T7 50 T48 9 T49 11


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 674 1 T7 23 T48 8 T49 5
auto[1] 1195 1 T7 70 T48 13 T49 16


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1095 1 T7 50 T48 12 T49 12
auto[1] 774 1 T7 43 T48 9 T49 9


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 0 18 100.00
Automatically Generated Cross Bins 18 0 18 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 130 1 T7 3 T48 1 T49 2
all_values[0] auto[0] auto[0] auto[1] 62 1 T7 2 T49 1 T136 2
all_values[0] auto[0] auto[1] auto[0] 120 1 T7 5 T48 2 T49 3
all_values[0] auto[0] auto[1] auto[1] 60 1 T7 5 T48 1 T18 5
all_values[0] auto[1] auto[0] auto[1] 121 1 T7 6 T49 1 T136 2
all_values[0] auto[1] auto[1] auto[1] 130 1 T7 10 T48 3 T18 3
all_values[1] auto[0] auto[0] auto[0] 109 1 T7 5 T48 3 T18 2
all_values[1] auto[0] auto[0] auto[1] 90 1 T7 5 T18 1 T136 2
all_values[1] auto[0] auto[1] auto[0] 86 1 T7 6 T48 1 T18 4
all_values[1] auto[0] auto[1] auto[1] 76 1 T7 4 T48 1 T49 3
all_values[1] auto[1] auto[0] auto[1] 151 1 T7 3 T48 2 T49 3
all_values[1] auto[1] auto[1] auto[1] 111 1 T7 8 T49 1 T136 3
all_values[2] auto[0] auto[0] auto[0] 122 1 T7 3 T48 1 T18 1
all_values[2] auto[0] auto[0] auto[1] 68 1 T7 7 T48 2 T125 4
all_values[2] auto[0] auto[1] auto[0] 107 1 T7 1 T18 5 T136 4
all_values[2] auto[0] auto[1] auto[1] 65 1 T7 4 T49 3 T18 1
all_values[2] auto[1] auto[0] auto[1] 134 1 T7 9 T48 3 T49 3
all_values[2] auto[1] auto[1] auto[1] 127 1 T7 7 T48 1 T49 1


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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