Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::cfg_cg

Group : hmac_env_pkg::hmac_env_cov::cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
76.47	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	2	18	90.00
Crosses	82	22	60	73.17

Variables for Group hmac_env_pkg::hmac_env_cov::cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_size	5	1	4	80.00	100	1	1	0
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	0
key_length	7	1	6	85.71	100	1	1	0
sha_en	2	0	2	100.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cfg_cross	8	0	8	100.00	100	1	1	0
hmac_dis_x_sha_en	4	0	4	100.00	100	1	1	0
key_x_digest_mismatch	35	11	24	68.57	100	1	1	0
key_length_x_digest_size	35	11	24	68.57	100	1	1	0

Summary for Variable digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	1	4	80.00

User Defined Bins for digest_size

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
sha2_invalid	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sha2_none	99	1			T7	2		T17	2		T84	1
sha2_512	41881	1			T3	1		T4	6		T11	225
sha2_384	38689	1			T2	386		T3	11		T4	11
sha2_256	22826	1			T3	2		T4	6		T7	304

---

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

99319

1

T2

386

T3

1

T4

8

auto[1]

4176

1

T3

13

T4

15

T7

52

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4056

1

T3

12

T4

14

T7

71

auto[1]

99439

1

T2

386

T3

2

T4

9

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

41458

1

T3

3

T4

8

T11

225

disabled

62037

1

T2

386

T3

11

T4

15

---

Summary for Variable key_length

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	1	6	85.71

User Defined Bins for key_length

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
key_invalid	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_none	59022	1			T2	386		T3	2		T4	5
key_1024	22523	1			T3	10		T4	4		T11	225
key_512	12192	1			T4	2		T7	108		T8	45
key_384	7036	1			T4	5		T7	204		T8	90
key_256	1400	1			T3	2		T4	5		T7	16
key_128	1322	1			T4	2		T7	22		T9	2

---

Summary for Variable sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

103254

1

T2

386

T3

10

T4

23

disabled

241

1

T3

4

T7

4

T17

10

---

Summary for Cross cfg_cross

Samples crossed: hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cfg_cross

Bins

hmac_en	endian_swap	digest_swap	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
enabled	auto[0]	auto[0]	907	1			T3	1		T4	1		T7	17
enabled	auto[0]	auto[1]	927	1			T3	1		T4	3		T7	11
enabled	auto[1]	auto[0]	38606	1			T4	1		T11	225		T7	504
enabled	auto[1]	auto[1]	1018	1			T3	1		T4	3		T7	5
disabled	auto[0]	auto[0]	1135	1			T4	4		T7	24		T16	2
disabled	auto[0]	auto[1]	1087	1			T3	10		T4	6		T7	19
disabled	auto[1]	auto[0]	58671	1			T2	386		T4	2		T7	397
disabled	auto[1]	auto[1]	1144	1			T3	1		T4	3		T7	17

---

Summary for Cross hmac_dis_x_sha_en

Samples crossed: hmac_en sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	3	0	3	100.00
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for hmac_dis_x_sha_en

Bins

hmac_en

sha_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

enabled

41327

1

T4

8

T11

225

T7

536

enabled

disabled

131

1

T3

3

T7

1

T17

4

disabled

disabled

110

1

T3

1

T7

3

T17

6

User Defined Cross Bins for hmac_dis_x_sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

61927

1

T2

386

T3

10

T4

15

---

Summary for Cross key_x_digest_mismatch

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	35	11	24	68.57	11
Automatically Generated Cross Bins	34	11	23	67.65	11
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for key_x_digest_mismatch

Element holes

key_length	digest_size	COUNT	AT LEAST	NUMBER	STATUS
[key_invalid]	*	--	--	5

Uncovered bins

key_length	digest_size	COUNT	AT LEAST	NUMBER	STATUS
[key_none , key_1024 , key_512 , key_384 , key_256 , key_128]	[sha2_invalid]	--	--	6

Covered bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_none	sha2_none	28	1			T17	1		T84	1		T33	2
key_none	sha2_512	22139	1			T7	395		T9	1		T17	9
key_none	sha2_384	24481	1			T2	386		T3	1		T4	3
key_none	sha2_256	12374	1			T3	1		T4	2		T7	8
key_1024	sha2_none	8	1			T49	2		T120	1		T121	1
key_1024	sha2_512	17891	1			T3	1		T4	1		T11	225
key_1024	sha2_384	4437	1			T3	9		T4	2		T7	7
key_512	sha2_none	21	1			T49	2		T18	1		T122	1
key_512	sha2_512	465	1			T7	9		T6	1		T15	2
key_512	sha2_384	8390	1			T4	1		T7	4		T15	2
key_512	sha2_256	3316	1			T4	1		T7	95		T8	45
key_384	sha2_none	13	1			T7	1		T48	1		T123	2
key_384	sha2_512	467	1			T4	3		T7	7		T9	1
key_384	sha2_384	500	1			T4	2		T7	12		T5	1
key_384	sha2_256	6056	1			T7	184		T8	90		T5	1
key_256	sha2_none	7	1			T120	1		T121	1		T65	1
key_256	sha2_512	458	1			T4	1		T7	5		T5	1
key_256	sha2_384	462	1			T3	1		T4	3		T7	3
key_256	sha2_256	473	1			T3	1		T4	1		T7	8
key_128	sha2_none	22	1			T7	1		T17	1		T124	1
key_128	sha2_512	461	1			T4	1		T7	12		T5	1
key_128	sha2_384	419	1			T7	2		T9	1		T5	1
key_128	sha2_256	420	1			T4	1		T7	7		T9	1

User Defined Cross Bins for key_x_digest_mismatch

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

187

1

T4

1

T7

2

T9

1

---

Summary for Cross key_length_x_digest_size

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	35	11	24	68.57	11

Automatically Generated Cross Bins for key_length_x_digest_size

Element holes

key_length	digest_size	COUNT	AT LEAST	NUMBER	STATUS
[key_invalid]	*	--	--	5

Uncovered bins

key_length	digest_size	COUNT	AT LEAST	NUMBER	STATUS
[key_none , key_1024 , key_512 , key_384 , key_256 , key_128]	[sha2_invalid]	--	--	6

Covered bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_none	sha2_none	28	1			T17	1		T84	1		T33	2
key_none	sha2_512	22139	1			T7	395		T9	1		T17	9
key_none	sha2_384	24481	1			T2	386		T3	1		T4	3
key_none	sha2_256	12374	1			T3	1		T4	2		T7	8
key_1024	sha2_none	8	1			T49	2		T120	1		T121	1
key_1024	sha2_512	17891	1			T3	1		T4	1		T11	225
key_1024	sha2_384	4437	1			T3	9		T4	2		T7	7
key_1024	sha2_256	187	1			T4	1		T7	2		T9	1
key_512	sha2_none	21	1			T49	2		T18	1		T122	1
key_512	sha2_512	465	1			T7	9		T6	1		T15	2
key_512	sha2_384	8390	1			T4	1		T7	4		T15	2
key_512	sha2_256	3316	1			T4	1		T7	95		T8	45
key_384	sha2_none	13	1			T7	1		T48	1		T123	2
key_384	sha2_512	467	1			T4	3		T7	7		T9	1
key_384	sha2_384	500	1			T4	2		T7	12		T5	1
key_384	sha2_256	6056	1			T7	184		T8	90		T5	1
key_256	sha2_none	7	1			T120	1		T121	1		T65	1
key_256	sha2_512	458	1			T4	1		T7	5		T5	1
key_256	sha2_384	462	1			T3	1		T4	3		T7	3
key_256	sha2_256	473	1			T3	1		T4	1		T7	8
key_128	sha2_none	22	1			T7	1		T17	1		T124	1
key_128	sha2_512	461	1			T4	1		T7	12		T5	1
key_128	sha2_384	419	1			T7	2		T9	1		T5	1
key_128	sha2_256	420	1			T4	1		T7	7		T9	1