Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
93.23 95.94 94.18 100.00 76.92 92.33 99.49 93.75


Total test records in report: 911
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T796 /workspace/coverage/cover_reg_top/4.hmac_intr_test.2365401323 Jun 30 06:27:08 PM PDT 24 Jun 30 06:27:12 PM PDT 24 83303802 ps
T797 /workspace/coverage/cover_reg_top/39.hmac_intr_test.3664776788 Jun 30 06:27:12 PM PDT 24 Jun 30 06:27:15 PM PDT 24 49174692 ps
T40 /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.4150077694 Jun 30 06:27:11 PM PDT 24 Jun 30 06:27:15 PM PDT 24 56374429 ps
T798 /workspace/coverage/cover_reg_top/15.hmac_csr_rw.1053219250 Jun 30 06:27:11 PM PDT 24 Jun 30 06:27:14 PM PDT 24 56767498 ps
T41 /workspace/coverage/cover_reg_top/15.hmac_tl_errors.4268001271 Jun 30 06:27:14 PM PDT 24 Jun 30 06:27:26 PM PDT 24 83918099 ps
T42 /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.2138164189 Jun 30 06:27:18 PM PDT 24 Jun 30 06:27:26 PM PDT 24 163270353 ps
T43 /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.2190559370 Jun 30 06:27:22 PM PDT 24 Jun 30 06:27:30 PM PDT 24 1187086934 ps
T54 /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.2501867329 Jun 30 06:27:22 PM PDT 24 Jun 30 06:27:31 PM PDT 24 1129435656 ps
T44 /workspace/coverage/cover_reg_top/0.hmac_tl_errors.672874443 Jun 30 06:27:07 PM PDT 24 Jun 30 06:27:12 PM PDT 24 477519539 ps
T799 /workspace/coverage/cover_reg_top/47.hmac_intr_test.2980397971 Jun 30 06:27:44 PM PDT 24 Jun 30 06:27:45 PM PDT 24 121081359 ps
T800 /workspace/coverage/cover_reg_top/44.hmac_intr_test.3099609631 Jun 30 06:27:14 PM PDT 24 Jun 30 06:27:17 PM PDT 24 30792596 ps
T801 /workspace/coverage/cover_reg_top/40.hmac_intr_test.3554837508 Jun 30 06:27:18 PM PDT 24 Jun 30 06:27:23 PM PDT 24 31386809 ps
T53 /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.314495147 Jun 30 06:27:16 PM PDT 24 Jun 30 06:27:23 PM PDT 24 311794787 ps
T68 /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.3869145538 Jun 30 06:27:12 PM PDT 24 Jun 30 06:27:15 PM PDT 24 109829171 ps
T106 /workspace/coverage/cover_reg_top/18.hmac_csr_rw.30414318 Jun 30 06:27:15 PM PDT 24 Jun 30 06:27:24 PM PDT 24 37470254 ps
T69 /workspace/coverage/cover_reg_top/13.hmac_csr_rw.3063907546 Jun 30 06:27:16 PM PDT 24 Jun 30 06:27:20 PM PDT 24 59717227 ps
T107 /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.2358643288 Jun 30 06:27:06 PM PDT 24 Jun 30 06:27:11 PM PDT 24 265337195 ps
T45 /workspace/coverage/cover_reg_top/17.hmac_tl_errors.1233508295 Jun 30 06:27:18 PM PDT 24 Jun 30 06:27:25 PM PDT 24 358404612 ps
T51 /workspace/coverage/cover_reg_top/16.hmac_tl_errors.3050214551 Jun 30 06:27:09 PM PDT 24 Jun 30 06:27:13 PM PDT 24 40769712 ps
T108 /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.2328006437 Jun 30 06:27:07 PM PDT 24 Jun 30 06:27:12 PM PDT 24 1037402648 ps
T802 /workspace/coverage/cover_reg_top/23.hmac_intr_test.2008352385 Jun 30 06:27:12 PM PDT 24 Jun 30 06:27:16 PM PDT 24 44415260 ps
T79 /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.1726236039 Jun 30 06:27:13 PM PDT 24 Jun 30 06:27:19 PM PDT 24 824433665 ps
T50 /workspace/coverage/cover_reg_top/1.hmac_tl_errors.2122892718 Jun 30 06:27:05 PM PDT 24 Jun 30 06:27:09 PM PDT 24 35991056 ps
T109 /workspace/coverage/cover_reg_top/19.hmac_csr_rw.1981174051 Jun 30 06:27:16 PM PDT 24 Jun 30 06:27:25 PM PDT 24 184979039 ps
T90 /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.1111704928 Jun 30 06:27:10 PM PDT 24 Jun 30 06:27:22 PM PDT 24 220775811 ps
T803 /workspace/coverage/cover_reg_top/1.hmac_intr_test.1742127168 Jun 30 06:27:18 PM PDT 24 Jun 30 06:27:22 PM PDT 24 14255517 ps
T804 /workspace/coverage/cover_reg_top/17.hmac_csr_rw.85877809 Jun 30 06:27:21 PM PDT 24 Jun 30 06:27:26 PM PDT 24 105101931 ps
T805 /workspace/coverage/cover_reg_top/15.hmac_intr_test.2061398471 Jun 30 06:27:08 PM PDT 24 Jun 30 06:27:11 PM PDT 24 14581044 ps
T806 /workspace/coverage/cover_reg_top/13.hmac_tl_errors.3616554686 Jun 30 06:27:21 PM PDT 24 Jun 30 06:27:28 PM PDT 24 76364623 ps
T807 /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.2546733735 Jun 30 06:27:05 PM PDT 24 Jun 30 06:27:21 PM PDT 24 361743469 ps
T808 /workspace/coverage/cover_reg_top/46.hmac_intr_test.1364409847 Jun 30 06:27:16 PM PDT 24 Jun 30 06:27:20 PM PDT 24 12959775 ps
T139 /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.3872209963 Jun 30 06:27:07 PM PDT 24 Jun 30 06:27:14 PM PDT 24 268600092 ps
T809 /workspace/coverage/cover_reg_top/26.hmac_intr_test.124195585 Jun 30 06:27:19 PM PDT 24 Jun 30 06:27:24 PM PDT 24 140625580 ps
T810 /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.660767621 Jun 30 06:27:15 PM PDT 24 Jun 30 06:27:21 PM PDT 24 84460006 ps
T811 /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.3171895218 Jun 30 06:27:19 PM PDT 24 Jun 30 06:27:25 PM PDT 24 38862088 ps
T52 /workspace/coverage/cover_reg_top/8.hmac_tl_errors.2445308780 Jun 30 06:27:10 PM PDT 24 Jun 30 06:27:16 PM PDT 24 241502656 ps
T812 /workspace/coverage/cover_reg_top/4.hmac_tl_errors.743297009 Jun 30 06:27:08 PM PDT 24 Jun 30 06:27:14 PM PDT 24 2240228108 ps
T813 /workspace/coverage/cover_reg_top/19.hmac_intr_test.55139678 Jun 30 06:27:13 PM PDT 24 Jun 30 06:27:17 PM PDT 24 11908609 ps
T46 /workspace/coverage/cover_reg_top/10.hmac_tl_errors.1380837029 Jun 30 06:27:08 PM PDT 24 Jun 30 06:27:13 PM PDT 24 59956298 ps
T140 /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.1584941660 Jun 30 06:27:21 PM PDT 24 Jun 30 06:27:28 PM PDT 24 674280836 ps
T814 /workspace/coverage/cover_reg_top/31.hmac_intr_test.3865240153 Jun 30 06:27:19 PM PDT 24 Jun 30 06:27:24 PM PDT 24 36729480 ps
T815 /workspace/coverage/cover_reg_top/14.hmac_tl_errors.2314130502 Jun 30 06:27:19 PM PDT 24 Jun 30 06:27:26 PM PDT 24 472078581 ps
T47 /workspace/coverage/cover_reg_top/7.hmac_tl_errors.2935926496 Jun 30 06:27:12 PM PDT 24 Jun 30 06:27:19 PM PDT 24 2543629564 ps
T816 /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.4117737901 Jun 30 06:27:16 PM PDT 24 Jun 30 06:27:21 PM PDT 24 41088981 ps
T817 /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.346034588 Jun 30 06:27:19 PM PDT 24 Jun 30 06:27:24 PM PDT 24 60306750 ps
T110 /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.3801230821 Jun 30 06:27:09 PM PDT 24 Jun 30 06:27:13 PM PDT 24 103103799 ps
T818 /workspace/coverage/cover_reg_top/3.hmac_intr_test.4130046833 Jun 30 06:27:01 PM PDT 24 Jun 30 06:27:02 PM PDT 24 21234777 ps
T819 /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.4014021935 Jun 30 06:27:13 PM PDT 24 Jun 30 06:27:18 PM PDT 24 238735273 ps
T820 /workspace/coverage/cover_reg_top/12.hmac_tl_errors.1603954674 Jun 30 06:27:16 PM PDT 24 Jun 30 06:27:23 PM PDT 24 208685238 ps
T821 /workspace/coverage/cover_reg_top/5.hmac_tl_errors.4257598286 Jun 30 06:27:06 PM PDT 24 Jun 30 06:27:10 PM PDT 24 152478741 ps
T822 /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.151381535 Jun 30 06:27:12 PM PDT 24 Jun 30 06:27:18 PM PDT 24 85564055 ps
T111 /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.2621609706 Jun 30 06:27:20 PM PDT 24 Jun 30 06:27:26 PM PDT 24 55228406 ps
T823 /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.459639917 Jun 30 06:27:13 PM PDT 24 Jun 30 06:27:17 PM PDT 24 171110907 ps
T824 /workspace/coverage/cover_reg_top/10.hmac_intr_test.3764619360 Jun 30 06:27:16 PM PDT 24 Jun 30 06:27:20 PM PDT 24 17342467 ps
T112 /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.4200090754 Jun 30 06:27:19 PM PDT 24 Jun 30 06:27:26 PM PDT 24 553851934 ps
T825 /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.407773850 Jun 30 06:27:20 PM PDT 24 Jun 30 06:45:00 PM PDT 24 227957697848 ps
T826 /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.3979784170 Jun 30 06:27:16 PM PDT 24 Jun 30 06:27:21 PM PDT 24 83884546 ps
T827 /workspace/coverage/cover_reg_top/27.hmac_intr_test.1621999391 Jun 30 06:27:20 PM PDT 24 Jun 30 06:27:25 PM PDT 24 20300947 ps
T828 /workspace/coverage/cover_reg_top/24.hmac_intr_test.283831281 Jun 30 06:27:18 PM PDT 24 Jun 30 06:27:23 PM PDT 24 14842079 ps
T91 /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.3262879443 Jun 30 06:27:12 PM PDT 24 Jun 30 06:27:18 PM PDT 24 62652447 ps
T99 /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.554976710 Jun 30 06:27:06 PM PDT 24 Jun 30 06:27:14 PM PDT 24 535105168 ps
T92 /workspace/coverage/cover_reg_top/6.hmac_csr_rw.1293350839 Jun 30 06:27:12 PM PDT 24 Jun 30 06:27:16 PM PDT 24 33382402 ps
T829 /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.395792566 Jun 30 06:27:17 PM PDT 24 Jun 30 06:27:22 PM PDT 24 37635298 ps
T113 /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.2538524642 Jun 30 06:27:20 PM PDT 24 Jun 30 06:27:26 PM PDT 24 361976803 ps
T830 /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.3964058121 Jun 30 06:27:18 PM PDT 24 Jun 30 06:27:24 PM PDT 24 48514401 ps
T831 /workspace/coverage/cover_reg_top/7.hmac_csr_rw.1762013316 Jun 30 06:27:09 PM PDT 24 Jun 30 06:27:12 PM PDT 24 41143517 ps
T137 /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.2893628580 Jun 30 06:27:18 PM PDT 24 Jun 30 06:27:26 PM PDT 24 229332791 ps
T832 /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.2371618550 Jun 30 06:27:14 PM PDT 24 Jun 30 06:27:17 PM PDT 24 154058315 ps
T142 /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.3735378292 Jun 30 06:27:17 PM PDT 24 Jun 30 06:27:25 PM PDT 24 430334033 ps
T833 /workspace/coverage/cover_reg_top/11.hmac_intr_test.920263083 Jun 30 06:27:16 PM PDT 24 Jun 30 06:27:20 PM PDT 24 58896363 ps
T100 /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.4106479923 Jun 30 06:27:22 PM PDT 24 Jun 30 06:27:37 PM PDT 24 1830875024 ps
T834 /workspace/coverage/cover_reg_top/34.hmac_intr_test.1947347199 Jun 30 06:27:18 PM PDT 24 Jun 30 06:27:22 PM PDT 24 13256429 ps
T835 /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.3327952327 Jun 30 06:27:21 PM PDT 24 Jun 30 06:27:27 PM PDT 24 360510574 ps
T836 /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.2662027124 Jun 30 06:27:17 PM PDT 24 Jun 30 06:27:22 PM PDT 24 35451866 ps
T837 /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.4234796090 Jun 30 06:27:12 PM PDT 24 Jun 30 06:27:17 PM PDT 24 39047535 ps
T838 /workspace/coverage/cover_reg_top/9.hmac_intr_test.2956243326 Jun 30 06:27:17 PM PDT 24 Jun 30 06:27:21 PM PDT 24 41989889 ps
T839 /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.57490795 Jun 30 06:27:25 PM PDT 24 Jun 30 06:27:29 PM PDT 24 409599915 ps
T840 /workspace/coverage/cover_reg_top/8.hmac_intr_test.701741535 Jun 30 06:27:07 PM PDT 24 Jun 30 06:27:10 PM PDT 24 12895844 ps
T841 /workspace/coverage/cover_reg_top/6.hmac_intr_test.1718278495 Jun 30 06:27:03 PM PDT 24 Jun 30 06:27:05 PM PDT 24 15152882 ps
T842 /workspace/coverage/cover_reg_top/14.hmac_csr_rw.805552226 Jun 30 06:27:28 PM PDT 24 Jun 30 06:27:30 PM PDT 24 29450476 ps
T843 /workspace/coverage/cover_reg_top/43.hmac_intr_test.2300062048 Jun 30 06:27:17 PM PDT 24 Jun 30 06:27:21 PM PDT 24 33880615 ps
T844 /workspace/coverage/cover_reg_top/18.hmac_intr_test.1491848769 Jun 30 06:27:11 PM PDT 24 Jun 30 06:27:14 PM PDT 24 17274479 ps
T845 /workspace/coverage/cover_reg_top/0.hmac_csr_rw.3682837303 Jun 30 06:26:57 PM PDT 24 Jun 30 06:26:58 PM PDT 24 14703661 ps
T846 /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.1410791822 Jun 30 06:27:12 PM PDT 24 Jun 30 06:27:17 PM PDT 24 55475309 ps
T847 /workspace/coverage/cover_reg_top/10.hmac_csr_rw.3671651298 Jun 30 06:27:06 PM PDT 24 Jun 30 06:27:10 PM PDT 24 90984928 ps
T848 /workspace/coverage/cover_reg_top/37.hmac_intr_test.860327696 Jun 30 06:27:18 PM PDT 24 Jun 30 06:27:22 PM PDT 24 20442414 ps
T141 /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.2982300369 Jun 30 06:27:15 PM PDT 24 Jun 30 06:27:22 PM PDT 24 362604256 ps
T849 /workspace/coverage/cover_reg_top/33.hmac_intr_test.3818408765 Jun 30 06:27:18 PM PDT 24 Jun 30 06:27:23 PM PDT 24 17863576 ps
T93 /workspace/coverage/cover_reg_top/12.hmac_csr_rw.3092110656 Jun 30 06:27:26 PM PDT 24 Jun 30 06:27:28 PM PDT 24 24149191 ps
T850 /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.106778643 Jun 30 06:27:13 PM PDT 24 Jun 30 06:27:18 PM PDT 24 112128484 ps
T101 /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.2210578024 Jun 30 06:26:55 PM PDT 24 Jun 30 06:27:11 PM PDT 24 322882263 ps
T851 /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.1747665730 Jun 30 06:27:24 PM PDT 24 Jun 30 06:27:29 PM PDT 24 440418876 ps
T852 /workspace/coverage/cover_reg_top/16.hmac_intr_test.1706523797 Jun 30 06:27:15 PM PDT 24 Jun 30 06:27:19 PM PDT 24 15741993 ps
T853 /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.2959949897 Jun 30 06:27:20 PM PDT 24 Jun 30 06:27:26 PM PDT 24 102924657 ps
T94 /workspace/coverage/cover_reg_top/2.hmac_csr_rw.1260701130 Jun 30 06:27:13 PM PDT 24 Jun 30 06:27:17 PM PDT 24 30973452 ps
T854 /workspace/coverage/cover_reg_top/25.hmac_intr_test.3092135247 Jun 30 06:27:18 PM PDT 24 Jun 30 06:27:22 PM PDT 24 46158023 ps
T855 /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.2659957244 Jun 30 06:27:05 PM PDT 24 Jun 30 06:27:10 PM PDT 24 611406377 ps
T856 /workspace/coverage/cover_reg_top/36.hmac_intr_test.1437866699 Jun 30 06:27:21 PM PDT 24 Jun 30 06:27:26 PM PDT 24 23170508 ps
T857 /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.481290560 Jun 30 06:27:00 PM PDT 24 Jun 30 06:27:03 PM PDT 24 444634462 ps
T858 /workspace/coverage/cover_reg_top/13.hmac_intr_test.3550580436 Jun 30 06:27:22 PM PDT 24 Jun 30 06:27:26 PM PDT 24 11528479 ps
T859 /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.4090239849 Jun 30 06:27:11 PM PDT 24 Jun 30 06:27:15 PM PDT 24 286534677 ps
T860 /workspace/coverage/cover_reg_top/2.hmac_intr_test.574773783 Jun 30 06:26:58 PM PDT 24 Jun 30 06:27:00 PM PDT 24 45407494 ps
T861 /workspace/coverage/cover_reg_top/11.hmac_tl_errors.1550571953 Jun 30 06:27:19 PM PDT 24 Jun 30 06:27:24 PM PDT 24 181268708 ps
T862 /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.3024949888 Jun 30 06:27:15 PM PDT 24 Jun 30 06:27:21 PM PDT 24 621079482 ps
T863 /workspace/coverage/cover_reg_top/42.hmac_intr_test.290389649 Jun 30 06:27:13 PM PDT 24 Jun 30 06:27:16 PM PDT 24 79071053 ps
T864 /workspace/coverage/cover_reg_top/7.hmac_intr_test.1333852344 Jun 30 06:27:10 PM PDT 24 Jun 30 06:27:13 PM PDT 24 15252957 ps
T865 /workspace/coverage/cover_reg_top/3.hmac_tl_errors.2080620358 Jun 30 06:27:18 PM PDT 24 Jun 30 06:27:24 PM PDT 24 731788782 ps
T866 /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.515010698 Jun 30 06:27:11 PM PDT 24 Jun 30 06:27:16 PM PDT 24 198474554 ps
T95 /workspace/coverage/cover_reg_top/5.hmac_csr_rw.1004079203 Jun 30 06:27:05 PM PDT 24 Jun 30 06:27:08 PM PDT 24 30494640 ps
T867 /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.3860368339 Jun 30 06:27:02 PM PDT 24 Jun 30 06:27:03 PM PDT 24 21043679 ps
T868 /workspace/coverage/cover_reg_top/6.hmac_tl_errors.3292948031 Jun 30 06:27:07 PM PDT 24 Jun 30 06:27:11 PM PDT 24 112636854 ps
T869 /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.672214808 Jun 30 06:27:03 PM PDT 24 Jun 30 06:27:11 PM PDT 24 388263643 ps
T870 /workspace/coverage/cover_reg_top/8.hmac_csr_rw.2523991489 Jun 30 06:27:03 PM PDT 24 Jun 30 06:27:05 PM PDT 24 30732923 ps
T871 /workspace/coverage/cover_reg_top/35.hmac_intr_test.892299998 Jun 30 06:27:23 PM PDT 24 Jun 30 06:27:27 PM PDT 24 20327662 ps
T872 /workspace/coverage/cover_reg_top/28.hmac_intr_test.3062336243 Jun 30 06:27:08 PM PDT 24 Jun 30 06:27:11 PM PDT 24 12297222 ps
T873 /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.4174472330 Jun 30 06:27:07 PM PDT 24 Jun 30 06:27:12 PM PDT 24 142727141 ps
T874 /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.357976034 Jun 30 06:27:12 PM PDT 24 Jun 30 06:27:15 PM PDT 24 67684265 ps
T875 /workspace/coverage/cover_reg_top/20.hmac_intr_test.877359113 Jun 30 06:27:17 PM PDT 24 Jun 30 06:27:21 PM PDT 24 28443985 ps
T876 /workspace/coverage/cover_reg_top/17.hmac_intr_test.2643352695 Jun 30 06:27:13 PM PDT 24 Jun 30 06:27:16 PM PDT 24 17572109 ps
T877 /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.2393888901 Jun 30 06:27:24 PM PDT 24 Jun 30 06:27:28 PM PDT 24 49822850 ps
T878 /workspace/coverage/cover_reg_top/41.hmac_intr_test.1347943421 Jun 30 06:27:11 PM PDT 24 Jun 30 06:27:14 PM PDT 24 17906375 ps
T879 /workspace/coverage/cover_reg_top/1.hmac_csr_rw.1156429905 Jun 30 06:27:14 PM PDT 24 Jun 30 06:27:17 PM PDT 24 52214706 ps
T880 /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.1524274607 Jun 30 06:27:06 PM PDT 24 Jun 30 06:27:12 PM PDT 24 410409060 ps
T881 /workspace/coverage/cover_reg_top/19.hmac_tl_errors.156504960 Jun 30 06:27:16 PM PDT 24 Jun 30 06:27:24 PM PDT 24 266289121 ps
T882 /workspace/coverage/cover_reg_top/38.hmac_intr_test.2546435880 Jun 30 06:27:12 PM PDT 24 Jun 30 06:27:15 PM PDT 24 30662588 ps
T883 /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.1693072263 Jun 30 06:27:22 PM PDT 24 Jun 30 06:27:27 PM PDT 24 93823793 ps
T884 /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.176129505 Jun 30 06:27:20 PM PDT 24 Jun 30 06:27:25 PM PDT 24 316715276 ps
T885 /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.624515190 Jun 30 06:27:20 PM PDT 24 Jun 30 06:27:26 PM PDT 24 326197789 ps
T886 /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.3276904664 Jun 30 06:27:03 PM PDT 24 Jun 30 06:27:06 PM PDT 24 49425981 ps
T887 /workspace/coverage/cover_reg_top/0.hmac_intr_test.2600407807 Jun 30 06:27:12 PM PDT 24 Jun 30 06:27:16 PM PDT 24 49278708 ps
T888 /workspace/coverage/cover_reg_top/5.hmac_intr_test.1735090233 Jun 30 06:27:21 PM PDT 24 Jun 30 06:27:26 PM PDT 24 56743496 ps
T889 /workspace/coverage/cover_reg_top/49.hmac_intr_test.2949884335 Jun 30 06:27:31 PM PDT 24 Jun 30 06:27:31 PM PDT 24 16273504 ps
T890 /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.3119811843 Jun 30 06:27:09 PM PDT 24 Jun 30 06:27:13 PM PDT 24 193242878 ps
T891 /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.2088537549 Jun 30 06:27:19 PM PDT 24 Jun 30 06:27:26 PM PDT 24 159745854 ps
T892 /workspace/coverage/cover_reg_top/32.hmac_intr_test.2847190052 Jun 30 06:27:21 PM PDT 24 Jun 30 06:27:25 PM PDT 24 22621317 ps
T893 /workspace/coverage/cover_reg_top/2.hmac_tl_errors.2320284241 Jun 30 06:27:18 PM PDT 24 Jun 30 06:27:25 PM PDT 24 157844703 ps
T894 /workspace/coverage/cover_reg_top/9.hmac_csr_rw.1659705558 Jun 30 06:27:05 PM PDT 24 Jun 30 06:27:09 PM PDT 24 16572391 ps
T138 /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.1920429821 Jun 30 06:27:15 PM PDT 24 Jun 30 06:27:20 PM PDT 24 154505550 ps
T895 /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.3457626358 Jun 30 06:27:19 PM PDT 24 Jun 30 06:27:29 PM PDT 24 360697009 ps
T96 /workspace/coverage/cover_reg_top/4.hmac_csr_rw.2517340483 Jun 30 06:27:09 PM PDT 24 Jun 30 06:27:13 PM PDT 24 313266772 ps
T896 /workspace/coverage/cover_reg_top/30.hmac_intr_test.2016124948 Jun 30 06:27:20 PM PDT 24 Jun 30 06:27:25 PM PDT 24 13968094 ps
T97 /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.3964423846 Jun 30 06:27:04 PM PDT 24 Jun 30 06:27:07 PM PDT 24 20795747 ps
T897 /workspace/coverage/cover_reg_top/9.hmac_tl_errors.2091596880 Jun 30 06:27:18 PM PDT 24 Jun 30 06:27:24 PM PDT 24 361775079 ps
T98 /workspace/coverage/cover_reg_top/3.hmac_csr_rw.1109676463 Jun 30 06:27:17 PM PDT 24 Jun 30 06:27:22 PM PDT 24 17417051 ps
T102 /workspace/coverage/cover_reg_top/11.hmac_csr_rw.159766078 Jun 30 06:27:20 PM PDT 24 Jun 30 06:27:25 PM PDT 24 14803331 ps
T898 /workspace/coverage/cover_reg_top/12.hmac_intr_test.766087960 Jun 30 06:27:15 PM PDT 24 Jun 30 06:27:18 PM PDT 24 11202888 ps
T899 /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.1041146273 Jun 30 06:27:17 PM PDT 24 Jun 30 06:27:23 PM PDT 24 63938581 ps
T900 /workspace/coverage/cover_reg_top/14.hmac_intr_test.1671285372 Jun 30 06:27:27 PM PDT 24 Jun 30 06:27:29 PM PDT 24 15180508 ps
T901 /workspace/coverage/cover_reg_top/29.hmac_intr_test.3777245029 Jun 30 06:27:10 PM PDT 24 Jun 30 06:27:13 PM PDT 24 40079613 ps
T902 /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.3793295799 Jun 30 06:27:12 PM PDT 24 Jun 30 06:38:37 PM PDT 24 248311634818 ps
T903 /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.1230914044 Jun 30 06:27:05 PM PDT 24 Jun 30 06:27:10 PM PDT 24 43561069 ps
T904 /workspace/coverage/cover_reg_top/18.hmac_tl_errors.458838905 Jun 30 06:27:13 PM PDT 24 Jun 30 06:27:18 PM PDT 24 71440320 ps
T905 /workspace/coverage/cover_reg_top/21.hmac_intr_test.3488948690 Jun 30 06:27:15 PM PDT 24 Jun 30 06:27:19 PM PDT 24 56512519 ps
T906 /workspace/coverage/cover_reg_top/45.hmac_intr_test.3792927347 Jun 30 06:27:22 PM PDT 24 Jun 30 06:27:26 PM PDT 24 11671198 ps
T103 /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.2577226144 Jun 30 06:27:18 PM PDT 24 Jun 30 06:27:25 PM PDT 24 271730857 ps
T104 /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.1697448451 Jun 30 06:27:06 PM PDT 24 Jun 30 06:27:10 PM PDT 24 84333376 ps
T907 /workspace/coverage/cover_reg_top/16.hmac_csr_rw.4078566024 Jun 30 06:27:16 PM PDT 24 Jun 30 06:27:20 PM PDT 24 24606578 ps
T908 /workspace/coverage/cover_reg_top/22.hmac_intr_test.949911666 Jun 30 06:27:19 PM PDT 24 Jun 30 06:27:24 PM PDT 24 12510683 ps
T909 /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.4116130428 Jun 30 06:27:11 PM PDT 24 Jun 30 06:27:15 PM PDT 24 102533091 ps
T910 /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.2059521695 Jun 30 06:27:18 PM PDT 24 Jun 30 06:27:28 PM PDT 24 188011793 ps
T911 /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.982595249 Jun 30 06:27:10 PM PDT 24 Jun 30 06:27:16 PM PDT 24 265912360 ps

Test location /workspace/coverage/default/10.hmac_long_msg.337694338
Short name T4
Test name
Test status
Simulation time 6523286887 ps
CPU time 94.02 seconds
Started Jun 30 06:34:28 PM PDT 24
Finished Jun 30 06:36:03 PM PDT 24
Peak memory 200332 kb
Host smart-2251479d-a2c5-428e-af73-9484db675f7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337694338 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_long_msg.337694338
Directory /workspace/10.hmac_long_msg/latest

Test location /workspace/coverage/default/3.hmac_stress_all_with_rand_reset.3465176523
Short name T18
Test name
Test status
Simulation time 51519409883 ps
CPU time 1358.56 seconds
Started Jun 30 06:34:17 PM PDT 24
Finished Jun 30 06:56:56 PM PDT 24
Peak memory 216876 kb
Host smart-38627ce9-fea1-4201-bc9f-559c060a1c7e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3465176523 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all_with_rand_reset.3465176523
Directory /workspace/3.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.hmac_stress_all.3450501071
Short name T7
Test name
Test status
Simulation time 272958869956 ps
CPU time 2589.12 seconds
Started Jun 30 06:37:22 PM PDT 24
Finished Jun 30 07:20:32 PM PDT 24
Peak memory 629564 kb
Host smart-fcdfd79a-bc31-430c-b03e-3189893c6728
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450501071 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.hmac_stress_all.3450501071
Directory /workspace/41.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.2501867329
Short name T54
Test name
Test status
Simulation time 1129435656 ps
CPU time 4.73 seconds
Started Jun 30 06:27:22 PM PDT 24
Finished Jun 30 06:27:31 PM PDT 24
Peak memory 199920 kb
Host smart-ff3f09a3-2e75-493f-ab5c-1317b75701f9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501867329 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_intg_err.2501867329
Directory /workspace/15.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/4.hmac_sec_cm.3525527620
Short name T20
Test name
Test status
Simulation time 80566938 ps
CPU time 1 seconds
Started Jun 30 06:34:21 PM PDT 24
Finished Jun 30 06:34:22 PM PDT 24
Peak memory 219772 kb
Host smart-33d3d3fa-d5ff-479a-b12e-98da02a899e0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525527620 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_sec_cm.3525527620
Directory /workspace/4.hmac_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.1111704928
Short name T90
Test name
Test status
Simulation time 220775811 ps
CPU time 9.73 seconds
Started Jun 30 06:27:10 PM PDT 24
Finished Jun 30 06:27:22 PM PDT 24
Peak memory 199796 kb
Host smart-b05df527-f4e4-4cdb-a5a7-5c419530738a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111704928 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_bit_bash.1111704928
Directory /workspace/1.hmac_csr_bit_bash/latest

Test location /workspace/coverage/default/10.hmac_back_pressure.649198883
Short name T27
Test name
Test status
Simulation time 2170801235 ps
CPU time 52.57 seconds
Started Jun 30 06:34:31 PM PDT 24
Finished Jun 30 06:35:24 PM PDT 24
Peak memory 200348 kb
Host smart-b2c19ea2-02e2-49ab-9b47-56865f200ead
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=649198883 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_back_pressure.649198883
Directory /workspace/10.hmac_back_pressure/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.2893628580
Short name T137
Test name
Test status
Simulation time 229332791 ps
CPU time 4.15 seconds
Started Jun 30 06:27:18 PM PDT 24
Finished Jun 30 06:27:26 PM PDT 24
Peak memory 199928 kb
Host smart-7b7ce437-f47b-42da-8afc-118e0bd5c67d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893628580 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_intg_err.2893628580
Directory /workspace/18.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/12.hmac_error.614883809
Short name T121
Test name
Test status
Simulation time 6052100506 ps
CPU time 72.02 seconds
Started Jun 30 06:34:35 PM PDT 24
Finished Jun 30 06:35:48 PM PDT 24
Peak memory 200352 kb
Host smart-9f4c46fe-89b1-4c0f-aa8a-9be0f2f87131
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614883809 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_error.614883809
Directory /workspace/12.hmac_error/latest

Test location /workspace/coverage/default/1.hmac_long_msg.1888993486
Short name T128
Test name
Test status
Simulation time 12898135692 ps
CPU time 43.75 seconds
Started Jun 30 06:34:07 PM PDT 24
Finished Jun 30 06:34:52 PM PDT 24
Peak memory 200308 kb
Host smart-ca7544eb-7d4f-4b18-ab88-6cd9c0687b3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888993486 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_long_msg.1888993486
Directory /workspace/1.hmac_long_msg/latest

Test location /workspace/coverage/default/29.hmac_stress_all.1099758179
Short name T126
Test name
Test status
Simulation time 2731266448513 ps
CPU time 5590.08 seconds
Started Jun 30 06:36:13 PM PDT 24
Finished Jun 30 08:09:24 PM PDT 24
Peak memory 712708 kb
Host smart-b2bc98ac-696e-4918-8fcf-ed18594d04fb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099758179 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.hmac_stress_all.1099758179
Directory /workspace/29.hmac_stress_all/latest

Test location /workspace/coverage/default/23.hmac_stress_all.241272674
Short name T48
Test name
Test status
Simulation time 106039182402 ps
CPU time 510.24 seconds
Started Jun 30 06:35:36 PM PDT 24
Finished Jun 30 06:44:06 PM PDT 24
Peak memory 216736 kb
Host smart-55c3c7e3-a0cc-4db7-9102-a78a6f3aefc7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241272674 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 23.hmac_stress_all.241272674
Directory /workspace/23.hmac_stress_all/latest

Test location /workspace/coverage/default/0.hmac_alert_test.1237254227
Short name T19
Test name
Test status
Simulation time 41235120 ps
CPU time 0.57 seconds
Started Jun 30 06:34:10 PM PDT 24
Finished Jun 30 06:34:11 PM PDT 24
Peak memory 195288 kb
Host smart-c5fcea0f-ccb4-43ae-8b96-0af5436342ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237254227 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_alert_test.1237254227
Directory /workspace/0.hmac_alert_test/latest

Test location /workspace/coverage/default/29.hmac_burst_wr.507703368
Short name T144
Test name
Test status
Simulation time 6192492171 ps
CPU time 48.96 seconds
Started Jun 30 06:36:05 PM PDT 24
Finished Jun 30 06:36:55 PM PDT 24
Peak memory 200348 kb
Host smart-5c40bae9-e55b-463e-871a-f489dba52ff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507703368 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_burst_wr.507703368
Directory /workspace/29.hmac_burst_wr/latest

Test location /workspace/coverage/default/4.hmac_datapath_stress.2565156284
Short name T132
Test name
Test status
Simulation time 10997695011 ps
CPU time 537.77 seconds
Started Jun 30 06:34:18 PM PDT 24
Finished Jun 30 06:43:17 PM PDT 24
Peak memory 638748 kb
Host smart-69fd9f89-0b76-4f17-bc60-b7a81632ae48
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2565156284 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_datapath_stress.2565156284
Directory /workspace/4.hmac_datapath_stress/latest

Test location /workspace/coverage/default/4.hmac_stress_all.2795138015
Short name T131
Test name
Test status
Simulation time 8398950101 ps
CPU time 119.43 seconds
Started Jun 30 06:34:20 PM PDT 24
Finished Jun 30 06:36:20 PM PDT 24
Peak memory 208508 kb
Host smart-8760f68c-cf62-4d00-972a-bcb19ca9d25d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795138015 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all.2795138015
Directory /workspace/4.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.4200090754
Short name T112
Test name
Test status
Simulation time 553851934 ps
CPU time 2.39 seconds
Started Jun 30 06:27:19 PM PDT 24
Finished Jun 30 06:27:26 PM PDT 24
Peak memory 199856 kb
Host smart-3f3981c5-6bbc-44f5-a3d6-6d403550a57e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200090754 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_same_cs
r_outstanding.4200090754
Directory /workspace/10.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.2982300369
Short name T141
Test name
Test status
Simulation time 362604256 ps
CPU time 3 seconds
Started Jun 30 06:27:15 PM PDT 24
Finished Jun 30 06:27:22 PM PDT 24
Peak memory 199840 kb
Host smart-f5ddf621-dd68-4b88-827a-75200aea1809
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982300369 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_intg_err.2982300369
Directory /workspace/12.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.1524274607
Short name T880
Test name
Test status
Simulation time 410409060 ps
CPU time 3.12 seconds
Started Jun 30 06:27:06 PM PDT 24
Finished Jun 30 06:27:12 PM PDT 24
Peak memory 199652 kb
Host smart-6c9b3825-ccb0-4c0c-9b06-6129265fdae9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524274607 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_aliasing.1524274607
Directory /workspace/0.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.2546733735
Short name T807
Test name
Test status
Simulation time 361743469 ps
CPU time 14.3 seconds
Started Jun 30 06:27:05 PM PDT 24
Finished Jun 30 06:27:21 PM PDT 24
Peak memory 199744 kb
Host smart-708802f3-39e6-451a-8500-f0113603255b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546733735 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_bit_bash.2546733735
Directory /workspace/0.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.1697448451
Short name T104
Test name
Test status
Simulation time 84333376 ps
CPU time 0.94 seconds
Started Jun 30 06:27:06 PM PDT 24
Finished Jun 30 06:27:10 PM PDT 24
Peak memory 199544 kb
Host smart-e84cfeef-965f-4b9a-a72a-26c9c11cbe91
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697448451 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_hw_reset.1697448451
Directory /workspace/0.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.3964058121
Short name T830
Test name
Test status
Simulation time 48514401 ps
CPU time 2.83 seconds
Started Jun 30 06:27:18 PM PDT 24
Finished Jun 30 06:27:24 PM PDT 24
Peak memory 216280 kb
Host smart-e8a9e73e-7458-4eda-9370-777a1f6c4ef9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964058121 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.hmac_csr_mem_rw_with_rand_reset.3964058121
Directory /workspace/0.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_rw.3682837303
Short name T845
Test name
Test status
Simulation time 14703661 ps
CPU time 0.72 seconds
Started Jun 30 06:26:57 PM PDT 24
Finished Jun 30 06:26:58 PM PDT 24
Peak memory 197300 kb
Host smart-e465f179-1a20-4fb3-ab80-a20164411211
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682837303 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_rw.3682837303
Directory /workspace/0.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_intr_test.2600407807
Short name T887
Test name
Test status
Simulation time 49278708 ps
CPU time 0.62 seconds
Started Jun 30 06:27:12 PM PDT 24
Finished Jun 30 06:27:16 PM PDT 24
Peak memory 194732 kb
Host smart-1d7f3951-39d3-4fcd-b863-b330e8f71e6f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600407807 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_intr_test.2600407807
Directory /workspace/0.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.106778643
Short name T850
Test name
Test status
Simulation time 112128484 ps
CPU time 1.57 seconds
Started Jun 30 06:27:13 PM PDT 24
Finished Jun 30 06:27:18 PM PDT 24
Peak memory 199816 kb
Host smart-eab2f4fb-b613-4562-a1c9-c18a9e9417dd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106778643 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_same_csr_
outstanding.106778643
Directory /workspace/0.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_errors.672874443
Short name T44
Test name
Test status
Simulation time 477519539 ps
CPU time 2.35 seconds
Started Jun 30 06:27:07 PM PDT 24
Finished Jun 30 06:27:12 PM PDT 24
Peak memory 199648 kb
Host smart-e7d7c8ef-5fbf-42df-8f01-05ca5dda2120
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672874443 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_errors.672874443
Directory /workspace/0.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.2138164189
Short name T42
Test name
Test status
Simulation time 163270353 ps
CPU time 3.25 seconds
Started Jun 30 06:27:18 PM PDT 24
Finished Jun 30 06:27:26 PM PDT 24
Peak memory 199912 kb
Host smart-c4d4ba6d-a466-4d08-bd26-8a66db454a92
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138164189 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_intg_err.2138164189
Directory /workspace/0.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.672214808
Short name T869
Test name
Test status
Simulation time 388263643 ps
CPU time 6.31 seconds
Started Jun 30 06:27:03 PM PDT 24
Finished Jun 30 06:27:11 PM PDT 24
Peak memory 199692 kb
Host smart-b8bc55ac-fef2-45a2-b858-1d9d482b47a0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672214808 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_aliasing.672214808
Directory /workspace/1.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.395792566
Short name T829
Test name
Test status
Simulation time 37635298 ps
CPU time 0.97 seconds
Started Jun 30 06:27:17 PM PDT 24
Finished Jun 30 06:27:22 PM PDT 24
Peak memory 199544 kb
Host smart-3f1b5832-7ad9-4b42-ba17-fb8fd6bb51c6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395792566 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_hw_reset.395792566
Directory /workspace/1.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.4174472330
Short name T873
Test name
Test status
Simulation time 142727141 ps
CPU time 2.44 seconds
Started Jun 30 06:27:07 PM PDT 24
Finished Jun 30 06:27:12 PM PDT 24
Peak memory 199888 kb
Host smart-b4768f20-5124-4482-961c-5977eab862d0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174472330 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.hmac_csr_mem_rw_with_rand_reset.4174472330
Directory /workspace/1.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_rw.1156429905
Short name T879
Test name
Test status
Simulation time 52214706 ps
CPU time 0.71 seconds
Started Jun 30 06:27:14 PM PDT 24
Finished Jun 30 06:27:17 PM PDT 24
Peak memory 197500 kb
Host smart-74f5f2cf-d43c-467e-a323-96b4ad666484
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156429905 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_rw.1156429905
Directory /workspace/1.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_intr_test.1742127168
Short name T803
Test name
Test status
Simulation time 14255517 ps
CPU time 0.6 seconds
Started Jun 30 06:27:18 PM PDT 24
Finished Jun 30 06:27:22 PM PDT 24
Peak memory 194760 kb
Host smart-21691da2-202e-481e-a34e-9f321354452f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742127168 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_intr_test.1742127168
Directory /workspace/1.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.481290560
Short name T857
Test name
Test status
Simulation time 444634462 ps
CPU time 2.13 seconds
Started Jun 30 06:27:00 PM PDT 24
Finished Jun 30 06:27:03 PM PDT 24
Peak memory 199920 kb
Host smart-8d61d97a-f534-4335-901f-b5f53fde56bd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481290560 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_same_csr_
outstanding.481290560
Directory /workspace/1.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_errors.2122892718
Short name T50
Test name
Test status
Simulation time 35991056 ps
CPU time 1.97 seconds
Started Jun 30 06:27:05 PM PDT 24
Finished Jun 30 06:27:09 PM PDT 24
Peak memory 199784 kb
Host smart-05ceb8e9-10af-4de9-9c9f-54f806cb3402
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122892718 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_errors.2122892718
Directory /workspace/1.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.982595249
Short name T911
Test name
Test status
Simulation time 265912360 ps
CPU time 2.88 seconds
Started Jun 30 06:27:10 PM PDT 24
Finished Jun 30 06:27:16 PM PDT 24
Peak memory 199792 kb
Host smart-3e2843bc-191f-4df3-84cc-4526e46dd736
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982595249 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_intg_err.982595249
Directory /workspace/1.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.658046121
Short name T35
Test name
Test status
Simulation time 280335908 ps
CPU time 2.47 seconds
Started Jun 30 06:27:07 PM PDT 24
Finished Jun 30 06:27:12 PM PDT 24
Peak memory 199892 kb
Host smart-3aa89278-f27c-427a-978a-bb4a58f881b3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658046121 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.hmac_csr_mem_rw_with_rand_reset.658046121
Directory /workspace/10.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_rw.3671651298
Short name T847
Test name
Test status
Simulation time 90984928 ps
CPU time 0.82 seconds
Started Jun 30 06:27:06 PM PDT 24
Finished Jun 30 06:27:10 PM PDT 24
Peak memory 199120 kb
Host smart-16aa7cea-8f28-408d-bab7-4240d6cccefa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671651298 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_rw.3671651298
Directory /workspace/10.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_intr_test.3764619360
Short name T824
Test name
Test status
Simulation time 17342467 ps
CPU time 0.62 seconds
Started Jun 30 06:27:16 PM PDT 24
Finished Jun 30 06:27:20 PM PDT 24
Peak memory 194724 kb
Host smart-a9b5b51e-aae2-40d1-a0b2-8eb927e7d9d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764619360 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_intr_test.3764619360
Directory /workspace/10.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_errors.1380837029
Short name T46
Test name
Test status
Simulation time 59956298 ps
CPU time 3.14 seconds
Started Jun 30 06:27:08 PM PDT 24
Finished Jun 30 06:27:13 PM PDT 24
Peak memory 199792 kb
Host smart-2d2a1b3b-fd56-45b9-928c-93605b35164a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380837029 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_errors.1380837029
Directory /workspace/10.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.3979784170
Short name T826
Test name
Test status
Simulation time 83884546 ps
CPU time 1.84 seconds
Started Jun 30 06:27:16 PM PDT 24
Finished Jun 30 06:27:21 PM PDT 24
Peak memory 199836 kb
Host smart-7d191b92-86f7-4f85-87b0-131f3fda60bc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979784170 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_intg_err.3979784170
Directory /workspace/10.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.1410791822
Short name T846
Test name
Test status
Simulation time 55475309 ps
CPU time 1.37 seconds
Started Jun 30 06:27:12 PM PDT 24
Finished Jun 30 06:27:17 PM PDT 24
Peak memory 199908 kb
Host smart-335ce8e8-dc60-481b-a7d7-45fe653b51ed
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410791822 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.hmac_csr_mem_rw_with_rand_reset.1410791822
Directory /workspace/11.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_rw.159766078
Short name T102
Test name
Test status
Simulation time 14803331 ps
CPU time 0.79 seconds
Started Jun 30 06:27:20 PM PDT 24
Finished Jun 30 06:27:25 PM PDT 24
Peak memory 198956 kb
Host smart-cd55d935-7864-48af-830d-85df90165af6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159766078 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_rw.159766078
Directory /workspace/11.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_intr_test.920263083
Short name T833
Test name
Test status
Simulation time 58896363 ps
CPU time 0.6 seconds
Started Jun 30 06:27:16 PM PDT 24
Finished Jun 30 06:27:20 PM PDT 24
Peak memory 194676 kb
Host smart-341eadc6-a936-4b75-a3f2-4a4b62477c6f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920263083 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_intr_test.920263083
Directory /workspace/11.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.4090239849
Short name T859
Test name
Test status
Simulation time 286534677 ps
CPU time 1.65 seconds
Started Jun 30 06:27:11 PM PDT 24
Finished Jun 30 06:27:15 PM PDT 24
Peak memory 199796 kb
Host smart-234fb0ba-e28b-4e7a-8fed-634543d49db0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090239849 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_same_cs
r_outstanding.4090239849
Directory /workspace/11.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_errors.1550571953
Short name T861
Test name
Test status
Simulation time 181268708 ps
CPU time 1.17 seconds
Started Jun 30 06:27:19 PM PDT 24
Finished Jun 30 06:27:24 PM PDT 24
Peak memory 199656 kb
Host smart-650ded83-6abb-4b1e-b084-a2cb0d8246a3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550571953 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_errors.1550571953
Directory /workspace/11.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.2088537549
Short name T891
Test name
Test status
Simulation time 159745854 ps
CPU time 3.02 seconds
Started Jun 30 06:27:19 PM PDT 24
Finished Jun 30 06:27:26 PM PDT 24
Peak memory 199856 kb
Host smart-7e287215-9c20-4645-a2d1-9d81302134f9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088537549 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_intg_err.2088537549
Directory /workspace/11.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.4150077694
Short name T40
Test name
Test status
Simulation time 56374429 ps
CPU time 1.5 seconds
Started Jun 30 06:27:11 PM PDT 24
Finished Jun 30 06:27:15 PM PDT 24
Peak memory 199912 kb
Host smart-b6528e6c-12d8-42ed-ad58-4b9092c302da
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150077694 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.hmac_csr_mem_rw_with_rand_reset.4150077694
Directory /workspace/12.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_rw.3092110656
Short name T93
Test name
Test status
Simulation time 24149191 ps
CPU time 0.69 seconds
Started Jun 30 06:27:26 PM PDT 24
Finished Jun 30 06:27:28 PM PDT 24
Peak memory 197804 kb
Host smart-a71513e6-5c18-423d-b4d5-3fd840013c07
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092110656 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_rw.3092110656
Directory /workspace/12.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_intr_test.766087960
Short name T898
Test name
Test status
Simulation time 11202888 ps
CPU time 0.59 seconds
Started Jun 30 06:27:15 PM PDT 24
Finished Jun 30 06:27:18 PM PDT 24
Peak memory 194636 kb
Host smart-8e7e319a-6985-41d7-97b4-2978e299b7f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766087960 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_intr_test.766087960
Directory /workspace/12.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.176129505
Short name T884
Test name
Test status
Simulation time 316715276 ps
CPU time 1.14 seconds
Started Jun 30 06:27:20 PM PDT 24
Finished Jun 30 06:27:25 PM PDT 24
Peak memory 199616 kb
Host smart-fe6517a7-70ae-469c-8679-976a3e53c735
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176129505 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_same_csr
_outstanding.176129505
Directory /workspace/12.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_errors.1603954674
Short name T820
Test name
Test status
Simulation time 208685238 ps
CPU time 3.3 seconds
Started Jun 30 06:27:16 PM PDT 24
Finished Jun 30 06:27:23 PM PDT 24
Peak memory 199752 kb
Host smart-ab6d61e1-9f7a-43e9-91af-e40d0d995f2c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603954674 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_errors.1603954674
Directory /workspace/12.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.2662027124
Short name T836
Test name
Test status
Simulation time 35451866 ps
CPU time 2.05 seconds
Started Jun 30 06:27:17 PM PDT 24
Finished Jun 30 06:27:22 PM PDT 24
Peak memory 208120 kb
Host smart-11f1beb4-70d2-4b1b-9d81-5e4452a99ce4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662027124 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.hmac_csr_mem_rw_with_rand_reset.2662027124
Directory /workspace/13.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_rw.3063907546
Short name T69
Test name
Test status
Simulation time 59717227 ps
CPU time 0.9 seconds
Started Jun 30 06:27:16 PM PDT 24
Finished Jun 30 06:27:20 PM PDT 24
Peak memory 199620 kb
Host smart-a3391881-1b6a-4db8-9d35-ae89af3ae7a0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063907546 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_rw.3063907546
Directory /workspace/13.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_intr_test.3550580436
Short name T858
Test name
Test status
Simulation time 11528479 ps
CPU time 0.62 seconds
Started Jun 30 06:27:22 PM PDT 24
Finished Jun 30 06:27:26 PM PDT 24
Peak memory 194660 kb
Host smart-efebae94-abd3-409a-a0bc-e8033c46bd1e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550580436 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_intr_test.3550580436
Directory /workspace/13.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.3628199781
Short name T105
Test name
Test status
Simulation time 169950176 ps
CPU time 1.11 seconds
Started Jun 30 06:27:11 PM PDT 24
Finished Jun 30 06:27:15 PM PDT 24
Peak memory 199648 kb
Host smart-fb05b533-eb9d-4d94-a0d2-60e0e1ca196b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628199781 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_same_cs
r_outstanding.3628199781
Directory /workspace/13.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_errors.3616554686
Short name T806
Test name
Test status
Simulation time 76364623 ps
CPU time 1.2 seconds
Started Jun 30 06:27:21 PM PDT 24
Finished Jun 30 06:27:28 PM PDT 24
Peak memory 199604 kb
Host smart-99f0dc37-9646-4380-8125-6a5b24b27b46
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616554686 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_errors.3616554686
Directory /workspace/13.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.515010698
Short name T866
Test name
Test status
Simulation time 198474554 ps
CPU time 3.19 seconds
Started Jun 30 06:27:11 PM PDT 24
Finished Jun 30 06:27:16 PM PDT 24
Peak memory 199796 kb
Host smart-0ccbe6dd-cc53-4b59-a7e8-79b4eb53a43a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515010698 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_intg_err.515010698
Directory /workspace/13.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.1747665730
Short name T851
Test name
Test status
Simulation time 440418876 ps
CPU time 1.74 seconds
Started Jun 30 06:27:24 PM PDT 24
Finished Jun 30 06:27:29 PM PDT 24
Peak memory 199896 kb
Host smart-706215f2-79f1-4fc0-8edd-7d1cb773866c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747665730 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.hmac_csr_mem_rw_with_rand_reset.1747665730
Directory /workspace/14.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_rw.805552226
Short name T842
Test name
Test status
Simulation time 29450476 ps
CPU time 0.91 seconds
Started Jun 30 06:27:28 PM PDT 24
Finished Jun 30 06:27:30 PM PDT 24
Peak memory 198880 kb
Host smart-bba153a3-60d2-435e-bbf3-ff69cd99be71
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805552226 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_rw.805552226
Directory /workspace/14.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_intr_test.1671285372
Short name T900
Test name
Test status
Simulation time 15180508 ps
CPU time 0.57 seconds
Started Jun 30 06:27:27 PM PDT 24
Finished Jun 30 06:27:29 PM PDT 24
Peak memory 194720 kb
Host smart-4b185528-1d52-48dd-9ed7-82917f6bedbe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671285372 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_intr_test.1671285372
Directory /workspace/14.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.2621609706
Short name T111
Test name
Test status
Simulation time 55228406 ps
CPU time 1.22 seconds
Started Jun 30 06:27:20 PM PDT 24
Finished Jun 30 06:27:26 PM PDT 24
Peak memory 199852 kb
Host smart-c81c6c9c-4ac8-4c42-bf60-ad2029480b97
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621609706 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_same_cs
r_outstanding.2621609706
Directory /workspace/14.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_errors.2314130502
Short name T815
Test name
Test status
Simulation time 472078581 ps
CPU time 2.62 seconds
Started Jun 30 06:27:19 PM PDT 24
Finished Jun 30 06:27:26 PM PDT 24
Peak memory 199804 kb
Host smart-bd9630df-8284-476a-8aa0-644007108ba4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314130502 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_errors.2314130502
Directory /workspace/14.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.624515190
Short name T885
Test name
Test status
Simulation time 326197789 ps
CPU time 1.92 seconds
Started Jun 30 06:27:20 PM PDT 24
Finished Jun 30 06:27:26 PM PDT 24
Peak memory 199852 kb
Host smart-7f089ab3-ead4-4e38-af9c-18d34f9a5dfc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624515190 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_intg_err.624515190
Directory /workspace/14.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.357976034
Short name T874
Test name
Test status
Simulation time 67684265 ps
CPU time 1.05 seconds
Started Jun 30 06:27:12 PM PDT 24
Finished Jun 30 06:27:15 PM PDT 24
Peak memory 199604 kb
Host smart-08ca6bcc-c8ec-41d4-8c16-9f9238c2de5a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357976034 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.hmac_csr_mem_rw_with_rand_reset.357976034
Directory /workspace/15.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_rw.1053219250
Short name T798
Test name
Test status
Simulation time 56767498 ps
CPU time 0.71 seconds
Started Jun 30 06:27:11 PM PDT 24
Finished Jun 30 06:27:14 PM PDT 24
Peak memory 197364 kb
Host smart-dad4e42f-323e-4b71-995c-d0d665dd2b84
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053219250 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_rw.1053219250
Directory /workspace/15.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_intr_test.2061398471
Short name T805
Test name
Test status
Simulation time 14581044 ps
CPU time 0.59 seconds
Started Jun 30 06:27:08 PM PDT 24
Finished Jun 30 06:27:11 PM PDT 24
Peak memory 194700 kb
Host smart-c5e86ff7-733f-4c46-a422-5ddb51c97542
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061398471 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_intr_test.2061398471
Directory /workspace/15.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.2538524642
Short name T113
Test name
Test status
Simulation time 361976803 ps
CPU time 1.7 seconds
Started Jun 30 06:27:20 PM PDT 24
Finished Jun 30 06:27:26 PM PDT 24
Peak memory 199900 kb
Host smart-facf4bc7-4934-461f-9fb5-fc332d597bc2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538524642 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_same_cs
r_outstanding.2538524642
Directory /workspace/15.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_errors.4268001271
Short name T41
Test name
Test status
Simulation time 83918099 ps
CPU time 2.89 seconds
Started Jun 30 06:27:14 PM PDT 24
Finished Jun 30 06:27:26 PM PDT 24
Peak memory 199768 kb
Host smart-e6a96cc5-2ddf-4d85-8d0c-018882a8b9a9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268001271 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_errors.4268001271
Directory /workspace/15.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.2959949897
Short name T853
Test name
Test status
Simulation time 102924657 ps
CPU time 2.28 seconds
Started Jun 30 06:27:20 PM PDT 24
Finished Jun 30 06:27:26 PM PDT 24
Peak memory 199856 kb
Host smart-36290dc5-10a2-44d7-a5d9-3e8cd4638aa8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959949897 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.hmac_csr_mem_rw_with_rand_reset.2959949897
Directory /workspace/16.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_rw.4078566024
Short name T907
Test name
Test status
Simulation time 24606578 ps
CPU time 0.81 seconds
Started Jun 30 06:27:16 PM PDT 24
Finished Jun 30 06:27:20 PM PDT 24
Peak memory 199180 kb
Host smart-862fc7c8-a865-48d5-98a6-e26defe9a9f9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078566024 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_rw.4078566024
Directory /workspace/16.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_intr_test.1706523797
Short name T852
Test name
Test status
Simulation time 15741993 ps
CPU time 0.62 seconds
Started Jun 30 06:27:15 PM PDT 24
Finished Jun 30 06:27:19 PM PDT 24
Peak memory 194612 kb
Host smart-dcf47bca-ebf6-4a9e-9eb2-c57c7e4d26a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706523797 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_intr_test.1706523797
Directory /workspace/16.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.3327952327
Short name T835
Test name
Test status
Simulation time 360510574 ps
CPU time 1.66 seconds
Started Jun 30 06:27:21 PM PDT 24
Finished Jun 30 06:27:27 PM PDT 24
Peak memory 199840 kb
Host smart-790a2414-7853-4b5c-b77e-bd54cc2bb65b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327952327 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_same_cs
r_outstanding.3327952327
Directory /workspace/16.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_errors.3050214551
Short name T51
Test name
Test status
Simulation time 40769712 ps
CPU time 2.03 seconds
Started Jun 30 06:27:09 PM PDT 24
Finished Jun 30 06:27:13 PM PDT 24
Peak memory 199764 kb
Host smart-da298d1d-ff05-4ab1-a42f-12a00a14e3d7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050214551 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_errors.3050214551
Directory /workspace/16.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.3957372663
Short name T34
Test name
Test status
Simulation time 757170675 ps
CPU time 3.21 seconds
Started Jun 30 06:27:14 PM PDT 24
Finished Jun 30 06:27:20 PM PDT 24
Peak memory 199852 kb
Host smart-6be2b3e3-60ee-4791-bba2-ab09a2e2bcda
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957372663 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_intg_err.3957372663
Directory /workspace/16.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.3793295799
Short name T902
Test name
Test status
Simulation time 248311634818 ps
CPU time 682.16 seconds
Started Jun 30 06:27:12 PM PDT 24
Finished Jun 30 06:38:37 PM PDT 24
Peak memory 224456 kb
Host smart-79d79ff6-cd6c-4fd3-9a2a-59540cba061b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793295799 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.hmac_csr_mem_rw_with_rand_reset.3793295799
Directory /workspace/17.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_rw.85877809
Short name T804
Test name
Test status
Simulation time 105101931 ps
CPU time 0.98 seconds
Started Jun 30 06:27:21 PM PDT 24
Finished Jun 30 06:27:26 PM PDT 24
Peak memory 199376 kb
Host smart-d15b0621-9fb5-4965-bf95-fcc50d1e58b6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85877809 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_rw.85877809
Directory /workspace/17.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_intr_test.2643352695
Short name T876
Test name
Test status
Simulation time 17572109 ps
CPU time 0.58 seconds
Started Jun 30 06:27:13 PM PDT 24
Finished Jun 30 06:27:16 PM PDT 24
Peak memory 194644 kb
Host smart-8920522c-9aed-47e2-b176-7720f09e86e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643352695 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_intr_test.2643352695
Directory /workspace/17.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.2371618550
Short name T832
Test name
Test status
Simulation time 154058315 ps
CPU time 1.09 seconds
Started Jun 30 06:27:14 PM PDT 24
Finished Jun 30 06:27:17 PM PDT 24
Peak memory 199784 kb
Host smart-73544f2d-337b-4fb6-a90f-8167f28faa50
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371618550 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_same_cs
r_outstanding.2371618550
Directory /workspace/17.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_errors.1233508295
Short name T45
Test name
Test status
Simulation time 358404612 ps
CPU time 3.35 seconds
Started Jun 30 06:27:18 PM PDT 24
Finished Jun 30 06:27:25 PM PDT 24
Peak memory 199784 kb
Host smart-c94b5e00-064a-4a8b-b211-7a195631007d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233508295 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_errors.1233508295
Directory /workspace/17.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.4116130428
Short name T909
Test name
Test status
Simulation time 102533091 ps
CPU time 1.75 seconds
Started Jun 30 06:27:11 PM PDT 24
Finished Jun 30 06:27:15 PM PDT 24
Peak memory 199856 kb
Host smart-c0f500fd-1aad-47bb-9297-a1d3893d3a89
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116130428 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_intg_err.4116130428
Directory /workspace/17.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.346034588
Short name T817
Test name
Test status
Simulation time 60306750 ps
CPU time 1.13 seconds
Started Jun 30 06:27:19 PM PDT 24
Finished Jun 30 06:27:24 PM PDT 24
Peak memory 199660 kb
Host smart-1ba2d455-5e4f-4fdf-86d7-c0f013ce2acd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346034588 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.hmac_csr_mem_rw_with_rand_reset.346034588
Directory /workspace/18.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_rw.30414318
Short name T106
Test name
Test status
Simulation time 37470254 ps
CPU time 0.8 seconds
Started Jun 30 06:27:15 PM PDT 24
Finished Jun 30 06:27:24 PM PDT 24
Peak memory 199552 kb
Host smart-c7d6fc53-17ef-43f4-ad10-03122b9f6ea3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30414318 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_rw.30414318
Directory /workspace/18.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_intr_test.1491848769
Short name T844
Test name
Test status
Simulation time 17274479 ps
CPU time 0.6 seconds
Started Jun 30 06:27:11 PM PDT 24
Finished Jun 30 06:27:14 PM PDT 24
Peak memory 194660 kb
Host smart-983431c4-f3cd-4e8b-be99-d0e5a5d5d4b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491848769 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_intr_test.1491848769
Directory /workspace/18.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.2393888901
Short name T877
Test name
Test status
Simulation time 49822850 ps
CPU time 1.2 seconds
Started Jun 30 06:27:24 PM PDT 24
Finished Jun 30 06:27:28 PM PDT 24
Peak memory 199524 kb
Host smart-8fff48e6-e3c3-4219-a9e1-1272cea5bc63
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393888901 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_same_cs
r_outstanding.2393888901
Directory /workspace/18.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_errors.458838905
Short name T904
Test name
Test status
Simulation time 71440320 ps
CPU time 1.52 seconds
Started Jun 30 06:27:13 PM PDT 24
Finished Jun 30 06:27:18 PM PDT 24
Peak memory 199768 kb
Host smart-f541c95a-1b70-4fed-b9af-db0ca018c1a0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458838905 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_errors.458838905
Directory /workspace/18.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.4014021935
Short name T819
Test name
Test status
Simulation time 238735273 ps
CPU time 1.24 seconds
Started Jun 30 06:27:13 PM PDT 24
Finished Jun 30 06:27:18 PM PDT 24
Peak memory 199712 kb
Host smart-71a46067-8997-4ea8-a945-03a237e23aff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014021935 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.hmac_csr_mem_rw_with_rand_reset.4014021935
Directory /workspace/19.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_rw.1981174051
Short name T109
Test name
Test status
Simulation time 184979039 ps
CPU time 0.68 seconds
Started Jun 30 06:27:16 PM PDT 24
Finished Jun 30 06:27:25 PM PDT 24
Peak memory 198016 kb
Host smart-7bf15989-cb69-447b-913c-1757ba9cd4a8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981174051 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_rw.1981174051
Directory /workspace/19.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_intr_test.55139678
Short name T813
Test name
Test status
Simulation time 11908609 ps
CPU time 0.58 seconds
Started Jun 30 06:27:13 PM PDT 24
Finished Jun 30 06:27:17 PM PDT 24
Peak memory 194652 kb
Host smart-9a1c0d59-8769-4bac-a7e8-d6802f0e777b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55139678 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_intr_test.55139678
Directory /workspace/19.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.57490795
Short name T839
Test name
Test status
Simulation time 409599915 ps
CPU time 2.23 seconds
Started Jun 30 06:27:25 PM PDT 24
Finished Jun 30 06:27:29 PM PDT 24
Peak memory 200120 kb
Host smart-31a2733b-378c-4b96-a0e4-36e7804ff3af
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57490795 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_same_csr_
outstanding.57490795
Directory /workspace/19.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_errors.156504960
Short name T881
Test name
Test status
Simulation time 266289121 ps
CPU time 4.21 seconds
Started Jun 30 06:27:16 PM PDT 24
Finished Jun 30 06:27:24 PM PDT 24
Peak memory 199784 kb
Host smart-2e58482d-691b-4265-93f9-155498ca7cab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156504960 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_errors.156504960
Directory /workspace/19.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.3735378292
Short name T142
Test name
Test status
Simulation time 430334033 ps
CPU time 4.29 seconds
Started Jun 30 06:27:17 PM PDT 24
Finished Jun 30 06:27:25 PM PDT 24
Peak memory 199776 kb
Host smart-9b0310c6-cdb2-4860-96cb-ff88dc273016
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735378292 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_intg_err.3735378292
Directory /workspace/19.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.3262879443
Short name T91
Test name
Test status
Simulation time 62652447 ps
CPU time 3.05 seconds
Started Jun 30 06:27:12 PM PDT 24
Finished Jun 30 06:27:18 PM PDT 24
Peak memory 198632 kb
Host smart-e547c778-9bff-4155-84b4-9bddd105800d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262879443 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_aliasing.3262879443
Directory /workspace/2.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.554976710
Short name T99
Test name
Test status
Simulation time 535105168 ps
CPU time 6.12 seconds
Started Jun 30 06:27:06 PM PDT 24
Finished Jun 30 06:27:14 PM PDT 24
Peak memory 199804 kb
Host smart-d8b6bef5-c92d-46d9-9241-2050fc8c49e4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554976710 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_bit_bash.554976710
Directory /workspace/2.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.3860368339
Short name T867
Test name
Test status
Simulation time 21043679 ps
CPU time 0.73 seconds
Started Jun 30 06:27:02 PM PDT 24
Finished Jun 30 06:27:03 PM PDT 24
Peak memory 197760 kb
Host smart-f5496a40-c2b4-4b7b-8ff5-2eca3a343b1f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860368339 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_hw_reset.3860368339
Directory /workspace/2.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.151381535
Short name T822
Test name
Test status
Simulation time 85564055 ps
CPU time 2.6 seconds
Started Jun 30 06:27:12 PM PDT 24
Finished Jun 30 06:27:18 PM PDT 24
Peak memory 199876 kb
Host smart-0ce10b3e-16c4-4c13-8742-3500e18a9cf6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151381535 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.hmac_csr_mem_rw_with_rand_reset.151381535
Directory /workspace/2.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_rw.1260701130
Short name T94
Test name
Test status
Simulation time 30973452 ps
CPU time 0.98 seconds
Started Jun 30 06:27:13 PM PDT 24
Finished Jun 30 06:27:17 PM PDT 24
Peak memory 199552 kb
Host smart-c718c3e8-c7c5-4632-a0c8-0f3ee8cd51f8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260701130 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_rw.1260701130
Directory /workspace/2.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_intr_test.574773783
Short name T860
Test name
Test status
Simulation time 45407494 ps
CPU time 0.6 seconds
Started Jun 30 06:26:58 PM PDT 24
Finished Jun 30 06:27:00 PM PDT 24
Peak memory 194660 kb
Host smart-d0d97333-bbaf-4563-bbba-e0b7068cd2d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574773783 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_intr_test.574773783
Directory /workspace/2.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.3119811843
Short name T890
Test name
Test status
Simulation time 193242878 ps
CPU time 1.65 seconds
Started Jun 30 06:27:09 PM PDT 24
Finished Jun 30 06:27:13 PM PDT 24
Peak memory 199912 kb
Host smart-703a9244-51d3-4bde-a485-84ac53b76fec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119811843 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_same_csr
_outstanding.3119811843
Directory /workspace/2.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_errors.2320284241
Short name T893
Test name
Test status
Simulation time 157844703 ps
CPU time 2.96 seconds
Started Jun 30 06:27:18 PM PDT 24
Finished Jun 30 06:27:25 PM PDT 24
Peak memory 199692 kb
Host smart-aaa8e9c3-329a-4cbb-bb18-8465a0272a91
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320284241 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_errors.2320284241
Directory /workspace/2.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.2059521695
Short name T910
Test name
Test status
Simulation time 188011793 ps
CPU time 1.81 seconds
Started Jun 30 06:27:18 PM PDT 24
Finished Jun 30 06:27:28 PM PDT 24
Peak memory 199824 kb
Host smart-302440c2-42d5-44e5-b9c3-d700bf3da37e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059521695 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_intg_err.2059521695
Directory /workspace/2.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.hmac_intr_test.877359113
Short name T875
Test name
Test status
Simulation time 28443985 ps
CPU time 0.59 seconds
Started Jun 30 06:27:17 PM PDT 24
Finished Jun 30 06:27:21 PM PDT 24
Peak memory 194656 kb
Host smart-c19ebba8-4a37-4d3f-b3c3-95b6452a018a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877359113 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.hmac_intr_test.877359113
Directory /workspace/20.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.hmac_intr_test.3488948690
Short name T905
Test name
Test status
Simulation time 56512519 ps
CPU time 0.58 seconds
Started Jun 30 06:27:15 PM PDT 24
Finished Jun 30 06:27:19 PM PDT 24
Peak memory 194620 kb
Host smart-1ddcab28-ce5f-403e-a315-8eafe7be4531
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488948690 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.hmac_intr_test.3488948690
Directory /workspace/21.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.hmac_intr_test.949911666
Short name T908
Test name
Test status
Simulation time 12510683 ps
CPU time 0.57 seconds
Started Jun 30 06:27:19 PM PDT 24
Finished Jun 30 06:27:24 PM PDT 24
Peak memory 194692 kb
Host smart-a73b256f-7c1e-41ad-95f8-a1f3053baeb0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949911666 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.hmac_intr_test.949911666
Directory /workspace/22.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.hmac_intr_test.2008352385
Short name T802
Test name
Test status
Simulation time 44415260 ps
CPU time 0.61 seconds
Started Jun 30 06:27:12 PM PDT 24
Finished Jun 30 06:27:16 PM PDT 24
Peak memory 194716 kb
Host smart-3719cd65-8ddd-4756-bbb8-a2885122171e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008352385 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.hmac_intr_test.2008352385
Directory /workspace/23.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.hmac_intr_test.283831281
Short name T828
Test name
Test status
Simulation time 14842079 ps
CPU time 0.57 seconds
Started Jun 30 06:27:18 PM PDT 24
Finished Jun 30 06:27:23 PM PDT 24
Peak memory 194684 kb
Host smart-fb328bb5-3889-4923-a8b8-96c5d7971bec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283831281 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.hmac_intr_test.283831281
Directory /workspace/24.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.hmac_intr_test.3092135247
Short name T854
Test name
Test status
Simulation time 46158023 ps
CPU time 0.63 seconds
Started Jun 30 06:27:18 PM PDT 24
Finished Jun 30 06:27:22 PM PDT 24
Peak memory 194984 kb
Host smart-63f3a6a4-0ca7-4e04-913b-bad7ce64c092
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092135247 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.hmac_intr_test.3092135247
Directory /workspace/25.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.hmac_intr_test.124195585
Short name T809
Test name
Test status
Simulation time 140625580 ps
CPU time 0.56 seconds
Started Jun 30 06:27:19 PM PDT 24
Finished Jun 30 06:27:24 PM PDT 24
Peak memory 194644 kb
Host smart-6657bd39-35d4-41e9-9748-1661c8791c69
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124195585 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.hmac_intr_test.124195585
Directory /workspace/26.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.hmac_intr_test.1621999391
Short name T827
Test name
Test status
Simulation time 20300947 ps
CPU time 0.61 seconds
Started Jun 30 06:27:20 PM PDT 24
Finished Jun 30 06:27:25 PM PDT 24
Peak memory 194484 kb
Host smart-f51dce07-1b2f-491c-8b08-8a9c6a7918d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621999391 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.hmac_intr_test.1621999391
Directory /workspace/27.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.hmac_intr_test.3062336243
Short name T872
Test name
Test status
Simulation time 12297222 ps
CPU time 0.57 seconds
Started Jun 30 06:27:08 PM PDT 24
Finished Jun 30 06:27:11 PM PDT 24
Peak memory 194644 kb
Host smart-4ed9609a-46b0-4599-b613-f13bb111453a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062336243 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.hmac_intr_test.3062336243
Directory /workspace/28.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.hmac_intr_test.3777245029
Short name T901
Test name
Test status
Simulation time 40079613 ps
CPU time 0.59 seconds
Started Jun 30 06:27:10 PM PDT 24
Finished Jun 30 06:27:13 PM PDT 24
Peak memory 194656 kb
Host smart-f4d07627-1998-4de2-8561-db89713552ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777245029 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.hmac_intr_test.3777245029
Directory /workspace/29.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.3457626358
Short name T895
Test name
Test status
Simulation time 360697009 ps
CPU time 5.72 seconds
Started Jun 30 06:27:19 PM PDT 24
Finished Jun 30 06:27:29 PM PDT 24
Peak memory 199660 kb
Host smart-03d748b4-c302-4521-84a5-fa2798fa26a6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457626358 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_aliasing.3457626358
Directory /workspace/3.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.2210578024
Short name T101
Test name
Test status
Simulation time 322882263 ps
CPU time 14.62 seconds
Started Jun 30 06:26:55 PM PDT 24
Finished Jun 30 06:27:11 PM PDT 24
Peak memory 198880 kb
Host smart-e4bf5121-50be-4cf6-8a00-da3876fd14fe
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210578024 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_bit_bash.2210578024
Directory /workspace/3.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.3869145538
Short name T68
Test name
Test status
Simulation time 109829171 ps
CPU time 0.88 seconds
Started Jun 30 06:27:12 PM PDT 24
Finished Jun 30 06:27:15 PM PDT 24
Peak memory 198476 kb
Host smart-47b2755a-15f0-4b3c-a58f-b8aa49027bf8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869145538 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_hw_reset.3869145538
Directory /workspace/3.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.1230914044
Short name T903
Test name
Test status
Simulation time 43561069 ps
CPU time 2.81 seconds
Started Jun 30 06:27:05 PM PDT 24
Finished Jun 30 06:27:10 PM PDT 24
Peak memory 216304 kb
Host smart-e5b316c6-eb51-4a0d-8436-ec51ae78e61d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230914044 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.hmac_csr_mem_rw_with_rand_reset.1230914044
Directory /workspace/3.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_rw.1109676463
Short name T98
Test name
Test status
Simulation time 17417051 ps
CPU time 0.7 seconds
Started Jun 30 06:27:17 PM PDT 24
Finished Jun 30 06:27:22 PM PDT 24
Peak memory 197524 kb
Host smart-86bfc106-7f69-4833-b054-ad447d548017
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109676463 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_rw.1109676463
Directory /workspace/3.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_intr_test.4130046833
Short name T818
Test name
Test status
Simulation time 21234777 ps
CPU time 0.61 seconds
Started Jun 30 06:27:01 PM PDT 24
Finished Jun 30 06:27:02 PM PDT 24
Peak memory 194664 kb
Host smart-3c62c704-b89c-42bf-b44a-af7a1a060293
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130046833 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_intr_test.4130046833
Directory /workspace/3.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.4234796090
Short name T837
Test name
Test status
Simulation time 39047535 ps
CPU time 1.74 seconds
Started Jun 30 06:27:12 PM PDT 24
Finished Jun 30 06:27:17 PM PDT 24
Peak memory 200156 kb
Host smart-a8959bda-fe15-4fce-bf59-d84114816c4b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234796090 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_same_csr
_outstanding.4234796090
Directory /workspace/3.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_errors.2080620358
Short name T865
Test name
Test status
Simulation time 731788782 ps
CPU time 2.75 seconds
Started Jun 30 06:27:18 PM PDT 24
Finished Jun 30 06:27:24 PM PDT 24
Peak memory 199784 kb
Host smart-1c83d7f6-ec9f-4296-a6af-d93f2a2d8540
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080620358 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_errors.2080620358
Directory /workspace/3.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.1726236039
Short name T79
Test name
Test status
Simulation time 824433665 ps
CPU time 3.32 seconds
Started Jun 30 06:27:13 PM PDT 24
Finished Jun 30 06:27:19 PM PDT 24
Peak memory 199860 kb
Host smart-a05ea06b-e81a-4c65-ae88-6fda4ff32a85
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726236039 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_intg_err.1726236039
Directory /workspace/3.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.hmac_intr_test.2016124948
Short name T896
Test name
Test status
Simulation time 13968094 ps
CPU time 0.61 seconds
Started Jun 30 06:27:20 PM PDT 24
Finished Jun 30 06:27:25 PM PDT 24
Peak memory 194908 kb
Host smart-166c5600-581b-4b8c-bb63-31e445d4aeeb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016124948 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.hmac_intr_test.2016124948
Directory /workspace/30.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.hmac_intr_test.3865240153
Short name T814
Test name
Test status
Simulation time 36729480 ps
CPU time 0.58 seconds
Started Jun 30 06:27:19 PM PDT 24
Finished Jun 30 06:27:24 PM PDT 24
Peak memory 194712 kb
Host smart-304774bd-bb8f-4e99-b941-21d2bd2b3bbb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865240153 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.hmac_intr_test.3865240153
Directory /workspace/31.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.hmac_intr_test.2847190052
Short name T892
Test name
Test status
Simulation time 22621317 ps
CPU time 0.58 seconds
Started Jun 30 06:27:21 PM PDT 24
Finished Jun 30 06:27:25 PM PDT 24
Peak memory 194672 kb
Host smart-bac8d5a0-d354-4e15-a46b-e475aac88c4d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847190052 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.hmac_intr_test.2847190052
Directory /workspace/32.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.hmac_intr_test.3818408765
Short name T849
Test name
Test status
Simulation time 17863576 ps
CPU time 0.63 seconds
Started Jun 30 06:27:18 PM PDT 24
Finished Jun 30 06:27:23 PM PDT 24
Peak memory 194616 kb
Host smart-cdf5a98f-3895-4dc1-8d6d-61f220833fee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818408765 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.hmac_intr_test.3818408765
Directory /workspace/33.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.hmac_intr_test.1947347199
Short name T834
Test name
Test status
Simulation time 13256429 ps
CPU time 0.58 seconds
Started Jun 30 06:27:18 PM PDT 24
Finished Jun 30 06:27:22 PM PDT 24
Peak memory 194848 kb
Host smart-10ef0531-5293-49ac-a0f8-5f0460563a8e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947347199 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.hmac_intr_test.1947347199
Directory /workspace/34.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.hmac_intr_test.892299998
Short name T871
Test name
Test status
Simulation time 20327662 ps
CPU time 0.59 seconds
Started Jun 30 06:27:23 PM PDT 24
Finished Jun 30 06:27:27 PM PDT 24
Peak memory 194668 kb
Host smart-4029b876-aec7-4dc9-a6b8-0d42612c73a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892299998 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.hmac_intr_test.892299998
Directory /workspace/35.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.hmac_intr_test.1437866699
Short name T856
Test name
Test status
Simulation time 23170508 ps
CPU time 0.57 seconds
Started Jun 30 06:27:21 PM PDT 24
Finished Jun 30 06:27:26 PM PDT 24
Peak memory 194620 kb
Host smart-f4a522f9-f692-450e-aa54-ed5deca0e8b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437866699 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.hmac_intr_test.1437866699
Directory /workspace/36.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.hmac_intr_test.860327696
Short name T848
Test name
Test status
Simulation time 20442414 ps
CPU time 0.61 seconds
Started Jun 30 06:27:18 PM PDT 24
Finished Jun 30 06:27:22 PM PDT 24
Peak memory 194892 kb
Host smart-42d40eb3-2b5c-4d4d-87aa-957903657c6f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860327696 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.hmac_intr_test.860327696
Directory /workspace/37.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.hmac_intr_test.2546435880
Short name T882
Test name
Test status
Simulation time 30662588 ps
CPU time 0.57 seconds
Started Jun 30 06:27:12 PM PDT 24
Finished Jun 30 06:27:15 PM PDT 24
Peak memory 194672 kb
Host smart-fcf7a7dd-9213-43c4-bc78-d37b406b3a24
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546435880 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.hmac_intr_test.2546435880
Directory /workspace/38.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.hmac_intr_test.3664776788
Short name T797
Test name
Test status
Simulation time 49174692 ps
CPU time 0.58 seconds
Started Jun 30 06:27:12 PM PDT 24
Finished Jun 30 06:27:15 PM PDT 24
Peak memory 194636 kb
Host smart-78ba64c3-2db2-44e0-b34c-ef2a95eaf8dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664776788 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.hmac_intr_test.3664776788
Directory /workspace/39.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.2577226144
Short name T103
Test name
Test status
Simulation time 271730857 ps
CPU time 3.13 seconds
Started Jun 30 06:27:18 PM PDT 24
Finished Jun 30 06:27:25 PM PDT 24
Peak memory 199648 kb
Host smart-0746049d-ca96-47dc-b3b6-d49300fb6d2b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577226144 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_aliasing.2577226144
Directory /workspace/4.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.4106479923
Short name T100
Test name
Test status
Simulation time 1830875024 ps
CPU time 11.37 seconds
Started Jun 30 06:27:22 PM PDT 24
Finished Jun 30 06:27:37 PM PDT 24
Peak memory 199716 kb
Host smart-0c19d574-d09c-4551-ac6f-be32395b0270
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106479923 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_bit_bash.4106479923
Directory /workspace/4.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.3964423846
Short name T97
Test name
Test status
Simulation time 20795747 ps
CPU time 0.97 seconds
Started Jun 30 06:27:04 PM PDT 24
Finished Jun 30 06:27:07 PM PDT 24
Peak memory 199560 kb
Host smart-cd16f487-d2a6-4fb2-98ff-cfc82ccf43a9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964423846 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_hw_reset.3964423846
Directory /workspace/4.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.4117737901
Short name T816
Test name
Test status
Simulation time 41088981 ps
CPU time 1.24 seconds
Started Jun 30 06:27:16 PM PDT 24
Finished Jun 30 06:27:21 PM PDT 24
Peak memory 199832 kb
Host smart-29541ab4-e1c6-437d-8436-86fd220389d2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117737901 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.hmac_csr_mem_rw_with_rand_reset.4117737901
Directory /workspace/4.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_rw.2517340483
Short name T96
Test name
Test status
Simulation time 313266772 ps
CPU time 0.92 seconds
Started Jun 30 06:27:09 PM PDT 24
Finished Jun 30 06:27:13 PM PDT 24
Peak memory 199572 kb
Host smart-5c7ef8d6-a984-46e4-9652-a1508a2251f1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517340483 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_rw.2517340483
Directory /workspace/4.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_intr_test.2365401323
Short name T796
Test name
Test status
Simulation time 83303802 ps
CPU time 0.61 seconds
Started Jun 30 06:27:08 PM PDT 24
Finished Jun 30 06:27:12 PM PDT 24
Peak memory 194688 kb
Host smart-32c639b1-963e-4e67-8a98-7fbb9c93bc13
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365401323 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_intr_test.2365401323
Directory /workspace/4.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.2659957244
Short name T855
Test name
Test status
Simulation time 611406377 ps
CPU time 2.35 seconds
Started Jun 30 06:27:05 PM PDT 24
Finished Jun 30 06:27:10 PM PDT 24
Peak memory 199712 kb
Host smart-ea704438-1838-4ec1-aa61-c46945b6ff53
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659957244 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_same_csr
_outstanding.2659957244
Directory /workspace/4.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_errors.743297009
Short name T812
Test name
Test status
Simulation time 2240228108 ps
CPU time 3.52 seconds
Started Jun 30 06:27:08 PM PDT 24
Finished Jun 30 06:27:14 PM PDT 24
Peak memory 199800 kb
Host smart-9d0ea97e-0c38-4e61-b89f-b9274a9e9378
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743297009 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_errors.743297009
Directory /workspace/4.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.314495147
Short name T53
Test name
Test status
Simulation time 311794787 ps
CPU time 3.9 seconds
Started Jun 30 06:27:16 PM PDT 24
Finished Jun 30 06:27:23 PM PDT 24
Peak memory 199856 kb
Host smart-eebb1b45-1509-424b-bc9f-200c7a2ff3ca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314495147 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_intg_err.314495147
Directory /workspace/4.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.hmac_intr_test.3554837508
Short name T801
Test name
Test status
Simulation time 31386809 ps
CPU time 0.6 seconds
Started Jun 30 06:27:18 PM PDT 24
Finished Jun 30 06:27:23 PM PDT 24
Peak memory 194768 kb
Host smart-680d2915-8731-4d28-8890-d828b1e02d35
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554837508 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.hmac_intr_test.3554837508
Directory /workspace/40.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.hmac_intr_test.1347943421
Short name T878
Test name
Test status
Simulation time 17906375 ps
CPU time 0.6 seconds
Started Jun 30 06:27:11 PM PDT 24
Finished Jun 30 06:27:14 PM PDT 24
Peak memory 194604 kb
Host smart-fc8625c4-9316-4ff2-917f-f28d824fc622
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347943421 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.hmac_intr_test.1347943421
Directory /workspace/41.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.hmac_intr_test.290389649
Short name T863
Test name
Test status
Simulation time 79071053 ps
CPU time 0.63 seconds
Started Jun 30 06:27:13 PM PDT 24
Finished Jun 30 06:27:16 PM PDT 24
Peak memory 194648 kb
Host smart-86d1a75c-b6a7-462c-9055-4c764649ee30
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290389649 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.hmac_intr_test.290389649
Directory /workspace/42.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.hmac_intr_test.2300062048
Short name T843
Test name
Test status
Simulation time 33880615 ps
CPU time 0.62 seconds
Started Jun 30 06:27:17 PM PDT 24
Finished Jun 30 06:27:21 PM PDT 24
Peak memory 194684 kb
Host smart-851cb6db-d2cf-4fbb-b53f-17c242275915
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300062048 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.hmac_intr_test.2300062048
Directory /workspace/43.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.hmac_intr_test.3099609631
Short name T800
Test name
Test status
Simulation time 30792596 ps
CPU time 0.58 seconds
Started Jun 30 06:27:14 PM PDT 24
Finished Jun 30 06:27:17 PM PDT 24
Peak memory 194636 kb
Host smart-76915d50-4019-46b4-9fc0-972396262429
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099609631 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.hmac_intr_test.3099609631
Directory /workspace/44.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.hmac_intr_test.3792927347
Short name T906
Test name
Test status
Simulation time 11671198 ps
CPU time 0.61 seconds
Started Jun 30 06:27:22 PM PDT 24
Finished Jun 30 06:27:26 PM PDT 24
Peak memory 194736 kb
Host smart-b63e971c-bf54-42cc-bdf4-021111ae54bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792927347 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.hmac_intr_test.3792927347
Directory /workspace/45.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.hmac_intr_test.1364409847
Short name T808
Test name
Test status
Simulation time 12959775 ps
CPU time 0.56 seconds
Started Jun 30 06:27:16 PM PDT 24
Finished Jun 30 06:27:20 PM PDT 24
Peak memory 194720 kb
Host smart-cd789250-21c0-4fb2-b34f-36f2fec00c20
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364409847 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.hmac_intr_test.1364409847
Directory /workspace/46.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.hmac_intr_test.2980397971
Short name T799
Test name
Test status
Simulation time 121081359 ps
CPU time 0.62 seconds
Started Jun 30 06:27:44 PM PDT 24
Finished Jun 30 06:27:45 PM PDT 24
Peak memory 194724 kb
Host smart-0fcc3c83-0e26-42e6-92e3-4f2819a6dd7d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980397971 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.hmac_intr_test.2980397971
Directory /workspace/47.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.hmac_intr_test.1376496080
Short name T67
Test name
Test status
Simulation time 17204167 ps
CPU time 0.63 seconds
Started Jun 30 06:27:23 PM PDT 24
Finished Jun 30 06:27:27 PM PDT 24
Peak memory 194732 kb
Host smart-200ee0e8-7e32-4d31-9bf0-6305aaeb7c06
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376496080 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.hmac_intr_test.1376496080
Directory /workspace/48.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.hmac_intr_test.2949884335
Short name T889
Test name
Test status
Simulation time 16273504 ps
CPU time 0.57 seconds
Started Jun 30 06:27:31 PM PDT 24
Finished Jun 30 06:27:31 PM PDT 24
Peak memory 194564 kb
Host smart-beb889f8-9000-4749-aa94-05e38ecef100
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949884335 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.hmac_intr_test.2949884335
Directory /workspace/49.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.407773850
Short name T825
Test name
Test status
Simulation time 227957697848 ps
CPU time 1055.36 seconds
Started Jun 30 06:27:20 PM PDT 24
Finished Jun 30 06:45:00 PM PDT 24
Peak memory 216116 kb
Host smart-c376b3f9-ef47-43f7-948b-43855056edc7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407773850 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.hmac_csr_mem_rw_with_rand_reset.407773850
Directory /workspace/5.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_rw.1004079203
Short name T95
Test name
Test status
Simulation time 30494640 ps
CPU time 1 seconds
Started Jun 30 06:27:05 PM PDT 24
Finished Jun 30 06:27:08 PM PDT 24
Peak memory 199584 kb
Host smart-ea8ad370-238a-4046-89fa-2344809f5311
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004079203 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_rw.1004079203
Directory /workspace/5.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_intr_test.1735090233
Short name T888
Test name
Test status
Simulation time 56743496 ps
CPU time 0.62 seconds
Started Jun 30 06:27:21 PM PDT 24
Finished Jun 30 06:27:26 PM PDT 24
Peak memory 194724 kb
Host smart-56dc923b-3e7e-46c8-96c2-bce5a163b49f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735090233 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_intr_test.1735090233
Directory /workspace/5.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.3801230821
Short name T110
Test name
Test status
Simulation time 103103799 ps
CPU time 1.75 seconds
Started Jun 30 06:27:09 PM PDT 24
Finished Jun 30 06:27:13 PM PDT 24
Peak memory 199764 kb
Host smart-a4cd9cd1-4033-4913-9020-85d32e50bcd0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801230821 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_same_csr
_outstanding.3801230821
Directory /workspace/5.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_errors.4257598286
Short name T821
Test name
Test status
Simulation time 152478741 ps
CPU time 1.97 seconds
Started Jun 30 06:27:06 PM PDT 24
Finished Jun 30 06:27:10 PM PDT 24
Peak memory 199788 kb
Host smart-f494365f-1126-4259-9cd8-062d2b5562e3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257598286 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_errors.4257598286
Directory /workspace/5.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.660767621
Short name T810
Test name
Test status
Simulation time 84460006 ps
CPU time 1.87 seconds
Started Jun 30 06:27:15 PM PDT 24
Finished Jun 30 06:27:21 PM PDT 24
Peak memory 199900 kb
Host smart-9faedb9b-5cea-4d41-a472-e39f67ff0e75
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660767621 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_intg_err.660767621
Directory /workspace/5.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.3171895218
Short name T811
Test name
Test status
Simulation time 38862088 ps
CPU time 1.1 seconds
Started Jun 30 06:27:19 PM PDT 24
Finished Jun 30 06:27:25 PM PDT 24
Peak memory 199716 kb
Host smart-70e64e22-bfdf-4e9e-b3d8-6ec0d1731f01
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171895218 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.hmac_csr_mem_rw_with_rand_reset.3171895218
Directory /workspace/6.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_rw.1293350839
Short name T92
Test name
Test status
Simulation time 33382402 ps
CPU time 0.96 seconds
Started Jun 30 06:27:12 PM PDT 24
Finished Jun 30 06:27:16 PM PDT 24
Peak memory 199556 kb
Host smart-61c7f2b4-8e80-45a8-b58a-35e8e7507ee6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293350839 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_rw.1293350839
Directory /workspace/6.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_intr_test.1718278495
Short name T841
Test name
Test status
Simulation time 15152882 ps
CPU time 0.59 seconds
Started Jun 30 06:27:03 PM PDT 24
Finished Jun 30 06:27:05 PM PDT 24
Peak memory 194704 kb
Host smart-94cff625-0f33-43e9-bfd3-48dcf5d7a6ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718278495 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_intr_test.1718278495
Directory /workspace/6.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.2328006437
Short name T108
Test name
Test status
Simulation time 1037402648 ps
CPU time 2.33 seconds
Started Jun 30 06:27:07 PM PDT 24
Finished Jun 30 06:27:12 PM PDT 24
Peak memory 199684 kb
Host smart-9d8d156c-62b7-442b-a869-1f74c65b0642
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328006437 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_same_csr
_outstanding.2328006437
Directory /workspace/6.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_errors.3292948031
Short name T868
Test name
Test status
Simulation time 112636854 ps
CPU time 1.98 seconds
Started Jun 30 06:27:07 PM PDT 24
Finished Jun 30 06:27:11 PM PDT 24
Peak memory 199796 kb
Host smart-945338ff-78c4-4af8-ba68-56c073c727ec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292948031 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_errors.3292948031
Directory /workspace/6.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.2190559370
Short name T43
Test name
Test status
Simulation time 1187086934 ps
CPU time 4.27 seconds
Started Jun 30 06:27:22 PM PDT 24
Finished Jun 30 06:27:30 PM PDT 24
Peak memory 199860 kb
Host smart-d3540180-e63a-4e9f-98fc-d4a6095c43e1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190559370 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_intg_err.2190559370
Directory /workspace/6.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.1041146273
Short name T899
Test name
Test status
Simulation time 63938581 ps
CPU time 2.01 seconds
Started Jun 30 06:27:17 PM PDT 24
Finished Jun 30 06:27:23 PM PDT 24
Peak memory 208108 kb
Host smart-b3956a69-ec53-474e-b540-565908abb3ab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041146273 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.hmac_csr_mem_rw_with_rand_reset.1041146273
Directory /workspace/7.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_rw.1762013316
Short name T831
Test name
Test status
Simulation time 41143517 ps
CPU time 0.84 seconds
Started Jun 30 06:27:09 PM PDT 24
Finished Jun 30 06:27:12 PM PDT 24
Peak memory 198928 kb
Host smart-b7ebd1d3-d614-4064-80eb-6b56a72d9e14
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762013316 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_rw.1762013316
Directory /workspace/7.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_intr_test.1333852344
Short name T864
Test name
Test status
Simulation time 15252957 ps
CPU time 0.61 seconds
Started Jun 30 06:27:10 PM PDT 24
Finished Jun 30 06:27:13 PM PDT 24
Peak memory 194648 kb
Host smart-9c1da204-ddc0-4d73-a2ab-546b47233f2e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333852344 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_intr_test.1333852344
Directory /workspace/7.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.1693072263
Short name T883
Test name
Test status
Simulation time 93823793 ps
CPU time 1.15 seconds
Started Jun 30 06:27:22 PM PDT 24
Finished Jun 30 06:27:27 PM PDT 24
Peak memory 199660 kb
Host smart-c9b1deba-fd90-4565-b4ef-ff4888e82d2b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693072263 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_same_csr
_outstanding.1693072263
Directory /workspace/7.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_errors.2935926496
Short name T47
Test name
Test status
Simulation time 2543629564 ps
CPU time 4.41 seconds
Started Jun 30 06:27:12 PM PDT 24
Finished Jun 30 06:27:19 PM PDT 24
Peak memory 199852 kb
Host smart-6e6e625e-9608-46ed-aa26-f7261ac045d4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935926496 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_errors.2935926496
Directory /workspace/7.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.3872209963
Short name T139
Test name
Test status
Simulation time 268600092 ps
CPU time 4.3 seconds
Started Jun 30 06:27:07 PM PDT 24
Finished Jun 30 06:27:14 PM PDT 24
Peak memory 199812 kb
Host smart-2353b6c8-0ecc-48d6-b8ef-8933d57c1555
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872209963 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_intg_err.3872209963
Directory /workspace/7.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.459639917
Short name T823
Test name
Test status
Simulation time 171110907 ps
CPU time 1.09 seconds
Started Jun 30 06:27:13 PM PDT 24
Finished Jun 30 06:27:17 PM PDT 24
Peak memory 199704 kb
Host smart-672b167a-5b91-4c36-a2b9-62c6a6d0b3bf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459639917 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.hmac_csr_mem_rw_with_rand_reset.459639917
Directory /workspace/8.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_rw.2523991489
Short name T870
Test name
Test status
Simulation time 30732923 ps
CPU time 0.71 seconds
Started Jun 30 06:27:03 PM PDT 24
Finished Jun 30 06:27:05 PM PDT 24
Peak memory 197640 kb
Host smart-7ed668ef-c68b-46e7-a895-6a1a6b7abb4a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523991489 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_rw.2523991489
Directory /workspace/8.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_intr_test.701741535
Short name T840
Test name
Test status
Simulation time 12895844 ps
CPU time 0.58 seconds
Started Jun 30 06:27:07 PM PDT 24
Finished Jun 30 06:27:10 PM PDT 24
Peak memory 194688 kb
Host smart-9a8bfeb6-755e-4ad6-9dc8-9a67e71c9287
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701741535 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_intr_test.701741535
Directory /workspace/8.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.2358643288
Short name T107
Test name
Test status
Simulation time 265337195 ps
CPU time 2.35 seconds
Started Jun 30 06:27:06 PM PDT 24
Finished Jun 30 06:27:11 PM PDT 24
Peak memory 199852 kb
Host smart-36310172-66da-4e66-b274-8ec74c14f287
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358643288 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_same_csr
_outstanding.2358643288
Directory /workspace/8.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_errors.2445308780
Short name T52
Test name
Test status
Simulation time 241502656 ps
CPU time 3.24 seconds
Started Jun 30 06:27:10 PM PDT 24
Finished Jun 30 06:27:16 PM PDT 24
Peak memory 199740 kb
Host smart-7c217fbd-c64c-43af-b9c6-400cd161906a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445308780 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_errors.2445308780
Directory /workspace/8.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.1920429821
Short name T138
Test name
Test status
Simulation time 154505550 ps
CPU time 1.78 seconds
Started Jun 30 06:27:15 PM PDT 24
Finished Jun 30 06:27:20 PM PDT 24
Peak memory 199816 kb
Host smart-7a6cbb10-7284-41f7-988f-e61259d1ffd3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920429821 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_intg_err.1920429821
Directory /workspace/8.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.3276904664
Short name T886
Test name
Test status
Simulation time 49425981 ps
CPU time 1.68 seconds
Started Jun 30 06:27:03 PM PDT 24
Finished Jun 30 06:27:06 PM PDT 24
Peak memory 199884 kb
Host smart-d2a04234-8df9-479a-ae9f-4443488b3f25
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276904664 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.hmac_csr_mem_rw_with_rand_reset.3276904664
Directory /workspace/9.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_rw.1659705558
Short name T894
Test name
Test status
Simulation time 16572391 ps
CPU time 0.71 seconds
Started Jun 30 06:27:05 PM PDT 24
Finished Jun 30 06:27:09 PM PDT 24
Peak memory 197552 kb
Host smart-afc13619-106f-4469-91c6-8d8f03e60609
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659705558 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_rw.1659705558
Directory /workspace/9.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_intr_test.2956243326
Short name T838
Test name
Test status
Simulation time 41989889 ps
CPU time 0.61 seconds
Started Jun 30 06:27:17 PM PDT 24
Finished Jun 30 06:27:21 PM PDT 24
Peak memory 194648 kb
Host smart-9b1eb70b-de62-428a-baa0-3bfcd6d29fda
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956243326 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_intr_test.2956243326
Directory /workspace/9.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.3024949888
Short name T862
Test name
Test status
Simulation time 621079482 ps
CPU time 2.34 seconds
Started Jun 30 06:27:15 PM PDT 24
Finished Jun 30 06:27:21 PM PDT 24
Peak memory 199836 kb
Host smart-53291aac-2f8c-49bf-9eeb-2f619a38a932
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024949888 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_same_csr
_outstanding.3024949888
Directory /workspace/9.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_errors.2091596880
Short name T897
Test name
Test status
Simulation time 361775079 ps
CPU time 1.79 seconds
Started Jun 30 06:27:18 PM PDT 24
Finished Jun 30 06:27:24 PM PDT 24
Peak memory 199828 kb
Host smart-9a3a719f-aaea-42be-abf9-286159db816c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091596880 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_errors.2091596880
Directory /workspace/9.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.1584941660
Short name T140
Test name
Test status
Simulation time 674280836 ps
CPU time 2.96 seconds
Started Jun 30 06:27:21 PM PDT 24
Finished Jun 30 06:27:28 PM PDT 24
Peak memory 199816 kb
Host smart-8e1b25fb-30f4-4ea5-a780-334866518a1a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584941660 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_intg_err.1584941660
Directory /workspace/9.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.hmac_back_pressure.193927649
Short name T12
Test name
Test status
Simulation time 617850835 ps
CPU time 16.21 seconds
Started Jun 30 06:34:12 PM PDT 24
Finished Jun 30 06:34:29 PM PDT 24
Peak memory 200252 kb
Host smart-5fdb47fc-678d-4f79-bcff-58c10f48845a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=193927649 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_back_pressure.193927649
Directory /workspace/0.hmac_back_pressure/latest

Test location /workspace/coverage/default/0.hmac_burst_wr.3426497588
Short name T598
Test name
Test status
Simulation time 3837244722 ps
CPU time 51.25 seconds
Started Jun 30 06:34:07 PM PDT 24
Finished Jun 30 06:34:59 PM PDT 24
Peak memory 200400 kb
Host smart-c19fdf5a-e997-4088-8b31-732ab9e06217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3426497588 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_burst_wr.3426497588
Directory /workspace/0.hmac_burst_wr/latest

Test location /workspace/coverage/default/0.hmac_datapath_stress.1338872261
Short name T638
Test name
Test status
Simulation time 2884215433 ps
CPU time 560.32 seconds
Started Jun 30 06:34:12 PM PDT 24
Finished Jun 30 06:43:33 PM PDT 24
Peak memory 667120 kb
Host smart-70e32941-e0d9-47bf-9252-2010dc91ad75
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1338872261 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_datapath_stress.1338872261
Directory /workspace/0.hmac_datapath_stress/latest

Test location /workspace/coverage/default/0.hmac_error.1112199205
Short name T122
Test name
Test status
Simulation time 3734231527 ps
CPU time 97.36 seconds
Started Jun 30 06:34:09 PM PDT 24
Finished Jun 30 06:35:47 PM PDT 24
Peak memory 200288 kb
Host smart-e51b452b-f0db-48dc-b7bf-2b208b71cb50
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112199205 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_error.1112199205
Directory /workspace/0.hmac_error/latest

Test location /workspace/coverage/default/0.hmac_long_msg.1397476436
Short name T293
Test name
Test status
Simulation time 687800847 ps
CPU time 41.97 seconds
Started Jun 30 06:34:08 PM PDT 24
Finished Jun 30 06:34:51 PM PDT 24
Peak memory 200304 kb
Host smart-e12b2a6c-76a4-4197-97e4-f12413303f9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1397476436 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_long_msg.1397476436
Directory /workspace/0.hmac_long_msg/latest

Test location /workspace/coverage/default/0.hmac_sec_cm.598078261
Short name T38
Test name
Test status
Simulation time 367527782 ps
CPU time 1.02 seconds
Started Jun 30 06:34:09 PM PDT 24
Finished Jun 30 06:34:10 PM PDT 24
Peak memory 219796 kb
Host smart-7b707ec9-6acd-427c-9dc5-ba1ab4cebc7d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598078261 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_sec_cm.598078261
Directory /workspace/0.hmac_sec_cm/latest

Test location /workspace/coverage/default/0.hmac_smoke.3306212770
Short name T531
Test name
Test status
Simulation time 499644336 ps
CPU time 8.5 seconds
Started Jun 30 06:34:03 PM PDT 24
Finished Jun 30 06:34:12 PM PDT 24
Peak memory 200356 kb
Host smart-bac52dad-f202-47d5-9a1d-1ef23859e032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306212770 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_smoke.3306212770
Directory /workspace/0.hmac_smoke/latest

Test location /workspace/coverage/default/0.hmac_stress_all.4193776916
Short name T768
Test name
Test status
Simulation time 4894802527 ps
CPU time 220.49 seconds
Started Jun 30 06:34:09 PM PDT 24
Finished Jun 30 06:37:50 PM PDT 24
Peak memory 200384 kb
Host smart-b2d1e854-fa16-4f86-aa0f-0ed7dc641c89
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193776916 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all.4193776916
Directory /workspace/0.hmac_stress_all/latest

Test location /workspace/coverage/default/0.hmac_test_hmac256_vectors.2805020666
Short name T56
Test name
Test status
Simulation time 1040443751 ps
CPU time 34.26 seconds
Started Jun 30 06:34:08 PM PDT 24
Finished Jun 30 06:34:42 PM PDT 24
Peak memory 200224 kb
Host smart-0756da64-4665-4a29-91ff-da3531757544
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2805020666 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac256_vectors.2805020666
Directory /workspace/0.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_hmac384_vectors.1194774757
Short name T751
Test name
Test status
Simulation time 20649536106 ps
CPU time 44.68 seconds
Started Jun 30 06:34:07 PM PDT 24
Finished Jun 30 06:34:52 PM PDT 24
Peak memory 200320 kb
Host smart-9c41cb2b-c583-4249-b224-3e4454742b8f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1194774757 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac384_vectors.1194774757
Directory /workspace/0.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_hmac512_vectors.2333569266
Short name T22
Test name
Test status
Simulation time 25416157948 ps
CPU time 70.39 seconds
Started Jun 30 06:34:10 PM PDT 24
Finished Jun 30 06:35:20 PM PDT 24
Peak memory 200284 kb
Host smart-7bdd2205-5c4b-4374-a00f-6a1573f29499
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2333569266 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac512_vectors.2333569266
Directory /workspace/0.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha256_vectors.736309935
Short name T200
Test name
Test status
Simulation time 55237459554 ps
CPU time 492.57 seconds
Started Jun 30 06:34:16 PM PDT 24
Finished Jun 30 06:42:29 PM PDT 24
Peak memory 200308 kb
Host smart-a824c96c-74e5-4829-88e6-500bb5d198f3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=736309935 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha256_vectors.736309935
Directory /workspace/0.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha512_vectors.1800578031
Short name T259
Test name
Test status
Simulation time 128012048086 ps
CPU time 1723.02 seconds
Started Jun 30 06:34:10 PM PDT 24
Finished Jun 30 07:02:53 PM PDT 24
Peak memory 215220 kb
Host smart-cd3ffaa6-320b-4cb0-a312-2f05c3350599
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1800578031 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha512_vectors.1800578031
Directory /workspace/0.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/0.hmac_wipe_secret.1732174654
Short name T71
Test name
Test status
Simulation time 22983390876 ps
CPU time 80.6 seconds
Started Jun 30 06:34:08 PM PDT 24
Finished Jun 30 06:35:29 PM PDT 24
Peak memory 200376 kb
Host smart-f9010fad-d943-49f9-b6fd-8687dca215db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732174654 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_wipe_secret.1732174654
Directory /workspace/0.hmac_wipe_secret/latest

Test location /workspace/coverage/default/1.hmac_alert_test.1242694128
Short name T295
Test name
Test status
Simulation time 108584445 ps
CPU time 0.58 seconds
Started Jun 30 06:34:10 PM PDT 24
Finished Jun 30 06:34:11 PM PDT 24
Peak memory 196360 kb
Host smart-80bdcf6c-925d-4911-aaad-1435773bbcd1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242694128 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_alert_test.1242694128
Directory /workspace/1.hmac_alert_test/latest

Test location /workspace/coverage/default/1.hmac_back_pressure.1211748590
Short name T86
Test name
Test status
Simulation time 304457966 ps
CPU time 14.39 seconds
Started Jun 30 06:34:16 PM PDT 24
Finished Jun 30 06:34:31 PM PDT 24
Peak memory 200276 kb
Host smart-babb70d4-ea4a-4bfa-82dd-5f3b7b77dd6f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1211748590 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_back_pressure.1211748590
Directory /workspace/1.hmac_back_pressure/latest

Test location /workspace/coverage/default/1.hmac_burst_wr.295495242
Short name T248
Test name
Test status
Simulation time 1064925300 ps
CPU time 14.52 seconds
Started Jun 30 06:34:07 PM PDT 24
Finished Jun 30 06:34:22 PM PDT 24
Peak memory 200280 kb
Host smart-e2a45404-910b-4974-a5af-113d8719c44b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295495242 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_burst_wr.295495242
Directory /workspace/1.hmac_burst_wr/latest

Test location /workspace/coverage/default/1.hmac_datapath_stress.1885662212
Short name T243
Test name
Test status
Simulation time 3057363701 ps
CPU time 872.94 seconds
Started Jun 30 06:34:09 PM PDT 24
Finished Jun 30 06:48:43 PM PDT 24
Peak memory 731036 kb
Host smart-8180e5bf-f976-4556-b86a-4b85f32a3dd4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1885662212 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_datapath_stress.1885662212
Directory /workspace/1.hmac_datapath_stress/latest

Test location /workspace/coverage/default/1.hmac_error.2046475593
Short name T764
Test name
Test status
Simulation time 1301884542 ps
CPU time 11.13 seconds
Started Jun 30 06:34:09 PM PDT 24
Finished Jun 30 06:34:20 PM PDT 24
Peak memory 200196 kb
Host smart-90b0b3ef-ce2e-429e-a006-3f5bdf0e8a0b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046475593 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_error.2046475593
Directory /workspace/1.hmac_error/latest

Test location /workspace/coverage/default/1.hmac_sec_cm.2727710843
Short name T36
Test name
Test status
Simulation time 1262594946 ps
CPU time 0.96 seconds
Started Jun 30 06:34:09 PM PDT 24
Finished Jun 30 06:34:11 PM PDT 24
Peak memory 219752 kb
Host smart-6a24994e-0a7b-4228-ba8c-1558d23396be
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727710843 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_sec_cm.2727710843
Directory /workspace/1.hmac_sec_cm/latest

Test location /workspace/coverage/default/1.hmac_smoke.834653627
Short name T184
Test name
Test status
Simulation time 1185653859 ps
CPU time 13.34 seconds
Started Jun 30 06:34:12 PM PDT 24
Finished Jun 30 06:34:26 PM PDT 24
Peak memory 200292 kb
Host smart-96d98677-ff5f-4e6c-956e-e36f3f477e96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834653627 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_smoke.834653627
Directory /workspace/1.hmac_smoke/latest

Test location /workspace/coverage/default/1.hmac_stress_all.420859905
Short name T700
Test name
Test status
Simulation time 1035156948156 ps
CPU time 2073.09 seconds
Started Jun 30 06:34:11 PM PDT 24
Finished Jun 30 07:08:45 PM PDT 24
Peak memory 216220 kb
Host smart-a3dda6a4-fcc9-49a6-927a-7490e7c2fb99
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420859905 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all.420859905
Directory /workspace/1.hmac_stress_all/latest

Test location /workspace/coverage/default/1.hmac_test_hmac256_vectors.3734182223
Short name T8
Test name
Test status
Simulation time 2004214293 ps
CPU time 34.63 seconds
Started Jun 30 06:34:12 PM PDT 24
Finished Jun 30 06:34:48 PM PDT 24
Peak memory 200268 kb
Host smart-f00e8f90-b0bc-4aa0-93b5-ab2a5bce9474
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3734182223 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac256_vectors.3734182223
Directory /workspace/1.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_hmac384_vectors.2093806430
Short name T540
Test name
Test status
Simulation time 3601185076 ps
CPU time 44.06 seconds
Started Jun 30 06:34:12 PM PDT 24
Finished Jun 30 06:34:57 PM PDT 24
Peak memory 200268 kb
Host smart-2ef20321-ab08-4e67-bb29-548d34dd9edc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2093806430 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac384_vectors.2093806430
Directory /workspace/1.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_hmac512_vectors.3352173591
Short name T484
Test name
Test status
Simulation time 6791303368 ps
CPU time 51.96 seconds
Started Jun 30 06:34:10 PM PDT 24
Finished Jun 30 06:35:03 PM PDT 24
Peak memory 200376 kb
Host smart-1c2c701b-f428-43d4-92d8-e730eba6a350
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3352173591 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac512_vectors.3352173591
Directory /workspace/1.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha256_vectors.3482960110
Short name T244
Test name
Test status
Simulation time 76376214867 ps
CPU time 527.12 seconds
Started Jun 30 06:34:10 PM PDT 24
Finished Jun 30 06:42:58 PM PDT 24
Peak memory 200328 kb
Host smart-f5847b58-b96a-4f7c-80ed-1335f215e208
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3482960110 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha256_vectors.3482960110
Directory /workspace/1.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha384_vectors.4170571537
Short name T324
Test name
Test status
Simulation time 165250595052 ps
CPU time 2149.96 seconds
Started Jun 30 06:34:08 PM PDT 24
Finished Jun 30 07:09:59 PM PDT 24
Peak memory 215860 kb
Host smart-f9cec4f8-02f5-4c1f-82fa-007ce8f80463
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4170571537 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha384_vectors.4170571537
Directory /workspace/1.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha512_vectors.3509949638
Short name T625
Test name
Test status
Simulation time 102789401987 ps
CPU time 1833.21 seconds
Started Jun 30 06:34:08 PM PDT 24
Finished Jun 30 07:04:42 PM PDT 24
Peak memory 215872 kb
Host smart-46788b03-5276-459b-a30f-281aff1b05cd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3509949638 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha512_vectors.3509949638
Directory /workspace/1.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/1.hmac_wipe_secret.730551061
Short name T16
Test name
Test status
Simulation time 10934033600 ps
CPU time 58.77 seconds
Started Jun 30 06:34:12 PM PDT 24
Finished Jun 30 06:35:11 PM PDT 24
Peak memory 200352 kb
Host smart-59be0d1a-c9d8-4f85-b20f-db30caaae51a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730551061 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_wipe_secret.730551061
Directory /workspace/1.hmac_wipe_secret/latest

Test location /workspace/coverage/default/10.hmac_alert_test.3716645044
Short name T406
Test name
Test status
Simulation time 16677109 ps
CPU time 0.6 seconds
Started Jun 30 06:34:33 PM PDT 24
Finished Jun 30 06:34:34 PM PDT 24
Peak memory 195452 kb
Host smart-a44ce464-7bf4-4a10-9b41-129a68b4a4fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716645044 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_alert_test.3716645044
Directory /workspace/10.hmac_alert_test/latest

Test location /workspace/coverage/default/10.hmac_burst_wr.1078437037
Short name T317
Test name
Test status
Simulation time 8426364503 ps
CPU time 30.66 seconds
Started Jun 30 06:34:29 PM PDT 24
Finished Jun 30 06:35:00 PM PDT 24
Peak memory 200332 kb
Host smart-1e95dc4e-9988-4d18-a141-314d0a8d407c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078437037 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_burst_wr.1078437037
Directory /workspace/10.hmac_burst_wr/latest

Test location /workspace/coverage/default/10.hmac_datapath_stress.979339590
Short name T479
Test name
Test status
Simulation time 13470467899 ps
CPU time 829.92 seconds
Started Jun 30 06:34:33 PM PDT 24
Finished Jun 30 06:48:23 PM PDT 24
Peak memory 742604 kb
Host smart-cd72d75e-5c90-467c-8174-6acdf07071f9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=979339590 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_datapath_stress.979339590
Directory /workspace/10.hmac_datapath_stress/latest

Test location /workspace/coverage/default/10.hmac_error.705809327
Short name T436
Test name
Test status
Simulation time 2354272771 ps
CPU time 65.32 seconds
Started Jun 30 06:34:31 PM PDT 24
Finished Jun 30 06:35:37 PM PDT 24
Peak memory 200396 kb
Host smart-da4640cf-e9e2-4674-956e-e191e2202d46
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705809327 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_error.705809327
Directory /workspace/10.hmac_error/latest

Test location /workspace/coverage/default/10.hmac_smoke.55215376
Short name T179
Test name
Test status
Simulation time 103508127 ps
CPU time 1.99 seconds
Started Jun 30 06:34:30 PM PDT 24
Finished Jun 30 06:34:33 PM PDT 24
Peak memory 200176 kb
Host smart-3231f27b-af01-409c-a44e-c10dcb603fa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55215376 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_smoke.55215376
Directory /workspace/10.hmac_smoke/latest

Test location /workspace/coverage/default/10.hmac_test_hmac256_vectors.1814467607
Short name T153
Test name
Test status
Simulation time 2453731571 ps
CPU time 32.42 seconds
Started Jun 30 06:34:32 PM PDT 24
Finished Jun 30 06:35:05 PM PDT 24
Peak memory 200368 kb
Host smart-bf5af820-db90-4e59-9d55-c284fc8f39d9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1814467607 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_test_hmac256_vectors.1814467607
Directory /workspace/10.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/10.hmac_test_hmac384_vectors.3125823948
Short name T271
Test name
Test status
Simulation time 10906759953 ps
CPU time 89.49 seconds
Started Jun 30 06:34:31 PM PDT 24
Finished Jun 30 06:36:01 PM PDT 24
Peak memory 200360 kb
Host smart-42780112-55b0-41b1-9294-049af82d1fde
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3125823948 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_test_hmac384_vectors.3125823948
Directory /workspace/10.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/10.hmac_test_hmac512_vectors.2137587926
Short name T375
Test name
Test status
Simulation time 8511113071 ps
CPU time 104.82 seconds
Started Jun 30 06:34:32 PM PDT 24
Finished Jun 30 06:36:17 PM PDT 24
Peak memory 200328 kb
Host smart-c9bbf2a9-2174-4ab7-86fa-e018bc4a1956
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2137587926 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_test_hmac512_vectors.2137587926
Directory /workspace/10.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/10.hmac_test_sha256_vectors.2179332335
Short name T585
Test name
Test status
Simulation time 32463465858 ps
CPU time 429.7 seconds
Started Jun 30 06:34:29 PM PDT 24
Finished Jun 30 06:41:39 PM PDT 24
Peak memory 200296 kb
Host smart-384615b2-03e4-4b54-ad0f-c3d0f09bf8f2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2179332335 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_test_sha256_vectors.2179332335
Directory /workspace/10.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/10.hmac_test_sha512_vectors.3758351514
Short name T611
Test name
Test status
Simulation time 150214440241 ps
CPU time 1816.84 seconds
Started Jun 30 06:34:31 PM PDT 24
Finished Jun 30 07:04:49 PM PDT 24
Peak memory 215652 kb
Host smart-eaf79f82-07ca-4ef9-aae8-1e765e436be2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3758351514 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_test_sha512_vectors.3758351514
Directory /workspace/10.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/10.hmac_wipe_secret.2033232505
Short name T88
Test name
Test status
Simulation time 3624100237 ps
CPU time 68.42 seconds
Started Jun 30 06:34:29 PM PDT 24
Finished Jun 30 06:35:38 PM PDT 24
Peak memory 200448 kb
Host smart-c3dddcca-fd3f-4fc4-9985-ea8e08c0c785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033232505 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_wipe_secret.2033232505
Directory /workspace/10.hmac_wipe_secret/latest

Test location /workspace/coverage/default/11.hmac_alert_test.964995358
Short name T612
Test name
Test status
Simulation time 38869377 ps
CPU time 0.65 seconds
Started Jun 30 06:34:37 PM PDT 24
Finished Jun 30 06:34:38 PM PDT 24
Peak memory 195980 kb
Host smart-b9418f48-e112-4eb6-aaa1-e4d5997e932c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964995358 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_alert_test.964995358
Directory /workspace/11.hmac_alert_test/latest

Test location /workspace/coverage/default/11.hmac_back_pressure.1756324261
Short name T305
Test name
Test status
Simulation time 611779652 ps
CPU time 25.11 seconds
Started Jun 30 06:34:40 PM PDT 24
Finished Jun 30 06:35:05 PM PDT 24
Peak memory 200304 kb
Host smart-28589451-e453-4447-9791-bb3bf170b34f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1756324261 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_back_pressure.1756324261
Directory /workspace/11.hmac_back_pressure/latest

Test location /workspace/coverage/default/11.hmac_burst_wr.640840943
Short name T80
Test name
Test status
Simulation time 795631992 ps
CPU time 44.88 seconds
Started Jun 30 06:34:34 PM PDT 24
Finished Jun 30 06:35:19 PM PDT 24
Peak memory 200280 kb
Host smart-0eab1303-4412-4323-a4de-80de7021ce2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640840943 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_burst_wr.640840943
Directory /workspace/11.hmac_burst_wr/latest

Test location /workspace/coverage/default/11.hmac_datapath_stress.3787932432
Short name T210
Test name
Test status
Simulation time 4529231027 ps
CPU time 256.92 seconds
Started Jun 30 06:34:33 PM PDT 24
Finished Jun 30 06:38:50 PM PDT 24
Peak memory 473432 kb
Host smart-6bbcdf21-8ecf-4de4-88a7-35e1b05afdcd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3787932432 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_datapath_stress.3787932432
Directory /workspace/11.hmac_datapath_stress/latest

Test location /workspace/coverage/default/11.hmac_error.1021326320
Short name T387
Test name
Test status
Simulation time 37280223653 ps
CPU time 158.1 seconds
Started Jun 30 06:34:41 PM PDT 24
Finished Jun 30 06:37:20 PM PDT 24
Peak memory 200396 kb
Host smart-1980b0c5-d7fe-4c48-aead-78654ec15115
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021326320 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_error.1021326320
Directory /workspace/11.hmac_error/latest

Test location /workspace/coverage/default/11.hmac_long_msg.2341182431
Short name T212
Test name
Test status
Simulation time 1532414996 ps
CPU time 88.22 seconds
Started Jun 30 06:34:39 PM PDT 24
Finished Jun 30 06:36:07 PM PDT 24
Peak memory 200544 kb
Host smart-f7f3d128-c727-44f2-8a3c-d604b96f4b4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341182431 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_long_msg.2341182431
Directory /workspace/11.hmac_long_msg/latest

Test location /workspace/coverage/default/11.hmac_smoke.2571135806
Short name T614
Test name
Test status
Simulation time 352940266 ps
CPU time 7.13 seconds
Started Jun 30 06:34:35 PM PDT 24
Finished Jun 30 06:34:43 PM PDT 24
Peak memory 200312 kb
Host smart-fb0660a8-d852-46fb-9de8-84ca2660eb0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571135806 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_smoke.2571135806
Directory /workspace/11.hmac_smoke/latest

Test location /workspace/coverage/default/11.hmac_stress_all.3969641645
Short name T33
Test name
Test status
Simulation time 1813279960629 ps
CPU time 7375.76 seconds
Started Jun 30 06:34:41 PM PDT 24
Finished Jun 30 08:37:39 PM PDT 24
Peak memory 675076 kb
Host smart-c4998380-3109-4e02-af9c-c927594cc0ff
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969641645 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.hmac_stress_all.3969641645
Directory /workspace/11.hmac_stress_all/latest

Test location /workspace/coverage/default/11.hmac_test_hmac256_vectors.1180844104
Short name T517
Test name
Test status
Simulation time 5194758375 ps
CPU time 37.08 seconds
Started Jun 30 06:34:35 PM PDT 24
Finished Jun 30 06:35:12 PM PDT 24
Peak memory 200352 kb
Host smart-3980bb2d-86d3-488b-b504-dfaa0aaed340
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1180844104 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_test_hmac256_vectors.1180844104
Directory /workspace/11.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/11.hmac_test_hmac384_vectors.871952097
Short name T657
Test name
Test status
Simulation time 2207428476 ps
CPU time 88.31 seconds
Started Jun 30 06:34:35 PM PDT 24
Finished Jun 30 06:36:04 PM PDT 24
Peak memory 200572 kb
Host smart-2bce2649-ac9d-4189-9214-b60193d9c6b9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=871952097 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_test_hmac384_vectors.871952097
Directory /workspace/11.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/11.hmac_test_hmac512_vectors.2662122378
Short name T182
Test name
Test status
Simulation time 7322937680 ps
CPU time 54.4 seconds
Started Jun 30 06:34:37 PM PDT 24
Finished Jun 30 06:35:32 PM PDT 24
Peak memory 200352 kb
Host smart-cad61881-f889-41bb-a83f-67f14e5cdb68
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2662122378 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_test_hmac512_vectors.2662122378
Directory /workspace/11.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/11.hmac_test_sha256_vectors.1446639337
Short name T468
Test name
Test status
Simulation time 26400298357 ps
CPU time 443.84 seconds
Started Jun 30 06:34:38 PM PDT 24
Finished Jun 30 06:42:02 PM PDT 24
Peak memory 200312 kb
Host smart-0ac1674a-03af-4a17-acd8-f2c88b7980ac
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1446639337 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_test_sha256_vectors.1446639337
Directory /workspace/11.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/11.hmac_test_sha384_vectors.1949976380
Short name T216
Test name
Test status
Simulation time 156139025237 ps
CPU time 2094.09 seconds
Started Jun 30 06:34:35 PM PDT 24
Finished Jun 30 07:09:30 PM PDT 24
Peak memory 215888 kb
Host smart-881661c7-0b43-4cf5-a307-7d70e252238d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1949976380 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_test_sha384_vectors.1949976380
Directory /workspace/11.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/11.hmac_test_sha512_vectors.2296021199
Short name T622
Test name
Test status
Simulation time 153410341246 ps
CPU time 1911.6 seconds
Started Jun 30 06:34:34 PM PDT 24
Finished Jun 30 07:06:26 PM PDT 24
Peak memory 216136 kb
Host smart-38c0190b-d1eb-499a-8cb4-848d6149f925
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2296021199 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_test_sha512_vectors.2296021199
Directory /workspace/11.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/11.hmac_wipe_secret.3329603073
Short name T429
Test name
Test status
Simulation time 12921518228 ps
CPU time 47.42 seconds
Started Jun 30 06:34:36 PM PDT 24
Finished Jun 30 06:35:24 PM PDT 24
Peak memory 200356 kb
Host smart-e140aa87-0f41-4050-899b-31b1620e1f46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3329603073 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_wipe_secret.3329603073
Directory /workspace/11.hmac_wipe_secret/latest

Test location /workspace/coverage/default/12.hmac_alert_test.508535361
Short name T400
Test name
Test status
Simulation time 11453108 ps
CPU time 0.58 seconds
Started Jun 30 06:34:36 PM PDT 24
Finished Jun 30 06:34:37 PM PDT 24
Peak memory 195212 kb
Host smart-2298591f-dcbd-44f7-b84d-8ad9613ad811
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508535361 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_alert_test.508535361
Directory /workspace/12.hmac_alert_test/latest

Test location /workspace/coverage/default/12.hmac_back_pressure.3689973952
Short name T87
Test name
Test status
Simulation time 1549206934 ps
CPU time 18.18 seconds
Started Jun 30 06:34:34 PM PDT 24
Finished Jun 30 06:34:53 PM PDT 24
Peak memory 200320 kb
Host smart-754f9933-6f68-4132-a4cf-44ced90ef89d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3689973952 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_back_pressure.3689973952
Directory /workspace/12.hmac_back_pressure/latest

Test location /workspace/coverage/default/12.hmac_burst_wr.3570186719
Short name T740
Test name
Test status
Simulation time 730660736 ps
CPU time 5.22 seconds
Started Jun 30 06:34:34 PM PDT 24
Finished Jun 30 06:34:40 PM PDT 24
Peak memory 200292 kb
Host smart-93b4340d-11d5-40d5-925a-1e0e72575756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570186719 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_burst_wr.3570186719
Directory /workspace/12.hmac_burst_wr/latest

Test location /workspace/coverage/default/12.hmac_datapath_stress.3309752627
Short name T310
Test name
Test status
Simulation time 3234982965 ps
CPU time 709.49 seconds
Started Jun 30 06:34:41 PM PDT 24
Finished Jun 30 06:46:31 PM PDT 24
Peak memory 633224 kb
Host smart-8a3046b1-f59b-495e-95d8-3e5970d24c2c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3309752627 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_datapath_stress.3309752627
Directory /workspace/12.hmac_datapath_stress/latest

Test location /workspace/coverage/default/12.hmac_long_msg.3292499183
Short name T560
Test name
Test status
Simulation time 102350100 ps
CPU time 5.78 seconds
Started Jun 30 06:34:35 PM PDT 24
Finished Jun 30 06:34:41 PM PDT 24
Peak memory 200172 kb
Host smart-4c63bc5f-299b-42e5-b914-c7caaff5256d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292499183 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_long_msg.3292499183
Directory /workspace/12.hmac_long_msg/latest

Test location /workspace/coverage/default/12.hmac_smoke.756993131
Short name T197
Test name
Test status
Simulation time 470154785 ps
CPU time 9.13 seconds
Started Jun 30 06:34:37 PM PDT 24
Finished Jun 30 06:34:46 PM PDT 24
Peak memory 200272 kb
Host smart-8bdca25d-1a51-4e9d-97e8-d31a0482a99a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756993131 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_smoke.756993131
Directory /workspace/12.hmac_smoke/latest

Test location /workspace/coverage/default/12.hmac_stress_all.1134824868
Short name T403
Test name
Test status
Simulation time 20241098130 ps
CPU time 356.39 seconds
Started Jun 30 06:34:33 PM PDT 24
Finished Jun 30 06:40:30 PM PDT 24
Peak memory 209712 kb
Host smart-fcd30ad0-2902-4bd9-9575-d892c48b9ac2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134824868 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.hmac_stress_all.1134824868
Directory /workspace/12.hmac_stress_all/latest

Test location /workspace/coverage/default/12.hmac_test_hmac256_vectors.3722094072
Short name T341
Test name
Test status
Simulation time 15252835385 ps
CPU time 63.24 seconds
Started Jun 30 06:34:36 PM PDT 24
Finished Jun 30 06:35:40 PM PDT 24
Peak memory 200316 kb
Host smart-e33a090d-d22b-4998-bf92-0a3ce192a571
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3722094072 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_test_hmac256_vectors.3722094072
Directory /workspace/12.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/12.hmac_test_hmac384_vectors.1173935676
Short name T291
Test name
Test status
Simulation time 39431694627 ps
CPU time 44.17 seconds
Started Jun 30 06:34:35 PM PDT 24
Finished Jun 30 06:35:20 PM PDT 24
Peak memory 200308 kb
Host smart-36e7d037-c576-4968-aef6-537670fde548
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1173935676 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_test_hmac384_vectors.1173935676
Directory /workspace/12.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/12.hmac_test_hmac512_vectors.2068110595
Short name T411
Test name
Test status
Simulation time 27630708290 ps
CPU time 101.96 seconds
Started Jun 30 06:34:37 PM PDT 24
Finished Jun 30 06:36:19 PM PDT 24
Peak memory 200320 kb
Host smart-0f75ab65-b9bc-4324-905f-e1788609bc5a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2068110595 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_test_hmac512_vectors.2068110595
Directory /workspace/12.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/12.hmac_test_sha256_vectors.3188992094
Short name T618
Test name
Test status
Simulation time 16157783759 ps
CPU time 448.33 seconds
Started Jun 30 06:34:33 PM PDT 24
Finished Jun 30 06:42:02 PM PDT 24
Peak memory 200272 kb
Host smart-807429e6-ff79-4bb5-bcfa-e2894f4ed353
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3188992094 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_test_sha256_vectors.3188992094
Directory /workspace/12.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/12.hmac_test_sha384_vectors.590553967
Short name T701
Test name
Test status
Simulation time 332926580362 ps
CPU time 2130.35 seconds
Started Jun 30 06:34:38 PM PDT 24
Finished Jun 30 07:10:09 PM PDT 24
Peak memory 216460 kb
Host smart-e9dae953-d5d5-40e4-80f4-d8def95067a9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=590553967 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_test_sha384_vectors.590553967
Directory /workspace/12.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/12.hmac_test_sha512_vectors.2477625383
Short name T227
Test name
Test status
Simulation time 122974893024 ps
CPU time 1686.6 seconds
Started Jun 30 06:34:36 PM PDT 24
Finished Jun 30 07:02:43 PM PDT 24
Peak memory 216308 kb
Host smart-dda471cd-abc7-4ece-b013-c25368145881
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2477625383 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_test_sha512_vectors.2477625383
Directory /workspace/12.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/12.hmac_wipe_secret.2570436638
Short name T213
Test name
Test status
Simulation time 6937072196 ps
CPU time 62.94 seconds
Started Jun 30 06:34:35 PM PDT 24
Finished Jun 30 06:35:38 PM PDT 24
Peak memory 200400 kb
Host smart-e80204e3-a875-4399-ac08-a3069d4b2d5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570436638 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_wipe_secret.2570436638
Directory /workspace/12.hmac_wipe_secret/latest

Test location /workspace/coverage/default/13.hmac_alert_test.1318933590
Short name T767
Test name
Test status
Simulation time 19570339 ps
CPU time 0.57 seconds
Started Jun 30 06:34:42 PM PDT 24
Finished Jun 30 06:34:43 PM PDT 24
Peak memory 195936 kb
Host smart-072fdda7-8e31-406e-9133-f4ac5ecd5ce9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318933590 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_alert_test.1318933590
Directory /workspace/13.hmac_alert_test/latest

Test location /workspace/coverage/default/13.hmac_back_pressure.2625861713
Short name T85
Test name
Test status
Simulation time 111165323 ps
CPU time 5.49 seconds
Started Jun 30 06:34:46 PM PDT 24
Finished Jun 30 06:34:52 PM PDT 24
Peak memory 200268 kb
Host smart-46b2d8a4-b2fd-45bd-8401-3b152997fcdf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2625861713 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_back_pressure.2625861713
Directory /workspace/13.hmac_back_pressure/latest

Test location /workspace/coverage/default/13.hmac_burst_wr.1268573316
Short name T577
Test name
Test status
Simulation time 1912889833 ps
CPU time 54.73 seconds
Started Jun 30 06:34:41 PM PDT 24
Finished Jun 30 06:35:36 PM PDT 24
Peak memory 200208 kb
Host smart-246b79a2-e5e6-465a-909e-687d07f6fc38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1268573316 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_burst_wr.1268573316
Directory /workspace/13.hmac_burst_wr/latest

Test location /workspace/coverage/default/13.hmac_datapath_stress.220882281
Short name T270
Test name
Test status
Simulation time 881815324 ps
CPU time 184.78 seconds
Started Jun 30 06:34:40 PM PDT 24
Finished Jun 30 06:37:45 PM PDT 24
Peak memory 612504 kb
Host smart-0b298055-725a-4a78-b166-572dccac2980
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=220882281 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_datapath_stress.220882281
Directory /workspace/13.hmac_datapath_stress/latest

Test location /workspace/coverage/default/13.hmac_error.2009121943
Short name T289
Test name
Test status
Simulation time 2805770610 ps
CPU time 59.06 seconds
Started Jun 30 06:34:41 PM PDT 24
Finished Jun 30 06:35:40 PM PDT 24
Peak memory 200364 kb
Host smart-c446e536-a6ab-4264-8e8a-669dc348feac
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009121943 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_error.2009121943
Directory /workspace/13.hmac_error/latest

Test location /workspace/coverage/default/13.hmac_long_msg.406595643
Short name T174
Test name
Test status
Simulation time 8367118959 ps
CPU time 118.52 seconds
Started Jun 30 06:34:39 PM PDT 24
Finished Jun 30 06:36:38 PM PDT 24
Peak memory 200416 kb
Host smart-b918a029-91b2-4348-a842-fccc10bca02f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406595643 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_long_msg.406595643
Directory /workspace/13.hmac_long_msg/latest

Test location /workspace/coverage/default/13.hmac_smoke.4001040462
Short name T180
Test name
Test status
Simulation time 2357703241 ps
CPU time 13.97 seconds
Started Jun 30 06:34:42 PM PDT 24
Finished Jun 30 06:34:56 PM PDT 24
Peak memory 200396 kb
Host smart-1a2df9d6-9b02-4bf3-8c34-aa338daeac35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001040462 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_smoke.4001040462
Directory /workspace/13.hmac_smoke/latest

Test location /workspace/coverage/default/13.hmac_stress_all.2462700575
Short name T433
Test name
Test status
Simulation time 1780773214 ps
CPU time 35.63 seconds
Started Jun 30 06:34:43 PM PDT 24
Finished Jun 30 06:35:19 PM PDT 24
Peak memory 200308 kb
Host smart-75502d1d-6c11-4c98-b02c-5ddb0a3f0cb0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462700575 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.hmac_stress_all.2462700575
Directory /workspace/13.hmac_stress_all/latest

Test location /workspace/coverage/default/13.hmac_test_hmac256_vectors.3578114711
Short name T458
Test name
Test status
Simulation time 13519221867 ps
CPU time 39.6 seconds
Started Jun 30 06:34:38 PM PDT 24
Finished Jun 30 06:35:18 PM PDT 24
Peak memory 200356 kb
Host smart-d8743d03-dae9-4d82-8a0a-5367b257e1b6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3578114711 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_test_hmac256_vectors.3578114711
Directory /workspace/13.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/13.hmac_test_hmac384_vectors.75147336
Short name T154
Test name
Test status
Simulation time 17185168964 ps
CPU time 98.2 seconds
Started Jun 30 06:34:42 PM PDT 24
Finished Jun 30 06:36:21 PM PDT 24
Peak memory 200336 kb
Host smart-9b251a93-b71d-474b-aaea-b7a47bf8ea80
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=75147336 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_test_hmac384_vectors.75147336
Directory /workspace/13.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/13.hmac_test_hmac512_vectors.1470537578
Short name T780
Test name
Test status
Simulation time 49992722815 ps
CPU time 73.2 seconds
Started Jun 30 06:34:41 PM PDT 24
Finished Jun 30 06:35:55 PM PDT 24
Peak memory 200376 kb
Host smart-e0fce5a7-7c49-441b-bc66-e3f1e2a1ceca
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1470537578 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_test_hmac512_vectors.1470537578
Directory /workspace/13.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/13.hmac_test_sha256_vectors.2446555559
Short name T412
Test name
Test status
Simulation time 34249789046 ps
CPU time 455.69 seconds
Started Jun 30 06:34:42 PM PDT 24
Finished Jun 30 06:42:18 PM PDT 24
Peak memory 200320 kb
Host smart-1c883e8d-d679-4333-ac90-0b300dd8157e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2446555559 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_test_sha256_vectors.2446555559
Directory /workspace/13.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/13.hmac_test_sha384_vectors.2423706021
Short name T603
Test name
Test status
Simulation time 118910782248 ps
CPU time 1679.61 seconds
Started Jun 30 06:34:39 PM PDT 24
Finished Jun 30 07:02:40 PM PDT 24
Peak memory 216184 kb
Host smart-e616a414-85ee-4267-8e30-4b1bb8a03b8c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2423706021 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_test_sha384_vectors.2423706021
Directory /workspace/13.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/13.hmac_test_sha512_vectors.3287675286
Short name T647
Test name
Test status
Simulation time 31374217788 ps
CPU time 1733.91 seconds
Started Jun 30 06:34:41 PM PDT 24
Finished Jun 30 07:03:36 PM PDT 24
Peak memory 216224 kb
Host smart-eac5f912-e3a3-481e-973e-e096f0a2654f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3287675286 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_test_sha512_vectors.3287675286
Directory /workspace/13.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/13.hmac_wipe_secret.2669768143
Short name T514
Test name
Test status
Simulation time 1307814857 ps
CPU time 7.19 seconds
Started Jun 30 06:34:39 PM PDT 24
Finished Jun 30 06:34:46 PM PDT 24
Peak memory 200316 kb
Host smart-1fa1a473-60fb-4536-8e08-20a0c0110537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669768143 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_wipe_secret.2669768143
Directory /workspace/13.hmac_wipe_secret/latest

Test location /workspace/coverage/default/14.hmac_alert_test.4082983126
Short name T55
Test name
Test status
Simulation time 46473112 ps
CPU time 0.57 seconds
Started Jun 30 06:34:46 PM PDT 24
Finished Jun 30 06:34:47 PM PDT 24
Peak memory 196292 kb
Host smart-ba8f2e8c-e58f-47c5-88af-441602ab0adf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082983126 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_alert_test.4082983126
Directory /workspace/14.hmac_alert_test/latest

Test location /workspace/coverage/default/14.hmac_back_pressure.1530457193
Short name T750
Test name
Test status
Simulation time 155280676 ps
CPU time 4.49 seconds
Started Jun 30 06:34:40 PM PDT 24
Finished Jun 30 06:34:45 PM PDT 24
Peak memory 200204 kb
Host smart-ba628c43-8a26-4eec-ae1d-7aca4b8345fc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1530457193 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_back_pressure.1530457193
Directory /workspace/14.hmac_back_pressure/latest

Test location /workspace/coverage/default/14.hmac_burst_wr.1698979388
Short name T706
Test name
Test status
Simulation time 2958600419 ps
CPU time 52.9 seconds
Started Jun 30 06:34:47 PM PDT 24
Finished Jun 30 06:35:40 PM PDT 24
Peak memory 200376 kb
Host smart-57efb463-1428-424c-a22d-b1550c4c44b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698979388 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_burst_wr.1698979388
Directory /workspace/14.hmac_burst_wr/latest

Test location /workspace/coverage/default/14.hmac_datapath_stress.855357011
Short name T460
Test name
Test status
Simulation time 27126926757 ps
CPU time 456.34 seconds
Started Jun 30 06:34:42 PM PDT 24
Finished Jun 30 06:42:19 PM PDT 24
Peak memory 670468 kb
Host smart-0b4be535-c1b3-4c42-8f06-2917a83f1898
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=855357011 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_datapath_stress.855357011
Directory /workspace/14.hmac_datapath_stress/latest

Test location /workspace/coverage/default/14.hmac_error.2596540325
Short name T278
Test name
Test status
Simulation time 752264190 ps
CPU time 42.07 seconds
Started Jun 30 06:34:42 PM PDT 24
Finished Jun 30 06:35:25 PM PDT 24
Peak memory 200204 kb
Host smart-45e2a70f-d98a-4f92-a455-4412bfa43f6a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596540325 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_error.2596540325
Directory /workspace/14.hmac_error/latest

Test location /workspace/coverage/default/14.hmac_long_msg.2902670926
Short name T520
Test name
Test status
Simulation time 6866634076 ps
CPU time 51.6 seconds
Started Jun 30 06:34:41 PM PDT 24
Finished Jun 30 06:35:33 PM PDT 24
Peak memory 200388 kb
Host smart-5719a4c0-834b-4b53-9986-7184476e5867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2902670926 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_long_msg.2902670926
Directory /workspace/14.hmac_long_msg/latest

Test location /workspace/coverage/default/14.hmac_smoke.440000650
Short name T420
Test name
Test status
Simulation time 301109570 ps
CPU time 2.52 seconds
Started Jun 30 06:34:37 PM PDT 24
Finished Jun 30 06:34:40 PM PDT 24
Peak memory 200288 kb
Host smart-cbed6542-fc48-499c-acb0-7375b0d99ba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440000650 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_smoke.440000650
Directory /workspace/14.hmac_smoke/latest

Test location /workspace/coverage/default/14.hmac_stress_all.2959513447
Short name T63
Test name
Test status
Simulation time 71189647257 ps
CPU time 427.69 seconds
Started Jun 30 06:34:43 PM PDT 24
Finished Jun 30 06:41:51 PM PDT 24
Peak memory 216768 kb
Host smart-cad8d2f7-8b9e-4d17-9723-9291d30d09bc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959513447 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.hmac_stress_all.2959513447
Directory /workspace/14.hmac_stress_all/latest

Test location /workspace/coverage/default/14.hmac_test_hmac256_vectors.1713628169
Short name T374
Test name
Test status
Simulation time 4074051760 ps
CPU time 62.89 seconds
Started Jun 30 06:34:40 PM PDT 24
Finished Jun 30 06:35:43 PM PDT 24
Peak memory 200368 kb
Host smart-fcd16c18-5bdb-444b-a38d-662e67aef7ac
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1713628169 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_test_hmac256_vectors.1713628169
Directory /workspace/14.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/14.hmac_test_hmac384_vectors.1074883610
Short name T237
Test name
Test status
Simulation time 20410107770 ps
CPU time 75.45 seconds
Started Jun 30 06:34:42 PM PDT 24
Finished Jun 30 06:35:58 PM PDT 24
Peak memory 200384 kb
Host smart-161f24dc-e22c-4ae4-8285-ab09f495a003
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1074883610 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_test_hmac384_vectors.1074883610
Directory /workspace/14.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/14.hmac_test_hmac512_vectors.3713420012
Short name T191
Test name
Test status
Simulation time 4838968993 ps
CPU time 53.31 seconds
Started Jun 30 06:34:39 PM PDT 24
Finished Jun 30 06:35:33 PM PDT 24
Peak memory 200344 kb
Host smart-19fa6d37-21e9-4ab7-861e-1fff154b5245
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3713420012 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_test_hmac512_vectors.3713420012
Directory /workspace/14.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/14.hmac_test_sha256_vectors.4018155971
Short name T532
Test name
Test status
Simulation time 15707446987 ps
CPU time 411.05 seconds
Started Jun 30 06:34:39 PM PDT 24
Finished Jun 30 06:41:31 PM PDT 24
Peak memory 200272 kb
Host smart-961c9e3d-975d-4a39-b4cf-319697f3ec92
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=4018155971 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_test_sha256_vectors.4018155971
Directory /workspace/14.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/14.hmac_test_sha384_vectors.3578692994
Short name T288
Test name
Test status
Simulation time 109854451254 ps
CPU time 1958.71 seconds
Started Jun 30 06:34:42 PM PDT 24
Finished Jun 30 07:07:22 PM PDT 24
Peak memory 215828 kb
Host smart-0877a1ca-40c3-41c2-a604-5b8daebff500
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3578692994 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_test_sha384_vectors.3578692994
Directory /workspace/14.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/14.hmac_test_sha512_vectors.1345138859
Short name T171
Test name
Test status
Simulation time 114976132620 ps
CPU time 2023.59 seconds
Started Jun 30 06:34:39 PM PDT 24
Finished Jun 30 07:08:23 PM PDT 24
Peak memory 208668 kb
Host smart-b3f4bcc6-5ecf-469d-b022-963153998384
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1345138859 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_test_sha512_vectors.1345138859
Directory /workspace/14.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/14.hmac_wipe_secret.3336874097
Short name T608
Test name
Test status
Simulation time 3369428595 ps
CPU time 62.84 seconds
Started Jun 30 06:34:43 PM PDT 24
Finished Jun 30 06:35:46 PM PDT 24
Peak memory 200404 kb
Host smart-8fac6ba5-e79e-4c05-a118-188ca3038438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336874097 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_wipe_secret.3336874097
Directory /workspace/14.hmac_wipe_secret/latest

Test location /workspace/coverage/default/15.hmac_alert_test.3895856185
Short name T681
Test name
Test status
Simulation time 13327880 ps
CPU time 0.6 seconds
Started Jun 30 06:34:47 PM PDT 24
Finished Jun 30 06:34:48 PM PDT 24
Peak memory 196288 kb
Host smart-c9be1b1c-87ec-49a2-b584-9f257fa2025b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895856185 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_alert_test.3895856185
Directory /workspace/15.hmac_alert_test/latest

Test location /workspace/coverage/default/15.hmac_back_pressure.1288944851
Short name T452
Test name
Test status
Simulation time 24975597592 ps
CPU time 69.86 seconds
Started Jun 30 06:34:42 PM PDT 24
Finished Jun 30 06:35:52 PM PDT 24
Peak memory 200312 kb
Host smart-f8a841eb-a895-429e-814c-3107deb1ef81
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1288944851 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_back_pressure.1288944851
Directory /workspace/15.hmac_back_pressure/latest

Test location /workspace/coverage/default/15.hmac_burst_wr.3866328999
Short name T476
Test name
Test status
Simulation time 15556576749 ps
CPU time 59.45 seconds
Started Jun 30 06:34:45 PM PDT 24
Finished Jun 30 06:35:45 PM PDT 24
Peak memory 200364 kb
Host smart-fe9734ed-b347-4d5a-b35b-80b9f1339857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866328999 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_burst_wr.3866328999
Directory /workspace/15.hmac_burst_wr/latest

Test location /workspace/coverage/default/15.hmac_datapath_stress.800068764
Short name T313
Test name
Test status
Simulation time 971433449 ps
CPU time 55.6 seconds
Started Jun 30 06:34:49 PM PDT 24
Finished Jun 30 06:35:45 PM PDT 24
Peak memory 269588 kb
Host smart-d99e3db2-4bde-400f-a115-0be31689d50d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=800068764 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_datapath_stress.800068764
Directory /workspace/15.hmac_datapath_stress/latest

Test location /workspace/coverage/default/15.hmac_error.3857186205
Short name T366
Test name
Test status
Simulation time 5724488021 ps
CPU time 163.25 seconds
Started Jun 30 06:34:44 PM PDT 24
Finished Jun 30 06:37:27 PM PDT 24
Peak memory 200376 kb
Host smart-e2af43fa-be9c-4a4a-941d-1843e49e437e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857186205 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_error.3857186205
Directory /workspace/15.hmac_error/latest

Test location /workspace/coverage/default/15.hmac_long_msg.2329233418
Short name T655
Test name
Test status
Simulation time 6001424994 ps
CPU time 84.28 seconds
Started Jun 30 06:34:42 PM PDT 24
Finished Jun 30 06:36:07 PM PDT 24
Peak memory 200348 kb
Host smart-70d2c78c-cdf2-4bc1-8a1a-a62b80ed2192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2329233418 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_long_msg.2329233418
Directory /workspace/15.hmac_long_msg/latest

Test location /workspace/coverage/default/15.hmac_smoke.1365526175
Short name T234
Test name
Test status
Simulation time 1186814085 ps
CPU time 12.61 seconds
Started Jun 30 06:34:44 PM PDT 24
Finished Jun 30 06:34:57 PM PDT 24
Peak memory 200240 kb
Host smart-b6c8e84d-0dcd-4127-a4b2-dd21c8a464da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365526175 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_smoke.1365526175
Directory /workspace/15.hmac_smoke/latest

Test location /workspace/coverage/default/15.hmac_stress_all.4125762419
Short name T642
Test name
Test status
Simulation time 3333797333 ps
CPU time 43.1 seconds
Started Jun 30 06:34:45 PM PDT 24
Finished Jun 30 06:35:28 PM PDT 24
Peak memory 200268 kb
Host smart-e9a8a39d-1d3c-4371-a33e-22b3003dd93b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125762419 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.hmac_stress_all.4125762419
Directory /workspace/15.hmac_stress_all/latest

Test location /workspace/coverage/default/15.hmac_test_hmac256_vectors.112635902
Short name T553
Test name
Test status
Simulation time 5858245393 ps
CPU time 60.7 seconds
Started Jun 30 06:34:44 PM PDT 24
Finished Jun 30 06:35:45 PM PDT 24
Peak memory 200344 kb
Host smart-e76f0ec5-7ca0-4275-9243-11ac27d61d6d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=112635902 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_test_hmac256_vectors.112635902
Directory /workspace/15.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/15.hmac_test_hmac384_vectors.2414448770
Short name T782
Test name
Test status
Simulation time 5957071333 ps
CPU time 86.82 seconds
Started Jun 30 06:34:46 PM PDT 24
Finished Jun 30 06:36:13 PM PDT 24
Peak memory 200420 kb
Host smart-d8a26186-9c12-4149-a1a6-6f18386f3938
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2414448770 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_test_hmac384_vectors.2414448770
Directory /workspace/15.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/15.hmac_test_hmac512_vectors.3418402974
Short name T447
Test name
Test status
Simulation time 18662569193 ps
CPU time 56.62 seconds
Started Jun 30 06:34:46 PM PDT 24
Finished Jun 30 06:35:43 PM PDT 24
Peak memory 200392 kb
Host smart-3d0ff945-320e-41f2-a13f-ce314eb2bc71
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3418402974 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_test_hmac512_vectors.3418402974
Directory /workspace/15.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/15.hmac_test_sha256_vectors.1582103771
Short name T673
Test name
Test status
Simulation time 43340358393 ps
CPU time 524.54 seconds
Started Jun 30 06:34:45 PM PDT 24
Finished Jun 30 06:43:30 PM PDT 24
Peak memory 200312 kb
Host smart-76683f74-6169-432f-86dd-22939e7900ea
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1582103771 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_test_sha256_vectors.1582103771
Directory /workspace/15.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/15.hmac_test_sha384_vectors.3386848344
Short name T298
Test name
Test status
Simulation time 221859641981 ps
CPU time 1670.64 seconds
Started Jun 30 06:34:44 PM PDT 24
Finished Jun 30 07:02:36 PM PDT 24
Peak memory 216740 kb
Host smart-23338dc5-b4b5-407b-b55f-c1ac20649b4b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3386848344 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_test_sha384_vectors.3386848344
Directory /workspace/15.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/15.hmac_test_sha512_vectors.1991112375
Short name T670
Test name
Test status
Simulation time 141116624551 ps
CPU time 1876.54 seconds
Started Jun 30 06:34:46 PM PDT 24
Finished Jun 30 07:06:03 PM PDT 24
Peak memory 216340 kb
Host smart-93bd05d4-fc37-4270-bbbe-12aedd807808
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1991112375 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_test_sha512_vectors.1991112375
Directory /workspace/15.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/15.hmac_wipe_secret.2306935743
Short name T578
Test name
Test status
Simulation time 516282906 ps
CPU time 3.72 seconds
Started Jun 30 06:34:49 PM PDT 24
Finished Jun 30 06:34:53 PM PDT 24
Peak memory 200200 kb
Host smart-4fd770f2-4e8d-4495-8d43-ace4c22bd96c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306935743 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_wipe_secret.2306935743
Directory /workspace/15.hmac_wipe_secret/latest

Test location /workspace/coverage/default/16.hmac_alert_test.703699823
Short name T684
Test name
Test status
Simulation time 28205570 ps
CPU time 0.6 seconds
Started Jun 30 06:34:58 PM PDT 24
Finished Jun 30 06:35:00 PM PDT 24
Peak memory 196324 kb
Host smart-4806d0e1-de14-4bae-990a-fb477d38d906
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703699823 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_alert_test.703699823
Directory /workspace/16.hmac_alert_test/latest

Test location /workspace/coverage/default/16.hmac_back_pressure.2398414577
Short name T653
Test name
Test status
Simulation time 799714155 ps
CPU time 35.21 seconds
Started Jun 30 06:34:45 PM PDT 24
Finished Jun 30 06:35:21 PM PDT 24
Peak memory 200308 kb
Host smart-79305509-28bd-457a-98e7-3a17ad70e387
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2398414577 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_back_pressure.2398414577
Directory /workspace/16.hmac_back_pressure/latest

Test location /workspace/coverage/default/16.hmac_burst_wr.2830453561
Short name T574
Test name
Test status
Simulation time 3023656790 ps
CPU time 40.46 seconds
Started Jun 30 06:34:50 PM PDT 24
Finished Jun 30 06:35:31 PM PDT 24
Peak memory 200364 kb
Host smart-59ff38dc-fd1c-4e6d-b228-7903cedaa9fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830453561 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_burst_wr.2830453561
Directory /workspace/16.hmac_burst_wr/latest

Test location /workspace/coverage/default/16.hmac_datapath_stress.58062822
Short name T59
Test name
Test status
Simulation time 149411124 ps
CPU time 0.97 seconds
Started Jun 30 06:34:54 PM PDT 24
Finished Jun 30 06:34:56 PM PDT 24
Peak memory 198368 kb
Host smart-1a936f6a-5a69-4251-99b4-79b13dcc71cb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=58062822 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_datapath_stress.58062822
Directory /workspace/16.hmac_datapath_stress/latest

Test location /workspace/coverage/default/16.hmac_error.667665260
Short name T530
Test name
Test status
Simulation time 4890924405 ps
CPU time 66.88 seconds
Started Jun 30 06:34:52 PM PDT 24
Finished Jun 30 06:35:59 PM PDT 24
Peak memory 200296 kb
Host smart-2f5433df-ee8a-4f4f-bb37-16c0a5cbe214
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667665260 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_error.667665260
Directory /workspace/16.hmac_error/latest

Test location /workspace/coverage/default/16.hmac_long_msg.2931538836
Short name T576
Test name
Test status
Simulation time 6150234025 ps
CPU time 110.89 seconds
Started Jun 30 06:34:45 PM PDT 24
Finished Jun 30 06:36:36 PM PDT 24
Peak memory 200448 kb
Host smart-a264abc9-e2f2-4c2d-8906-a0cf4eba5a22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931538836 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_long_msg.2931538836
Directory /workspace/16.hmac_long_msg/latest

Test location /workspace/coverage/default/16.hmac_smoke.2645255659
Short name T766
Test name
Test status
Simulation time 158078593 ps
CPU time 3.51 seconds
Started Jun 30 06:34:45 PM PDT 24
Finished Jun 30 06:34:49 PM PDT 24
Peak memory 200352 kb
Host smart-9f521fa9-8ed4-4a19-9c85-89f4c9f1eda2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645255659 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_smoke.2645255659
Directory /workspace/16.hmac_smoke/latest

Test location /workspace/coverage/default/16.hmac_stress_all.3869677967
Short name T497
Test name
Test status
Simulation time 45254703911 ps
CPU time 1492.86 seconds
Started Jun 30 06:34:56 PM PDT 24
Finished Jun 30 06:59:49 PM PDT 24
Peak memory 769384 kb
Host smart-df080092-fe40-4d0b-ad0a-02c46ea3b3ff
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869677967 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.hmac_stress_all.3869677967
Directory /workspace/16.hmac_stress_all/latest

Test location /workspace/coverage/default/16.hmac_test_hmac256_vectors.4042461841
Short name T161
Test name
Test status
Simulation time 4800770331 ps
CPU time 53.54 seconds
Started Jun 30 06:34:51 PM PDT 24
Finished Jun 30 06:35:45 PM PDT 24
Peak memory 200420 kb
Host smart-1ffcda37-5723-4212-b367-352d96ddeb9e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4042461841 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_test_hmac256_vectors.4042461841
Directory /workspace/16.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/16.hmac_test_hmac384_vectors.1973381378
Short name T444
Test name
Test status
Simulation time 4859491889 ps
CPU time 54.11 seconds
Started Jun 30 06:34:49 PM PDT 24
Finished Jun 30 06:35:43 PM PDT 24
Peak memory 200324 kb
Host smart-14b97858-e7d3-49ad-bc09-f915c1d4f643
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1973381378 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_test_hmac384_vectors.1973381378
Directory /workspace/16.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/16.hmac_test_hmac512_vectors.2359222606
Short name T708
Test name
Test status
Simulation time 3973545600 ps
CPU time 54.38 seconds
Started Jun 30 06:34:56 PM PDT 24
Finished Jun 30 06:35:50 PM PDT 24
Peak memory 200408 kb
Host smart-5bbc87dc-3857-43ef-ab58-82813fc6b32d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2359222606 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_test_hmac512_vectors.2359222606
Directory /workspace/16.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/16.hmac_test_sha256_vectors.3708615
Short name T695
Test name
Test status
Simulation time 39438334143 ps
CPU time 521.79 seconds
Started Jun 30 06:34:53 PM PDT 24
Finished Jun 30 06:43:35 PM PDT 24
Peak memory 200272 kb
Host smart-81604678-6dd3-4430-895f-36e09975d811
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3708615 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_test_sha256_vectors.3708615
Directory /workspace/16.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/16.hmac_test_sha384_vectors.2490044555
Short name T589
Test name
Test status
Simulation time 445692812764 ps
CPU time 2039.56 seconds
Started Jun 30 06:34:51 PM PDT 24
Finished Jun 30 07:08:51 PM PDT 24
Peak memory 216692 kb
Host smart-4ff41a52-5949-4a49-b49a-5fd43478fef8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2490044555 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_test_sha384_vectors.2490044555
Directory /workspace/16.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/16.hmac_test_sha512_vectors.3099074336
Short name T306
Test name
Test status
Simulation time 159833791557 ps
CPU time 2260.75 seconds
Started Jun 30 06:34:51 PM PDT 24
Finished Jun 30 07:12:33 PM PDT 24
Peak memory 216884 kb
Host smart-22600674-73be-4b6a-b1ab-a3bc61882939
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3099074336 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_test_sha512_vectors.3099074336
Directory /workspace/16.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/16.hmac_wipe_secret.2069306541
Short name T330
Test name
Test status
Simulation time 6778926946 ps
CPU time 89.47 seconds
Started Jun 30 06:34:54 PM PDT 24
Finished Jun 30 06:36:24 PM PDT 24
Peak memory 200388 kb
Host smart-177cb7d5-d819-4b58-bf98-03cea58e55c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069306541 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_wipe_secret.2069306541
Directory /workspace/16.hmac_wipe_secret/latest

Test location /workspace/coverage/default/17.hmac_alert_test.3695033529
Short name T669
Test name
Test status
Simulation time 41014495 ps
CPU time 0.57 seconds
Started Jun 30 06:35:14 PM PDT 24
Finished Jun 30 06:35:15 PM PDT 24
Peak memory 195252 kb
Host smart-54a11de7-4781-4f1c-b466-710926048c49
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695033529 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_alert_test.3695033529
Directory /workspace/17.hmac_alert_test/latest

Test location /workspace/coverage/default/17.hmac_back_pressure.2585813601
Short name T746
Test name
Test status
Simulation time 9183835372 ps
CPU time 42.96 seconds
Started Jun 30 06:34:55 PM PDT 24
Finished Jun 30 06:35:39 PM PDT 24
Peak memory 200284 kb
Host smart-40affa22-8de2-4edc-a9f9-3b9eb28344b2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2585813601 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_back_pressure.2585813601
Directory /workspace/17.hmac_back_pressure/latest

Test location /workspace/coverage/default/17.hmac_burst_wr.204641124
Short name T503
Test name
Test status
Simulation time 8257821568 ps
CPU time 33.73 seconds
Started Jun 30 06:34:56 PM PDT 24
Finished Jun 30 06:35:30 PM PDT 24
Peak memory 200420 kb
Host smart-20e250d7-2d35-48bf-8067-d8c7ce850092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204641124 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_burst_wr.204641124
Directory /workspace/17.hmac_burst_wr/latest

Test location /workspace/coverage/default/17.hmac_datapath_stress.4287911447
Short name T665
Test name
Test status
Simulation time 1283101765 ps
CPU time 92.87 seconds
Started Jun 30 06:34:54 PM PDT 24
Finished Jun 30 06:36:28 PM PDT 24
Peak memory 562940 kb
Host smart-3e14ae20-0f84-475f-93e7-0dbdad366168
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4287911447 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_datapath_stress.4287911447
Directory /workspace/17.hmac_datapath_stress/latest

Test location /workspace/coverage/default/17.hmac_error.3466926086
Short name T123
Test name
Test status
Simulation time 2969638871 ps
CPU time 39.85 seconds
Started Jun 30 06:34:55 PM PDT 24
Finished Jun 30 06:35:36 PM PDT 24
Peak memory 200276 kb
Host smart-8b02b140-13a6-4493-91ba-a4569b3371c5
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466926086 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_error.3466926086
Directory /workspace/17.hmac_error/latest

Test location /workspace/coverage/default/17.hmac_long_msg.806142859
Short name T385
Test name
Test status
Simulation time 47265305553 ps
CPU time 126.66 seconds
Started Jun 30 06:35:00 PM PDT 24
Finished Jun 30 06:37:07 PM PDT 24
Peak memory 200408 kb
Host smart-5cd2db1c-3720-450d-bbc5-2d4e2fef1bd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806142859 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_long_msg.806142859
Directory /workspace/17.hmac_long_msg/latest

Test location /workspace/coverage/default/17.hmac_smoke.2135077297
Short name T616
Test name
Test status
Simulation time 269032676 ps
CPU time 3.07 seconds
Started Jun 30 06:34:55 PM PDT 24
Finished Jun 30 06:34:59 PM PDT 24
Peak memory 200324 kb
Host smart-926c4147-d352-4ced-ae39-1417439d7164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135077297 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_smoke.2135077297
Directory /workspace/17.hmac_smoke/latest

Test location /workspace/coverage/default/17.hmac_stress_all.1149782543
Short name T687
Test name
Test status
Simulation time 5964200194 ps
CPU time 67.04 seconds
Started Jun 30 06:35:01 PM PDT 24
Finished Jun 30 06:36:09 PM PDT 24
Peak memory 200420 kb
Host smart-595108c5-0400-41c2-bc98-7bbfffc75adb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149782543 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.hmac_stress_all.1149782543
Directory /workspace/17.hmac_stress_all/latest

Test location /workspace/coverage/default/17.hmac_test_hmac256_vectors.3369583131
Short name T597
Test name
Test status
Simulation time 922228360 ps
CPU time 28.02 seconds
Started Jun 30 06:35:10 PM PDT 24
Finished Jun 30 06:35:39 PM PDT 24
Peak memory 200240 kb
Host smart-e45ebe21-1c1d-4de5-afd7-932cdbe7d610
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3369583131 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_test_hmac256_vectors.3369583131
Directory /workspace/17.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/17.hmac_test_hmac384_vectors.220665071
Short name T731
Test name
Test status
Simulation time 7467480700 ps
CPU time 85.19 seconds
Started Jun 30 06:35:02 PM PDT 24
Finished Jun 30 06:36:28 PM PDT 24
Peak memory 200296 kb
Host smart-81e58ca5-953f-4249-9c14-ab0a1d452291
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=220665071 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_test_hmac384_vectors.220665071
Directory /workspace/17.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/17.hmac_test_hmac512_vectors.1733480139
Short name T158
Test name
Test status
Simulation time 2763341629 ps
CPU time 104.83 seconds
Started Jun 30 06:35:01 PM PDT 24
Finished Jun 30 06:36:46 PM PDT 24
Peak memory 200348 kb
Host smart-09ebd508-6cab-46b7-9fc0-65cf53daacba
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1733480139 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_test_hmac512_vectors.1733480139
Directory /workspace/17.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/17.hmac_test_sha256_vectors.335380248
Short name T533
Test name
Test status
Simulation time 36220535481 ps
CPU time 512.93 seconds
Started Jun 30 06:35:03 PM PDT 24
Finished Jun 30 06:43:36 PM PDT 24
Peak memory 200308 kb
Host smart-99098fcb-48aa-4757-8703-eeb5f8623ac3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=335380248 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_test_sha256_vectors.335380248
Directory /workspace/17.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/17.hmac_test_sha384_vectors.3011030232
Short name T761
Test name
Test status
Simulation time 217286098376 ps
CPU time 1906.3 seconds
Started Jun 30 06:35:05 PM PDT 24
Finished Jun 30 07:06:52 PM PDT 24
Peak memory 200348 kb
Host smart-c8408f1a-d59f-43e3-a322-8031cd192c87
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3011030232 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_test_sha384_vectors.3011030232
Directory /workspace/17.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/17.hmac_test_sha512_vectors.2597610216
Short name T555
Test name
Test status
Simulation time 28414685192 ps
CPU time 1644.23 seconds
Started Jun 30 06:35:05 PM PDT 24
Finished Jun 30 07:02:29 PM PDT 24
Peak memory 216200 kb
Host smart-a06ee628-b2b1-476a-b843-84b702e719ca
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2597610216 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_test_sha512_vectors.2597610216
Directory /workspace/17.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/17.hmac_wipe_secret.3579188251
Short name T114
Test name
Test status
Simulation time 1366238682 ps
CPU time 19.8 seconds
Started Jun 30 06:34:55 PM PDT 24
Finished Jun 30 06:35:16 PM PDT 24
Peak memory 200268 kb
Host smart-fcd49fe9-6015-4cc9-921c-98f6571743d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579188251 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_wipe_secret.3579188251
Directory /workspace/17.hmac_wipe_secret/latest

Test location /workspace/coverage/default/18.hmac_alert_test.2796998773
Short name T500
Test name
Test status
Simulation time 42336987 ps
CPU time 0.59 seconds
Started Jun 30 06:35:07 PM PDT 24
Finished Jun 30 06:35:08 PM PDT 24
Peak memory 195948 kb
Host smart-cc4b2452-abbd-4670-aee9-2cfea3fbd3df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796998773 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_alert_test.2796998773
Directory /workspace/18.hmac_alert_test/latest

Test location /workspace/coverage/default/18.hmac_back_pressure.4005737426
Short name T256
Test name
Test status
Simulation time 601550025 ps
CPU time 6.19 seconds
Started Jun 30 06:35:01 PM PDT 24
Finished Jun 30 06:35:07 PM PDT 24
Peak memory 200264 kb
Host smart-3a7fd0f9-d50e-49d7-b883-d0afeef9cdc8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4005737426 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_back_pressure.4005737426
Directory /workspace/18.hmac_back_pressure/latest

Test location /workspace/coverage/default/18.hmac_burst_wr.2848650456
Short name T660
Test name
Test status
Simulation time 1706809444 ps
CPU time 36.02 seconds
Started Jun 30 06:35:12 PM PDT 24
Finished Jun 30 06:35:48 PM PDT 24
Peak memory 200304 kb
Host smart-3fdcc054-14aa-423a-820c-1e24c7fb0a9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848650456 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_burst_wr.2848650456
Directory /workspace/18.hmac_burst_wr/latest

Test location /workspace/coverage/default/18.hmac_datapath_stress.1988996709
Short name T774
Test name
Test status
Simulation time 3417953982 ps
CPU time 1058.2 seconds
Started Jun 30 06:35:02 PM PDT 24
Finished Jun 30 06:52:41 PM PDT 24
Peak memory 762276 kb
Host smart-404682af-6b01-4bb5-9e69-9b28316a2df7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1988996709 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_datapath_stress.1988996709
Directory /workspace/18.hmac_datapath_stress/latest

Test location /workspace/coverage/default/18.hmac_error.3611647177
Short name T297
Test name
Test status
Simulation time 2462875928 ps
CPU time 37.48 seconds
Started Jun 30 06:34:59 PM PDT 24
Finished Jun 30 06:35:37 PM PDT 24
Peak memory 200352 kb
Host smart-379e7f60-43ce-4e79-a768-5f0046fea93a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611647177 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_error.3611647177
Directory /workspace/18.hmac_error/latest

Test location /workspace/coverage/default/18.hmac_long_msg.2937134287
Short name T659
Test name
Test status
Simulation time 1835156413 ps
CPU time 111.05 seconds
Started Jun 30 06:35:02 PM PDT 24
Finished Jun 30 06:36:53 PM PDT 24
Peak memory 200352 kb
Host smart-878b2d73-cf67-4c9f-89bc-912707808055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937134287 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_long_msg.2937134287
Directory /workspace/18.hmac_long_msg/latest

Test location /workspace/coverage/default/18.hmac_smoke.595739251
Short name T325
Test name
Test status
Simulation time 220479394 ps
CPU time 5.88 seconds
Started Jun 30 06:35:16 PM PDT 24
Finished Jun 30 06:35:23 PM PDT 24
Peak memory 200292 kb
Host smart-837b6cc7-3779-4fc9-8fb4-26e77e56a5b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595739251 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_smoke.595739251
Directory /workspace/18.hmac_smoke/latest

Test location /workspace/coverage/default/18.hmac_stress_all.820382704
Short name T499
Test name
Test status
Simulation time 6271555241 ps
CPU time 96.48 seconds
Started Jun 30 06:35:12 PM PDT 24
Finished Jun 30 06:36:49 PM PDT 24
Peak memory 200360 kb
Host smart-7f36987d-788f-4837-8723-d3dcbb328b44
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820382704 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 18.hmac_stress_all.820382704
Directory /workspace/18.hmac_stress_all/latest

Test location /workspace/coverage/default/18.hmac_test_hmac256_vectors.3360792685
Short name T283
Test name
Test status
Simulation time 2045546692 ps
CPU time 35.14 seconds
Started Jun 30 06:35:13 PM PDT 24
Finished Jun 30 06:35:48 PM PDT 24
Peak memory 200324 kb
Host smart-6db6ff87-da20-4c83-8930-216d22d47614
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3360792685 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_test_hmac256_vectors.3360792685
Directory /workspace/18.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/18.hmac_test_hmac384_vectors.2914200170
Short name T258
Test name
Test status
Simulation time 8346369413 ps
CPU time 72.04 seconds
Started Jun 30 06:35:07 PM PDT 24
Finished Jun 30 06:36:19 PM PDT 24
Peak memory 200380 kb
Host smart-ec257c2a-f30a-4fd9-ad79-8230415913fc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2914200170 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_test_hmac384_vectors.2914200170
Directory /workspace/18.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/18.hmac_test_hmac512_vectors.3588920018
Short name T770
Test name
Test status
Simulation time 2093995357 ps
CPU time 62.07 seconds
Started Jun 30 06:35:14 PM PDT 24
Finished Jun 30 06:36:17 PM PDT 24
Peak memory 200264 kb
Host smart-3651a4a0-ec25-4c86-be59-814de35a80f8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3588920018 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_test_hmac512_vectors.3588920018
Directory /workspace/18.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/18.hmac_test_sha256_vectors.4154215429
Short name T338
Test name
Test status
Simulation time 105749575755 ps
CPU time 470.14 seconds
Started Jun 30 06:35:02 PM PDT 24
Finished Jun 30 06:42:53 PM PDT 24
Peak memory 200532 kb
Host smart-9d11dbd1-c12b-4db6-a13a-8f0da1cadd2b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=4154215429 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_test_sha256_vectors.4154215429
Directory /workspace/18.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/18.hmac_test_sha384_vectors.3994188913
Short name T262
Test name
Test status
Simulation time 30648528476 ps
CPU time 1747.11 seconds
Started Jun 30 06:35:01 PM PDT 24
Finished Jun 30 07:04:08 PM PDT 24
Peak memory 215792 kb
Host smart-15fd4be6-2da7-4dd8-ba75-5982e48ecb30
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3994188913 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_test_sha384_vectors.3994188913
Directory /workspace/18.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/18.hmac_test_sha512_vectors.2036358568
Short name T410
Test name
Test status
Simulation time 431994234113 ps
CPU time 1993.73 seconds
Started Jun 30 06:35:06 PM PDT 24
Finished Jun 30 07:08:20 PM PDT 24
Peak memory 216260 kb
Host smart-39252050-e134-4c19-b1e2-94a9685d82c6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2036358568 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_test_sha512_vectors.2036358568
Directory /workspace/18.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/18.hmac_wipe_secret.3787538251
Short name T543
Test name
Test status
Simulation time 40992816699 ps
CPU time 79.27 seconds
Started Jun 30 06:35:00 PM PDT 24
Finished Jun 30 06:36:20 PM PDT 24
Peak memory 200320 kb
Host smart-c4f81280-fc39-4ee1-875d-88a10b80448e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787538251 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_wipe_secret.3787538251
Directory /workspace/18.hmac_wipe_secret/latest

Test location /workspace/coverage/default/19.hmac_alert_test.931999183
Short name T668
Test name
Test status
Simulation time 48889667 ps
CPU time 0.56 seconds
Started Jun 30 06:35:12 PM PDT 24
Finished Jun 30 06:35:13 PM PDT 24
Peak memory 195232 kb
Host smart-8894f6dc-74e8-481d-abad-d8827de1c97b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931999183 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_alert_test.931999183
Directory /workspace/19.hmac_alert_test/latest

Test location /workspace/coverage/default/19.hmac_back_pressure.2959326555
Short name T635
Test name
Test status
Simulation time 691577227 ps
CPU time 33.69 seconds
Started Jun 30 06:35:14 PM PDT 24
Finished Jun 30 06:35:49 PM PDT 24
Peak memory 200272 kb
Host smart-8a586bc1-ed40-40fa-b360-b93fa7d02d4d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2959326555 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_back_pressure.2959326555
Directory /workspace/19.hmac_back_pressure/latest

Test location /workspace/coverage/default/19.hmac_burst_wr.836579099
Short name T784
Test name
Test status
Simulation time 7226254150 ps
CPU time 51.02 seconds
Started Jun 30 06:35:14 PM PDT 24
Finished Jun 30 06:36:05 PM PDT 24
Peak memory 200376 kb
Host smart-c71bdeca-f836-430b-923a-3fd6a3b7461a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836579099 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_burst_wr.836579099
Directory /workspace/19.hmac_burst_wr/latest

Test location /workspace/coverage/default/19.hmac_datapath_stress.3932227417
Short name T632
Test name
Test status
Simulation time 2013705960 ps
CPU time 119.89 seconds
Started Jun 30 06:35:16 PM PDT 24
Finished Jun 30 06:37:17 PM PDT 24
Peak memory 577184 kb
Host smart-14421574-79d2-49da-8644-a14f3276d892
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3932227417 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_datapath_stress.3932227417
Directory /workspace/19.hmac_datapath_stress/latest

Test location /workspace/coverage/default/19.hmac_error.2644809507
Short name T443
Test name
Test status
Simulation time 42799709493 ps
CPU time 127.1 seconds
Started Jun 30 06:35:14 PM PDT 24
Finished Jun 30 06:37:21 PM PDT 24
Peak memory 200532 kb
Host smart-fcf5b643-bdb0-49da-9b5f-0f0383313368
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644809507 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_error.2644809507
Directory /workspace/19.hmac_error/latest

Test location /workspace/coverage/default/19.hmac_long_msg.2208413875
Short name T394
Test name
Test status
Simulation time 1727627870 ps
CPU time 44.85 seconds
Started Jun 30 06:35:13 PM PDT 24
Finished Jun 30 06:35:59 PM PDT 24
Peak memory 200292 kb
Host smart-1c20a23f-0c6f-437a-9f01-96cfd24e722a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208413875 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_long_msg.2208413875
Directory /workspace/19.hmac_long_msg/latest

Test location /workspace/coverage/default/19.hmac_smoke.4286775508
Short name T513
Test name
Test status
Simulation time 806273121 ps
CPU time 11.04 seconds
Started Jun 30 06:35:14 PM PDT 24
Finished Jun 30 06:35:26 PM PDT 24
Peak memory 200292 kb
Host smart-a5883fb5-bef2-4186-a0ef-0d6f9d755950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286775508 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_smoke.4286775508
Directory /workspace/19.hmac_smoke/latest

Test location /workspace/coverage/default/19.hmac_stress_all.611124056
Short name T732
Test name
Test status
Simulation time 42834341 ps
CPU time 0.67 seconds
Started Jun 30 06:35:12 PM PDT 24
Finished Jun 30 06:35:13 PM PDT 24
Peak memory 195988 kb
Host smart-735dbdb3-aa22-4d1b-b35b-43f4cc789f4e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611124056 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 19.hmac_stress_all.611124056
Directory /workspace/19.hmac_stress_all/latest

Test location /workspace/coverage/default/19.hmac_test_hmac256_vectors.3134575444
Short name T646
Test name
Test status
Simulation time 16889953611 ps
CPU time 60.45 seconds
Started Jun 30 06:35:11 PM PDT 24
Finished Jun 30 06:36:12 PM PDT 24
Peak memory 200244 kb
Host smart-5e760662-e247-4dbb-ad57-2a18543a1707
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3134575444 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_test_hmac256_vectors.3134575444
Directory /workspace/19.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/19.hmac_test_hmac384_vectors.2309741663
Short name T572
Test name
Test status
Simulation time 19485746164 ps
CPU time 55.16 seconds
Started Jun 30 06:35:14 PM PDT 24
Finished Jun 30 06:36:10 PM PDT 24
Peak memory 200284 kb
Host smart-7beb5192-1bb2-4b1d-a328-1d72de134cf5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2309741663 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_test_hmac384_vectors.2309741663
Directory /workspace/19.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/19.hmac_test_hmac512_vectors.34182009
Short name T515
Test name
Test status
Simulation time 5771864296 ps
CPU time 70.64 seconds
Started Jun 30 06:35:13 PM PDT 24
Finished Jun 30 06:36:24 PM PDT 24
Peak memory 200348 kb
Host smart-84688e92-d8a4-474e-a671-8d8683d56089
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=34182009 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_test_hmac512_vectors.34182009
Directory /workspace/19.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/19.hmac_test_sha256_vectors.723139397
Short name T309
Test name
Test status
Simulation time 312553907734 ps
CPU time 508.99 seconds
Started Jun 30 06:35:13 PM PDT 24
Finished Jun 30 06:43:43 PM PDT 24
Peak memory 200304 kb
Host smart-e4a027ab-6fb1-440b-bff5-4d7a8044ab1a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=723139397 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_test_sha256_vectors.723139397
Directory /workspace/19.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/19.hmac_test_sha384_vectors.1313581867
Short name T683
Test name
Test status
Simulation time 449627391623 ps
CPU time 1951.88 seconds
Started Jun 30 06:35:12 PM PDT 24
Finished Jun 30 07:07:44 PM PDT 24
Peak memory 215128 kb
Host smart-dc3f049e-604e-4317-bdc7-f06f9965251b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1313581867 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_test_sha384_vectors.1313581867
Directory /workspace/19.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/19.hmac_test_sha512_vectors.1834943209
Short name T464
Test name
Test status
Simulation time 851113251266 ps
CPU time 2008 seconds
Started Jun 30 06:35:11 PM PDT 24
Finished Jun 30 07:08:40 PM PDT 24
Peak memory 216000 kb
Host smart-f62710a5-8f06-40d8-961a-f975ea740b46
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1834943209 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_test_sha512_vectors.1834943209
Directory /workspace/19.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/19.hmac_wipe_secret.2309231976
Short name T789
Test name
Test status
Simulation time 4799900038 ps
CPU time 65.9 seconds
Started Jun 30 06:35:13 PM PDT 24
Finished Jun 30 06:36:19 PM PDT 24
Peak memory 200332 kb
Host smart-c254f0ea-43eb-4880-9bfa-d5b77183dfb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309231976 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_wipe_secret.2309231976
Directory /workspace/19.hmac_wipe_secret/latest

Test location /workspace/coverage/default/2.hmac_alert_test.705259207
Short name T157
Test name
Test status
Simulation time 111862930 ps
CPU time 0.61 seconds
Started Jun 30 06:34:15 PM PDT 24
Finished Jun 30 06:34:16 PM PDT 24
Peak memory 196948 kb
Host smart-60ba01aa-da45-417e-a3c7-1cf98a79f050
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705259207 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_alert_test.705259207
Directory /workspace/2.hmac_alert_test/latest

Test location /workspace/coverage/default/2.hmac_back_pressure.2080893257
Short name T342
Test name
Test status
Simulation time 849626745 ps
CPU time 18.91 seconds
Started Jun 30 06:34:09 PM PDT 24
Finished Jun 30 06:34:29 PM PDT 24
Peak memory 200260 kb
Host smart-4f0b38ee-6c61-42a9-9ecd-07adf0101b2d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2080893257 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_back_pressure.2080893257
Directory /workspace/2.hmac_back_pressure/latest

Test location /workspace/coverage/default/2.hmac_burst_wr.1563111206
Short name T580
Test name
Test status
Simulation time 1706223334 ps
CPU time 45.56 seconds
Started Jun 30 06:34:12 PM PDT 24
Finished Jun 30 06:34:58 PM PDT 24
Peak memory 200312 kb
Host smart-0c2347d0-b34d-4416-a999-3ba3449b1f4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563111206 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_burst_wr.1563111206
Directory /workspace/2.hmac_burst_wr/latest

Test location /workspace/coverage/default/2.hmac_datapath_stress.3793418603
Short name T494
Test name
Test status
Simulation time 239289028 ps
CPU time 31.07 seconds
Started Jun 30 06:34:10 PM PDT 24
Finished Jun 30 06:34:42 PM PDT 24
Peak memory 307512 kb
Host smart-0a54a322-f687-4192-bd47-af90de9c351e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3793418603 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_datapath_stress.3793418603
Directory /workspace/2.hmac_datapath_stress/latest

Test location /workspace/coverage/default/2.hmac_error.753784496
Short name T285
Test name
Test status
Simulation time 49685604581 ps
CPU time 150.97 seconds
Started Jun 30 06:34:16 PM PDT 24
Finished Jun 30 06:36:48 PM PDT 24
Peak memory 200332 kb
Host smart-d37a0300-7b58-4987-934c-1a1490daa526
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753784496 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_error.753784496
Directory /workspace/2.hmac_error/latest

Test location /workspace/coverage/default/2.hmac_long_msg.1900732477
Short name T661
Test name
Test status
Simulation time 2372933696 ps
CPU time 34.97 seconds
Started Jun 30 06:34:12 PM PDT 24
Finished Jun 30 06:34:48 PM PDT 24
Peak memory 200360 kb
Host smart-ed3ce005-4f26-4073-897f-b33040756056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900732477 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_long_msg.1900732477
Directory /workspace/2.hmac_long_msg/latest

Test location /workspace/coverage/default/2.hmac_sec_cm.737181532
Short name T39
Test name
Test status
Simulation time 65890576 ps
CPU time 0.9 seconds
Started Jun 30 06:34:18 PM PDT 24
Finished Jun 30 06:34:19 PM PDT 24
Peak memory 218800 kb
Host smart-92a79938-725c-4862-b501-88f742978236
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737181532 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_sec_cm.737181532
Directory /workspace/2.hmac_sec_cm/latest

Test location /workspace/coverage/default/2.hmac_smoke.2959537517
Short name T250
Test name
Test status
Simulation time 638830732 ps
CPU time 11.25 seconds
Started Jun 30 06:34:12 PM PDT 24
Finished Jun 30 06:34:24 PM PDT 24
Peak memory 200380 kb
Host smart-74c15b4d-7864-4022-9bbb-28b25fff8516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959537517 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_smoke.2959537517
Directory /workspace/2.hmac_smoke/latest

Test location /workspace/coverage/default/2.hmac_stress_all.2384053082
Short name T326
Test name
Test status
Simulation time 46404788297 ps
CPU time 2967.34 seconds
Started Jun 30 06:34:16 PM PDT 24
Finished Jun 30 07:23:44 PM PDT 24
Peak memory 658040 kb
Host smart-1907886d-d8f3-456c-aa03-8ec6aecba728
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384053082 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all.2384053082
Directory /workspace/2.hmac_stress_all/latest

Test location /workspace/coverage/default/2.hmac_test_hmac256_vectors.3533911538
Short name T617
Test name
Test status
Simulation time 3005199511 ps
CPU time 60.42 seconds
Started Jun 30 06:34:16 PM PDT 24
Finished Jun 30 06:35:17 PM PDT 24
Peak memory 200392 kb
Host smart-5db19836-76df-456b-ae52-6927c1b7b8cb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3533911538 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac256_vectors.3533911538
Directory /workspace/2.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_hmac384_vectors.1261252292
Short name T340
Test name
Test status
Simulation time 8614260045 ps
CPU time 83.66 seconds
Started Jun 30 06:34:17 PM PDT 24
Finished Jun 30 06:35:41 PM PDT 24
Peak memory 200432 kb
Host smart-019e4f9b-b34a-4345-909a-181d70aca03f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1261252292 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac384_vectors.1261252292
Directory /workspace/2.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_hmac512_vectors.2420976014
Short name T667
Test name
Test status
Simulation time 19692177696 ps
CPU time 108.86 seconds
Started Jun 30 06:34:16 PM PDT 24
Finished Jun 30 06:36:06 PM PDT 24
Peak memory 200408 kb
Host smart-b94ef831-f9ab-4f2c-9fa5-e44e51537af0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2420976014 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac512_vectors.2420976014
Directory /workspace/2.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha256_vectors.660859835
Short name T778
Test name
Test status
Simulation time 8597279461 ps
CPU time 474.88 seconds
Started Jun 30 06:34:12 PM PDT 24
Finished Jun 30 06:42:07 PM PDT 24
Peak memory 200268 kb
Host smart-b5f53fd4-3a35-45dc-95a3-fca217a7fbe6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=660859835 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha256_vectors.660859835
Directory /workspace/2.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha384_vectors.532213494
Short name T357
Test name
Test status
Simulation time 433365346940 ps
CPU time 1801.67 seconds
Started Jun 30 06:34:09 PM PDT 24
Finished Jun 30 07:04:12 PM PDT 24
Peak memory 215884 kb
Host smart-09356dfa-764b-4ee6-95dc-f664a9c9f660
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=532213494 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha384_vectors.532213494
Directory /workspace/2.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha512_vectors.2444171332
Short name T312
Test name
Test status
Simulation time 33467506649 ps
CPU time 1872.75 seconds
Started Jun 30 06:34:16 PM PDT 24
Finished Jun 30 07:05:29 PM PDT 24
Peak memory 216724 kb
Host smart-30905c64-98b2-49ec-b774-0a5dc5cd4b39
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2444171332 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha512_vectors.2444171332
Directory /workspace/2.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/2.hmac_wipe_secret.603577755
Short name T222
Test name
Test status
Simulation time 856753527 ps
CPU time 24.99 seconds
Started Jun 30 06:34:12 PM PDT 24
Finished Jun 30 06:34:37 PM PDT 24
Peak memory 200328 kb
Host smart-aea1aa61-d1e5-47fb-80ef-00edcdba81c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603577755 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_wipe_secret.603577755
Directory /workspace/2.hmac_wipe_secret/latest

Test location /workspace/coverage/default/20.hmac_alert_test.239863486
Short name T492
Test name
Test status
Simulation time 11451865 ps
CPU time 0.58 seconds
Started Jun 30 06:35:16 PM PDT 24
Finished Jun 30 06:35:18 PM PDT 24
Peak memory 195268 kb
Host smart-7580fe1d-4b82-4592-b14f-fd1da59c4880
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239863486 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_alert_test.239863486
Directory /workspace/20.hmac_alert_test/latest

Test location /workspace/coverage/default/20.hmac_back_pressure.2846586590
Short name T25
Test name
Test status
Simulation time 709501973 ps
CPU time 34.64 seconds
Started Jun 30 06:35:18 PM PDT 24
Finished Jun 30 06:35:54 PM PDT 24
Peak memory 200312 kb
Host smart-74a3aeb7-1bd1-4b0e-a945-aa8122e8b97a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2846586590 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_back_pressure.2846586590
Directory /workspace/20.hmac_back_pressure/latest

Test location /workspace/coverage/default/20.hmac_burst_wr.1718027204
Short name T522
Test name
Test status
Simulation time 8876375528 ps
CPU time 63.8 seconds
Started Jun 30 06:35:17 PM PDT 24
Finished Jun 30 06:36:21 PM PDT 24
Peak memory 208608 kb
Host smart-8483821d-a36f-4e0e-865b-cad8770a813e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1718027204 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_burst_wr.1718027204
Directory /workspace/20.hmac_burst_wr/latest

Test location /workspace/coverage/default/20.hmac_datapath_stress.3359758967
Short name T423
Test name
Test status
Simulation time 3428651134 ps
CPU time 876.99 seconds
Started Jun 30 06:35:17 PM PDT 24
Finished Jun 30 06:49:54 PM PDT 24
Peak memory 740152 kb
Host smart-740546cd-bab8-40fb-a5fa-625478b98b53
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3359758967 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_datapath_stress.3359758967
Directory /workspace/20.hmac_datapath_stress/latest

Test location /workspace/coverage/default/20.hmac_error.1801132153
Short name T707
Test name
Test status
Simulation time 2432433059 ps
CPU time 68.6 seconds
Started Jun 30 06:35:17 PM PDT 24
Finished Jun 30 06:36:26 PM PDT 24
Peak memory 200308 kb
Host smart-6d38aaf0-f65c-45ba-96f6-96d6b1274f4b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801132153 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_error.1801132153
Directory /workspace/20.hmac_error/latest

Test location /workspace/coverage/default/20.hmac_long_msg.4289367537
Short name T376
Test name
Test status
Simulation time 1675041810 ps
CPU time 34.7 seconds
Started Jun 30 06:35:19 PM PDT 24
Finished Jun 30 06:35:54 PM PDT 24
Peak memory 200368 kb
Host smart-cf6c839f-9f7f-4dee-a402-956673e14fc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289367537 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_long_msg.4289367537
Directory /workspace/20.hmac_long_msg/latest

Test location /workspace/coverage/default/20.hmac_smoke.3835486956
Short name T15
Test name
Test status
Simulation time 266572058 ps
CPU time 11.48 seconds
Started Jun 30 06:35:16 PM PDT 24
Finished Jun 30 06:35:28 PM PDT 24
Peak memory 200240 kb
Host smart-2a706a68-1e2c-47d2-a3d0-b0b93c47ecc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835486956 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_smoke.3835486956
Directory /workspace/20.hmac_smoke/latest

Test location /workspace/coverage/default/20.hmac_stress_all.2597218146
Short name T66
Test name
Test status
Simulation time 54461580170 ps
CPU time 1891.41 seconds
Started Jun 30 06:35:18 PM PDT 24
Finished Jun 30 07:06:50 PM PDT 24
Peak memory 787348 kb
Host smart-d31d122a-d751-4b0f-849a-3189f9703b38
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597218146 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.hmac_stress_all.2597218146
Directory /workspace/20.hmac_stress_all/latest

Test location /workspace/coverage/default/20.hmac_test_hmac256_vectors.2343658667
Short name T162
Test name
Test status
Simulation time 7332705280 ps
CPU time 27.54 seconds
Started Jun 30 06:35:18 PM PDT 24
Finished Jun 30 06:35:46 PM PDT 24
Peak memory 200288 kb
Host smart-1111e6fe-35ba-468e-b2f1-1a17c4d6c967
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2343658667 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_test_hmac256_vectors.2343658667
Directory /workspace/20.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/20.hmac_test_hmac384_vectors.2816083903
Short name T593
Test name
Test status
Simulation time 17286648072 ps
CPU time 54.66 seconds
Started Jun 30 06:35:17 PM PDT 24
Finished Jun 30 06:36:12 PM PDT 24
Peak memory 200348 kb
Host smart-927a4e02-6157-4edd-8381-97bf82cac33b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2816083903 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_test_hmac384_vectors.2816083903
Directory /workspace/20.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/20.hmac_test_hmac512_vectors.1836809160
Short name T588
Test name
Test status
Simulation time 20994432529 ps
CPU time 117.79 seconds
Started Jun 30 06:35:17 PM PDT 24
Finished Jun 30 06:37:15 PM PDT 24
Peak memory 200376 kb
Host smart-22867c6b-71d8-4311-b8d8-17ed64c8802b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1836809160 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_test_hmac512_vectors.1836809160
Directory /workspace/20.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/20.hmac_test_sha256_vectors.1457177920
Short name T690
Test name
Test status
Simulation time 123993782833 ps
CPU time 487.04 seconds
Started Jun 30 06:35:15 PM PDT 24
Finished Jun 30 06:43:23 PM PDT 24
Peak memory 200268 kb
Host smart-2eb880a5-3ccd-4b75-a473-66ca3a4a557d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1457177920 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_test_sha256_vectors.1457177920
Directory /workspace/20.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/20.hmac_test_sha384_vectors.431529624
Short name T178
Test name
Test status
Simulation time 104757783598 ps
CPU time 1971.08 seconds
Started Jun 30 06:35:16 PM PDT 24
Finished Jun 30 07:08:08 PM PDT 24
Peak memory 216208 kb
Host smart-5deb1325-d408-457d-8947-3af2bef1fd32
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=431529624 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_test_sha384_vectors.431529624
Directory /workspace/20.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/20.hmac_test_sha512_vectors.1858914123
Short name T703
Test name
Test status
Simulation time 68321478549 ps
CPU time 2007.01 seconds
Started Jun 30 06:35:19 PM PDT 24
Finished Jun 30 07:08:46 PM PDT 24
Peak memory 215732 kb
Host smart-573c387d-285f-4452-b448-b6e6cf93047d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1858914123 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_test_sha512_vectors.1858914123
Directory /workspace/20.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/20.hmac_wipe_secret.2802419720
Short name T236
Test name
Test status
Simulation time 2284920276 ps
CPU time 43.21 seconds
Started Jun 30 06:35:18 PM PDT 24
Finished Jun 30 06:36:01 PM PDT 24
Peak memory 200372 kb
Host smart-757d52f5-b178-4005-8b77-d85cdadac1de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802419720 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_wipe_secret.2802419720
Directory /workspace/20.hmac_wipe_secret/latest

Test location /workspace/coverage/default/21.hmac_alert_test.2159457977
Short name T571
Test name
Test status
Simulation time 32308693 ps
CPU time 0.55 seconds
Started Jun 30 06:35:32 PM PDT 24
Finished Jun 30 06:35:33 PM PDT 24
Peak memory 195244 kb
Host smart-9cb9ba54-feb7-40ca-af42-ef20bb8aacc4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159457977 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_alert_test.2159457977
Directory /workspace/21.hmac_alert_test/latest

Test location /workspace/coverage/default/21.hmac_back_pressure.3536863606
Short name T466
Test name
Test status
Simulation time 2474134171 ps
CPU time 57.22 seconds
Started Jun 30 06:35:24 PM PDT 24
Finished Jun 30 06:36:22 PM PDT 24
Peak memory 200380 kb
Host smart-a6cb425d-c9c3-41e9-b372-ed1c2b172709
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3536863606 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_back_pressure.3536863606
Directory /workspace/21.hmac_back_pressure/latest

Test location /workspace/coverage/default/21.hmac_burst_wr.2325697206
Short name T737
Test name
Test status
Simulation time 1385467004 ps
CPU time 4.68 seconds
Started Jun 30 06:35:21 PM PDT 24
Finished Jun 30 06:35:26 PM PDT 24
Peak memory 200328 kb
Host smart-444d5956-9eb3-413f-acc0-b22cd48aeb62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325697206 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_burst_wr.2325697206
Directory /workspace/21.hmac_burst_wr/latest

Test location /workspace/coverage/default/21.hmac_datapath_stress.2787042627
Short name T509
Test name
Test status
Simulation time 10576503794 ps
CPU time 784.09 seconds
Started Jun 30 06:35:22 PM PDT 24
Finished Jun 30 06:48:27 PM PDT 24
Peak memory 756512 kb
Host smart-dcf0e098-c49e-499f-a95c-3a55a81fc340
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2787042627 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_datapath_stress.2787042627
Directory /workspace/21.hmac_datapath_stress/latest

Test location /workspace/coverage/default/21.hmac_error.3369226637
Short name T677
Test name
Test status
Simulation time 12638678184 ps
CPU time 85.16 seconds
Started Jun 30 06:35:23 PM PDT 24
Finished Jun 30 06:36:49 PM PDT 24
Peak memory 200388 kb
Host smart-2502560d-834b-4fab-b1e3-29c2f8452a83
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369226637 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_error.3369226637
Directory /workspace/21.hmac_error/latest

Test location /workspace/coverage/default/21.hmac_long_msg.2844835039
Short name T31
Test name
Test status
Simulation time 5559942807 ps
CPU time 81.19 seconds
Started Jun 30 06:35:20 PM PDT 24
Finished Jun 30 06:36:42 PM PDT 24
Peak memory 200336 kb
Host smart-4a0ea4cc-f857-4bad-b4e3-f321c1496ba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844835039 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_long_msg.2844835039
Directory /workspace/21.hmac_long_msg/latest

Test location /workspace/coverage/default/21.hmac_smoke.3177320979
Short name T615
Test name
Test status
Simulation time 250770442 ps
CPU time 7.95 seconds
Started Jun 30 06:35:23 PM PDT 24
Finished Jun 30 06:35:31 PM PDT 24
Peak memory 200260 kb
Host smart-d868c707-e516-4534-8aee-b64049e47925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177320979 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_smoke.3177320979
Directory /workspace/21.hmac_smoke/latest

Test location /workspace/coverage/default/21.hmac_stress_all.1057589918
Short name T475
Test name
Test status
Simulation time 6154324304 ps
CPU time 549.57 seconds
Started Jun 30 06:35:33 PM PDT 24
Finished Jun 30 06:44:43 PM PDT 24
Peak memory 707628 kb
Host smart-018c7bb6-0c86-48a6-9873-221b149df70a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057589918 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.hmac_stress_all.1057589918
Directory /workspace/21.hmac_stress_all/latest

Test location /workspace/coverage/default/21.hmac_test_hmac256_vectors.1127248659
Short name T567
Test name
Test status
Simulation time 1764160478 ps
CPU time 27.73 seconds
Started Jun 30 06:35:22 PM PDT 24
Finished Jun 30 06:35:51 PM PDT 24
Peak memory 200356 kb
Host smart-777d7940-b8be-4a2e-ae76-ea4f3b1d2e44
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1127248659 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_test_hmac256_vectors.1127248659
Directory /workspace/21.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/21.hmac_test_hmac384_vectors.4258030735
Short name T788
Test name
Test status
Simulation time 24640993174 ps
CPU time 49.44 seconds
Started Jun 30 06:35:23 PM PDT 24
Finished Jun 30 06:36:13 PM PDT 24
Peak memory 200292 kb
Host smart-635893f3-bace-416c-86da-e9ab76e13792
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4258030735 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_test_hmac384_vectors.4258030735
Directory /workspace/21.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/21.hmac_test_hmac512_vectors.706189652
Short name T596
Test name
Test status
Simulation time 24524004573 ps
CPU time 59.87 seconds
Started Jun 30 06:35:28 PM PDT 24
Finished Jun 30 06:36:28 PM PDT 24
Peak memory 200368 kb
Host smart-f42727d6-940b-4fd7-9f06-ae6c1efe4f6d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=706189652 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_test_hmac512_vectors.706189652
Directory /workspace/21.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/21.hmac_test_sha256_vectors.1898540668
Short name T194
Test name
Test status
Simulation time 111879357638 ps
CPU time 510.42 seconds
Started Jun 30 06:35:22 PM PDT 24
Finished Jun 30 06:43:53 PM PDT 24
Peak memory 200292 kb
Host smart-24715a78-2dab-4ec1-af81-bb0211049b7b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1898540668 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_test_sha256_vectors.1898540668
Directory /workspace/21.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/21.hmac_test_sha384_vectors.3277139579
Short name T172
Test name
Test status
Simulation time 596281275101 ps
CPU time 2035.73 seconds
Started Jun 30 06:35:21 PM PDT 24
Finished Jun 30 07:09:18 PM PDT 24
Peak memory 215696 kb
Host smart-accb85ca-747b-4d34-816b-ae5429a2b988
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3277139579 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_test_sha384_vectors.3277139579
Directory /workspace/21.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/21.hmac_test_sha512_vectors.3357688737
Short name T336
Test name
Test status
Simulation time 235649991636 ps
CPU time 2081.3 seconds
Started Jun 30 06:35:24 PM PDT 24
Finished Jun 30 07:10:06 PM PDT 24
Peak memory 216680 kb
Host smart-70eac5ec-6536-41b5-8f17-9b264a3541fc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3357688737 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_test_sha512_vectors.3357688737
Directory /workspace/21.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/21.hmac_wipe_secret.3628068649
Short name T595
Test name
Test status
Simulation time 15505705530 ps
CPU time 107.72 seconds
Started Jun 30 06:35:24 PM PDT 24
Finished Jun 30 06:37:13 PM PDT 24
Peak memory 200428 kb
Host smart-584b5ef6-e46b-42fd-b92c-6a8bccf949fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628068649 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_wipe_secret.3628068649
Directory /workspace/21.hmac_wipe_secret/latest

Test location /workspace/coverage/default/22.hmac_alert_test.729323534
Short name T518
Test name
Test status
Simulation time 38561261 ps
CPU time 0.58 seconds
Started Jun 30 06:35:34 PM PDT 24
Finished Jun 30 06:35:35 PM PDT 24
Peak memory 195264 kb
Host smart-51d1a4b8-90d0-44e9-8f1f-c70722945e7b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729323534 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_alert_test.729323534
Directory /workspace/22.hmac_alert_test/latest

Test location /workspace/coverage/default/22.hmac_back_pressure.2705783622
Short name T73
Test name
Test status
Simulation time 3883967015 ps
CPU time 42.17 seconds
Started Jun 30 06:35:28 PM PDT 24
Finished Jun 30 06:36:11 PM PDT 24
Peak memory 216608 kb
Host smart-f211fc09-7a96-4648-bd02-f590d7395b84
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2705783622 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_back_pressure.2705783622
Directory /workspace/22.hmac_back_pressure/latest

Test location /workspace/coverage/default/22.hmac_burst_wr.3008981562
Short name T359
Test name
Test status
Simulation time 902144878 ps
CPU time 13.61 seconds
Started Jun 30 06:35:28 PM PDT 24
Finished Jun 30 06:35:42 PM PDT 24
Peak memory 200200 kb
Host smart-98af968c-507a-4248-a0f3-ab5b1a8b37f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008981562 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_burst_wr.3008981562
Directory /workspace/22.hmac_burst_wr/latest

Test location /workspace/coverage/default/22.hmac_datapath_stress.567041175
Short name T781
Test name
Test status
Simulation time 3442632851 ps
CPU time 920.54 seconds
Started Jun 30 06:35:28 PM PDT 24
Finished Jun 30 06:50:49 PM PDT 24
Peak memory 771852 kb
Host smart-1e954894-e191-4490-9f79-2a1c936dfcbb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=567041175 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_datapath_stress.567041175
Directory /workspace/22.hmac_datapath_stress/latest

Test location /workspace/coverage/default/22.hmac_error.3193905874
Short name T177
Test name
Test status
Simulation time 8592645521 ps
CPU time 66.34 seconds
Started Jun 30 06:35:28 PM PDT 24
Finished Jun 30 06:36:35 PM PDT 24
Peak memory 200304 kb
Host smart-aa3397b6-8cd5-448d-b791-4a7da96fb04b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193905874 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_error.3193905874
Directory /workspace/22.hmac_error/latest

Test location /workspace/coverage/default/22.hmac_long_msg.1891197154
Short name T696
Test name
Test status
Simulation time 1531869443 ps
CPU time 86.81 seconds
Started Jun 30 06:35:28 PM PDT 24
Finished Jun 30 06:36:55 PM PDT 24
Peak memory 200312 kb
Host smart-dafff4a7-925d-41f1-9a67-b9de9020d7f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891197154 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_long_msg.1891197154
Directory /workspace/22.hmac_long_msg/latest

Test location /workspace/coverage/default/22.hmac_smoke.1457464416
Short name T710
Test name
Test status
Simulation time 3885967183 ps
CPU time 12.25 seconds
Started Jun 30 06:35:33 PM PDT 24
Finished Jun 30 06:35:45 PM PDT 24
Peak memory 200380 kb
Host smart-eb093d20-9120-458e-9976-d2b3e381932d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457464416 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_smoke.1457464416
Directory /workspace/22.hmac_smoke/latest

Test location /workspace/coverage/default/22.hmac_stress_all.4165665030
Short name T773
Test name
Test status
Simulation time 120460462283 ps
CPU time 4883.41 seconds
Started Jun 30 06:35:31 PM PDT 24
Finished Jun 30 07:56:57 PM PDT 24
Peak memory 603220 kb
Host smart-9a40ddc3-a546-46cb-84f2-71550eabb3a8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165665030 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.hmac_stress_all.4165665030
Directory /workspace/22.hmac_stress_all/latest

Test location /workspace/coverage/default/22.hmac_test_hmac256_vectors.1792855854
Short name T274
Test name
Test status
Simulation time 30682614654 ps
CPU time 61.2 seconds
Started Jun 30 06:35:30 PM PDT 24
Finished Jun 30 06:36:31 PM PDT 24
Peak memory 200352 kb
Host smart-d63f6796-e408-4bf3-a5d1-b02d28faaef1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1792855854 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_test_hmac256_vectors.1792855854
Directory /workspace/22.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/22.hmac_test_hmac384_vectors.1469228097
Short name T448
Test name
Test status
Simulation time 7698718732 ps
CPU time 86.38 seconds
Started Jun 30 06:35:29 PM PDT 24
Finished Jun 30 06:36:55 PM PDT 24
Peak memory 200324 kb
Host smart-6d43dc57-ecca-4340-a0cc-f7958c24479c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1469228097 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_test_hmac384_vectors.1469228097
Directory /workspace/22.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/22.hmac_test_hmac512_vectors.1279237073
Short name T199
Test name
Test status
Simulation time 3889312180 ps
CPU time 55.84 seconds
Started Jun 30 06:35:35 PM PDT 24
Finished Jun 30 06:36:31 PM PDT 24
Peak memory 200340 kb
Host smart-f56ba9fe-611e-498b-a497-965dcf8eef24
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1279237073 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_test_hmac512_vectors.1279237073
Directory /workspace/22.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/22.hmac_test_sha256_vectors.2393931311
Short name T396
Test name
Test status
Simulation time 72156539467 ps
CPU time 489.27 seconds
Started Jun 30 06:35:28 PM PDT 24
Finished Jun 30 06:43:38 PM PDT 24
Peak memory 200276 kb
Host smart-f85f1365-ef2d-47e7-b72a-bc9beec508ce
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2393931311 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_test_sha256_vectors.2393931311
Directory /workspace/22.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/22.hmac_test_sha384_vectors.3910556978
Short name T609
Test name
Test status
Simulation time 188901863902 ps
CPU time 1972.38 seconds
Started Jun 30 06:35:33 PM PDT 24
Finished Jun 30 07:08:26 PM PDT 24
Peak memory 215748 kb
Host smart-edfa4cb3-96d4-4bf6-8f65-9fc55699ee27
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3910556978 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_test_sha384_vectors.3910556978
Directory /workspace/22.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/22.hmac_test_sha512_vectors.921299347
Short name T268
Test name
Test status
Simulation time 556063250758 ps
CPU time 1820.14 seconds
Started Jun 30 06:35:29 PM PDT 24
Finished Jun 30 07:05:49 PM PDT 24
Peak memory 215780 kb
Host smart-813ba717-dbb2-40bc-9e71-b5383bc6612c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=921299347 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_test_sha512_vectors.921299347
Directory /workspace/22.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/22.hmac_wipe_secret.3510000182
Short name T426
Test name
Test status
Simulation time 10695404626 ps
CPU time 80.14 seconds
Started Jun 30 06:35:27 PM PDT 24
Finished Jun 30 06:36:48 PM PDT 24
Peak memory 200392 kb
Host smart-1169e8aa-b78a-40e0-8835-5c7b492a42ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510000182 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_wipe_secret.3510000182
Directory /workspace/22.hmac_wipe_secret/latest

Test location /workspace/coverage/default/23.hmac_alert_test.2682633291
Short name T21
Test name
Test status
Simulation time 45594575 ps
CPU time 0.56 seconds
Started Jun 30 06:35:31 PM PDT 24
Finished Jun 30 06:35:32 PM PDT 24
Peak memory 195916 kb
Host smart-e2b6e730-1ca9-48f8-9ed4-a81427d31ecc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682633291 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_alert_test.2682633291
Directory /workspace/23.hmac_alert_test/latest

Test location /workspace/coverage/default/23.hmac_back_pressure.1628248637
Short name T743
Test name
Test status
Simulation time 177964034 ps
CPU time 8.99 seconds
Started Jun 30 06:35:35 PM PDT 24
Finished Jun 30 06:35:45 PM PDT 24
Peak memory 200332 kb
Host smart-964c3972-4f2c-4851-a1fd-08f8e3379dc6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1628248637 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_back_pressure.1628248637
Directory /workspace/23.hmac_back_pressure/latest

Test location /workspace/coverage/default/23.hmac_burst_wr.3533951168
Short name T641
Test name
Test status
Simulation time 12199730704 ps
CPU time 26.58 seconds
Started Jun 30 06:35:41 PM PDT 24
Finished Jun 30 06:36:08 PM PDT 24
Peak memory 200396 kb
Host smart-064705fe-5870-4755-8f29-3aca186f40f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3533951168 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_burst_wr.3533951168
Directory /workspace/23.hmac_burst_wr/latest

Test location /workspace/coverage/default/23.hmac_datapath_stress.1408812578
Short name T508
Test name
Test status
Simulation time 2122572260 ps
CPU time 535.06 seconds
Started Jun 30 06:35:35 PM PDT 24
Finished Jun 30 06:44:30 PM PDT 24
Peak memory 712532 kb
Host smart-990ffad4-7f6e-4248-91b1-f3eaf7d4f84b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1408812578 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_datapath_stress.1408812578
Directory /workspace/23.hmac_datapath_stress/latest

Test location /workspace/coverage/default/23.hmac_error.3715062570
Short name T17
Test name
Test status
Simulation time 5799078678 ps
CPU time 154.13 seconds
Started Jun 30 06:35:38 PM PDT 24
Finished Jun 30 06:38:13 PM PDT 24
Peak memory 200348 kb
Host smart-2fe2cc10-c163-4608-979b-f9e6516f789c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715062570 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_error.3715062570
Directory /workspace/23.hmac_error/latest

Test location /workspace/coverage/default/23.hmac_long_msg.4084546879
Short name T143
Test name
Test status
Simulation time 528023864 ps
CPU time 28.66 seconds
Started Jun 30 06:35:34 PM PDT 24
Finished Jun 30 06:36:03 PM PDT 24
Peak memory 200252 kb
Host smart-7472ab17-24e3-4e11-b025-4575bcbde2a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084546879 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_long_msg.4084546879
Directory /workspace/23.hmac_long_msg/latest

Test location /workspace/coverage/default/23.hmac_smoke.2562013898
Short name T537
Test name
Test status
Simulation time 2301449333 ps
CPU time 12 seconds
Started Jun 30 06:35:38 PM PDT 24
Finished Jun 30 06:35:50 PM PDT 24
Peak memory 200416 kb
Host smart-14229911-4736-4bf5-bd2a-edcaa8656dd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562013898 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_smoke.2562013898
Directory /workspace/23.hmac_smoke/latest

Test location /workspace/coverage/default/23.hmac_test_hmac256_vectors.1909071936
Short name T167
Test name
Test status
Simulation time 15120393302 ps
CPU time 58.58 seconds
Started Jun 30 06:35:37 PM PDT 24
Finished Jun 30 06:36:36 PM PDT 24
Peak memory 200384 kb
Host smart-7e6f1989-ea5b-4240-b451-e581906b947b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1909071936 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_test_hmac256_vectors.1909071936
Directory /workspace/23.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/23.hmac_test_hmac384_vectors.2119385413
Short name T362
Test name
Test status
Simulation time 2000726261 ps
CPU time 70.84 seconds
Started Jun 30 06:35:40 PM PDT 24
Finished Jun 30 06:36:51 PM PDT 24
Peak memory 200268 kb
Host smart-dc97c493-2177-454d-b462-5e473b6fa6a2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2119385413 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_test_hmac384_vectors.2119385413
Directory /workspace/23.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/23.hmac_test_hmac512_vectors.155312693
Short name T206
Test name
Test status
Simulation time 10965264635 ps
CPU time 129.57 seconds
Started Jun 30 06:35:40 PM PDT 24
Finished Jun 30 06:37:50 PM PDT 24
Peak memory 200348 kb
Host smart-25e7ce0b-f3d9-4e2d-868a-f2a4f6a9f314
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=155312693 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_test_hmac512_vectors.155312693
Directory /workspace/23.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/23.hmac_test_sha256_vectors.4219359028
Short name T355
Test name
Test status
Simulation time 36554778246 ps
CPU time 444.47 seconds
Started Jun 30 06:35:35 PM PDT 24
Finished Jun 30 06:43:00 PM PDT 24
Peak memory 200312 kb
Host smart-5803e3d2-f9f1-4bfe-b7d4-9efe715261ae
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=4219359028 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_test_sha256_vectors.4219359028
Directory /workspace/23.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/23.hmac_test_sha384_vectors.1593612384
Short name T656
Test name
Test status
Simulation time 30556729159 ps
CPU time 1698.97 seconds
Started Jun 30 06:35:41 PM PDT 24
Finished Jun 30 07:04:01 PM PDT 24
Peak memory 215888 kb
Host smart-07106267-e51e-44e4-a6d1-ab91bfc01d46
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1593612384 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_test_sha384_vectors.1593612384
Directory /workspace/23.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/23.hmac_test_sha512_vectors.541875624
Short name T644
Test name
Test status
Simulation time 127967348944 ps
CPU time 1852.23 seconds
Started Jun 30 06:35:40 PM PDT 24
Finished Jun 30 07:06:33 PM PDT 24
Peak memory 215944 kb
Host smart-7aabc0ca-22b7-4dc9-b4ae-96abdf65a7b0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=541875624 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_test_sha512_vectors.541875624
Directory /workspace/23.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/23.hmac_wipe_secret.2738451708
Short name T763
Test name
Test status
Simulation time 2875761082 ps
CPU time 39.28 seconds
Started Jun 30 06:35:37 PM PDT 24
Finished Jun 30 06:36:17 PM PDT 24
Peak memory 200392 kb
Host smart-bccce278-cdf0-4de9-a382-bf9d0ff9a29e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2738451708 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_wipe_secret.2738451708
Directory /workspace/23.hmac_wipe_secret/latest

Test location /workspace/coverage/default/24.hmac_alert_test.373693449
Short name T333
Test name
Test status
Simulation time 16006001 ps
CPU time 0.63 seconds
Started Jun 30 06:35:45 PM PDT 24
Finished Jun 30 06:35:46 PM PDT 24
Peak memory 196544 kb
Host smart-cf4d77c8-9bd9-45a4-8677-a1467036abc5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373693449 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_alert_test.373693449
Directory /workspace/24.hmac_alert_test/latest

Test location /workspace/coverage/default/24.hmac_back_pressure.1258973902
Short name T758
Test name
Test status
Simulation time 1139982078 ps
CPU time 25.71 seconds
Started Jun 30 06:35:37 PM PDT 24
Finished Jun 30 06:36:03 PM PDT 24
Peak memory 200360 kb
Host smart-84a97671-2aba-48a7-aa43-a815d9c21e83
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1258973902 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_back_pressure.1258973902
Directory /workspace/24.hmac_back_pressure/latest

Test location /workspace/coverage/default/24.hmac_burst_wr.1407587563
Short name T282
Test name
Test status
Simulation time 3137782692 ps
CPU time 43.65 seconds
Started Jun 30 06:35:40 PM PDT 24
Finished Jun 30 06:36:24 PM PDT 24
Peak memory 200404 kb
Host smart-5af93849-01ab-4bea-842a-562974df7e27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407587563 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_burst_wr.1407587563
Directory /workspace/24.hmac_burst_wr/latest

Test location /workspace/coverage/default/24.hmac_datapath_stress.2819668686
Short name T228
Test name
Test status
Simulation time 4371324486 ps
CPU time 538.82 seconds
Started Jun 30 06:35:39 PM PDT 24
Finished Jun 30 06:44:38 PM PDT 24
Peak memory 725020 kb
Host smart-450a9498-867c-46fa-8aea-4f35af9c0c54
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2819668686 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_datapath_stress.2819668686
Directory /workspace/24.hmac_datapath_stress/latest

Test location /workspace/coverage/default/24.hmac_error.3596131351
Short name T610
Test name
Test status
Simulation time 24642168230 ps
CPU time 122.02 seconds
Started Jun 30 06:35:40 PM PDT 24
Finished Jun 30 06:37:42 PM PDT 24
Peak memory 200364 kb
Host smart-a1d5385c-7b97-4986-ab45-f2395c5d1c01
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596131351 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_error.3596131351
Directory /workspace/24.hmac_error/latest

Test location /workspace/coverage/default/24.hmac_long_msg.1001893045
Short name T266
Test name
Test status
Simulation time 1830628393 ps
CPU time 104.39 seconds
Started Jun 30 06:35:38 PM PDT 24
Finished Jun 30 06:37:22 PM PDT 24
Peak memory 200300 kb
Host smart-734f6196-0a07-4cac-93f5-a9dc62d2c6e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001893045 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_long_msg.1001893045
Directory /workspace/24.hmac_long_msg/latest

Test location /workspace/coverage/default/24.hmac_smoke.46688370
Short name T727
Test name
Test status
Simulation time 347984230 ps
CPU time 8.31 seconds
Started Jun 30 06:35:38 PM PDT 24
Finished Jun 30 06:35:47 PM PDT 24
Peak memory 200348 kb
Host smart-a6e9c3d3-b813-4fe1-9692-2e957a340faf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46688370 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_smoke.46688370
Directory /workspace/24.hmac_smoke/latest

Test location /workspace/coverage/default/24.hmac_stress_all.1352006068
Short name T211
Test name
Test status
Simulation time 124932731497 ps
CPU time 521.83 seconds
Started Jun 30 06:35:43 PM PDT 24
Finished Jun 30 06:44:25 PM PDT 24
Peak memory 200400 kb
Host smart-b7311f52-4e1e-49f8-ac2b-7a9da14ade72
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352006068 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.hmac_stress_all.1352006068
Directory /workspace/24.hmac_stress_all/latest

Test location /workspace/coverage/default/24.hmac_test_hmac256_vectors.45493716
Short name T415
Test name
Test status
Simulation time 909893632 ps
CPU time 28.73 seconds
Started Jun 30 06:35:37 PM PDT 24
Finished Jun 30 06:36:07 PM PDT 24
Peak memory 200308 kb
Host smart-f095417c-f838-4700-b146-1ff3b834decf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=45493716 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_test_hmac256_vectors.45493716
Directory /workspace/24.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/24.hmac_test_hmac384_vectors.2572368468
Short name T352
Test name
Test status
Simulation time 8255905092 ps
CPU time 97.27 seconds
Started Jun 30 06:35:45 PM PDT 24
Finished Jun 30 06:37:23 PM PDT 24
Peak memory 200308 kb
Host smart-0cce4b0b-c451-4684-ab97-99329c8121e1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2572368468 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_test_hmac384_vectors.2572368468
Directory /workspace/24.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/24.hmac_test_hmac512_vectors.1689605473
Short name T725
Test name
Test status
Simulation time 5326132820 ps
CPU time 59.17 seconds
Started Jun 30 06:35:44 PM PDT 24
Finished Jun 30 06:36:44 PM PDT 24
Peak memory 200348 kb
Host smart-c7df6c52-4f90-4a5b-b2ef-7ac14aa1d180
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1689605473 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_test_hmac512_vectors.1689605473
Directory /workspace/24.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/24.hmac_test_sha256_vectors.2993212841
Short name T164
Test name
Test status
Simulation time 40640642123 ps
CPU time 534.73 seconds
Started Jun 30 06:35:45 PM PDT 24
Finished Jun 30 06:44:40 PM PDT 24
Peak memory 200264 kb
Host smart-fe9c754b-b8bd-4bc4-aed9-73ed233ae62c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2993212841 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_test_sha256_vectors.2993212841
Directory /workspace/24.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/24.hmac_test_sha384_vectors.3233664606
Short name T624
Test name
Test status
Simulation time 289890093439 ps
CPU time 2082.22 seconds
Started Jun 30 06:35:40 PM PDT 24
Finished Jun 30 07:10:23 PM PDT 24
Peak memory 208604 kb
Host smart-7194d9e5-1d32-4c0e-bc4d-294681e2a9b2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3233664606 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_test_sha384_vectors.3233664606
Directory /workspace/24.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/24.hmac_wipe_secret.2853012475
Short name T150
Test name
Test status
Simulation time 4760266621 ps
CPU time 77.54 seconds
Started Jun 30 06:35:41 PM PDT 24
Finished Jun 30 06:36:59 PM PDT 24
Peak memory 200400 kb
Host smart-b55e5919-a015-4047-9c2f-ae05fd9c447b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853012475 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_wipe_secret.2853012475
Directory /workspace/24.hmac_wipe_secret/latest

Test location /workspace/coverage/default/25.hmac_alert_test.2815637747
Short name T437
Test name
Test status
Simulation time 13772420 ps
CPU time 0.59 seconds
Started Jun 30 06:35:47 PM PDT 24
Finished Jun 30 06:35:48 PM PDT 24
Peak memory 195864 kb
Host smart-68de2f9d-34c9-4f4d-9daa-f9f16038bd9d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815637747 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_alert_test.2815637747
Directory /workspace/25.hmac_alert_test/latest

Test location /workspace/coverage/default/25.hmac_back_pressure.3580729483
Short name T401
Test name
Test status
Simulation time 5233571245 ps
CPU time 39.47 seconds
Started Jun 30 06:35:43 PM PDT 24
Finished Jun 30 06:36:23 PM PDT 24
Peak memory 208592 kb
Host smart-ff3de525-3f8b-41a0-a911-8ac209e54c57
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3580729483 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_back_pressure.3580729483
Directory /workspace/25.hmac_back_pressure/latest

Test location /workspace/coverage/default/25.hmac_burst_wr.985344439
Short name T471
Test name
Test status
Simulation time 4515005032 ps
CPU time 81.77 seconds
Started Jun 30 06:35:48 PM PDT 24
Finished Jun 30 06:37:10 PM PDT 24
Peak memory 200292 kb
Host smart-001c7dc7-7584-496a-a5e2-1c58858c2f90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985344439 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_burst_wr.985344439
Directory /workspace/25.hmac_burst_wr/latest

Test location /workspace/coverage/default/25.hmac_datapath_stress.2018099084
Short name T422
Test name
Test status
Simulation time 943734216 ps
CPU time 58.54 seconds
Started Jun 30 06:35:53 PM PDT 24
Finished Jun 30 06:36:52 PM PDT 24
Peak memory 349868 kb
Host smart-e9453a90-9a3c-4420-b5c5-c98ec8aa6cab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2018099084 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_datapath_stress.2018099084
Directory /workspace/25.hmac_datapath_stress/latest

Test location /workspace/coverage/default/25.hmac_error.1015769896
Short name T678
Test name
Test status
Simulation time 1595645525 ps
CPU time 6.73 seconds
Started Jun 30 06:35:46 PM PDT 24
Finished Jun 30 06:35:53 PM PDT 24
Peak memory 200148 kb
Host smart-79656b13-08fb-4a9a-8fec-b0d4f88f0fe4
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015769896 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_error.1015769896
Directory /workspace/25.hmac_error/latest

Test location /workspace/coverage/default/25.hmac_long_msg.848450714
Short name T654
Test name
Test status
Simulation time 22885218959 ps
CPU time 86.45 seconds
Started Jun 30 06:35:43 PM PDT 24
Finished Jun 30 06:37:10 PM PDT 24
Peak memory 200340 kb
Host smart-a51cb408-19b1-4bd7-a298-5a0e791fdd80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848450714 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_long_msg.848450714
Directory /workspace/25.hmac_long_msg/latest

Test location /workspace/coverage/default/25.hmac_smoke.4197658414
Short name T233
Test name
Test status
Simulation time 1860597070 ps
CPU time 10.63 seconds
Started Jun 30 06:35:46 PM PDT 24
Finished Jun 30 06:35:58 PM PDT 24
Peak memory 200284 kb
Host smart-f184cf1e-b7bd-4a4b-ac01-92ec2c2226e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4197658414 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_smoke.4197658414
Directory /workspace/25.hmac_smoke/latest

Test location /workspace/coverage/default/25.hmac_stress_all.2539319293
Short name T634
Test name
Test status
Simulation time 3508942567 ps
CPU time 49.79 seconds
Started Jun 30 06:35:57 PM PDT 24
Finished Jun 30 06:36:48 PM PDT 24
Peak memory 200332 kb
Host smart-7b3bcdaf-394d-4419-9cbf-5e9348f49843
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539319293 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.hmac_stress_all.2539319293
Directory /workspace/25.hmac_stress_all/latest

Test location /workspace/coverage/default/25.hmac_test_hmac256_vectors.3029903851
Short name T483
Test name
Test status
Simulation time 941290243 ps
CPU time 26.82 seconds
Started Jun 30 06:35:58 PM PDT 24
Finished Jun 30 06:36:25 PM PDT 24
Peak memory 200312 kb
Host smart-618b1f4d-35a4-4d8c-87b4-d984d56d2fd4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3029903851 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_test_hmac256_vectors.3029903851
Directory /workspace/25.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/25.hmac_test_hmac384_vectors.1923675689
Short name T525
Test name
Test status
Simulation time 3495269652 ps
CPU time 52.8 seconds
Started Jun 30 06:35:48 PM PDT 24
Finished Jun 30 06:36:42 PM PDT 24
Peak memory 200388 kb
Host smart-c2891728-f7e8-493f-a510-0157aca199e7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1923675689 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_test_hmac384_vectors.1923675689
Directory /workspace/25.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/25.hmac_test_hmac512_vectors.1471035887
Short name T382
Test name
Test status
Simulation time 6252822399 ps
CPU time 72.71 seconds
Started Jun 30 06:35:50 PM PDT 24
Finished Jun 30 06:37:03 PM PDT 24
Peak memory 200344 kb
Host smart-04446d9c-0fd0-42d2-885c-1575624e7868
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1471035887 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_test_hmac512_vectors.1471035887
Directory /workspace/25.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/25.hmac_test_sha256_vectors.1591738524
Short name T370
Test name
Test status
Simulation time 28456166000 ps
CPU time 495.07 seconds
Started Jun 30 06:35:52 PM PDT 24
Finished Jun 30 06:44:08 PM PDT 24
Peak memory 200264 kb
Host smart-1cf6876d-7849-4d61-8e0c-cf6460cc6df4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1591738524 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_test_sha256_vectors.1591738524
Directory /workspace/25.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/25.hmac_test_sha384_vectors.348719934
Short name T599
Test name
Test status
Simulation time 211275647771 ps
CPU time 1750.71 seconds
Started Jun 30 06:35:58 PM PDT 24
Finished Jun 30 07:05:09 PM PDT 24
Peak memory 215940 kb
Host smart-a5ac244b-a7ff-4f39-9d90-77b8339b8335
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=348719934 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_test_sha384_vectors.348719934
Directory /workspace/25.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/25.hmac_test_sha512_vectors.2041880696
Short name T454
Test name
Test status
Simulation time 533326684204 ps
CPU time 1923.04 seconds
Started Jun 30 06:35:58 PM PDT 24
Finished Jun 30 07:08:01 PM PDT 24
Peak memory 215736 kb
Host smart-618e186e-23d8-4512-aa3d-c64f6cc1bd2c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2041880696 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_test_sha512_vectors.2041880696
Directory /workspace/25.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/25.hmac_wipe_secret.1757409762
Short name T217
Test name
Test status
Simulation time 3942664102 ps
CPU time 19.32 seconds
Started Jun 30 06:35:45 PM PDT 24
Finished Jun 30 06:36:05 PM PDT 24
Peak memory 200396 kb
Host smart-c0b2ff37-444b-4e39-bab9-3f86cf45821b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757409762 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_wipe_secret.1757409762
Directory /workspace/25.hmac_wipe_secret/latest

Test location /workspace/coverage/default/26.hmac_alert_test.1855328495
Short name T470
Test name
Test status
Simulation time 41639702 ps
CPU time 0.56 seconds
Started Jun 30 06:35:55 PM PDT 24
Finished Jun 30 06:35:56 PM PDT 24
Peak memory 196004 kb
Host smart-83c953a9-086b-47cd-94fc-8ec71f36abad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855328495 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_alert_test.1855328495
Directory /workspace/26.hmac_alert_test/latest

Test location /workspace/coverage/default/26.hmac_back_pressure.1859907030
Short name T75
Test name
Test status
Simulation time 349280469 ps
CPU time 15.38 seconds
Started Jun 30 06:35:57 PM PDT 24
Finished Jun 30 06:36:13 PM PDT 24
Peak memory 200260 kb
Host smart-ca4f27ed-bf0a-44eb-98f0-c7288bccd39a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1859907030 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_back_pressure.1859907030
Directory /workspace/26.hmac_back_pressure/latest

Test location /workspace/coverage/default/26.hmac_burst_wr.2057351627
Short name T785
Test name
Test status
Simulation time 3840812233 ps
CPU time 68.74 seconds
Started Jun 30 06:35:49 PM PDT 24
Finished Jun 30 06:36:59 PM PDT 24
Peak memory 200392 kb
Host smart-eae89137-753f-410c-a223-5ee2aa123056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057351627 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_burst_wr.2057351627
Directory /workspace/26.hmac_burst_wr/latest

Test location /workspace/coverage/default/26.hmac_datapath_stress.1121509105
Short name T219
Test name
Test status
Simulation time 3501061464 ps
CPU time 219.07 seconds
Started Jun 30 06:35:50 PM PDT 24
Finished Jun 30 06:39:30 PM PDT 24
Peak memory 657172 kb
Host smart-3273d093-e857-44ee-b7a8-b330131cf7f2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1121509105 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_datapath_stress.1121509105
Directory /workspace/26.hmac_datapath_stress/latest

Test location /workspace/coverage/default/26.hmac_error.958197736
Short name T594
Test name
Test status
Simulation time 36411688523 ps
CPU time 117.79 seconds
Started Jun 30 06:35:57 PM PDT 24
Finished Jun 30 06:37:55 PM PDT 24
Peak memory 200312 kb
Host smart-eb57f78e-6c85-4ddd-bc1b-b28d64d8699a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958197736 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_error.958197736
Directory /workspace/26.hmac_error/latest

Test location /workspace/coverage/default/26.hmac_long_msg.2086338558
Short name T323
Test name
Test status
Simulation time 40310487328 ps
CPU time 94.85 seconds
Started Jun 30 06:35:49 PM PDT 24
Finished Jun 30 06:37:25 PM PDT 24
Peak memory 200548 kb
Host smart-44fb9874-161a-4d62-8118-936826f7e266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086338558 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_long_msg.2086338558
Directory /workspace/26.hmac_long_msg/latest

Test location /workspace/coverage/default/26.hmac_smoke.542681079
Short name T83
Test name
Test status
Simulation time 879504150 ps
CPU time 8.94 seconds
Started Jun 30 06:35:49 PM PDT 24
Finished Jun 30 06:35:59 PM PDT 24
Peak memory 200348 kb
Host smart-5ffb9a4c-3eaf-4dfd-ba25-3b7d700d0a73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542681079 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_smoke.542681079
Directory /workspace/26.hmac_smoke/latest

Test location /workspace/coverage/default/26.hmac_stress_all.3755931174
Short name T713
Test name
Test status
Simulation time 824885764360 ps
CPU time 2824.07 seconds
Started Jun 30 06:37:24 PM PDT 24
Finished Jun 30 07:24:29 PM PDT 24
Peak memory 216340 kb
Host smart-5e3f9293-05ce-401b-850e-cf6e3b5534eb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755931174 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.hmac_stress_all.3755931174
Directory /workspace/26.hmac_stress_all/latest

Test location /workspace/coverage/default/26.hmac_test_hmac256_vectors.4205717072
Short name T734
Test name
Test status
Simulation time 912934568 ps
CPU time 26.68 seconds
Started Jun 30 06:37:24 PM PDT 24
Finished Jun 30 06:37:51 PM PDT 24
Peak memory 199900 kb
Host smart-20ef8637-25ba-45ee-b0b7-a0546edc06cc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4205717072 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_test_hmac256_vectors.4205717072
Directory /workspace/26.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/26.hmac_test_hmac384_vectors.280268539
Short name T215
Test name
Test status
Simulation time 3906885953 ps
CPU time 52.5 seconds
Started Jun 30 06:35:54 PM PDT 24
Finished Jun 30 06:36:47 PM PDT 24
Peak memory 200340 kb
Host smart-cdea3540-0e89-4290-9b22-d3c9d660829c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=280268539 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_test_hmac384_vectors.280268539
Directory /workspace/26.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/26.hmac_test_hmac512_vectors.3467182080
Short name T631
Test name
Test status
Simulation time 35231367373 ps
CPU time 47.66 seconds
Started Jun 30 06:37:24 PM PDT 24
Finished Jun 30 06:38:12 PM PDT 24
Peak memory 199884 kb
Host smart-486eae3e-993f-4ec5-b056-e8de304eff2d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3467182080 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_test_hmac512_vectors.3467182080
Directory /workspace/26.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/26.hmac_test_sha256_vectors.2629471458
Short name T225
Test name
Test status
Simulation time 25511395656 ps
CPU time 444.22 seconds
Started Jun 30 06:35:54 PM PDT 24
Finished Jun 30 06:43:19 PM PDT 24
Peak memory 200272 kb
Host smart-0cb61ade-c38c-466e-afda-dd2a45aa4980
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2629471458 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_test_sha256_vectors.2629471458
Directory /workspace/26.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/26.hmac_test_sha384_vectors.3856742008
Short name T2
Test name
Test status
Simulation time 103926490905 ps
CPU time 1883.24 seconds
Started Jun 30 06:35:56 PM PDT 24
Finished Jun 30 07:07:20 PM PDT 24
Peak memory 216664 kb
Host smart-0d4572a4-2a67-4eda-826f-73166a879592
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3856742008 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_test_sha384_vectors.3856742008
Directory /workspace/26.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/26.hmac_test_sha512_vectors.2019088144
Short name T365
Test name
Test status
Simulation time 68417989256 ps
CPU time 1554.59 seconds
Started Jun 30 06:35:58 PM PDT 24
Finished Jun 30 07:01:53 PM PDT 24
Peak memory 216268 kb
Host smart-488374b4-eaac-4e0a-8969-27fbe3d4d724
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2019088144 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_test_sha512_vectors.2019088144
Directory /workspace/26.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/26.hmac_wipe_secret.2948195943
Short name T459
Test name
Test status
Simulation time 1182621891 ps
CPU time 15.94 seconds
Started Jun 30 06:37:24 PM PDT 24
Finished Jun 30 06:37:40 PM PDT 24
Peak memory 199828 kb
Host smart-78fafdf7-f5c1-449d-a852-3d7c9e6be6be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948195943 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_wipe_secret.2948195943
Directory /workspace/26.hmac_wipe_secret/latest

Test location /workspace/coverage/default/27.hmac_alert_test.81795492
Short name T351
Test name
Test status
Simulation time 12283045 ps
CPU time 0.57 seconds
Started Jun 30 06:36:00 PM PDT 24
Finished Jun 30 06:36:01 PM PDT 24
Peak memory 196012 kb
Host smart-cf13be83-0e21-4877-8d08-f9e0dcd4e544
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81795492 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_alert_test.81795492
Directory /workspace/27.hmac_alert_test/latest

Test location /workspace/coverage/default/27.hmac_back_pressure.1129517847
Short name T565
Test name
Test status
Simulation time 1132662429 ps
CPU time 9.5 seconds
Started Jun 30 06:37:24 PM PDT 24
Finished Jun 30 06:37:34 PM PDT 24
Peak memory 199820 kb
Host smart-bf61b106-1253-4622-90c1-e511017707ff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1129517847 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_back_pressure.1129517847
Directory /workspace/27.hmac_back_pressure/latest

Test location /workspace/coverage/default/27.hmac_burst_wr.2475630646
Short name T424
Test name
Test status
Simulation time 409859811 ps
CPU time 19.06 seconds
Started Jun 30 06:37:24 PM PDT 24
Finished Jun 30 06:37:44 PM PDT 24
Peak memory 199732 kb
Host smart-2c657d96-12ea-4ffc-9c4b-7c248743cf2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2475630646 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_burst_wr.2475630646
Directory /workspace/27.hmac_burst_wr/latest

Test location /workspace/coverage/default/27.hmac_datapath_stress.685783883
Short name T557
Test name
Test status
Simulation time 5496399993 ps
CPU time 327.28 seconds
Started Jun 30 06:35:56 PM PDT 24
Finished Jun 30 06:41:23 PM PDT 24
Peak memory 672508 kb
Host smart-afdbab0f-c509-4334-aa1b-6b3c89bf157f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=685783883 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_datapath_stress.685783883
Directory /workspace/27.hmac_datapath_stress/latest

Test location /workspace/coverage/default/27.hmac_error.1786644602
Short name T386
Test name
Test status
Simulation time 20676069181 ps
CPU time 142.32 seconds
Started Jun 30 06:36:01 PM PDT 24
Finished Jun 30 06:38:24 PM PDT 24
Peak memory 200344 kb
Host smart-daeb6335-3006-4f62-9999-0cbde9bd935f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786644602 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_error.1786644602
Directory /workspace/27.hmac_error/latest

Test location /workspace/coverage/default/27.hmac_long_msg.2637463089
Short name T32
Test name
Test status
Simulation time 15854591711 ps
CPU time 50.72 seconds
Started Jun 30 06:37:24 PM PDT 24
Finished Jun 30 06:38:15 PM PDT 24
Peak memory 199940 kb
Host smart-5ba39382-4704-4be5-adc8-202d08898d7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637463089 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_long_msg.2637463089
Directory /workspace/27.hmac_long_msg/latest

Test location /workspace/coverage/default/27.hmac_smoke.1729991975
Short name T170
Test name
Test status
Simulation time 28322909 ps
CPU time 0.89 seconds
Started Jun 30 06:35:54 PM PDT 24
Finished Jun 30 06:35:55 PM PDT 24
Peak memory 199604 kb
Host smart-b73f9f10-af60-40c9-a510-cf84cc18b776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729991975 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_smoke.1729991975
Directory /workspace/27.hmac_smoke/latest

Test location /workspace/coverage/default/27.hmac_stress_all.2896435332
Short name T398
Test name
Test status
Simulation time 439302383 ps
CPU time 10.39 seconds
Started Jun 30 06:35:59 PM PDT 24
Finished Jun 30 06:36:10 PM PDT 24
Peak memory 200340 kb
Host smart-9154e172-f34f-4a4a-abe7-cf3174fe3f2c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896435332 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.hmac_stress_all.2896435332
Directory /workspace/27.hmac_stress_all/latest

Test location /workspace/coverage/default/27.hmac_test_hmac256_vectors.3357422772
Short name T675
Test name
Test status
Simulation time 14220023133 ps
CPU time 33.85 seconds
Started Jun 30 06:36:00 PM PDT 24
Finished Jun 30 06:36:34 PM PDT 24
Peak memory 200368 kb
Host smart-6f190cd2-9b27-4b49-b1eb-5981ee41b1b5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3357422772 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_test_hmac256_vectors.3357422772
Directory /workspace/27.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/27.hmac_test_hmac384_vectors.534622429
Short name T349
Test name
Test status
Simulation time 5448289065 ps
CPU time 75.94 seconds
Started Jun 30 06:36:00 PM PDT 24
Finished Jun 30 06:37:17 PM PDT 24
Peak memory 200380 kb
Host smart-29455ec5-386c-4617-92a4-923ae27e728c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=534622429 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_test_hmac384_vectors.534622429
Directory /workspace/27.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/27.hmac_test_hmac512_vectors.606208732
Short name T331
Test name
Test status
Simulation time 12686682109 ps
CPU time 104.73 seconds
Started Jun 30 06:35:59 PM PDT 24
Finished Jun 30 06:37:44 PM PDT 24
Peak memory 200328 kb
Host smart-d78b9546-41fb-4f55-839b-491f64ddb1f0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=606208732 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_test_hmac512_vectors.606208732
Directory /workspace/27.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/27.hmac_test_sha256_vectors.2386079787
Short name T575
Test name
Test status
Simulation time 9054688167 ps
CPU time 511.55 seconds
Started Jun 30 06:36:00 PM PDT 24
Finished Jun 30 06:44:32 PM PDT 24
Peak memory 200304 kb
Host smart-4bfa2fe8-7853-4661-9eb0-638d74de8de3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2386079787 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_test_sha256_vectors.2386079787
Directory /workspace/27.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/27.hmac_test_sha384_vectors.2668903451
Short name T712
Test name
Test status
Simulation time 96055421027 ps
CPU time 1670.48 seconds
Started Jun 30 06:36:00 PM PDT 24
Finished Jun 30 07:03:51 PM PDT 24
Peak memory 216548 kb
Host smart-8f0e9dd1-0034-4430-b50b-2ae03b6653ef
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2668903451 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_test_sha384_vectors.2668903451
Directory /workspace/27.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/27.hmac_test_sha512_vectors.2569888266
Short name T416
Test name
Test status
Simulation time 31160993969 ps
CPU time 1748.69 seconds
Started Jun 30 06:36:02 PM PDT 24
Finished Jun 30 07:05:11 PM PDT 24
Peak memory 215844 kb
Host smart-eb4f33aa-6f78-424b-8c85-0ced9d5609cc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2569888266 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_test_sha512_vectors.2569888266
Directory /workspace/27.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/27.hmac_wipe_secret.4051368917
Short name T507
Test name
Test status
Simulation time 4545029255 ps
CPU time 50.98 seconds
Started Jun 30 06:37:09 PM PDT 24
Finished Jun 30 06:38:01 PM PDT 24
Peak memory 199380 kb
Host smart-7b3e1e2a-b743-41b8-9f4f-8897a348cfd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051368917 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_wipe_secret.4051368917
Directory /workspace/27.hmac_wipe_secret/latest

Test location /workspace/coverage/default/28.hmac_alert_test.2668554727
Short name T744
Test name
Test status
Simulation time 13964808 ps
CPU time 0.6 seconds
Started Jun 30 06:36:08 PM PDT 24
Finished Jun 30 06:36:09 PM PDT 24
Peak memory 196292 kb
Host smart-e9d4f609-6915-4dd0-8f81-9e8c836b598a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668554727 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_alert_test.2668554727
Directory /workspace/28.hmac_alert_test/latest

Test location /workspace/coverage/default/28.hmac_back_pressure.1286516611
Short name T13
Test name
Test status
Simulation time 1023727975 ps
CPU time 46.26 seconds
Started Jun 30 06:36:02 PM PDT 24
Finished Jun 30 06:36:48 PM PDT 24
Peak memory 200284 kb
Host smart-ddabea2f-d851-417e-a309-38e5b92a7f37
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1286516611 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_back_pressure.1286516611
Directory /workspace/28.hmac_back_pressure/latest

Test location /workspace/coverage/default/28.hmac_burst_wr.441354212
Short name T736
Test name
Test status
Simulation time 1116514492 ps
CPU time 63.72 seconds
Started Jun 30 06:36:00 PM PDT 24
Finished Jun 30 06:37:04 PM PDT 24
Peak memory 200308 kb
Host smart-d3758e38-05a7-41e1-ad53-f93abe8c7c8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441354212 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_burst_wr.441354212
Directory /workspace/28.hmac_burst_wr/latest

Test location /workspace/coverage/default/28.hmac_datapath_stress.2449735001
Short name T455
Test name
Test status
Simulation time 6681360263 ps
CPU time 362.18 seconds
Started Jun 30 06:36:03 PM PDT 24
Finished Jun 30 06:42:06 PM PDT 24
Peak memory 629660 kb
Host smart-27f38e19-772d-41ff-af96-9e75837eeac9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2449735001 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_datapath_stress.2449735001
Directory /workspace/28.hmac_datapath_stress/latest

Test location /workspace/coverage/default/28.hmac_error.3038998097
Short name T124
Test name
Test status
Simulation time 5518374482 ps
CPU time 153.7 seconds
Started Jun 30 06:36:02 PM PDT 24
Finished Jun 30 06:38:36 PM PDT 24
Peak memory 200360 kb
Host smart-ca56998f-57df-4113-ad73-8982eeb01086
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038998097 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_error.3038998097
Directory /workspace/28.hmac_error/latest

Test location /workspace/coverage/default/28.hmac_long_msg.306184705
Short name T185
Test name
Test status
Simulation time 627222757 ps
CPU time 3.65 seconds
Started Jun 30 06:36:03 PM PDT 24
Finished Jun 30 06:36:07 PM PDT 24
Peak memory 200268 kb
Host smart-28f4b457-f69f-40e0-8095-22dd0201a04b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306184705 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_long_msg.306184705
Directory /workspace/28.hmac_long_msg/latest

Test location /workspace/coverage/default/28.hmac_smoke.3864585522
Short name T267
Test name
Test status
Simulation time 127182713 ps
CPU time 2.98 seconds
Started Jun 30 06:36:00 PM PDT 24
Finished Jun 30 06:36:04 PM PDT 24
Peak memory 200352 kb
Host smart-f59cc4bd-e5b9-4d91-a52f-76941df41a28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3864585522 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_smoke.3864585522
Directory /workspace/28.hmac_smoke/latest

Test location /workspace/coverage/default/28.hmac_test_hmac256_vectors.2120836192
Short name T549
Test name
Test status
Simulation time 4111479289 ps
CPU time 68.28 seconds
Started Jun 30 06:36:09 PM PDT 24
Finished Jun 30 06:37:18 PM PDT 24
Peak memory 200368 kb
Host smart-c74441fc-d061-43d2-a942-b96dcfabdf1b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2120836192 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_test_hmac256_vectors.2120836192
Directory /workspace/28.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/28.hmac_test_hmac384_vectors.1742425614
Short name T772
Test name
Test status
Simulation time 20444633161 ps
CPU time 85.17 seconds
Started Jun 30 06:36:06 PM PDT 24
Finished Jun 30 06:37:32 PM PDT 24
Peak memory 200420 kb
Host smart-f0722b6a-be3f-4766-a78c-3350de75a48e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1742425614 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_test_hmac384_vectors.1742425614
Directory /workspace/28.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/28.hmac_test_hmac512_vectors.2791122753
Short name T663
Test name
Test status
Simulation time 6871144543 ps
CPU time 103.11 seconds
Started Jun 30 06:36:08 PM PDT 24
Finished Jun 30 06:37:51 PM PDT 24
Peak memory 200308 kb
Host smart-8fbe4b9b-0c43-4b4b-a560-9b239048a156
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2791122753 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_test_hmac512_vectors.2791122753
Directory /workspace/28.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/28.hmac_test_sha256_vectors.2536099330
Short name T187
Test name
Test status
Simulation time 32512689970 ps
CPU time 458.55 seconds
Started Jun 30 06:35:59 PM PDT 24
Finished Jun 30 06:43:38 PM PDT 24
Peak memory 200272 kb
Host smart-5f5fc8b8-83da-4b0d-b2ec-0af3948949fd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2536099330 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_test_sha256_vectors.2536099330
Directory /workspace/28.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/28.hmac_test_sha384_vectors.3190726473
Short name T339
Test name
Test status
Simulation time 29841768185 ps
CPU time 1689.91 seconds
Started Jun 30 06:35:59 PM PDT 24
Finished Jun 30 07:04:09 PM PDT 24
Peak memory 216388 kb
Host smart-f79f05d1-3324-4462-b864-ea74c4e7c806
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3190726473 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_test_sha384_vectors.3190726473
Directory /workspace/28.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/28.hmac_test_sha512_vectors.4019263193
Short name T214
Test name
Test status
Simulation time 555349773280 ps
CPU time 1732.07 seconds
Started Jun 30 06:36:01 PM PDT 24
Finished Jun 30 07:04:54 PM PDT 24
Peak memory 216324 kb
Host smart-90014408-77a9-4026-b349-3bfeaac06d7c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4019263193 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_test_sha512_vectors.4019263193
Directory /workspace/28.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/28.hmac_wipe_secret.999260873
Short name T674
Test name
Test status
Simulation time 1799801515 ps
CPU time 33.49 seconds
Started Jun 30 06:36:02 PM PDT 24
Finished Jun 30 06:36:36 PM PDT 24
Peak memory 200320 kb
Host smart-ce1c3688-09da-49f4-983c-f85eff15baf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999260873 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_wipe_secret.999260873
Directory /workspace/28.hmac_wipe_secret/latest

Test location /workspace/coverage/default/29.hmac_alert_test.1505320954
Short name T1
Test name
Test status
Simulation time 14130218 ps
CPU time 0.66 seconds
Started Jun 30 06:36:13 PM PDT 24
Finished Jun 30 06:36:14 PM PDT 24
Peak memory 196288 kb
Host smart-e8480143-6223-483e-be79-1a6850826ff2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505320954 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_alert_test.1505320954
Directory /workspace/29.hmac_alert_test/latest

Test location /workspace/coverage/default/29.hmac_back_pressure.1827642533
Short name T769
Test name
Test status
Simulation time 300441324 ps
CPU time 7.4 seconds
Started Jun 30 06:36:07 PM PDT 24
Finished Jun 30 06:36:15 PM PDT 24
Peak memory 200272 kb
Host smart-944b3fdd-956c-4436-94fe-c4f8b3246372
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1827642533 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_back_pressure.1827642533
Directory /workspace/29.hmac_back_pressure/latest

Test location /workspace/coverage/default/29.hmac_datapath_stress.3886661804
Short name T224
Test name
Test status
Simulation time 10338720206 ps
CPU time 1405.63 seconds
Started Jun 30 06:36:07 PM PDT 24
Finished Jun 30 06:59:33 PM PDT 24
Peak memory 787432 kb
Host smart-12c633d4-a9e3-4a2c-ba00-cb8913dd274a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3886661804 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_datapath_stress.3886661804
Directory /workspace/29.hmac_datapath_stress/latest

Test location /workspace/coverage/default/29.hmac_error.2628594971
Short name T208
Test name
Test status
Simulation time 9476404450 ps
CPU time 42.61 seconds
Started Jun 30 06:36:10 PM PDT 24
Finished Jun 30 06:36:53 PM PDT 24
Peak memory 200300 kb
Host smart-8c94798b-5575-4ba5-b826-f83d69120e20
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628594971 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_error.2628594971
Directory /workspace/29.hmac_error/latest

Test location /workspace/coverage/default/29.hmac_long_msg.2184984465
Short name T704
Test name
Test status
Simulation time 502018670 ps
CPU time 9.85 seconds
Started Jun 30 06:36:06 PM PDT 24
Finished Jun 30 06:36:16 PM PDT 24
Peak memory 200320 kb
Host smart-ee31bf5b-6986-4c48-ab3a-aa11bc840a00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184984465 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_long_msg.2184984465
Directory /workspace/29.hmac_long_msg/latest

Test location /workspace/coverage/default/29.hmac_smoke.651688735
Short name T249
Test name
Test status
Simulation time 539487601 ps
CPU time 3.34 seconds
Started Jun 30 06:36:09 PM PDT 24
Finished Jun 30 06:36:13 PM PDT 24
Peak memory 200304 kb
Host smart-bc9874e7-4139-4a61-a6cc-e3b970a8f431
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651688735 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_smoke.651688735
Directory /workspace/29.hmac_smoke/latest

Test location /workspace/coverage/default/29.hmac_test_hmac256_vectors.867953065
Short name T501
Test name
Test status
Simulation time 10830279642 ps
CPU time 67.89 seconds
Started Jun 30 06:36:15 PM PDT 24
Finished Jun 30 06:37:23 PM PDT 24
Peak memory 200356 kb
Host smart-2c612643-946b-4103-93b2-8d739f2abca3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=867953065 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_test_hmac256_vectors.867953065
Directory /workspace/29.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/29.hmac_test_hmac384_vectors.1188765695
Short name T527
Test name
Test status
Simulation time 1390975079 ps
CPU time 38.88 seconds
Started Jun 30 06:36:12 PM PDT 24
Finished Jun 30 06:36:51 PM PDT 24
Peak memory 200320 kb
Host smart-e07fc7f6-830c-43d4-9cc6-15aba2b9da9a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1188765695 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_test_hmac384_vectors.1188765695
Directory /workspace/29.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/29.hmac_test_hmac512_vectors.1075320541
Short name T221
Test name
Test status
Simulation time 7044434441 ps
CPU time 56.59 seconds
Started Jun 30 06:36:14 PM PDT 24
Finished Jun 30 06:37:11 PM PDT 24
Peak memory 200360 kb
Host smart-eeb1b284-6267-4e27-afff-1a96b5527d24
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1075320541 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_test_hmac512_vectors.1075320541
Directory /workspace/29.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/29.hmac_test_sha256_vectors.3144537464
Short name T762
Test name
Test status
Simulation time 81735767644 ps
CPU time 461.79 seconds
Started Jun 30 06:36:12 PM PDT 24
Finished Jun 30 06:43:54 PM PDT 24
Peak memory 200284 kb
Host smart-1ec9033e-f7c6-4050-a002-ce1ddbe59153
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3144537464 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_test_sha256_vectors.3144537464
Directory /workspace/29.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/29.hmac_test_sha384_vectors.3619633988
Short name T163
Test name
Test status
Simulation time 219324762935 ps
CPU time 1958.53 seconds
Started Jun 30 06:36:13 PM PDT 24
Finished Jun 30 07:08:52 PM PDT 24
Peak memory 208576 kb
Host smart-d7a81a82-31e1-409f-9d9a-5aa51e3dd064
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3619633988 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_test_sha384_vectors.3619633988
Directory /workspace/29.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/29.hmac_test_sha512_vectors.490338430
Short name T404
Test name
Test status
Simulation time 29278796725 ps
CPU time 1712.8 seconds
Started Jun 30 06:36:14 PM PDT 24
Finished Jun 30 07:04:48 PM PDT 24
Peak memory 208560 kb
Host smart-c3daf035-52c9-472c-a0d4-a9d03acaba40
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=490338430 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_test_sha512_vectors.490338430
Directory /workspace/29.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/29.hmac_wipe_secret.4088464396
Short name T613
Test name
Test status
Simulation time 6301861105 ps
CPU time 74.06 seconds
Started Jun 30 06:36:06 PM PDT 24
Finished Jun 30 06:37:21 PM PDT 24
Peak memory 200392 kb
Host smart-7e3d20eb-0df9-4681-88b0-a87335c4d7a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088464396 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_wipe_secret.4088464396
Directory /workspace/29.hmac_wipe_secret/latest

Test location /workspace/coverage/default/3.hmac_alert_test.1069273836
Short name T630
Test name
Test status
Simulation time 14018057 ps
CPU time 0.61 seconds
Started Jun 30 06:34:27 PM PDT 24
Finished Jun 30 06:34:28 PM PDT 24
Peak memory 196228 kb
Host smart-d713c652-bfa0-4cc1-a236-faa9fedd1720
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069273836 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_alert_test.1069273836
Directory /workspace/3.hmac_alert_test/latest

Test location /workspace/coverage/default/3.hmac_back_pressure.2025454643
Short name T504
Test name
Test status
Simulation time 5986532070 ps
CPU time 55.37 seconds
Started Jun 30 06:34:14 PM PDT 24
Finished Jun 30 06:35:10 PM PDT 24
Peak memory 200360 kb
Host smart-908fb9dc-7b7b-4197-af55-c2ca8c783569
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2025454643 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_back_pressure.2025454643
Directory /workspace/3.hmac_back_pressure/latest

Test location /workspace/coverage/default/3.hmac_burst_wr.1021096220
Short name T446
Test name
Test status
Simulation time 330705231 ps
CPU time 9.68 seconds
Started Jun 30 06:34:15 PM PDT 24
Finished Jun 30 06:34:25 PM PDT 24
Peak memory 200312 kb
Host smart-ceef1fd6-19c1-4d7a-b456-aa1bd24222d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021096220 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_burst_wr.1021096220
Directory /workspace/3.hmac_burst_wr/latest

Test location /workspace/coverage/default/3.hmac_datapath_stress.440299721
Short name T502
Test name
Test status
Simulation time 38653472737 ps
CPU time 779.19 seconds
Started Jun 30 06:34:15 PM PDT 24
Finished Jun 30 06:47:14 PM PDT 24
Peak memory 711600 kb
Host smart-0b2ef415-6e44-4951-80ff-716363756b36
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=440299721 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_datapath_stress.440299721
Directory /workspace/3.hmac_datapath_stress/latest

Test location /workspace/coverage/default/3.hmac_error.3414276201
Short name T775
Test name
Test status
Simulation time 1232455640 ps
CPU time 34.21 seconds
Started Jun 30 06:34:21 PM PDT 24
Finished Jun 30 06:34:56 PM PDT 24
Peak memory 200260 kb
Host smart-9075baba-15d3-409d-a799-6e7cf44595c3
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414276201 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_error.3414276201
Directory /workspace/3.hmac_error/latest

Test location /workspace/coverage/default/3.hmac_long_msg.2271215817
Short name T204
Test name
Test status
Simulation time 1970864403 ps
CPU time 28.03 seconds
Started Jun 30 06:34:15 PM PDT 24
Finished Jun 30 06:34:44 PM PDT 24
Peak memory 200328 kb
Host smart-bb2d2f79-ed40-4595-9d65-be726daad687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271215817 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_long_msg.2271215817
Directory /workspace/3.hmac_long_msg/latest

Test location /workspace/coverage/default/3.hmac_sec_cm.188284531
Short name T37
Test name
Test status
Simulation time 100771734 ps
CPU time 0.9 seconds
Started Jun 30 06:34:15 PM PDT 24
Finished Jun 30 06:34:16 PM PDT 24
Peak memory 218760 kb
Host smart-9553069f-764c-4d73-bfcf-7253f5f75bd2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188284531 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_sec_cm.188284531
Directory /workspace/3.hmac_sec_cm/latest

Test location /workspace/coverage/default/3.hmac_smoke.4000495833
Short name T563
Test name
Test status
Simulation time 471211188 ps
CPU time 10.63 seconds
Started Jun 30 06:34:12 PM PDT 24
Finished Jun 30 06:34:23 PM PDT 24
Peak memory 200352 kb
Host smart-40035802-3eb6-4838-a95b-23d77f72b57b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000495833 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_smoke.4000495833
Directory /workspace/3.hmac_smoke/latest

Test location /workspace/coverage/default/3.hmac_stress_all.424264624
Short name T765
Test name
Test status
Simulation time 127258975856 ps
CPU time 2211.76 seconds
Started Jun 30 06:34:14 PM PDT 24
Finished Jun 30 07:11:07 PM PDT 24
Peak memory 216784 kb
Host smart-052ed878-8fc3-4da2-b8fd-6f9871284007
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424264624 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all.424264624
Directory /workspace/3.hmac_stress_all/latest

Test location /workspace/coverage/default/3.hmac_test_hmac256_vectors.3604746497
Short name T389
Test name
Test status
Simulation time 19444178780 ps
CPU time 57.45 seconds
Started Jun 30 06:34:27 PM PDT 24
Finished Jun 30 06:35:25 PM PDT 24
Peak memory 200240 kb
Host smart-d4e415a0-7ff2-43d7-9c27-10e4a40bb4ca
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3604746497 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac256_vectors.3604746497
Directory /workspace/3.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_hmac384_vectors.3831990941
Short name T348
Test name
Test status
Simulation time 12939833345 ps
CPU time 87.69 seconds
Started Jun 30 06:34:15 PM PDT 24
Finished Jun 30 06:35:44 PM PDT 24
Peak memory 200348 kb
Host smart-11f8b992-c100-41a1-b732-e6868d767367
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3831990941 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac384_vectors.3831990941
Directory /workspace/3.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_hmac512_vectors.275040891
Short name T223
Test name
Test status
Simulation time 25148934543 ps
CPU time 72.39 seconds
Started Jun 30 06:34:17 PM PDT 24
Finished Jun 30 06:35:30 PM PDT 24
Peak memory 200376 kb
Host smart-d8cf1d12-a944-4973-a136-ad22602c4aa8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=275040891 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac512_vectors.275040891
Directory /workspace/3.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha256_vectors.3944007532
Short name T255
Test name
Test status
Simulation time 81608231801 ps
CPU time 501.28 seconds
Started Jun 30 06:34:19 PM PDT 24
Finished Jun 30 06:42:41 PM PDT 24
Peak memory 200268 kb
Host smart-ada00d4f-bcd7-46f6-915d-7abe97cb5aaa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3944007532 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha256_vectors.3944007532
Directory /workspace/3.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha384_vectors.2021339963
Short name T364
Test name
Test status
Simulation time 153229572856 ps
CPU time 1960.22 seconds
Started Jun 30 06:34:16 PM PDT 24
Finished Jun 30 07:06:57 PM PDT 24
Peak memory 216260 kb
Host smart-978bff56-4179-45af-be70-46151486e61e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2021339963 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha384_vectors.2021339963
Directory /workspace/3.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha512_vectors.624514627
Short name T393
Test name
Test status
Simulation time 170328952310 ps
CPU time 2203.15 seconds
Started Jun 30 06:34:17 PM PDT 24
Finished Jun 30 07:11:00 PM PDT 24
Peak memory 216484 kb
Host smart-00eb417d-bae2-4d34-8925-ab410b9cfaf9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=624514627 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha512_vectors.624514627
Directory /workspace/3.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/3.hmac_wipe_secret.1045641127
Short name T118
Test name
Test status
Simulation time 1364270050 ps
CPU time 52.03 seconds
Started Jun 30 06:34:17 PM PDT 24
Finished Jun 30 06:35:09 PM PDT 24
Peak memory 200260 kb
Host smart-e0c6c4d6-3bbd-4445-8910-70f2bfe31343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045641127 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_wipe_secret.1045641127
Directory /workspace/3.hmac_wipe_secret/latest

Test location /workspace/coverage/default/30.hmac_alert_test.2283299281
Short name T721
Test name
Test status
Simulation time 44059692 ps
CPU time 0.58 seconds
Started Jun 30 06:36:18 PM PDT 24
Finished Jun 30 06:36:19 PM PDT 24
Peak memory 196360 kb
Host smart-a470f109-0e1b-4879-915a-c2aa8f59db7d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283299281 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_alert_test.2283299281
Directory /workspace/30.hmac_alert_test/latest

Test location /workspace/coverage/default/30.hmac_back_pressure.987553929
Short name T600
Test name
Test status
Simulation time 3408282714 ps
CPU time 41.75 seconds
Started Jun 30 06:36:12 PM PDT 24
Finished Jun 30 06:36:55 PM PDT 24
Peak memory 200588 kb
Host smart-79b38f5e-d2c3-41e1-aa04-988d67207ebe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=987553929 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_back_pressure.987553929
Directory /workspace/30.hmac_back_pressure/latest

Test location /workspace/coverage/default/30.hmac_burst_wr.1078549225
Short name T57
Test name
Test status
Simulation time 2575736250 ps
CPU time 34.99 seconds
Started Jun 30 06:36:15 PM PDT 24
Finished Jun 30 06:36:51 PM PDT 24
Peak memory 200336 kb
Host smart-7df77a55-60ae-499d-9925-f548348751a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078549225 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_burst_wr.1078549225
Directory /workspace/30.hmac_burst_wr/latest

Test location /workspace/coverage/default/30.hmac_datapath_stress.3606441145
Short name T201
Test name
Test status
Simulation time 16952681843 ps
CPU time 1268.46 seconds
Started Jun 30 06:36:11 PM PDT 24
Finished Jun 30 06:57:20 PM PDT 24
Peak memory 788812 kb
Host smart-f079135c-25fc-4ae5-b947-0d92e45dd916
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3606441145 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_datapath_stress.3606441145
Directory /workspace/30.hmac_datapath_stress/latest

Test location /workspace/coverage/default/30.hmac_error.750143697
Short name T777
Test name
Test status
Simulation time 14752186210 ps
CPU time 77.62 seconds
Started Jun 30 06:36:11 PM PDT 24
Finished Jun 30 06:37:29 PM PDT 24
Peak memory 200360 kb
Host smart-3987c9a0-44da-4eac-8f74-4bdf60429cf5
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750143697 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_error.750143697
Directory /workspace/30.hmac_error/latest

Test location /workspace/coverage/default/30.hmac_long_msg.1099968096
Short name T318
Test name
Test status
Simulation time 38856201777 ps
CPU time 110.09 seconds
Started Jun 30 06:36:10 PM PDT 24
Finished Jun 30 06:38:00 PM PDT 24
Peak memory 200412 kb
Host smart-f0e6a7d6-70f6-4b76-84f9-ebee0f09aade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099968096 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_long_msg.1099968096
Directory /workspace/30.hmac_long_msg/latest

Test location /workspace/coverage/default/30.hmac_smoke.1728015506
Short name T320
Test name
Test status
Simulation time 4242215176 ps
CPU time 18.7 seconds
Started Jun 30 06:36:11 PM PDT 24
Finished Jun 30 06:36:31 PM PDT 24
Peak memory 200532 kb
Host smart-66ea3f16-60d3-4bb4-8b83-dacc13f4dd44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728015506 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_smoke.1728015506
Directory /workspace/30.hmac_smoke/latest

Test location /workspace/coverage/default/30.hmac_stress_all.2562938511
Short name T125
Test name
Test status
Simulation time 35807655056 ps
CPU time 4515.58 seconds
Started Jun 30 06:36:18 PM PDT 24
Finished Jun 30 07:51:35 PM PDT 24
Peak memory 864396 kb
Host smart-4937c310-e1f8-468e-9809-8f02c664de38
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562938511 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.hmac_stress_all.2562938511
Directory /workspace/30.hmac_stress_all/latest

Test location /workspace/coverage/default/30.hmac_test_hmac256_vectors.3615531717
Short name T381
Test name
Test status
Simulation time 12468465240 ps
CPU time 35.65 seconds
Started Jun 30 06:36:18 PM PDT 24
Finished Jun 30 06:36:55 PM PDT 24
Peak memory 200400 kb
Host smart-c93aa78a-9e4b-4663-bb44-e35a2115b67c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3615531717 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_test_hmac256_vectors.3615531717
Directory /workspace/30.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/30.hmac_test_hmac384_vectors.47313477
Short name T676
Test name
Test status
Simulation time 1425793462 ps
CPU time 39.03 seconds
Started Jun 30 06:36:19 PM PDT 24
Finished Jun 30 06:36:59 PM PDT 24
Peak memory 200308 kb
Host smart-c2954a0c-24fc-4837-a1f0-67beaf119215
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=47313477 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_test_hmac384_vectors.47313477
Directory /workspace/30.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/30.hmac_test_hmac512_vectors.1081034017
Short name T521
Test name
Test status
Simulation time 10809228403 ps
CPU time 122.85 seconds
Started Jun 30 06:36:19 PM PDT 24
Finished Jun 30 06:38:22 PM PDT 24
Peak memory 200380 kb
Host smart-fa6234fa-8268-4ec7-8864-37402a1c3358
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1081034017 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_test_hmac512_vectors.1081034017
Directory /workspace/30.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/30.hmac_test_sha256_vectors.1826730784
Short name T685
Test name
Test status
Simulation time 9026478302 ps
CPU time 488.49 seconds
Started Jun 30 06:36:12 PM PDT 24
Finished Jun 30 06:44:21 PM PDT 24
Peak memory 200296 kb
Host smart-d846ec5e-9c25-40da-97d2-71cd8f2a02ca
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1826730784 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_test_sha256_vectors.1826730784
Directory /workspace/30.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/30.hmac_test_sha384_vectors.1779751441
Short name T754
Test name
Test status
Simulation time 561695746642 ps
CPU time 1896.97 seconds
Started Jun 30 06:36:10 PM PDT 24
Finished Jun 30 07:07:48 PM PDT 24
Peak memory 216488 kb
Host smart-ea2afcc0-282f-4f4d-80bc-f14fe1d45abe
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1779751441 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_test_sha384_vectors.1779751441
Directory /workspace/30.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/30.hmac_test_sha512_vectors.3356105433
Short name T427
Test name
Test status
Simulation time 623548864179 ps
CPU time 1960.91 seconds
Started Jun 30 06:36:12 PM PDT 24
Finished Jun 30 07:08:54 PM PDT 24
Peak memory 215868 kb
Host smart-167192cd-05bc-4c84-9f51-7c2549c13ddd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3356105433 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_test_sha512_vectors.3356105433
Directory /workspace/30.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/30.hmac_wipe_secret.3355171750
Short name T590
Test name
Test status
Simulation time 16052889595 ps
CPU time 59.86 seconds
Started Jun 30 06:36:11 PM PDT 24
Finished Jun 30 06:37:11 PM PDT 24
Peak memory 200352 kb
Host smart-8bcd391e-f6bb-4903-aca0-e89eda9b01f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355171750 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_wipe_secret.3355171750
Directory /workspace/30.hmac_wipe_secret/latest

Test location /workspace/coverage/default/31.hmac_alert_test.210673056
Short name T745
Test name
Test status
Simulation time 54624680 ps
CPU time 0.55 seconds
Started Jun 30 06:36:17 PM PDT 24
Finished Jun 30 06:36:18 PM PDT 24
Peak memory 195260 kb
Host smart-c1c4dbf2-52eb-44cf-9b6b-a759795cc390
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210673056 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_alert_test.210673056
Directory /workspace/31.hmac_alert_test/latest

Test location /workspace/coverage/default/31.hmac_back_pressure.2648888279
Short name T344
Test name
Test status
Simulation time 2230706165 ps
CPU time 32 seconds
Started Jun 30 06:36:22 PM PDT 24
Finished Jun 30 06:36:54 PM PDT 24
Peak memory 200368 kb
Host smart-53490630-a545-456d-9bd3-5e2531e71616
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2648888279 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_back_pressure.2648888279
Directory /workspace/31.hmac_back_pressure/latest

Test location /workspace/coverage/default/31.hmac_burst_wr.1820391061
Short name T145
Test name
Test status
Simulation time 473822279 ps
CPU time 12.58 seconds
Started Jun 30 06:36:18 PM PDT 24
Finished Jun 30 06:36:31 PM PDT 24
Peak memory 200364 kb
Host smart-38c81b4d-4058-414c-9115-f9b33a4a622f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820391061 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_burst_wr.1820391061
Directory /workspace/31.hmac_burst_wr/latest

Test location /workspace/coverage/default/31.hmac_datapath_stress.4027811699
Short name T308
Test name
Test status
Simulation time 4056990051 ps
CPU time 1025.3 seconds
Started Jun 30 06:36:18 PM PDT 24
Finished Jun 30 06:53:24 PM PDT 24
Peak memory 738796 kb
Host smart-e0fcdcb5-d620-4a3f-b105-e1d09767db3f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4027811699 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_datapath_stress.4027811699
Directory /workspace/31.hmac_datapath_stress/latest

Test location /workspace/coverage/default/31.hmac_error.2154826327
Short name T581
Test name
Test status
Simulation time 2826883771 ps
CPU time 25.41 seconds
Started Jun 30 06:36:17 PM PDT 24
Finished Jun 30 06:36:43 PM PDT 24
Peak memory 200396 kb
Host smart-e543816d-f037-430e-91f1-e888f3a09597
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154826327 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_error.2154826327
Directory /workspace/31.hmac_error/latest

Test location /workspace/coverage/default/31.hmac_long_msg.3019565170
Short name T550
Test name
Test status
Simulation time 2887848099 ps
CPU time 10.09 seconds
Started Jun 30 06:36:17 PM PDT 24
Finished Jun 30 06:36:28 PM PDT 24
Peak memory 200364 kb
Host smart-b1c66646-e843-42f4-889c-ed3c24a5ca1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3019565170 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_long_msg.3019565170
Directory /workspace/31.hmac_long_msg/latest

Test location /workspace/coverage/default/31.hmac_smoke.2374805219
Short name T652
Test name
Test status
Simulation time 908629292 ps
CPU time 11.31 seconds
Started Jun 30 06:36:17 PM PDT 24
Finished Jun 30 06:36:28 PM PDT 24
Peak memory 200388 kb
Host smart-1169592d-4a43-445a-a77f-c102cf8597df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374805219 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_smoke.2374805219
Directory /workspace/31.hmac_smoke/latest

Test location /workspace/coverage/default/31.hmac_test_hmac256_vectors.640239207
Short name T149
Test name
Test status
Simulation time 7650246288 ps
CPU time 56.8 seconds
Started Jun 30 06:36:16 PM PDT 24
Finished Jun 30 06:37:13 PM PDT 24
Peak memory 200376 kb
Host smart-a70131af-2a78-46d7-ba40-774956bd53eb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=640239207 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_test_hmac256_vectors.640239207
Directory /workspace/31.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/31.hmac_test_hmac384_vectors.3734018901
Short name T151
Test name
Test status
Simulation time 5460222082 ps
CPU time 40.46 seconds
Started Jun 30 06:36:16 PM PDT 24
Finished Jun 30 06:36:57 PM PDT 24
Peak memory 200428 kb
Host smart-1910a1b2-65c7-49ff-9410-e67d88a93bb0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3734018901 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_test_hmac384_vectors.3734018901
Directory /workspace/31.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/31.hmac_test_hmac512_vectors.818138402
Short name T717
Test name
Test status
Simulation time 5510733833 ps
CPU time 108.75 seconds
Started Jun 30 06:36:20 PM PDT 24
Finished Jun 30 06:38:09 PM PDT 24
Peak memory 200428 kb
Host smart-22ce24e3-8b1a-4373-95ce-caf0b72bf950
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=818138402 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_test_hmac512_vectors.818138402
Directory /workspace/31.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/31.hmac_test_sha256_vectors.1880744026
Short name T648
Test name
Test status
Simulation time 49740047936 ps
CPU time 423.65 seconds
Started Jun 30 06:36:18 PM PDT 24
Finished Jun 30 06:43:22 PM PDT 24
Peak memory 200220 kb
Host smart-69db850b-b05d-48f7-a96f-1d65d92fc41e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1880744026 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_test_sha256_vectors.1880744026
Directory /workspace/31.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/31.hmac_test_sha384_vectors.2832551183
Short name T441
Test name
Test status
Simulation time 64392383920 ps
CPU time 1858.39 seconds
Started Jun 30 06:36:18 PM PDT 24
Finished Jun 30 07:07:17 PM PDT 24
Peak memory 216264 kb
Host smart-ad1a2663-85ff-472f-8f83-509e92cac595
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2832551183 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_test_sha384_vectors.2832551183
Directory /workspace/31.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/31.hmac_test_sha512_vectors.3508379114
Short name T183
Test name
Test status
Simulation time 437940755598 ps
CPU time 2010.83 seconds
Started Jun 30 06:36:18 PM PDT 24
Finished Jun 30 07:09:50 PM PDT 24
Peak memory 216380 kb
Host smart-8f9c04c6-6460-43f5-a147-8db461fa21dc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3508379114 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_test_sha512_vectors.3508379114
Directory /workspace/31.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/31.hmac_wipe_secret.2059743335
Short name T604
Test name
Test status
Simulation time 7044375251 ps
CPU time 64.9 seconds
Started Jun 30 06:36:19 PM PDT 24
Finished Jun 30 06:37:24 PM PDT 24
Peak memory 200300 kb
Host smart-3c89cbb5-0433-4580-8ade-fddfeb9d0b2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059743335 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_wipe_secret.2059743335
Directory /workspace/31.hmac_wipe_secret/latest

Test location /workspace/coverage/default/32.hmac_alert_test.3556227775
Short name T428
Test name
Test status
Simulation time 12909659 ps
CPU time 0.58 seconds
Started Jun 30 06:36:21 PM PDT 24
Finished Jun 30 06:36:22 PM PDT 24
Peak memory 197004 kb
Host smart-52f63a9e-583f-47dc-b535-d43fcb5efd9c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556227775 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_alert_test.3556227775
Directory /workspace/32.hmac_alert_test/latest

Test location /workspace/coverage/default/32.hmac_back_pressure.2484151035
Short name T6
Test name
Test status
Simulation time 2783172377 ps
CPU time 34.76 seconds
Started Jun 30 06:36:26 PM PDT 24
Finished Jun 30 06:37:01 PM PDT 24
Peak memory 200392 kb
Host smart-3d87191d-000f-47b2-9a51-6030679e5f83
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2484151035 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_back_pressure.2484151035
Directory /workspace/32.hmac_back_pressure/latest

Test location /workspace/coverage/default/32.hmac_burst_wr.4044301494
Short name T81
Test name
Test status
Simulation time 1058308549 ps
CPU time 4.56 seconds
Started Jun 30 06:36:21 PM PDT 24
Finished Jun 30 06:36:26 PM PDT 24
Peak memory 200248 kb
Host smart-fef2c331-23f5-4749-bcb6-ad769dcbef1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044301494 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_burst_wr.4044301494
Directory /workspace/32.hmac_burst_wr/latest

Test location /workspace/coverage/default/32.hmac_datapath_stress.1979338675
Short name T718
Test name
Test status
Simulation time 2632141607 ps
CPU time 562.66 seconds
Started Jun 30 06:36:21 PM PDT 24
Finished Jun 30 06:45:44 PM PDT 24
Peak memory 662572 kb
Host smart-850c648e-4d3a-48dc-b1e7-55a6b256855c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1979338675 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_datapath_stress.1979338675
Directory /workspace/32.hmac_datapath_stress/latest

Test location /workspace/coverage/default/32.hmac_error.29345232
Short name T619
Test name
Test status
Simulation time 5513800828 ps
CPU time 154.03 seconds
Started Jun 30 06:36:23 PM PDT 24
Finished Jun 30 06:38:58 PM PDT 24
Peak memory 200424 kb
Host smart-9d44be8d-597d-44cc-8255-2cdb9553d43e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29345232 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_error.29345232
Directory /workspace/32.hmac_error/latest

Test location /workspace/coverage/default/32.hmac_long_msg.2754951722
Short name T241
Test name
Test status
Simulation time 1498759869 ps
CPU time 41.35 seconds
Started Jun 30 06:36:17 PM PDT 24
Finished Jun 30 06:36:59 PM PDT 24
Peak memory 200328 kb
Host smart-c8c29d09-45b9-4dc1-96cb-57009cd7168e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754951722 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_long_msg.2754951722
Directory /workspace/32.hmac_long_msg/latest

Test location /workspace/coverage/default/32.hmac_smoke.2439628877
Short name T726
Test name
Test status
Simulation time 2090788039 ps
CPU time 8.37 seconds
Started Jun 30 06:36:21 PM PDT 24
Finished Jun 30 06:36:30 PM PDT 24
Peak memory 200380 kb
Host smart-c5fbc656-7d9b-426c-a94e-79f181fd0f12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2439628877 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_smoke.2439628877
Directory /workspace/32.hmac_smoke/latest

Test location /workspace/coverage/default/32.hmac_test_hmac256_vectors.490433151
Short name T425
Test name
Test status
Simulation time 3671700039 ps
CPU time 31 seconds
Started Jun 30 06:36:24 PM PDT 24
Finished Jun 30 06:36:55 PM PDT 24
Peak memory 200572 kb
Host smart-ed2bf3f1-8743-4003-89cd-32ef96df2aeb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=490433151 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_test_hmac256_vectors.490433151
Directory /workspace/32.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/32.hmac_test_hmac384_vectors.1488099004
Short name T705
Test name
Test status
Simulation time 7227570651 ps
CPU time 49.26 seconds
Started Jun 30 06:36:30 PM PDT 24
Finished Jun 30 06:37:19 PM PDT 24
Peak memory 200356 kb
Host smart-250832d1-94a6-49f9-863e-44297124bd1f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1488099004 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_test_hmac384_vectors.1488099004
Directory /workspace/32.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/32.hmac_test_hmac512_vectors.2218018864
Short name T439
Test name
Test status
Simulation time 13788351023 ps
CPU time 104.73 seconds
Started Jun 30 06:36:21 PM PDT 24
Finished Jun 30 06:38:06 PM PDT 24
Peak memory 200332 kb
Host smart-f9e4adf6-4c7d-4429-9c11-82f165f76ea3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2218018864 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_test_hmac512_vectors.2218018864
Directory /workspace/32.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/32.hmac_test_sha256_vectors.2495118862
Short name T516
Test name
Test status
Simulation time 27442544403 ps
CPU time 481.45 seconds
Started Jun 30 06:36:25 PM PDT 24
Finished Jun 30 06:44:27 PM PDT 24
Peak memory 200328 kb
Host smart-c5a8fdd2-7f47-4c4e-9169-2719d5305bc3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2495118862 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_test_sha256_vectors.2495118862
Directory /workspace/32.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/32.hmac_test_sha384_vectors.1759602109
Short name T28
Test name
Test status
Simulation time 117452697169 ps
CPU time 1719.9 seconds
Started Jun 30 06:36:23 PM PDT 24
Finished Jun 30 07:05:03 PM PDT 24
Peak memory 215940 kb
Host smart-4c0d68c6-6aa5-4947-9d88-b801f4733145
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1759602109 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_test_sha384_vectors.1759602109
Directory /workspace/32.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/32.hmac_test_sha512_vectors.2299087502
Short name T757
Test name
Test status
Simulation time 156318411341 ps
CPU time 2031.11 seconds
Started Jun 30 06:36:22 PM PDT 24
Finished Jun 30 07:10:14 PM PDT 24
Peak memory 216656 kb
Host smart-93a889f1-94c6-43e5-9b2d-b61e9c33f04f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2299087502 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_test_sha512_vectors.2299087502
Directory /workspace/32.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/32.hmac_wipe_secret.2066273265
Short name T335
Test name
Test status
Simulation time 7332830571 ps
CPU time 50.52 seconds
Started Jun 30 06:36:23 PM PDT 24
Finished Jun 30 06:37:14 PM PDT 24
Peak memory 200400 kb
Host smart-86360eb7-27a7-4d38-ba2a-106d9b50211d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066273265 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_wipe_secret.2066273265
Directory /workspace/32.hmac_wipe_secret/latest

Test location /workspace/coverage/default/33.hmac_alert_test.216779
Short name T277
Test name
Test status
Simulation time 30444634 ps
CPU time 0.58 seconds
Started Jun 30 06:36:30 PM PDT 24
Finished Jun 30 06:36:31 PM PDT 24
Peak memory 196324 kb
Host smart-99fe99c5-c9bc-4c48-8a8d-21a5622a457f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216779 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_alert_test.216779
Directory /workspace/33.hmac_alert_test/latest

Test location /workspace/coverage/default/33.hmac_back_pressure.37079593
Short name T440
Test name
Test status
Simulation time 1710865212 ps
CPU time 19 seconds
Started Jun 30 06:36:22 PM PDT 24
Finished Jun 30 06:36:41 PM PDT 24
Peak memory 200320 kb
Host smart-1deb8028-8b24-4848-867c-f3d8b76aa45c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=37079593 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_back_pressure.37079593
Directory /workspace/33.hmac_back_pressure/latest

Test location /workspace/coverage/default/33.hmac_burst_wr.409957333
Short name T493
Test name
Test status
Simulation time 977017309 ps
CPU time 56.16 seconds
Started Jun 30 06:36:26 PM PDT 24
Finished Jun 30 06:37:23 PM PDT 24
Peak memory 200316 kb
Host smart-28f213cf-2841-4b44-b0b5-d425489a1622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409957333 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_burst_wr.409957333
Directory /workspace/33.hmac_burst_wr/latest

Test location /workspace/coverage/default/33.hmac_datapath_stress.2863042529
Short name T792
Test name
Test status
Simulation time 8136503673 ps
CPU time 136.3 seconds
Started Jun 30 06:36:26 PM PDT 24
Finished Jun 30 06:38:43 PM PDT 24
Peak memory 416228 kb
Host smart-a5206a48-7a0e-4b22-99e6-b7eecd4f0cd8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2863042529 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_datapath_stress.2863042529
Directory /workspace/33.hmac_datapath_stress/latest

Test location /workspace/coverage/default/33.hmac_error.3982591101
Short name T166
Test name
Test status
Simulation time 2040790471 ps
CPU time 57.62 seconds
Started Jun 30 06:36:25 PM PDT 24
Finished Jun 30 06:37:23 PM PDT 24
Peak memory 200344 kb
Host smart-568e5f87-fd84-4bf1-86cd-e0408897fcfb
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982591101 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_error.3982591101
Directory /workspace/33.hmac_error/latest

Test location /workspace/coverage/default/33.hmac_long_msg.1105251220
Short name T76
Test name
Test status
Simulation time 68948764856 ps
CPU time 122.9 seconds
Started Jun 30 06:36:22 PM PDT 24
Finished Jun 30 06:38:25 PM PDT 24
Peak memory 200376 kb
Host smart-f1975f02-806d-4054-b504-fc72c246c534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1105251220 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_long_msg.1105251220
Directory /workspace/33.hmac_long_msg/latest

Test location /workspace/coverage/default/33.hmac_smoke.1559873824
Short name T569
Test name
Test status
Simulation time 234180979 ps
CPU time 4.89 seconds
Started Jun 30 06:36:29 PM PDT 24
Finished Jun 30 06:36:34 PM PDT 24
Peak memory 200332 kb
Host smart-1f114797-c92a-4db5-8891-d562cc13d76a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1559873824 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_smoke.1559873824
Directory /workspace/33.hmac_smoke/latest

Test location /workspace/coverage/default/33.hmac_stress_all.2519372128
Short name T315
Test name
Test status
Simulation time 16220579207 ps
CPU time 1820.55 seconds
Started Jun 30 06:36:29 PM PDT 24
Finished Jun 30 07:06:50 PM PDT 24
Peak memory 772324 kb
Host smart-14b2f90b-ba0e-4863-8ac6-ae551ed8a53d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519372128 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.hmac_stress_all.2519372128
Directory /workspace/33.hmac_stress_all/latest

Test location /workspace/coverage/default/33.hmac_test_hmac256_vectors.4022665280
Short name T281
Test name
Test status
Simulation time 9057508709 ps
CPU time 53.52 seconds
Started Jun 30 06:36:29 PM PDT 24
Finished Jun 30 06:37:23 PM PDT 24
Peak memory 200344 kb
Host smart-34574fde-abfd-4019-90a0-05b602b8359d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4022665280 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_test_hmac256_vectors.4022665280
Directory /workspace/33.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/33.hmac_test_hmac384_vectors.1689940171
Short name T626
Test name
Test status
Simulation time 31841610250 ps
CPU time 55.38 seconds
Started Jun 30 06:36:31 PM PDT 24
Finished Jun 30 06:37:26 PM PDT 24
Peak memory 200340 kb
Host smart-cd5f8e6b-d1d1-48c2-80e8-287963027f23
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1689940171 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_test_hmac384_vectors.1689940171
Directory /workspace/33.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/33.hmac_test_hmac512_vectors.3241209609
Short name T407
Test name
Test status
Simulation time 1769456765 ps
CPU time 51.69 seconds
Started Jun 30 06:36:32 PM PDT 24
Finished Jun 30 06:37:25 PM PDT 24
Peak memory 200228 kb
Host smart-2fede7b0-cd28-41ef-a8f3-195162d23a80
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3241209609 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_test_hmac512_vectors.3241209609
Directory /workspace/33.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/33.hmac_test_sha256_vectors.3437512248
Short name T488
Test name
Test status
Simulation time 220478517081 ps
CPU time 473.1 seconds
Started Jun 30 06:36:29 PM PDT 24
Finished Jun 30 06:44:23 PM PDT 24
Peak memory 200344 kb
Host smart-af2acde2-5530-49d7-baf1-70a9cee6d946
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3437512248 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_test_sha256_vectors.3437512248
Directory /workspace/33.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/33.hmac_test_sha384_vectors.1429799462
Short name T473
Test name
Test status
Simulation time 30399252989 ps
CPU time 1617.56 seconds
Started Jun 30 06:36:32 PM PDT 24
Finished Jun 30 07:03:30 PM PDT 24
Peak memory 215776 kb
Host smart-29bc0024-2fef-42fe-a790-fc55d9c6693e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1429799462 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_test_sha384_vectors.1429799462
Directory /workspace/33.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/33.hmac_test_sha512_vectors.852105807
Short name T198
Test name
Test status
Simulation time 432436594249 ps
CPU time 1933.63 seconds
Started Jun 30 06:36:30 PM PDT 24
Finished Jun 30 07:08:44 PM PDT 24
Peak memory 216408 kb
Host smart-afc7dd40-ecd6-42c4-a7b8-10914c35f798
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=852105807 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_test_sha512_vectors.852105807
Directory /workspace/33.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/33.hmac_wipe_secret.1395709780
Short name T790
Test name
Test status
Simulation time 2862737821 ps
CPU time 38.34 seconds
Started Jun 30 06:36:29 PM PDT 24
Finished Jun 30 06:37:08 PM PDT 24
Peak memory 200360 kb
Host smart-3917b601-d3ef-4b3d-a3fc-2eeebb068383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395709780 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_wipe_secret.1395709780
Directory /workspace/33.hmac_wipe_secret/latest

Test location /workspace/coverage/default/34.hmac_alert_test.2542254942
Short name T756
Test name
Test status
Simulation time 50163751 ps
CPU time 0.58 seconds
Started Jun 30 06:36:33 PM PDT 24
Finished Jun 30 06:36:34 PM PDT 24
Peak memory 196284 kb
Host smart-ddbad061-376c-49d7-81a5-83aa58b7bc85
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542254942 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_alert_test.2542254942
Directory /workspace/34.hmac_alert_test/latest

Test location /workspace/coverage/default/34.hmac_back_pressure.3213600699
Short name T89
Test name
Test status
Simulation time 857464420 ps
CPU time 39.35 seconds
Started Jun 30 06:36:29 PM PDT 24
Finished Jun 30 06:37:09 PM PDT 24
Peak memory 200328 kb
Host smart-db685e6a-c064-4c21-93c3-fb602b733490
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3213600699 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_back_pressure.3213600699
Directory /workspace/34.hmac_back_pressure/latest

Test location /workspace/coverage/default/34.hmac_burst_wr.1225287689
Short name T636
Test name
Test status
Simulation time 4541726272 ps
CPU time 42.88 seconds
Started Jun 30 06:36:29 PM PDT 24
Finished Jun 30 06:37:13 PM PDT 24
Peak memory 200332 kb
Host smart-90fbf5f4-b3e0-4e14-b4ee-a80d96633167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225287689 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_burst_wr.1225287689
Directory /workspace/34.hmac_burst_wr/latest

Test location /workspace/coverage/default/34.hmac_datapath_stress.891329875
Short name T129
Test name
Test status
Simulation time 6263572595 ps
CPU time 790.42 seconds
Started Jun 30 06:36:29 PM PDT 24
Finished Jun 30 06:49:39 PM PDT 24
Peak memory 687704 kb
Host smart-62cd18f0-7920-4082-a791-e4a721fcc517
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=891329875 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_datapath_stress.891329875
Directory /workspace/34.hmac_datapath_stress/latest

Test location /workspace/coverage/default/34.hmac_error.1080880157
Short name T327
Test name
Test status
Simulation time 3673739494 ps
CPU time 14.61 seconds
Started Jun 30 06:36:34 PM PDT 24
Finished Jun 30 06:36:49 PM PDT 24
Peak memory 200264 kb
Host smart-4f7e977c-8425-4f5c-b0be-12a56b4ed721
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080880157 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_error.1080880157
Directory /workspace/34.hmac_error/latest

Test location /workspace/coverage/default/34.hmac_long_msg.3913200908
Short name T299
Test name
Test status
Simulation time 17973888937 ps
CPU time 72.88 seconds
Started Jun 30 06:36:31 PM PDT 24
Finished Jun 30 06:37:44 PM PDT 24
Peak memory 216804 kb
Host smart-1019ba28-b67f-4d6a-bfc7-651b4a0608e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913200908 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_long_msg.3913200908
Directory /workspace/34.hmac_long_msg/latest

Test location /workspace/coverage/default/34.hmac_smoke.1507043416
Short name T716
Test name
Test status
Simulation time 1019420355 ps
CPU time 4.75 seconds
Started Jun 30 06:36:30 PM PDT 24
Finished Jun 30 06:36:35 PM PDT 24
Peak memory 200308 kb
Host smart-427eb6af-5a4a-45fa-a7c5-2f8de3d8c008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507043416 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_smoke.1507043416
Directory /workspace/34.hmac_smoke/latest

Test location /workspace/coverage/default/34.hmac_stress_all.867346858
Short name T373
Test name
Test status
Simulation time 202809797762 ps
CPU time 3616.25 seconds
Started Jun 30 06:36:37 PM PDT 24
Finished Jun 30 07:36:54 PM PDT 24
Peak memory 754276 kb
Host smart-251ef9f4-d680-47f8-a0f7-4cb1d5a8d2b6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867346858 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 34.hmac_stress_all.867346858
Directory /workspace/34.hmac_stress_all/latest

Test location /workspace/coverage/default/34.hmac_test_hmac256_vectors.3639525808
Short name T160
Test name
Test status
Simulation time 11447114376 ps
CPU time 64.65 seconds
Started Jun 30 06:36:35 PM PDT 24
Finished Jun 30 06:37:40 PM PDT 24
Peak memory 200324 kb
Host smart-c23863e0-b7f9-43d2-9037-8f840daa79bd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3639525808 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_test_hmac256_vectors.3639525808
Directory /workspace/34.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/34.hmac_test_hmac384_vectors.3965769180
Short name T477
Test name
Test status
Simulation time 2208191963 ps
CPU time 85.55 seconds
Started Jun 30 06:36:34 PM PDT 24
Finished Jun 30 06:38:00 PM PDT 24
Peak memory 200420 kb
Host smart-59321b09-372d-42b5-a777-88f00f85d1a9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3965769180 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_test_hmac384_vectors.3965769180
Directory /workspace/34.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/34.hmac_test_hmac512_vectors.2484951727
Short name T165
Test name
Test status
Simulation time 3664952980 ps
CPU time 50.92 seconds
Started Jun 30 06:36:34 PM PDT 24
Finished Jun 30 06:37:25 PM PDT 24
Peak memory 200400 kb
Host smart-f1851a41-899b-4f98-b39d-0924268a5068
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2484951727 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_test_hmac512_vectors.2484951727
Directory /workspace/34.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/34.hmac_test_sha256_vectors.4033870646
Short name T60
Test name
Test status
Simulation time 40067615997 ps
CPU time 569.85 seconds
Started Jun 30 06:36:33 PM PDT 24
Finished Jun 30 06:46:04 PM PDT 24
Peak memory 200308 kb
Host smart-b580d15e-8e0c-4db0-80f2-daaa36d5d925
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=4033870646 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_test_sha256_vectors.4033870646
Directory /workspace/34.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/34.hmac_test_sha384_vectors.3641183336
Short name T257
Test name
Test status
Simulation time 112520424534 ps
CPU time 1986.43 seconds
Started Jun 30 06:36:33 PM PDT 24
Finished Jun 30 07:09:40 PM PDT 24
Peak memory 215824 kb
Host smart-aeb47931-1fbe-4fb9-b215-5e9873ff8967
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3641183336 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_test_sha384_vectors.3641183336
Directory /workspace/34.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/34.hmac_test_sha512_vectors.783480441
Short name T591
Test name
Test status
Simulation time 117633820039 ps
CPU time 1677.67 seconds
Started Jun 30 06:36:35 PM PDT 24
Finished Jun 30 07:04:34 PM PDT 24
Peak memory 208492 kb
Host smart-107e5fc4-5bcd-46fa-8ebd-b44475ecbc7e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=783480441 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_test_sha512_vectors.783480441
Directory /workspace/34.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/34.hmac_wipe_secret.826019872
Short name T602
Test name
Test status
Simulation time 3527509769 ps
CPU time 81.95 seconds
Started Jun 30 06:36:32 PM PDT 24
Finished Jun 30 06:37:54 PM PDT 24
Peak memory 200348 kb
Host smart-993fdee4-7b91-4c92-acd0-c87a924053ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826019872 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_wipe_secret.826019872
Directory /workspace/34.hmac_wipe_secret/latest

Test location /workspace/coverage/default/35.hmac_alert_test.2956604634
Short name T649
Test name
Test status
Simulation time 70038964 ps
CPU time 0.58 seconds
Started Jun 30 06:36:39 PM PDT 24
Finished Jun 30 06:36:39 PM PDT 24
Peak memory 197000 kb
Host smart-9b705a35-749f-4550-a2f6-770c1fa0f6ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956604634 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_alert_test.2956604634
Directory /workspace/35.hmac_alert_test/latest

Test location /workspace/coverage/default/35.hmac_back_pressure.789688937
Short name T379
Test name
Test status
Simulation time 716599413 ps
CPU time 18.22 seconds
Started Jun 30 06:36:35 PM PDT 24
Finished Jun 30 06:36:54 PM PDT 24
Peak memory 200260 kb
Host smart-4ba9ebb8-59a3-465c-ba34-15c141888ea2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=789688937 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_back_pressure.789688937
Directory /workspace/35.hmac_back_pressure/latest

Test location /workspace/coverage/default/35.hmac_burst_wr.393988996
Short name T462
Test name
Test status
Simulation time 1907902170 ps
CPU time 37.09 seconds
Started Jun 30 06:36:40 PM PDT 24
Finished Jun 30 06:37:17 PM PDT 24
Peak memory 200324 kb
Host smart-a12306e6-f4cf-4efc-b5a4-726e243f9d06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393988996 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_burst_wr.393988996
Directory /workspace/35.hmac_burst_wr/latest

Test location /workspace/coverage/default/35.hmac_datapath_stress.3351647422
Short name T739
Test name
Test status
Simulation time 32262467994 ps
CPU time 1568.23 seconds
Started Jun 30 06:36:37 PM PDT 24
Finished Jun 30 07:02:46 PM PDT 24
Peak memory 793452 kb
Host smart-6a241516-6883-4002-864c-01e28c37511f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3351647422 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_datapath_stress.3351647422
Directory /workspace/35.hmac_datapath_stress/latest

Test location /workspace/coverage/default/35.hmac_error.2669482878
Short name T311
Test name
Test status
Simulation time 6495519483 ps
CPU time 83.69 seconds
Started Jun 30 06:36:38 PM PDT 24
Finished Jun 30 06:38:02 PM PDT 24
Peak memory 200384 kb
Host smart-18d121f5-c1fe-446a-959a-2e97d961912c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669482878 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_error.2669482878
Directory /workspace/35.hmac_error/latest

Test location /workspace/coverage/default/35.hmac_long_msg.4020132117
Short name T689
Test name
Test status
Simulation time 11721888593 ps
CPU time 43.35 seconds
Started Jun 30 06:36:31 PM PDT 24
Finished Jun 30 06:37:14 PM PDT 24
Peak memory 200384 kb
Host smart-f778b6e2-7e69-4e93-977b-323cb460978f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020132117 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_long_msg.4020132117
Directory /workspace/35.hmac_long_msg/latest

Test location /workspace/coverage/default/35.hmac_smoke.4240852338
Short name T193
Test name
Test status
Simulation time 561322098 ps
CPU time 8.43 seconds
Started Jun 30 06:36:34 PM PDT 24
Finished Jun 30 06:36:43 PM PDT 24
Peak memory 200352 kb
Host smart-0350844f-e426-46c4-82ad-994f94e3526c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4240852338 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_smoke.4240852338
Directory /workspace/35.hmac_smoke/latest

Test location /workspace/coverage/default/35.hmac_test_hmac256_vectors.1008969088
Short name T633
Test name
Test status
Simulation time 5212353738 ps
CPU time 51.41 seconds
Started Jun 30 06:36:37 PM PDT 24
Finished Jun 30 06:37:29 PM PDT 24
Peak memory 200400 kb
Host smart-ac7871bf-b126-4747-ab6b-22ae65ae9c18
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1008969088 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_test_hmac256_vectors.1008969088
Directory /workspace/35.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/35.hmac_test_hmac384_vectors.2066964433
Short name T156
Test name
Test status
Simulation time 16995193787 ps
CPU time 40.23 seconds
Started Jun 30 06:36:39 PM PDT 24
Finished Jun 30 06:37:20 PM PDT 24
Peak memory 200388 kb
Host smart-36267500-06ca-48e9-b6ff-b36a7500a0c7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2066964433 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_test_hmac384_vectors.2066964433
Directory /workspace/35.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/35.hmac_test_hmac512_vectors.199988736
Short name T246
Test name
Test status
Simulation time 8656742962 ps
CPU time 70.83 seconds
Started Jun 30 06:36:40 PM PDT 24
Finished Jun 30 06:37:51 PM PDT 24
Peak memory 200380 kb
Host smart-58255713-e752-4422-a510-730fd2b90faf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=199988736 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_test_hmac512_vectors.199988736
Directory /workspace/35.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/35.hmac_test_sha256_vectors.690561728
Short name T495
Test name
Test status
Simulation time 103514045787 ps
CPU time 476.94 seconds
Started Jun 30 06:36:39 PM PDT 24
Finished Jun 30 06:44:36 PM PDT 24
Peak memory 200344 kb
Host smart-9cba9af6-92a8-4e72-a721-5d75550dcb9a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=690561728 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_test_sha256_vectors.690561728
Directory /workspace/35.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/35.hmac_test_sha384_vectors.1814320768
Short name T380
Test name
Test status
Simulation time 101343675650 ps
CPU time 1924.67 seconds
Started Jun 30 06:36:39 PM PDT 24
Finished Jun 30 07:08:44 PM PDT 24
Peak memory 216044 kb
Host smart-135ad7b8-90c3-43eb-bba7-f52493cf5769
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1814320768 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_test_sha384_vectors.1814320768
Directory /workspace/35.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/35.hmac_test_sha512_vectors.1400219042
Short name T506
Test name
Test status
Simulation time 52352805514 ps
CPU time 1751.13 seconds
Started Jun 30 06:36:37 PM PDT 24
Finished Jun 30 07:05:49 PM PDT 24
Peak memory 215924 kb
Host smart-972f85da-a5e6-44e1-b168-327ffe278686
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1400219042 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_test_sha512_vectors.1400219042
Directory /workspace/35.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/35.hmac_wipe_secret.2494944827
Short name T794
Test name
Test status
Simulation time 17654950628 ps
CPU time 70.59 seconds
Started Jun 30 06:36:39 PM PDT 24
Finished Jun 30 06:37:50 PM PDT 24
Peak memory 200392 kb
Host smart-a7475eae-4202-4e9b-b8e3-cf604e7d48a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494944827 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_wipe_secret.2494944827
Directory /workspace/35.hmac_wipe_secret/latest

Test location /workspace/coverage/default/36.hmac_alert_test.2836855773
Short name T481
Test name
Test status
Simulation time 36766740 ps
CPU time 0.58 seconds
Started Jun 30 06:36:46 PM PDT 24
Finished Jun 30 06:36:48 PM PDT 24
Peak memory 195264 kb
Host smart-11cf49d0-adac-47a8-a24b-c1563e815d18
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836855773 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_alert_test.2836855773
Directory /workspace/36.hmac_alert_test/latest

Test location /workspace/coverage/default/36.hmac_back_pressure.2178127828
Short name T23
Test name
Test status
Simulation time 1060091637 ps
CPU time 17.99 seconds
Started Jun 30 06:36:40 PM PDT 24
Finished Jun 30 06:36:59 PM PDT 24
Peak memory 200272 kb
Host smart-dce9170c-83c5-49b8-bb90-c42bb8012b43
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2178127828 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_back_pressure.2178127828
Directory /workspace/36.hmac_back_pressure/latest

Test location /workspace/coverage/default/36.hmac_burst_wr.1879093076
Short name T671
Test name
Test status
Simulation time 1685639119 ps
CPU time 33.19 seconds
Started Jun 30 06:36:39 PM PDT 24
Finished Jun 30 06:37:13 PM PDT 24
Peak memory 200288 kb
Host smart-60547227-9324-4b0d-9dad-d561b7ed274f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1879093076 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_burst_wr.1879093076
Directory /workspace/36.hmac_burst_wr/latest

Test location /workspace/coverage/default/36.hmac_datapath_stress.2638125080
Short name T535
Test name
Test status
Simulation time 1650216406 ps
CPU time 441.43 seconds
Started Jun 30 06:36:39 PM PDT 24
Finished Jun 30 06:44:01 PM PDT 24
Peak memory 690016 kb
Host smart-fb488496-d40a-4eaa-82cb-ba9a1634e61a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2638125080 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_datapath_stress.2638125080
Directory /workspace/36.hmac_datapath_stress/latest

Test location /workspace/coverage/default/36.hmac_error.3278951795
Short name T786
Test name
Test status
Simulation time 1415250265 ps
CPU time 17.18 seconds
Started Jun 30 06:37:38 PM PDT 24
Finished Jun 30 06:37:56 PM PDT 24
Peak memory 200040 kb
Host smart-6500446d-4381-4c3e-b66e-138bf9b64416
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278951795 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_error.3278951795
Directory /workspace/36.hmac_error/latest

Test location /workspace/coverage/default/36.hmac_long_msg.3238887343
Short name T658
Test name
Test status
Simulation time 877662776 ps
CPU time 47.31 seconds
Started Jun 30 06:36:40 PM PDT 24
Finished Jun 30 06:37:28 PM PDT 24
Peak memory 200316 kb
Host smart-2ca11f07-e468-4c32-aa7d-f3a73869704d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238887343 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_long_msg.3238887343
Directory /workspace/36.hmac_long_msg/latest

Test location /workspace/coverage/default/36.hmac_smoke.2368654320
Short name T9
Test name
Test status
Simulation time 822000699 ps
CPU time 7.59 seconds
Started Jun 30 06:36:40 PM PDT 24
Finished Jun 30 06:36:48 PM PDT 24
Peak memory 200316 kb
Host smart-9d61325b-22ba-4ae7-831e-0cb2aab812fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368654320 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_smoke.2368654320
Directory /workspace/36.hmac_smoke/latest

Test location /workspace/coverage/default/36.hmac_stress_all.229282875
Short name T390
Test name
Test status
Simulation time 2661055081 ps
CPU time 12.26 seconds
Started Jun 30 06:36:46 PM PDT 24
Finished Jun 30 06:36:59 PM PDT 24
Peak memory 200364 kb
Host smart-3da00998-398e-4490-80a6-4b75e5d260f5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229282875 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 36.hmac_stress_all.229282875
Directory /workspace/36.hmac_stress_all/latest

Test location /workspace/coverage/default/36.hmac_test_hmac256_vectors.1475887130
Short name T146
Test name
Test status
Simulation time 7947323395 ps
CPU time 58.96 seconds
Started Jun 30 06:36:47 PM PDT 24
Finished Jun 30 06:37:47 PM PDT 24
Peak memory 200340 kb
Host smart-246ca9d6-5c4b-494d-b4dc-758fc8b4ea3d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1475887130 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_test_hmac256_vectors.1475887130
Directory /workspace/36.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/36.hmac_test_hmac384_vectors.3877951910
Short name T314
Test name
Test status
Simulation time 19992582753 ps
CPU time 60.07 seconds
Started Jun 30 06:36:47 PM PDT 24
Finished Jun 30 06:37:48 PM PDT 24
Peak memory 200416 kb
Host smart-c3c2a6ee-fa19-4505-b379-2dbec6bf8c54
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3877951910 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_test_hmac384_vectors.3877951910
Directory /workspace/36.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/36.hmac_test_hmac512_vectors.2648946476
Short name T554
Test name
Test status
Simulation time 21494651477 ps
CPU time 126.53 seconds
Started Jun 30 06:36:46 PM PDT 24
Finished Jun 30 06:38:53 PM PDT 24
Peak memory 200368 kb
Host smart-5fc5843d-beb7-4dd1-8c02-5c2ef995d740
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2648946476 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_test_hmac512_vectors.2648946476
Directory /workspace/36.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/36.hmac_test_sha256_vectors.765701492
Short name T263
Test name
Test status
Simulation time 97224100182 ps
CPU time 423.05 seconds
Started Jun 30 06:36:48 PM PDT 24
Finished Jun 30 06:43:52 PM PDT 24
Peak memory 200300 kb
Host smart-5cbd1e07-1576-429f-822b-058e3eba73d1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=765701492 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_test_sha256_vectors.765701492
Directory /workspace/36.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/36.hmac_test_sha384_vectors.3989471627
Short name T442
Test name
Test status
Simulation time 29855679854 ps
CPU time 1764.64 seconds
Started Jun 30 06:36:47 PM PDT 24
Finished Jun 30 07:06:13 PM PDT 24
Peak memory 215744 kb
Host smart-b554fab5-fab9-4a2f-867f-b4ad1af374a3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3989471627 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_test_sha384_vectors.3989471627
Directory /workspace/36.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/36.hmac_test_sha512_vectors.4082150995
Short name T176
Test name
Test status
Simulation time 163020224479 ps
CPU time 1596.83 seconds
Started Jun 30 06:36:46 PM PDT 24
Finished Jun 30 07:03:24 PM PDT 24
Peak memory 215656 kb
Host smart-17394281-140e-4523-8b37-aa3f23fcdda2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4082150995 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_test_sha512_vectors.4082150995
Directory /workspace/36.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/36.hmac_wipe_secret.659496159
Short name T562
Test name
Test status
Simulation time 7776626387 ps
CPU time 81 seconds
Started Jun 30 06:36:46 PM PDT 24
Finished Jun 30 06:38:07 PM PDT 24
Peak memory 200296 kb
Host smart-b00bd461-595d-4933-b7cf-cef802dd4d47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659496159 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_wipe_secret.659496159
Directory /workspace/36.hmac_wipe_secret/latest

Test location /workspace/coverage/default/37.hmac_alert_test.1092540761
Short name T319
Test name
Test status
Simulation time 28186314 ps
CPU time 0.57 seconds
Started Jun 30 06:36:50 PM PDT 24
Finished Jun 30 06:36:51 PM PDT 24
Peak memory 196040 kb
Host smart-7cbf8361-1318-45b1-ac7f-13e27b41b54d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092540761 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_alert_test.1092540761
Directory /workspace/37.hmac_alert_test/latest

Test location /workspace/coverage/default/37.hmac_back_pressure.126868822
Short name T536
Test name
Test status
Simulation time 5233315706 ps
CPU time 18.04 seconds
Started Jun 30 06:36:46 PM PDT 24
Finished Jun 30 06:37:05 PM PDT 24
Peak memory 200572 kb
Host smart-dc989e06-dac8-49a2-a93b-e37bdaa5b38a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=126868822 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_back_pressure.126868822
Directory /workspace/37.hmac_back_pressure/latest

Test location /workspace/coverage/default/37.hmac_burst_wr.3210666331
Short name T418
Test name
Test status
Simulation time 565404916 ps
CPU time 12.1 seconds
Started Jun 30 06:36:47 PM PDT 24
Finished Jun 30 06:36:59 PM PDT 24
Peak memory 200364 kb
Host smart-5e62e9c9-8b4b-4817-9948-d48748bfce4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210666331 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_burst_wr.3210666331
Directory /workspace/37.hmac_burst_wr/latest

Test location /workspace/coverage/default/37.hmac_datapath_stress.1191183116
Short name T337
Test name
Test status
Simulation time 12939519692 ps
CPU time 1166.21 seconds
Started Jun 30 06:36:46 PM PDT 24
Finished Jun 30 06:56:13 PM PDT 24
Peak memory 769488 kb
Host smart-3fafe380-ce14-4f09-935e-2b31721cdf15
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1191183116 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_datapath_stress.1191183116
Directory /workspace/37.hmac_datapath_stress/latest

Test location /workspace/coverage/default/37.hmac_error.2778592711
Short name T3
Test name
Test status
Simulation time 871328487 ps
CPU time 49.84 seconds
Started Jun 30 06:36:48 PM PDT 24
Finished Jun 30 06:37:38 PM PDT 24
Peak memory 200232 kb
Host smart-8a9d9773-dec8-4b59-9c64-2e7539cfded5
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778592711 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_error.2778592711
Directory /workspace/37.hmac_error/latest

Test location /workspace/coverage/default/37.hmac_long_msg.4229367209
Short name T371
Test name
Test status
Simulation time 2960228108 ps
CPU time 59.64 seconds
Started Jun 30 06:36:47 PM PDT 24
Finished Jun 30 06:37:48 PM PDT 24
Peak memory 200340 kb
Host smart-cab3b79c-49e4-4138-a9a9-84bc28de74ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229367209 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_long_msg.4229367209
Directory /workspace/37.hmac_long_msg/latest

Test location /workspace/coverage/default/37.hmac_smoke.2664430030
Short name T186
Test name
Test status
Simulation time 38264972 ps
CPU time 1.95 seconds
Started Jun 30 06:36:49 PM PDT 24
Finished Jun 30 06:36:52 PM PDT 24
Peak memory 200372 kb
Host smart-bd5b2389-0940-4dfa-a210-1904a914b411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664430030 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_smoke.2664430030
Directory /workspace/37.hmac_smoke/latest

Test location /workspace/coverage/default/37.hmac_test_hmac256_vectors.3232875729
Short name T606
Test name
Test status
Simulation time 5204169273 ps
CPU time 52.52 seconds
Started Jun 30 06:36:49 PM PDT 24
Finished Jun 30 06:37:42 PM PDT 24
Peak memory 200352 kb
Host smart-fa54e5bd-5218-4cfd-a95f-2c7e85ed035a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3232875729 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_test_hmac256_vectors.3232875729
Directory /workspace/37.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/37.hmac_test_hmac384_vectors.30325185
Short name T72
Test name
Test status
Simulation time 9069919890 ps
CPU time 78.95 seconds
Started Jun 30 06:36:51 PM PDT 24
Finished Jun 30 06:38:10 PM PDT 24
Peak memory 200408 kb
Host smart-785c4666-64b3-4197-ad1c-c555313c31d5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=30325185 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_test_hmac384_vectors.30325185
Directory /workspace/37.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/37.hmac_test_hmac512_vectors.927373468
Short name T719
Test name
Test status
Simulation time 4544694893 ps
CPU time 68.94 seconds
Started Jun 30 06:36:50 PM PDT 24
Finished Jun 30 06:38:00 PM PDT 24
Peak memory 200368 kb
Host smart-30850cf4-77d3-4090-b7be-21eb36984693
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=927373468 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_test_hmac512_vectors.927373468
Directory /workspace/37.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/37.hmac_test_sha256_vectors.688733876
Short name T414
Test name
Test status
Simulation time 33109669117 ps
CPU time 452.57 seconds
Started Jun 30 06:36:51 PM PDT 24
Finished Jun 30 06:44:24 PM PDT 24
Peak memory 200312 kb
Host smart-15b9c6ec-70a3-4e3c-a8c5-b406b1754ff8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=688733876 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_test_sha256_vectors.688733876
Directory /workspace/37.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/37.hmac_test_sha384_vectors.4109390901
Short name T383
Test name
Test status
Simulation time 29489455334 ps
CPU time 1645.6 seconds
Started Jun 30 06:36:51 PM PDT 24
Finished Jun 30 07:04:17 PM PDT 24
Peak memory 215940 kb
Host smart-bdd0cd0a-24ec-4114-a612-62c0602b09f7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4109390901 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_test_sha384_vectors.4109390901
Directory /workspace/37.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/37.hmac_test_sha512_vectors.2986921959
Short name T457
Test name
Test status
Simulation time 111612093284 ps
CPU time 1983.51 seconds
Started Jun 30 06:36:50 PM PDT 24
Finished Jun 30 07:09:55 PM PDT 24
Peak memory 215860 kb
Host smart-80f4b4b6-5b44-4dde-a3a1-27bc7f0b681e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2986921959 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_test_sha512_vectors.2986921959
Directory /workspace/37.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/37.hmac_wipe_secret.1464310782
Short name T628
Test name
Test status
Simulation time 6338375168 ps
CPU time 75.39 seconds
Started Jun 30 06:36:48 PM PDT 24
Finished Jun 30 06:38:04 PM PDT 24
Peak memory 200344 kb
Host smart-6b30ef2e-6f46-485f-be1d-c3a411cf7a76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464310782 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_wipe_secret.1464310782
Directory /workspace/37.hmac_wipe_secret/latest

Test location /workspace/coverage/default/38.hmac_alert_test.1759961805
Short name T155
Test name
Test status
Simulation time 13543275 ps
CPU time 0.59 seconds
Started Jun 30 06:36:54 PM PDT 24
Finished Jun 30 06:36:55 PM PDT 24
Peak memory 195872 kb
Host smart-b9c29f03-b71c-4f90-9ed4-9ef9fa15394f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759961805 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_alert_test.1759961805
Directory /workspace/38.hmac_alert_test/latest

Test location /workspace/coverage/default/38.hmac_back_pressure.4066997203
Short name T639
Test name
Test status
Simulation time 349936838 ps
CPU time 8.93 seconds
Started Jun 30 06:36:50 PM PDT 24
Finished Jun 30 06:36:59 PM PDT 24
Peak memory 200308 kb
Host smart-3909530c-6222-436c-a5d4-c806caa200df
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4066997203 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_back_pressure.4066997203
Directory /workspace/38.hmac_back_pressure/latest

Test location /workspace/coverage/default/38.hmac_burst_wr.626088590
Short name T133
Test name
Test status
Simulation time 14938004417 ps
CPU time 61.47 seconds
Started Jun 30 06:36:50 PM PDT 24
Finished Jun 30 06:37:52 PM PDT 24
Peak memory 200316 kb
Host smart-7ebd32a3-e170-4f81-8b93-9f8fc4111e4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626088590 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_burst_wr.626088590
Directory /workspace/38.hmac_burst_wr/latest

Test location /workspace/coverage/default/38.hmac_datapath_stress.2105950710
Short name T329
Test name
Test status
Simulation time 2554428637 ps
CPU time 637.1 seconds
Started Jun 30 06:36:51 PM PDT 24
Finished Jun 30 06:47:29 PM PDT 24
Peak memory 663620 kb
Host smart-1d392876-ce2a-449f-89b0-4151254df240
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2105950710 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_datapath_stress.2105950710
Directory /workspace/38.hmac_datapath_stress/latest

Test location /workspace/coverage/default/38.hmac_error.1881826902
Short name T173
Test name
Test status
Simulation time 28861968201 ps
CPU time 85.86 seconds
Started Jun 30 06:36:56 PM PDT 24
Finished Jun 30 06:38:22 PM PDT 24
Peak memory 200336 kb
Host smart-70f6edbf-83b5-4330-9ad8-4c3244dc02d4
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881826902 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_error.1881826902
Directory /workspace/38.hmac_error/latest

Test location /workspace/coverage/default/38.hmac_long_msg.871003056
Short name T253
Test name
Test status
Simulation time 8214864420 ps
CPU time 28.35 seconds
Started Jun 30 06:36:49 PM PDT 24
Finished Jun 30 06:37:18 PM PDT 24
Peak memory 200384 kb
Host smart-87a5f3d5-55e5-4992-b0bb-e5b4e3d94cc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871003056 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_long_msg.871003056
Directory /workspace/38.hmac_long_msg/latest

Test location /workspace/coverage/default/38.hmac_smoke.345306469
Short name T793
Test name
Test status
Simulation time 911205359 ps
CPU time 11.16 seconds
Started Jun 30 06:36:50 PM PDT 24
Finished Jun 30 06:37:02 PM PDT 24
Peak memory 200304 kb
Host smart-5869a227-914f-48f7-90bc-903170652ad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345306469 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_smoke.345306469
Directory /workspace/38.hmac_smoke/latest

Test location /workspace/coverage/default/38.hmac_stress_all.780318795
Short name T643
Test name
Test status
Simulation time 1479521279475 ps
CPU time 5043.64 seconds
Started Jun 30 06:36:57 PM PDT 24
Finished Jun 30 08:01:02 PM PDT 24
Peak memory 208584 kb
Host smart-afc6349e-df58-4b55-97a8-3d7f590215b7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780318795 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 38.hmac_stress_all.780318795
Directory /workspace/38.hmac_stress_all/latest

Test location /workspace/coverage/default/38.hmac_test_hmac256_vectors.2427893961
Short name T730
Test name
Test status
Simulation time 1362012429 ps
CPU time 56.19 seconds
Started Jun 30 06:36:56 PM PDT 24
Finished Jun 30 06:37:53 PM PDT 24
Peak memory 200264 kb
Host smart-c1dd4ccb-9a8c-4efc-b60d-f70ac413f4e0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2427893961 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_test_hmac256_vectors.2427893961
Directory /workspace/38.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/38.hmac_test_hmac384_vectors.2447234670
Short name T220
Test name
Test status
Simulation time 5988543106 ps
CPU time 79.11 seconds
Started Jun 30 06:36:55 PM PDT 24
Finished Jun 30 06:38:15 PM PDT 24
Peak memory 200376 kb
Host smart-f352a004-569a-40ae-b04e-282582d068f2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2447234670 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_test_hmac384_vectors.2447234670
Directory /workspace/38.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/38.hmac_test_hmac512_vectors.770373196
Short name T512
Test name
Test status
Simulation time 7995312680 ps
CPU time 57.21 seconds
Started Jun 30 06:36:55 PM PDT 24
Finished Jun 30 06:37:53 PM PDT 24
Peak memory 200404 kb
Host smart-a1333ff7-084f-4a8f-acd0-29f6e4e95f2b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=770373196 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_test_hmac512_vectors.770373196
Directory /workspace/38.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/38.hmac_test_sha256_vectors.3744187624
Short name T353
Test name
Test status
Simulation time 8056031097 ps
CPU time 386.01 seconds
Started Jun 30 06:36:55 PM PDT 24
Finished Jun 30 06:43:22 PM PDT 24
Peak memory 200308 kb
Host smart-a05ca63f-2c8c-4a92-ac4b-494b41077264
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3744187624 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_test_sha256_vectors.3744187624
Directory /workspace/38.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/38.hmac_test_sha384_vectors.3233454757
Short name T391
Test name
Test status
Simulation time 97163645782 ps
CPU time 1740.69 seconds
Started Jun 30 06:36:55 PM PDT 24
Finished Jun 30 07:05:57 PM PDT 24
Peak memory 215764 kb
Host smart-df325cb8-defe-4227-b529-37753e9221ac
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3233454757 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_test_sha384_vectors.3233454757
Directory /workspace/38.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/38.hmac_test_sha512_vectors.3990217337
Short name T510
Test name
Test status
Simulation time 478748130188 ps
CPU time 2140.36 seconds
Started Jun 30 06:36:56 PM PDT 24
Finished Jun 30 07:12:37 PM PDT 24
Peak memory 215820 kb
Host smart-62915b71-fadd-48ee-bda8-5aee71bc9733
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3990217337 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_test_sha512_vectors.3990217337
Directory /workspace/38.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/38.hmac_wipe_secret.865263579
Short name T490
Test name
Test status
Simulation time 8578236308 ps
CPU time 41.48 seconds
Started Jun 30 06:36:56 PM PDT 24
Finished Jun 30 06:37:38 PM PDT 24
Peak memory 200296 kb
Host smart-96d62fbb-fdb9-416e-9fed-896e7d2463be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=865263579 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_wipe_secret.865263579
Directory /workspace/38.hmac_wipe_secret/latest

Test location /workspace/coverage/default/39.hmac_alert_test.1081495608
Short name T175
Test name
Test status
Simulation time 30167841 ps
CPU time 0.59 seconds
Started Jun 30 06:37:06 PM PDT 24
Finished Jun 30 06:37:07 PM PDT 24
Peak memory 195204 kb
Host smart-4ab1d84b-47b4-4c6c-ac6c-ee6342f5c342
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081495608 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_alert_test.1081495608
Directory /workspace/39.hmac_alert_test/latest

Test location /workspace/coverage/default/39.hmac_back_pressure.3220596119
Short name T450
Test name
Test status
Simulation time 11856060953 ps
CPU time 45.45 seconds
Started Jun 30 06:36:57 PM PDT 24
Finished Jun 30 06:37:43 PM PDT 24
Peak memory 200356 kb
Host smart-988b840b-51ac-4b67-84cb-5a21d094bd74
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3220596119 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_back_pressure.3220596119
Directory /workspace/39.hmac_back_pressure/latest

Test location /workspace/coverage/default/39.hmac_burst_wr.3202400223
Short name T5
Test name
Test status
Simulation time 1950087561 ps
CPU time 22.37 seconds
Started Jun 30 06:36:56 PM PDT 24
Finished Jun 30 06:37:19 PM PDT 24
Peak memory 200316 kb
Host smart-a7493f26-5cfe-499c-a7bb-c61b6aa133d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202400223 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_burst_wr.3202400223
Directory /workspace/39.hmac_burst_wr/latest

Test location /workspace/coverage/default/39.hmac_datapath_stress.3663326242
Short name T307
Test name
Test status
Simulation time 816346631 ps
CPU time 172.49 seconds
Started Jun 30 06:36:58 PM PDT 24
Finished Jun 30 06:39:50 PM PDT 24
Peak memory 467076 kb
Host smart-97c5e432-7374-4d99-803d-2ae078d83ffd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3663326242 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_datapath_stress.3663326242
Directory /workspace/39.hmac_datapath_stress/latest

Test location /workspace/coverage/default/39.hmac_error.3027400767
Short name T467
Test name
Test status
Simulation time 11867739202 ps
CPU time 24.9 seconds
Started Jun 30 06:37:00 PM PDT 24
Finished Jun 30 06:37:25 PM PDT 24
Peak memory 200236 kb
Host smart-5a8df906-8333-4bc6-ad1e-a7c7f385ad55
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027400767 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_error.3027400767
Directory /workspace/39.hmac_error/latest

Test location /workspace/coverage/default/39.hmac_long_msg.3147013477
Short name T196
Test name
Test status
Simulation time 67940906139 ps
CPU time 124.89 seconds
Started Jun 30 06:36:54 PM PDT 24
Finished Jun 30 06:39:00 PM PDT 24
Peak memory 200324 kb
Host smart-e946f084-a8db-4d8c-9774-f21b3ea4572c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147013477 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_long_msg.3147013477
Directory /workspace/39.hmac_long_msg/latest

Test location /workspace/coverage/default/39.hmac_smoke.1398355001
Short name T485
Test name
Test status
Simulation time 482859104 ps
CPU time 8.8 seconds
Started Jun 30 06:36:55 PM PDT 24
Finished Jun 30 06:37:04 PM PDT 24
Peak memory 200284 kb
Host smart-755c487e-4e1a-4727-a0e5-1a7f0452d2f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1398355001 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_smoke.1398355001
Directory /workspace/39.hmac_smoke/latest

Test location /workspace/coverage/default/39.hmac_stress_all.2558977133
Short name T130
Test name
Test status
Simulation time 65863697839 ps
CPU time 1745.3 seconds
Started Jun 30 06:36:59 PM PDT 24
Finished Jun 30 07:06:05 PM PDT 24
Peak memory 771376 kb
Host smart-d598cc5c-6dab-4034-86ed-89765309b790
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558977133 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.hmac_stress_all.2558977133
Directory /workspace/39.hmac_stress_all/latest

Test location /workspace/coverage/default/39.hmac_test_hmac256_vectors.934406061
Short name T534
Test name
Test status
Simulation time 15203027650 ps
CPU time 66.52 seconds
Started Jun 30 06:37:00 PM PDT 24
Finished Jun 30 06:38:07 PM PDT 24
Peak memory 200384 kb
Host smart-aaf1b063-2ec0-419b-ba04-fe9caf242ef2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=934406061 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_test_hmac256_vectors.934406061
Directory /workspace/39.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/39.hmac_test_hmac384_vectors.2835058772
Short name T238
Test name
Test status
Simulation time 14743825809 ps
CPU time 47.23 seconds
Started Jun 30 06:37:01 PM PDT 24
Finished Jun 30 06:37:48 PM PDT 24
Peak memory 200380 kb
Host smart-a2d10b63-cde9-4abb-a83e-b15a7313dd9b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2835058772 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_test_hmac384_vectors.2835058772
Directory /workspace/39.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/39.hmac_test_hmac512_vectors.1877369190
Short name T627
Test name
Test status
Simulation time 36549934694 ps
CPU time 115.19 seconds
Started Jun 30 06:37:03 PM PDT 24
Finished Jun 30 06:38:59 PM PDT 24
Peak memory 200328 kb
Host smart-85cd9bc5-009a-4c6d-8eb9-6410a7a3e672
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1877369190 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_test_hmac512_vectors.1877369190
Directory /workspace/39.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/39.hmac_test_sha256_vectors.2823307048
Short name T538
Test name
Test status
Simulation time 34649807415 ps
CPU time 471.64 seconds
Started Jun 30 06:37:01 PM PDT 24
Finished Jun 30 06:44:53 PM PDT 24
Peak memory 200268 kb
Host smart-65a31b32-d9e0-4625-a4c2-ede85402fabb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2823307048 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_test_sha256_vectors.2823307048
Directory /workspace/39.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/39.hmac_test_sha384_vectors.3933400224
Short name T686
Test name
Test status
Simulation time 140768443127 ps
CPU time 1891.52 seconds
Started Jun 30 06:37:03 PM PDT 24
Finished Jun 30 07:08:35 PM PDT 24
Peak memory 216700 kb
Host smart-a776b007-62f9-42b1-82b4-f6caf8bad2cc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3933400224 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_test_sha384_vectors.3933400224
Directory /workspace/39.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/39.hmac_test_sha512_vectors.1970388166
Short name T413
Test name
Test status
Simulation time 27432726105 ps
CPU time 1594.38 seconds
Started Jun 30 06:37:00 PM PDT 24
Finished Jun 30 07:03:35 PM PDT 24
Peak memory 215760 kb
Host smart-2a631e37-c86e-41ee-9f1b-ba42cdf47203
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1970388166 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_test_sha512_vectors.1970388166
Directory /workspace/39.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/39.hmac_wipe_secret.2783493879
Short name T430
Test name
Test status
Simulation time 2005934198 ps
CPU time 16.26 seconds
Started Jun 30 06:37:01 PM PDT 24
Finished Jun 30 06:37:18 PM PDT 24
Peak memory 200328 kb
Host smart-1c7dd4f2-6497-441e-b454-fe24a093e38f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783493879 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_wipe_secret.2783493879
Directory /workspace/39.hmac_wipe_secret/latest

Test location /workspace/coverage/default/4.hmac_alert_test.2774742890
Short name T579
Test name
Test status
Simulation time 32360800 ps
CPU time 0.59 seconds
Started Jun 30 06:34:27 PM PDT 24
Finished Jun 30 06:34:29 PM PDT 24
Peak memory 195924 kb
Host smart-d09c19e7-3ac0-46cf-9bae-315f8702a236
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774742890 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_alert_test.2774742890
Directory /workspace/4.hmac_alert_test/latest

Test location /workspace/coverage/default/4.hmac_back_pressure.926183298
Short name T664
Test name
Test status
Simulation time 2081584188 ps
CPU time 49.29 seconds
Started Jun 30 06:34:15 PM PDT 24
Finished Jun 30 06:35:04 PM PDT 24
Peak memory 200260 kb
Host smart-70714b30-557b-4c0f-824e-5a9254ea9190
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=926183298 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_back_pressure.926183298
Directory /workspace/4.hmac_back_pressure/latest

Test location /workspace/coverage/default/4.hmac_burst_wr.3110677515
Short name T546
Test name
Test status
Simulation time 1340830820 ps
CPU time 17.68 seconds
Started Jun 30 06:34:27 PM PDT 24
Finished Jun 30 06:34:45 PM PDT 24
Peak memory 200148 kb
Host smart-739b5391-9421-40b8-9674-168326b70815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3110677515 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_burst_wr.3110677515
Directory /workspace/4.hmac_burst_wr/latest

Test location /workspace/coverage/default/4.hmac_error.1201230161
Short name T369
Test name
Test status
Simulation time 8367622503 ps
CPU time 91.46 seconds
Started Jun 30 06:34:13 PM PDT 24
Finished Jun 30 06:35:45 PM PDT 24
Peak memory 200384 kb
Host smart-0af7e88c-8fb9-4d27-b2c7-c1e6805a15f8
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201230161 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_error.1201230161
Directory /workspace/4.hmac_error/latest

Test location /workspace/coverage/default/4.hmac_long_msg.3850260155
Short name T405
Test name
Test status
Simulation time 9708539965 ps
CPU time 125.36 seconds
Started Jun 30 06:34:14 PM PDT 24
Finished Jun 30 06:36:19 PM PDT 24
Peak memory 200384 kb
Host smart-dba9d832-05ba-451e-928b-398d6e586d0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850260155 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_long_msg.3850260155
Directory /workspace/4.hmac_long_msg/latest

Test location /workspace/coverage/default/4.hmac_smoke.2234410639
Short name T296
Test name
Test status
Simulation time 248410522 ps
CPU time 10.44 seconds
Started Jun 30 06:34:17 PM PDT 24
Finished Jun 30 06:34:28 PM PDT 24
Peak memory 200260 kb
Host smart-81e62f54-47c6-4111-b24d-195ff75834d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234410639 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_smoke.2234410639
Directory /workspace/4.hmac_smoke/latest

Test location /workspace/coverage/default/4.hmac_test_hmac256_vectors.1163405058
Short name T287
Test name
Test status
Simulation time 9957669599 ps
CPU time 37.06 seconds
Started Jun 30 06:34:18 PM PDT 24
Finished Jun 30 06:34:55 PM PDT 24
Peak memory 200376 kb
Host smart-ccc95173-dd77-4433-a59a-312659015d93
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1163405058 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac256_vectors.1163405058
Directory /workspace/4.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_hmac384_vectors.1733270371
Short name T346
Test name
Test status
Simulation time 19525190900 ps
CPU time 78.41 seconds
Started Jun 30 06:34:21 PM PDT 24
Finished Jun 30 06:35:40 PM PDT 24
Peak memory 200388 kb
Host smart-474f2892-4822-471d-9c87-56d3d9bdfb39
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1733270371 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac384_vectors.1733270371
Directory /workspace/4.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_hmac512_vectors.1358752640
Short name T392
Test name
Test status
Simulation time 5880659674 ps
CPU time 106.33 seconds
Started Jun 30 06:34:20 PM PDT 24
Finished Jun 30 06:36:07 PM PDT 24
Peak memory 200360 kb
Host smart-396c0299-ab41-4870-8c8c-68aae93cb92a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1358752640 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac512_vectors.1358752640
Directory /workspace/4.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha256_vectors.3163445647
Short name T417
Test name
Test status
Simulation time 122866123075 ps
CPU time 508.39 seconds
Started Jun 30 06:34:14 PM PDT 24
Finished Jun 30 06:42:43 PM PDT 24
Peak memory 200336 kb
Host smart-72857ad1-ceda-4ede-a3b7-26c0d53fbf9c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3163445647 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha256_vectors.3163445647
Directory /workspace/4.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha384_vectors.1092363300
Short name T519
Test name
Test status
Simulation time 109164692162 ps
CPU time 1910.28 seconds
Started Jun 30 06:34:14 PM PDT 24
Finished Jun 30 07:06:05 PM PDT 24
Peak memory 215792 kb
Host smart-5789ddd0-1ce6-4e3a-910b-a910a514f29d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1092363300 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha384_vectors.1092363300
Directory /workspace/4.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha512_vectors.970866406
Short name T738
Test name
Test status
Simulation time 32477398718 ps
CPU time 1757.92 seconds
Started Jun 30 06:34:27 PM PDT 24
Finished Jun 30 07:03:46 PM PDT 24
Peak memory 215748 kb
Host smart-c595cc6e-fbda-48d1-9f05-3d7c5975da9c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=970866406 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha512_vectors.970866406
Directory /workspace/4.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/4.hmac_wipe_secret.627288827
Short name T779
Test name
Test status
Simulation time 10754632788 ps
CPU time 85.83 seconds
Started Jun 30 06:34:27 PM PDT 24
Finished Jun 30 06:35:53 PM PDT 24
Peak memory 200228 kb
Host smart-fe48749d-c210-4ea2-90b0-bd9ece7c7d89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627288827 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_wipe_secret.627288827
Directory /workspace/4.hmac_wipe_secret/latest

Test location /workspace/coverage/default/40.hmac_alert_test.3110593919
Short name T239
Test name
Test status
Simulation time 32933592 ps
CPU time 0.59 seconds
Started Jun 30 06:37:12 PM PDT 24
Finished Jun 30 06:37:13 PM PDT 24
Peak memory 196220 kb
Host smart-e7c00362-49ad-4ea8-a4ea-9a95b79867f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110593919 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_alert_test.3110593919
Directory /workspace/40.hmac_alert_test/latest

Test location /workspace/coverage/default/40.hmac_back_pressure.2655640600
Short name T273
Test name
Test status
Simulation time 1985484770 ps
CPU time 42.78 seconds
Started Jun 30 06:37:02 PM PDT 24
Finished Jun 30 06:37:45 PM PDT 24
Peak memory 200320 kb
Host smart-e04cd056-5cfb-47ae-8b43-516f524b78e6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2655640600 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_back_pressure.2655640600
Directory /workspace/40.hmac_back_pressure/latest

Test location /workspace/coverage/default/40.hmac_burst_wr.1212422029
Short name T480
Test name
Test status
Simulation time 2720462943 ps
CPU time 48.57 seconds
Started Jun 30 06:37:05 PM PDT 24
Finished Jun 30 06:37:54 PM PDT 24
Peak memory 200320 kb
Host smart-bb2b290a-50ff-4637-b82e-5953a00ceee1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212422029 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_burst_wr.1212422029
Directory /workspace/40.hmac_burst_wr/latest

Test location /workspace/coverage/default/40.hmac_datapath_stress.4222945825
Short name T334
Test name
Test status
Simulation time 29759162162 ps
CPU time 483.33 seconds
Started Jun 30 06:36:59 PM PDT 24
Finished Jun 30 06:45:03 PM PDT 24
Peak memory 494032 kb
Host smart-97a1b607-9b7a-45bf-a0f6-4c9c8946c2fe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4222945825 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_datapath_stress.4222945825
Directory /workspace/40.hmac_datapath_stress/latest

Test location /workspace/coverage/default/40.hmac_error.3498162686
Short name T620
Test name
Test status
Simulation time 901475176 ps
CPU time 54.41 seconds
Started Jun 30 06:37:07 PM PDT 24
Finished Jun 30 06:38:02 PM PDT 24
Peak memory 200244 kb
Host smart-0accb356-f061-46e8-ab2b-784ce762af1b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498162686 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_error.3498162686
Directory /workspace/40.hmac_error/latest

Test location /workspace/coverage/default/40.hmac_long_msg.2948073727
Short name T168
Test name
Test status
Simulation time 1927571848 ps
CPU time 112.43 seconds
Started Jun 30 06:37:06 PM PDT 24
Finished Jun 30 06:38:59 PM PDT 24
Peak memory 200276 kb
Host smart-02fd5abf-3402-42db-9174-297f75f0d9d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948073727 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_long_msg.2948073727
Directory /workspace/40.hmac_long_msg/latest

Test location /workspace/coverage/default/40.hmac_smoke.3402498713
Short name T70
Test name
Test status
Simulation time 2163086846 ps
CPU time 13.24 seconds
Started Jun 30 06:37:01 PM PDT 24
Finished Jun 30 06:37:15 PM PDT 24
Peak memory 200412 kb
Host smart-88a4bae5-6a37-4ed7-9e70-367428724f31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402498713 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_smoke.3402498713
Directory /workspace/40.hmac_smoke/latest

Test location /workspace/coverage/default/40.hmac_stress_all.1490887843
Short name T136
Test name
Test status
Simulation time 680841348980 ps
CPU time 2965.74 seconds
Started Jun 30 06:37:07 PM PDT 24
Finished Jun 30 07:26:33 PM PDT 24
Peak memory 504140 kb
Host smart-01d2e23c-8bc2-42c2-9748-273fe6ab0ad6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490887843 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.hmac_stress_all.1490887843
Directory /workspace/40.hmac_stress_all/latest

Test location /workspace/coverage/default/40.hmac_test_hmac256_vectors.3173339389
Short name T650
Test name
Test status
Simulation time 2040553044 ps
CPU time 30.05 seconds
Started Jun 30 06:37:06 PM PDT 24
Finished Jun 30 06:37:36 PM PDT 24
Peak memory 200324 kb
Host smart-f2f5270b-27f2-4749-98fc-138f76fc79b3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3173339389 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_test_hmac256_vectors.3173339389
Directory /workspace/40.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/40.hmac_test_hmac384_vectors.3704044276
Short name T261
Test name
Test status
Simulation time 23624709180 ps
CPU time 88.02 seconds
Started Jun 30 06:37:06 PM PDT 24
Finished Jun 30 06:38:35 PM PDT 24
Peak memory 200360 kb
Host smart-372ee499-ae99-477e-a7c9-3a5ccc68f999
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3704044276 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_test_hmac384_vectors.3704044276
Directory /workspace/40.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/40.hmac_test_hmac512_vectors.4048957311
Short name T482
Test name
Test status
Simulation time 42082557586 ps
CPU time 56.5 seconds
Started Jun 30 06:37:05 PM PDT 24
Finished Jun 30 06:38:02 PM PDT 24
Peak memory 200340 kb
Host smart-226aa323-a996-4128-9c8a-df0abecc2c57
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4048957311 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_test_hmac512_vectors.4048957311
Directory /workspace/40.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/40.hmac_test_sha256_vectors.817872568
Short name T795
Test name
Test status
Simulation time 30054697255 ps
CPU time 422.72 seconds
Started Jun 30 06:37:06 PM PDT 24
Finished Jun 30 06:44:09 PM PDT 24
Peak memory 200512 kb
Host smart-251c3ec1-0dca-4ce6-bd85-2c04ebdced95
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=817872568 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_test_sha256_vectors.817872568
Directory /workspace/40.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/40.hmac_test_sha384_vectors.1638871234
Short name T566
Test name
Test status
Simulation time 31243139628 ps
CPU time 1828.65 seconds
Started Jun 30 06:37:07 PM PDT 24
Finished Jun 30 07:07:36 PM PDT 24
Peak memory 216692 kb
Host smart-b3c015f2-56d8-4cda-872e-517e35413791
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1638871234 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_test_sha384_vectors.1638871234
Directory /workspace/40.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/40.hmac_test_sha512_vectors.114192891
Short name T491
Test name
Test status
Simulation time 476488120606 ps
CPU time 2079.2 seconds
Started Jun 30 06:37:05 PM PDT 24
Finished Jun 30 07:11:45 PM PDT 24
Peak memory 215772 kb
Host smart-93b61d7e-f2f5-4541-9830-17cb05c86da9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=114192891 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_test_sha512_vectors.114192891
Directory /workspace/40.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/40.hmac_wipe_secret.2648471148
Short name T486
Test name
Test status
Simulation time 74170179942 ps
CPU time 88.94 seconds
Started Jun 30 06:37:05 PM PDT 24
Finished Jun 30 06:38:35 PM PDT 24
Peak memory 200408 kb
Host smart-4692e8ed-ab8c-4778-8e7a-e05095c85040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648471148 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_wipe_secret.2648471148
Directory /workspace/40.hmac_wipe_secret/latest

Test location /workspace/coverage/default/41.hmac_alert_test.100991527
Short name T747
Test name
Test status
Simulation time 105287339 ps
CPU time 0.55 seconds
Started Jun 30 06:37:23 PM PDT 24
Finished Jun 30 06:37:25 PM PDT 24
Peak memory 197004 kb
Host smart-5a8c532e-3037-4fd5-ac16-39533a5f82fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100991527 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_alert_test.100991527
Directory /workspace/41.hmac_alert_test/latest

Test location /workspace/coverage/default/41.hmac_back_pressure.2406370980
Short name T551
Test name
Test status
Simulation time 965197476 ps
CPU time 47.83 seconds
Started Jun 30 06:37:11 PM PDT 24
Finished Jun 30 06:37:59 PM PDT 24
Peak memory 200356 kb
Host smart-473037b5-3283-4f6c-ad4c-231567f050d7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2406370980 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_back_pressure.2406370980
Directory /workspace/41.hmac_back_pressure/latest

Test location /workspace/coverage/default/41.hmac_burst_wr.4022256643
Short name T692
Test name
Test status
Simulation time 117110401 ps
CPU time 3.41 seconds
Started Jun 30 06:37:11 PM PDT 24
Finished Jun 30 06:37:15 PM PDT 24
Peak memory 200240 kb
Host smart-189cad29-bffc-4dc3-a6f9-c225aaf263bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022256643 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_burst_wr.4022256643
Directory /workspace/41.hmac_burst_wr/latest

Test location /workspace/coverage/default/41.hmac_datapath_stress.2797740021
Short name T752
Test name
Test status
Simulation time 4134705447 ps
CPU time 1097.79 seconds
Started Jun 30 06:37:11 PM PDT 24
Finished Jun 30 06:55:29 PM PDT 24
Peak memory 751000 kb
Host smart-99339ace-a218-4a4c-a805-4bb67cd192a1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2797740021 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_datapath_stress.2797740021
Directory /workspace/41.hmac_datapath_stress/latest

Test location /workspace/coverage/default/41.hmac_error.1245971626
Short name T722
Test name
Test status
Simulation time 8449368275 ps
CPU time 122.11 seconds
Started Jun 30 06:37:12 PM PDT 24
Finished Jun 30 06:39:14 PM PDT 24
Peak memory 200532 kb
Host smart-4cb9b1b1-5be9-4f58-a59e-e3cf6d4e29c4
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245971626 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_error.1245971626
Directory /workspace/41.hmac_error/latest

Test location /workspace/coverage/default/41.hmac_long_msg.4274695136
Short name T694
Test name
Test status
Simulation time 51311927854 ps
CPU time 61.64 seconds
Started Jun 30 06:37:13 PM PDT 24
Finished Jun 30 06:38:14 PM PDT 24
Peak memory 200360 kb
Host smart-1953619e-2bb7-4bb5-8a08-236c6f4480c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274695136 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_long_msg.4274695136
Directory /workspace/41.hmac_long_msg/latest

Test location /workspace/coverage/default/41.hmac_smoke.1305274885
Short name T461
Test name
Test status
Simulation time 55294457 ps
CPU time 1.71 seconds
Started Jun 30 06:37:11 PM PDT 24
Finished Jun 30 06:37:14 PM PDT 24
Peak memory 200320 kb
Host smart-a45ec7b9-0c47-49ef-925a-b63ba322d1b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305274885 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_smoke.1305274885
Directory /workspace/41.hmac_smoke/latest

Test location /workspace/coverage/default/41.hmac_test_hmac256_vectors.3191481834
Short name T280
Test name
Test status
Simulation time 10982589984 ps
CPU time 40.05 seconds
Started Jun 30 06:37:22 PM PDT 24
Finished Jun 30 06:38:03 PM PDT 24
Peak memory 200312 kb
Host smart-06b51013-a6fa-48be-bbdf-7adaf23df5a3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3191481834 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_test_hmac256_vectors.3191481834
Directory /workspace/41.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/41.hmac_test_hmac384_vectors.2437974166
Short name T284
Test name
Test status
Simulation time 5464125752 ps
CPU time 38.75 seconds
Started Jun 30 06:37:22 PM PDT 24
Finished Jun 30 06:38:01 PM PDT 24
Peak memory 200352 kb
Host smart-68048d31-5e50-47b5-83c8-3e424ec87935
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2437974166 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_test_hmac384_vectors.2437974166
Directory /workspace/41.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/41.hmac_test_hmac512_vectors.3504547832
Short name T548
Test name
Test status
Simulation time 11923042296 ps
CPU time 104.17 seconds
Started Jun 30 06:37:17 PM PDT 24
Finished Jun 30 06:39:01 PM PDT 24
Peak memory 200380 kb
Host smart-bc2bf095-b720-47fb-894d-dc7631ae57fa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3504547832 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_test_hmac512_vectors.3504547832
Directory /workspace/41.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/41.hmac_test_sha256_vectors.1833548839
Short name T587
Test name
Test status
Simulation time 7790075871 ps
CPU time 442.54 seconds
Started Jun 30 06:37:22 PM PDT 24
Finished Jun 30 06:44:45 PM PDT 24
Peak memory 200244 kb
Host smart-25ebdfc0-5fc4-4a72-b2f0-3fad66e7410a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1833548839 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_test_sha256_vectors.1833548839
Directory /workspace/41.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/41.hmac_test_sha384_vectors.3083349431
Short name T541
Test name
Test status
Simulation time 583626793008 ps
CPU time 2213.38 seconds
Started Jun 30 06:37:16 PM PDT 24
Finished Jun 30 07:14:10 PM PDT 24
Peak memory 216508 kb
Host smart-e5935c8d-c1a8-48ab-bdb7-5e223e0c357d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3083349431 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_test_sha384_vectors.3083349431
Directory /workspace/41.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/41.hmac_test_sha512_vectors.4184060924
Short name T343
Test name
Test status
Simulation time 266082522082 ps
CPU time 1949.25 seconds
Started Jun 30 06:37:15 PM PDT 24
Finished Jun 30 07:09:45 PM PDT 24
Peak memory 215864 kb
Host smart-7b45a1ec-1c4e-42c7-9852-ca4a670e79c9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4184060924 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_test_sha512_vectors.4184060924
Directory /workspace/41.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/41.hmac_wipe_secret.1595346393
Short name T119
Test name
Test status
Simulation time 3742864602 ps
CPU time 45.58 seconds
Started Jun 30 06:37:22 PM PDT 24
Finished Jun 30 06:38:08 PM PDT 24
Peak memory 200364 kb
Host smart-3662349d-e14b-4355-a066-c28c7471bec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1595346393 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_wipe_secret.1595346393
Directory /workspace/41.hmac_wipe_secret/latest

Test location /workspace/coverage/default/42.hmac_alert_test.423030993
Short name T438
Test name
Test status
Simulation time 30916996 ps
CPU time 0.6 seconds
Started Jun 30 06:37:31 PM PDT 24
Finished Jun 30 06:37:32 PM PDT 24
Peak memory 196348 kb
Host smart-2680a8fe-f753-480d-8924-e392fc94d11d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423030993 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_alert_test.423030993
Directory /workspace/42.hmac_alert_test/latest

Test location /workspace/coverage/default/42.hmac_back_pressure.1624837648
Short name T367
Test name
Test status
Simulation time 1469321425 ps
CPU time 11.4 seconds
Started Jun 30 06:37:23 PM PDT 24
Finished Jun 30 06:37:35 PM PDT 24
Peak memory 200312 kb
Host smart-f04add36-edd4-415b-adcb-36fee437af5e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1624837648 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_back_pressure.1624837648
Directory /workspace/42.hmac_back_pressure/latest

Test location /workspace/coverage/default/42.hmac_burst_wr.2954151995
Short name T539
Test name
Test status
Simulation time 1642903879 ps
CPU time 7.85 seconds
Started Jun 30 06:37:28 PM PDT 24
Finished Jun 30 06:37:36 PM PDT 24
Peak memory 200248 kb
Host smart-98935d06-3511-4a20-820a-8cddcac8a395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954151995 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_burst_wr.2954151995
Directory /workspace/42.hmac_burst_wr/latest

Test location /workspace/coverage/default/42.hmac_datapath_stress.1937820245
Short name T30
Test name
Test status
Simulation time 10342133356 ps
CPU time 610.59 seconds
Started Jun 30 06:37:22 PM PDT 24
Finished Jun 30 06:47:33 PM PDT 24
Peak memory 712856 kb
Host smart-79284d0a-443d-44ab-a09e-7788d578eaf7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1937820245 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_datapath_stress.1937820245
Directory /workspace/42.hmac_datapath_stress/latest

Test location /workspace/coverage/default/42.hmac_error.1767792509
Short name T629
Test name
Test status
Simulation time 93742848912 ps
CPU time 164.67 seconds
Started Jun 30 06:37:22 PM PDT 24
Finished Jun 30 06:40:07 PM PDT 24
Peak memory 200364 kb
Host smart-0a29a33e-aacf-4a3a-bef0-0ba979902e59
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767792509 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_error.1767792509
Directory /workspace/42.hmac_error/latest

Test location /workspace/coverage/default/42.hmac_long_msg.1739033581
Short name T561
Test name
Test status
Simulation time 3426638749 ps
CPU time 97.57 seconds
Started Jun 30 06:37:22 PM PDT 24
Finished Jun 30 06:39:00 PM PDT 24
Peak memory 200348 kb
Host smart-c7644fba-1cf1-46fa-9a68-01f820aaa0b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739033581 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_long_msg.1739033581
Directory /workspace/42.hmac_long_msg/latest

Test location /workspace/coverage/default/42.hmac_smoke.3153114525
Short name T260
Test name
Test status
Simulation time 749873187 ps
CPU time 10.96 seconds
Started Jun 30 06:37:23 PM PDT 24
Finished Jun 30 06:37:34 PM PDT 24
Peak memory 200304 kb
Host smart-707c0cfd-0028-4d64-8915-3ebaa7c45502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153114525 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_smoke.3153114525
Directory /workspace/42.hmac_smoke/latest

Test location /workspace/coverage/default/42.hmac_stress_all.790002390
Short name T760
Test name
Test status
Simulation time 1020941054623 ps
CPU time 4331.48 seconds
Started Jun 30 06:37:30 PM PDT 24
Finished Jun 30 07:49:43 PM PDT 24
Peak memory 748824 kb
Host smart-de90ca47-0e49-47c3-a5c7-8cf17487f52e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790002390 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 42.hmac_stress_all.790002390
Directory /workspace/42.hmac_stress_all/latest

Test location /workspace/coverage/default/42.hmac_test_hmac256_vectors.3695597907
Short name T449
Test name
Test status
Simulation time 893094027 ps
CPU time 29.77 seconds
Started Jun 30 06:37:22 PM PDT 24
Finished Jun 30 06:37:53 PM PDT 24
Peak memory 200340 kb
Host smart-a0e9cc8f-1271-44ca-85eb-8b73a09d0c91
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3695597907 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_test_hmac256_vectors.3695597907
Directory /workspace/42.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/42.hmac_test_hmac384_vectors.3657722323
Short name T528
Test name
Test status
Simulation time 1379121038 ps
CPU time 38.03 seconds
Started Jun 30 06:37:22 PM PDT 24
Finished Jun 30 06:38:00 PM PDT 24
Peak memory 200340 kb
Host smart-c729ae72-02ff-4bd9-8008-252815af7880
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3657722323 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_test_hmac384_vectors.3657722323
Directory /workspace/42.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/42.hmac_test_hmac512_vectors.1143679086
Short name T345
Test name
Test status
Simulation time 16088784987 ps
CPU time 51.52 seconds
Started Jun 30 06:37:28 PM PDT 24
Finished Jun 30 06:38:20 PM PDT 24
Peak memory 200372 kb
Host smart-99373a4c-031c-4559-b8e4-c2d9cf59cc1c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1143679086 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_test_hmac512_vectors.1143679086
Directory /workspace/42.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/42.hmac_test_sha256_vectors.2392144822
Short name T368
Test name
Test status
Simulation time 23781257691 ps
CPU time 428.98 seconds
Started Jun 30 06:37:27 PM PDT 24
Finished Jun 30 06:44:37 PM PDT 24
Peak memory 200192 kb
Host smart-25c247b3-b828-4082-8fd8-9dbb881da0fc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2392144822 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_test_sha256_vectors.2392144822
Directory /workspace/42.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/42.hmac_test_sha384_vectors.583771059
Short name T395
Test name
Test status
Simulation time 107055006629 ps
CPU time 1869.25 seconds
Started Jun 30 06:37:22 PM PDT 24
Finished Jun 30 07:08:32 PM PDT 24
Peak memory 216340 kb
Host smart-84d35ecb-8d9c-44d1-a24b-791becccd294
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=583771059 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_test_sha384_vectors.583771059
Directory /workspace/42.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/42.hmac_test_sha512_vectors.30533080
Short name T226
Test name
Test status
Simulation time 68321180031 ps
CPU time 2081.86 seconds
Started Jun 30 06:37:23 PM PDT 24
Finished Jun 30 07:12:05 PM PDT 24
Peak memory 215932 kb
Host smart-ccf1fe53-ffa5-4dc7-8188-4e429829b871
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=30533080 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_test_sha512_vectors.30533080
Directory /workspace/42.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/42.hmac_wipe_secret.961320262
Short name T332
Test name
Test status
Simulation time 5905775511 ps
CPU time 16.46 seconds
Started Jun 30 06:37:23 PM PDT 24
Finished Jun 30 06:37:40 PM PDT 24
Peak memory 200316 kb
Host smart-1574a829-5c4a-426d-aff2-a2f49a01f382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=961320262 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_wipe_secret.961320262
Directory /workspace/42.hmac_wipe_secret/latest

Test location /workspace/coverage/default/43.hmac_alert_test.2740931368
Short name T279
Test name
Test status
Simulation time 35340652 ps
CPU time 0.57 seconds
Started Jun 30 06:37:31 PM PDT 24
Finished Jun 30 06:37:32 PM PDT 24
Peak memory 195288 kb
Host smart-b9a580c2-9abc-4aa9-9291-a1586b863586
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740931368 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_alert_test.2740931368
Directory /workspace/43.hmac_alert_test/latest

Test location /workspace/coverage/default/43.hmac_back_pressure.360608574
Short name T601
Test name
Test status
Simulation time 834311207 ps
CPU time 40.27 seconds
Started Jun 30 06:37:29 PM PDT 24
Finished Jun 30 06:38:10 PM PDT 24
Peak memory 200284 kb
Host smart-51ea14cf-282a-402a-a052-ad1dc1ac5b04
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=360608574 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_back_pressure.360608574
Directory /workspace/43.hmac_back_pressure/latest

Test location /workspace/coverage/default/43.hmac_burst_wr.705599027
Short name T607
Test name
Test status
Simulation time 4094979757 ps
CPU time 54.39 seconds
Started Jun 30 06:37:29 PM PDT 24
Finished Jun 30 06:38:24 PM PDT 24
Peak memory 200480 kb
Host smart-ce291071-e3c6-4b5d-aaca-e14ec7b80dc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=705599027 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_burst_wr.705599027
Directory /workspace/43.hmac_burst_wr/latest

Test location /workspace/coverage/default/43.hmac_datapath_stress.3612124652
Short name T474
Test name
Test status
Simulation time 3593568046 ps
CPU time 874.99 seconds
Started Jun 30 06:37:29 PM PDT 24
Finished Jun 30 06:52:05 PM PDT 24
Peak memory 731020 kb
Host smart-69e068a1-64c8-40c3-b065-ae7924376031
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3612124652 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_datapath_stress.3612124652
Directory /workspace/43.hmac_datapath_stress/latest

Test location /workspace/coverage/default/43.hmac_error.1606302459
Short name T361
Test name
Test status
Simulation time 699136175 ps
CPU time 37.23 seconds
Started Jun 30 06:37:30 PM PDT 24
Finished Jun 30 06:38:08 PM PDT 24
Peak memory 200292 kb
Host smart-acb05e2b-e054-42a3-b263-91b11685ef86
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606302459 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_error.1606302459
Directory /workspace/43.hmac_error/latest

Test location /workspace/coverage/default/43.hmac_long_msg.1930425089
Short name T742
Test name
Test status
Simulation time 508489346 ps
CPU time 5.59 seconds
Started Jun 30 06:37:30 PM PDT 24
Finished Jun 30 06:37:36 PM PDT 24
Peak memory 200284 kb
Host smart-d386aa7c-a5bd-4e2b-a8a4-14ed6495a4b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1930425089 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_long_msg.1930425089
Directory /workspace/43.hmac_long_msg/latest

Test location /workspace/coverage/default/43.hmac_smoke.4251019131
Short name T640
Test name
Test status
Simulation time 320693375 ps
CPU time 6.17 seconds
Started Jun 30 06:37:33 PM PDT 24
Finished Jun 30 06:37:40 PM PDT 24
Peak memory 200240 kb
Host smart-388546e9-cd87-4426-8636-04c6d48caa12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251019131 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_smoke.4251019131
Directory /workspace/43.hmac_smoke/latest

Test location /workspace/coverage/default/43.hmac_stress_all.3859591388
Short name T117
Test name
Test status
Simulation time 23640382854 ps
CPU time 284.32 seconds
Started Jun 30 06:37:30 PM PDT 24
Finished Jun 30 06:42:15 PM PDT 24
Peak memory 200592 kb
Host smart-a2ea75d7-2c00-404f-b4e8-f3eab22393e4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859591388 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.hmac_stress_all.3859591388
Directory /workspace/43.hmac_stress_all/latest

Test location /workspace/coverage/default/43.hmac_test_hmac256_vectors.3373640655
Short name T463
Test name
Test status
Simulation time 12112208808 ps
CPU time 70.79 seconds
Started Jun 30 06:37:28 PM PDT 24
Finished Jun 30 06:38:39 PM PDT 24
Peak memory 200352 kb
Host smart-1763b0cc-6460-4278-990f-85a72fbe054e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3373640655 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_test_hmac256_vectors.3373640655
Directory /workspace/43.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/43.hmac_test_hmac384_vectors.2289056355
Short name T231
Test name
Test status
Simulation time 9063587457 ps
CPU time 74.23 seconds
Started Jun 30 06:37:30 PM PDT 24
Finished Jun 30 06:38:45 PM PDT 24
Peak memory 200360 kb
Host smart-2a3b1eff-7a70-4216-a84b-c2e0394c3c57
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2289056355 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_test_hmac384_vectors.2289056355
Directory /workspace/43.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/43.hmac_test_hmac512_vectors.1760394853
Short name T148
Test name
Test status
Simulation time 6653316697 ps
CPU time 105.85 seconds
Started Jun 30 06:37:29 PM PDT 24
Finished Jun 30 06:39:15 PM PDT 24
Peak memory 200616 kb
Host smart-8563b7eb-c67a-40c6-84ec-fedac8d73e34
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1760394853 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_test_hmac512_vectors.1760394853
Directory /workspace/43.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/43.hmac_test_sha256_vectors.2141726482
Short name T582
Test name
Test status
Simulation time 7966286863 ps
CPU time 436.01 seconds
Started Jun 30 06:37:33 PM PDT 24
Finished Jun 30 06:44:50 PM PDT 24
Peak memory 200252 kb
Host smart-40ce43d7-6d8e-443e-91d4-9cf80b089cf6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2141726482 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_test_sha256_vectors.2141726482
Directory /workspace/43.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/43.hmac_test_sha384_vectors.648412312
Short name T645
Test name
Test status
Simulation time 28548184701 ps
CPU time 1634.86 seconds
Started Jun 30 06:37:30 PM PDT 24
Finished Jun 30 07:04:46 PM PDT 24
Peak memory 216188 kb
Host smart-71dedb17-7725-466c-8579-2a9367767397
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=648412312 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_test_sha384_vectors.648412312
Directory /workspace/43.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/43.hmac_test_sha512_vectors.3348077187
Short name T147
Test name
Test status
Simulation time 64012504864 ps
CPU time 1815.67 seconds
Started Jun 30 06:37:33 PM PDT 24
Finished Jun 30 07:07:49 PM PDT 24
Peak memory 216164 kb
Host smart-5007d6f6-5574-422f-8793-c1455af8f58e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3348077187 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_test_sha512_vectors.3348077187
Directory /workspace/43.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/43.hmac_wipe_secret.2608613544
Short name T290
Test name
Test status
Simulation time 3020367724 ps
CPU time 42.53 seconds
Started Jun 30 06:37:30 PM PDT 24
Finished Jun 30 06:38:13 PM PDT 24
Peak memory 200332 kb
Host smart-35608fc6-ef01-45d4-bee4-a5ff230cef94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608613544 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_wipe_secret.2608613544
Directory /workspace/43.hmac_wipe_secret/latest

Test location /workspace/coverage/default/44.hmac_alert_test.2453702678
Short name T372
Test name
Test status
Simulation time 21071578 ps
CPU time 0.61 seconds
Started Jun 30 06:37:34 PM PDT 24
Finished Jun 30 06:37:36 PM PDT 24
Peak memory 196264 kb
Host smart-006fa8db-f7a6-4420-b70d-750242852839
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453702678 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_alert_test.2453702678
Directory /workspace/44.hmac_alert_test/latest

Test location /workspace/coverage/default/44.hmac_back_pressure.2267935165
Short name T360
Test name
Test status
Simulation time 5344814784 ps
CPU time 47.65 seconds
Started Jun 30 06:37:32 PM PDT 24
Finished Jun 30 06:38:20 PM PDT 24
Peak memory 200332 kb
Host smart-c49748cc-dbe2-43f6-80c0-0a438f29dcde
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2267935165 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_back_pressure.2267935165
Directory /workspace/44.hmac_back_pressure/latest

Test location /workspace/coverage/default/44.hmac_burst_wr.3185655264
Short name T275
Test name
Test status
Simulation time 2942868446 ps
CPU time 41.15 seconds
Started Jun 30 06:37:38 PM PDT 24
Finished Jun 30 06:38:19 PM PDT 24
Peak memory 200388 kb
Host smart-7a63ff35-5ced-4e82-8a0f-c15ee2f3d927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185655264 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_burst_wr.3185655264
Directory /workspace/44.hmac_burst_wr/latest

Test location /workspace/coverage/default/44.hmac_datapath_stress.1699115268
Short name T242
Test name
Test status
Simulation time 11868762982 ps
CPU time 765.4 seconds
Started Jun 30 06:37:29 PM PDT 24
Finished Jun 30 06:50:15 PM PDT 24
Peak memory 730420 kb
Host smart-33f2a6cd-a7c8-4a9c-87e8-c9cf7075deeb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1699115268 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_datapath_stress.1699115268
Directory /workspace/44.hmac_datapath_stress/latest

Test location /workspace/coverage/default/44.hmac_error.3692601102
Short name T662
Test name
Test status
Simulation time 38436767935 ps
CPU time 163.11 seconds
Started Jun 30 06:37:36 PM PDT 24
Finished Jun 30 06:40:19 PM PDT 24
Peak memory 200376 kb
Host smart-aacbbe85-1784-4ec0-ba75-d323ab0b07de
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692601102 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_error.3692601102
Directory /workspace/44.hmac_error/latest

Test location /workspace/coverage/default/44.hmac_long_msg.405146292
Short name T230
Test name
Test status
Simulation time 790806086 ps
CPU time 45.68 seconds
Started Jun 30 06:37:33 PM PDT 24
Finished Jun 30 06:38:19 PM PDT 24
Peak memory 200256 kb
Host smart-49c43edb-52c5-48df-b06f-531f0272954b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=405146292 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_long_msg.405146292
Directory /workspace/44.hmac_long_msg/latest

Test location /workspace/coverage/default/44.hmac_smoke.3740459162
Short name T505
Test name
Test status
Simulation time 528770543 ps
CPU time 5.24 seconds
Started Jun 30 06:37:29 PM PDT 24
Finished Jun 30 06:37:35 PM PDT 24
Peak memory 200384 kb
Host smart-453188c6-92c3-4450-9d8a-18d91ba2c2cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740459162 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_smoke.3740459162
Directory /workspace/44.hmac_smoke/latest

Test location /workspace/coverage/default/44.hmac_stress_all.1719544128
Short name T58
Test name
Test status
Simulation time 38763646115 ps
CPU time 160.58 seconds
Started Jun 30 06:37:34 PM PDT 24
Finished Jun 30 06:40:15 PM PDT 24
Peak memory 200340 kb
Host smart-fad4aec7-2295-4e7a-96b2-169811d55329
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719544128 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.hmac_stress_all.1719544128
Directory /workspace/44.hmac_stress_all/latest

Test location /workspace/coverage/default/44.hmac_test_hmac256_vectors.1782994400
Short name T328
Test name
Test status
Simulation time 919996563 ps
CPU time 30.31 seconds
Started Jun 30 06:37:35 PM PDT 24
Finished Jun 30 06:38:06 PM PDT 24
Peak memory 200356 kb
Host smart-f30f4878-127a-44be-9bea-9b6b72e83cb3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1782994400 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_test_hmac256_vectors.1782994400
Directory /workspace/44.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/44.hmac_test_hmac384_vectors.244787614
Short name T573
Test name
Test status
Simulation time 29506236595 ps
CPU time 82.71 seconds
Started Jun 30 06:37:34 PM PDT 24
Finished Jun 30 06:38:57 PM PDT 24
Peak memory 200380 kb
Host smart-4df730c7-93f6-4b14-81d6-56bc1795c605
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=244787614 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_test_hmac384_vectors.244787614
Directory /workspace/44.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/44.hmac_test_hmac512_vectors.3996464803
Short name T605
Test name
Test status
Simulation time 15835081691 ps
CPU time 58.51 seconds
Started Jun 30 06:37:36 PM PDT 24
Finished Jun 30 06:38:35 PM PDT 24
Peak memory 200344 kb
Host smart-6db48071-74c1-4985-961a-3006ba1fe744
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3996464803 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_test_hmac512_vectors.3996464803
Directory /workspace/44.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/44.hmac_test_sha256_vectors.2750237840
Short name T358
Test name
Test status
Simulation time 194582864788 ps
CPU time 495.67 seconds
Started Jun 30 06:37:35 PM PDT 24
Finished Jun 30 06:45:51 PM PDT 24
Peak memory 200300 kb
Host smart-eee7e06a-8250-4ae9-b0b1-f7c49cab59f8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2750237840 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_test_sha256_vectors.2750237840
Directory /workspace/44.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/44.hmac_test_sha384_vectors.2391422408
Short name T10
Test name
Test status
Simulation time 28687663767 ps
CPU time 1557.92 seconds
Started Jun 30 06:37:35 PM PDT 24
Finished Jun 30 07:03:33 PM PDT 24
Peak memory 215876 kb
Host smart-6952a67e-832b-4447-abd2-838fcac251ad
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2391422408 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_test_sha384_vectors.2391422408
Directory /workspace/44.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/44.hmac_test_sha512_vectors.184707123
Short name T556
Test name
Test status
Simulation time 79140679011 ps
CPU time 1764.16 seconds
Started Jun 30 06:37:35 PM PDT 24
Finished Jun 30 07:07:00 PM PDT 24
Peak memory 215796 kb
Host smart-ac9ff9cd-6e4f-4033-be91-b859b3d943eb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=184707123 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_test_sha512_vectors.184707123
Directory /workspace/44.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/44.hmac_wipe_secret.3412700690
Short name T568
Test name
Test status
Simulation time 1555798607 ps
CPU time 64.66 seconds
Started Jun 30 06:37:34 PM PDT 24
Finished Jun 30 06:38:39 PM PDT 24
Peak memory 200328 kb
Host smart-0b6db813-a8af-4bd6-9d07-7c2de01a12ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412700690 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_wipe_secret.3412700690
Directory /workspace/44.hmac_wipe_secret/latest

Test location /workspace/coverage/default/45.hmac_alert_test.1003694408
Short name T354
Test name
Test status
Simulation time 13676537 ps
CPU time 0.6 seconds
Started Jun 30 06:37:43 PM PDT 24
Finished Jun 30 06:37:44 PM PDT 24
Peak memory 196256 kb
Host smart-f9e53f69-3816-42b6-b65f-e75b5e81268c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003694408 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_alert_test.1003694408
Directory /workspace/45.hmac_alert_test/latest

Test location /workspace/coverage/default/45.hmac_back_pressure.201340050
Short name T235
Test name
Test status
Simulation time 445493047 ps
CPU time 12.85 seconds
Started Jun 30 06:37:37 PM PDT 24
Finished Jun 30 06:37:50 PM PDT 24
Peak memory 200244 kb
Host smart-0d60d666-37b9-4be1-9376-7db8539bbfaf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=201340050 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_back_pressure.201340050
Directory /workspace/45.hmac_back_pressure/latest

Test location /workspace/coverage/default/45.hmac_burst_wr.2078861049
Short name T456
Test name
Test status
Simulation time 817494989 ps
CPU time 44.91 seconds
Started Jun 30 06:37:35 PM PDT 24
Finished Jun 30 06:38:20 PM PDT 24
Peak memory 200368 kb
Host smart-c4c285be-9b98-4d36-b939-c5d21854d1a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078861049 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_burst_wr.2078861049
Directory /workspace/45.hmac_burst_wr/latest

Test location /workspace/coverage/default/45.hmac_datapath_stress.2944189586
Short name T552
Test name
Test status
Simulation time 11628756509 ps
CPU time 897.02 seconds
Started Jun 30 06:37:36 PM PDT 24
Finished Jun 30 06:52:34 PM PDT 24
Peak memory 713332 kb
Host smart-2a122064-01ab-413e-a8d4-14469a3a773f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2944189586 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_datapath_stress.2944189586
Directory /workspace/45.hmac_datapath_stress/latest

Test location /workspace/coverage/default/45.hmac_error.3194619876
Short name T715
Test name
Test status
Simulation time 62812649200 ps
CPU time 140.54 seconds
Started Jun 30 06:37:38 PM PDT 24
Finished Jun 30 06:39:59 PM PDT 24
Peak memory 200372 kb
Host smart-0650fe11-ce3e-45f3-bd2b-3ad3856963d2
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194619876 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_error.3194619876
Directory /workspace/45.hmac_error/latest

Test location /workspace/coverage/default/45.hmac_long_msg.654683901
Short name T724
Test name
Test status
Simulation time 16402632397 ps
CPU time 84.13 seconds
Started Jun 30 06:37:36 PM PDT 24
Finished Jun 30 06:39:00 PM PDT 24
Peak memory 200448 kb
Host smart-a3c5667e-d8b0-49ca-acce-16fadc5ec634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654683901 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_long_msg.654683901
Directory /workspace/45.hmac_long_msg/latest

Test location /workspace/coverage/default/45.hmac_smoke.3975120827
Short name T188
Test name
Test status
Simulation time 66111648 ps
CPU time 3.21 seconds
Started Jun 30 06:37:36 PM PDT 24
Finished Jun 30 06:37:40 PM PDT 24
Peak memory 200268 kb
Host smart-575c4648-547b-4a3a-b040-47057b45cfa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975120827 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_smoke.3975120827
Directory /workspace/45.hmac_smoke/latest

Test location /workspace/coverage/default/45.hmac_stress_all.1057925007
Short name T748
Test name
Test status
Simulation time 333159866674 ps
CPU time 1913.13 seconds
Started Jun 30 06:37:44 PM PDT 24
Finished Jun 30 07:09:38 PM PDT 24
Peak memory 208636 kb
Host smart-be2bc17c-7255-4832-a88f-f87fac952158
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057925007 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.hmac_stress_all.1057925007
Directory /workspace/45.hmac_stress_all/latest

Test location /workspace/coverage/default/45.hmac_test_hmac256_vectors.3941565343
Short name T378
Test name
Test status
Simulation time 19897718793 ps
CPU time 40.83 seconds
Started Jun 30 06:37:44 PM PDT 24
Finished Jun 30 06:38:25 PM PDT 24
Peak memory 200404 kb
Host smart-f80d05e4-06dd-4409-96f7-09d8db30f849
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3941565343 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_test_hmac256_vectors.3941565343
Directory /workspace/45.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/45.hmac_test_hmac384_vectors.2439877762
Short name T399
Test name
Test status
Simulation time 10239731984 ps
CPU time 84.19 seconds
Started Jun 30 06:37:44 PM PDT 24
Finished Jun 30 06:39:08 PM PDT 24
Peak memory 200376 kb
Host smart-cb0014c9-bdbd-424d-8eed-d351465efe0e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2439877762 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_test_hmac384_vectors.2439877762
Directory /workspace/45.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/45.hmac_test_hmac512_vectors.2231279747
Short name T526
Test name
Test status
Simulation time 39509819733 ps
CPU time 113.93 seconds
Started Jun 30 06:37:39 PM PDT 24
Finished Jun 30 06:39:34 PM PDT 24
Peak memory 200340 kb
Host smart-5a59fb57-eb02-4596-86b0-7e0ef6aaa725
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2231279747 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_test_hmac512_vectors.2231279747
Directory /workspace/45.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/45.hmac_test_sha256_vectors.2238824266
Short name T702
Test name
Test status
Simulation time 36918999237 ps
CPU time 484.48 seconds
Started Jun 30 06:37:38 PM PDT 24
Finished Jun 30 06:45:43 PM PDT 24
Peak memory 200344 kb
Host smart-9ab345e5-13e6-4249-a176-bc1561a6fe4f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2238824266 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_test_sha256_vectors.2238824266
Directory /workspace/45.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/45.hmac_test_sha384_vectors.344041672
Short name T453
Test name
Test status
Simulation time 31898913983 ps
CPU time 1898.9 seconds
Started Jun 30 06:37:42 PM PDT 24
Finished Jun 30 07:09:22 PM PDT 24
Peak memory 216560 kb
Host smart-49912276-11c4-4a3d-975e-90c1002dbe35
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=344041672 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_test_sha384_vectors.344041672
Directory /workspace/45.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/45.hmac_test_sha512_vectors.1525719270
Short name T478
Test name
Test status
Simulation time 115881973413 ps
CPU time 1589.3 seconds
Started Jun 30 06:37:42 PM PDT 24
Finished Jun 30 07:04:12 PM PDT 24
Peak memory 216728 kb
Host smart-4bc7fc19-d8bf-4d94-8032-8ca5cc9b6005
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1525719270 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_test_sha512_vectors.1525719270
Directory /workspace/45.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/45.hmac_wipe_secret.2860803831
Short name T14
Test name
Test status
Simulation time 4116245361 ps
CPU time 60.61 seconds
Started Jun 30 06:37:35 PM PDT 24
Finished Jun 30 06:38:36 PM PDT 24
Peak memory 200412 kb
Host smart-3cb05ab8-711a-4215-b9f3-b23bb7c53e0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860803831 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_wipe_secret.2860803831
Directory /workspace/45.hmac_wipe_secret/latest

Test location /workspace/coverage/default/46.hmac_alert_test.730233793
Short name T74
Test name
Test status
Simulation time 11365326 ps
CPU time 0.57 seconds
Started Jun 30 06:37:47 PM PDT 24
Finished Jun 30 06:37:48 PM PDT 24
Peak memory 195240 kb
Host smart-456e2b84-edd8-4203-a071-a3304a19145f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730233793 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_alert_test.730233793
Directory /workspace/46.hmac_alert_test/latest

Test location /workspace/coverage/default/46.hmac_back_pressure.3917697813
Short name T469
Test name
Test status
Simulation time 428538621 ps
CPU time 4.45 seconds
Started Jun 30 06:37:42 PM PDT 24
Finished Jun 30 06:37:46 PM PDT 24
Peak memory 200184 kb
Host smart-9eaca2ed-df3a-428b-b7fa-6afb72cc6bbc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3917697813 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_back_pressure.3917697813
Directory /workspace/46.hmac_back_pressure/latest

Test location /workspace/coverage/default/46.hmac_burst_wr.4056927507
Short name T245
Test name
Test status
Simulation time 8926695242 ps
CPU time 59.64 seconds
Started Jun 30 06:37:46 PM PDT 24
Finished Jun 30 06:38:47 PM PDT 24
Peak memory 208624 kb
Host smart-a0dd26d2-8635-4523-99fe-723ee2011b05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4056927507 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_burst_wr.4056927507
Directory /workspace/46.hmac_burst_wr/latest

Test location /workspace/coverage/default/46.hmac_datapath_stress.3448666083
Short name T697
Test name
Test status
Simulation time 5669675452 ps
CPU time 364.54 seconds
Started Jun 30 06:37:46 PM PDT 24
Finished Jun 30 06:43:51 PM PDT 24
Peak memory 662312 kb
Host smart-47139833-5585-418f-8656-7dc7a473eeea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3448666083 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_datapath_stress.3448666083
Directory /workspace/46.hmac_datapath_stress/latest

Test location /workspace/coverage/default/46.hmac_error.162426029
Short name T286
Test name
Test status
Simulation time 34057770900 ps
CPU time 49.81 seconds
Started Jun 30 06:37:49 PM PDT 24
Finished Jun 30 06:38:39 PM PDT 24
Peak memory 200416 kb
Host smart-228ed73d-6542-4ceb-a4aa-1232b4cbcb54
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162426029 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_error.162426029
Directory /workspace/46.hmac_error/latest

Test location /workspace/coverage/default/46.hmac_long_msg.2937555553
Short name T240
Test name
Test status
Simulation time 7934079478 ps
CPU time 115.68 seconds
Started Jun 30 06:37:40 PM PDT 24
Finished Jun 30 06:39:36 PM PDT 24
Peak memory 200352 kb
Host smart-5d2e098e-fa5b-4437-ae9a-4befa55f524d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937555553 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_long_msg.2937555553
Directory /workspace/46.hmac_long_msg/latest

Test location /workspace/coverage/default/46.hmac_smoke.170331320
Short name T451
Test name
Test status
Simulation time 69258569 ps
CPU time 3.25 seconds
Started Jun 30 06:37:41 PM PDT 24
Finished Jun 30 06:37:45 PM PDT 24
Peak memory 200316 kb
Host smart-62f348b4-500e-42e3-8197-6e9afdc35a3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=170331320 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_smoke.170331320
Directory /workspace/46.hmac_smoke/latest

Test location /workspace/coverage/default/46.hmac_stress_all.617685725
Short name T64
Test name
Test status
Simulation time 548228722603 ps
CPU time 1278.11 seconds
Started Jun 30 06:37:49 PM PDT 24
Finished Jun 30 06:59:07 PM PDT 24
Peak memory 618788 kb
Host smart-cfcc7f9f-2305-49d8-b49c-5aa7c23f91d7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617685725 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 46.hmac_stress_all.617685725
Directory /workspace/46.hmac_stress_all/latest

Test location /workspace/coverage/default/46.hmac_test_hmac256_vectors.3860622320
Short name T207
Test name
Test status
Simulation time 21203436238 ps
CPU time 64.13 seconds
Started Jun 30 06:37:47 PM PDT 24
Finished Jun 30 06:38:51 PM PDT 24
Peak memory 200316 kb
Host smart-a6a0cc09-e9af-4822-810f-92e4cca2d187
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3860622320 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_test_hmac256_vectors.3860622320
Directory /workspace/46.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/46.hmac_test_hmac384_vectors.2337062576
Short name T232
Test name
Test status
Simulation time 11435566649 ps
CPU time 94.4 seconds
Started Jun 30 06:37:48 PM PDT 24
Finished Jun 30 06:39:22 PM PDT 24
Peak memory 200308 kb
Host smart-af71bd80-3bd3-4309-baff-06a18779872f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2337062576 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_test_hmac384_vectors.2337062576
Directory /workspace/46.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/46.hmac_test_hmac512_vectors.3660054342
Short name T11
Test name
Test status
Simulation time 51763852219 ps
CPU time 104.88 seconds
Started Jun 30 06:37:46 PM PDT 24
Finished Jun 30 06:39:31 PM PDT 24
Peak memory 200288 kb
Host smart-a675ce09-7e45-4d70-ad51-35767e87c539
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3660054342 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_test_hmac512_vectors.3660054342
Directory /workspace/46.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/46.hmac_test_sha256_vectors.838008582
Short name T496
Test name
Test status
Simulation time 221462093736 ps
CPU time 549.28 seconds
Started Jun 30 06:37:47 PM PDT 24
Finished Jun 30 06:46:57 PM PDT 24
Peak memory 200268 kb
Host smart-854ebe08-3d0f-45c3-b176-873fd94ee6dc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=838008582 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_test_sha256_vectors.838008582
Directory /workspace/46.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/46.hmac_test_sha384_vectors.1477910948
Short name T741
Test name
Test status
Simulation time 621836255495 ps
CPU time 2078.09 seconds
Started Jun 30 06:37:48 PM PDT 24
Finished Jun 30 07:12:27 PM PDT 24
Peak memory 216336 kb
Host smart-7069f4a7-a8f7-46e1-bd0b-c90eaa38a0d3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1477910948 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_test_sha384_vectors.1477910948
Directory /workspace/46.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/46.hmac_test_sha512_vectors.1292483970
Short name T264
Test name
Test status
Simulation time 358929586065 ps
CPU time 2350.67 seconds
Started Jun 30 06:37:45 PM PDT 24
Finished Jun 30 07:16:56 PM PDT 24
Peak memory 216672 kb
Host smart-253757a8-5b10-438e-af1f-59df16f6bfe2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1292483970 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_test_sha512_vectors.1292483970
Directory /workspace/46.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/46.hmac_wipe_secret.1409436268
Short name T302
Test name
Test status
Simulation time 5001043135 ps
CPU time 25.99 seconds
Started Jun 30 06:37:47 PM PDT 24
Finished Jun 30 06:38:13 PM PDT 24
Peak memory 200360 kb
Host smart-9a0b14ac-f94c-4956-b9a5-decc12e91571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409436268 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_wipe_secret.1409436268
Directory /workspace/46.hmac_wipe_secret/latest

Test location /workspace/coverage/default/47.hmac_alert_test.1482625779
Short name T544
Test name
Test status
Simulation time 13518939 ps
CPU time 0.58 seconds
Started Jun 30 06:37:52 PM PDT 24
Finished Jun 30 06:37:53 PM PDT 24
Peak memory 196252 kb
Host smart-aad59231-ec88-4e83-8feb-ddfbb069e9fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482625779 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_alert_test.1482625779
Directory /workspace/47.hmac_alert_test/latest

Test location /workspace/coverage/default/47.hmac_back_pressure.874481074
Short name T682
Test name
Test status
Simulation time 1629643431 ps
CPU time 18.64 seconds
Started Jun 30 06:37:52 PM PDT 24
Finished Jun 30 06:38:12 PM PDT 24
Peak memory 200288 kb
Host smart-1d6b3ac2-16cc-4c7a-87b9-2f7dcb3c3aa1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=874481074 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_back_pressure.874481074
Directory /workspace/47.hmac_back_pressure/latest

Test location /workspace/coverage/default/47.hmac_burst_wr.1564670885
Short name T363
Test name
Test status
Simulation time 964811985 ps
CPU time 49.62 seconds
Started Jun 30 06:37:52 PM PDT 24
Finished Jun 30 06:38:42 PM PDT 24
Peak memory 200328 kb
Host smart-34ebb309-84b8-47e8-9c6c-36cb368c8059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1564670885 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_burst_wr.1564670885
Directory /workspace/47.hmac_burst_wr/latest

Test location /workspace/coverage/default/47.hmac_datapath_stress.589489886
Short name T472
Test name
Test status
Simulation time 2225823521 ps
CPU time 594.31 seconds
Started Jun 30 06:37:52 PM PDT 24
Finished Jun 30 06:47:47 PM PDT 24
Peak memory 690720 kb
Host smart-5447f244-959b-4c27-9121-ecb89a86a813
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=589489886 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_datapath_stress.589489886
Directory /workspace/47.hmac_datapath_stress/latest

Test location /workspace/coverage/default/47.hmac_error.438086244
Short name T421
Test name
Test status
Simulation time 613694901 ps
CPU time 4.95 seconds
Started Jun 30 06:37:52 PM PDT 24
Finished Jun 30 06:37:57 PM PDT 24
Peak memory 200208 kb
Host smart-13232d42-af74-411c-9516-4c28884d4269
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438086244 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_error.438086244
Directory /workspace/47.hmac_error/latest

Test location /workspace/coverage/default/47.hmac_long_msg.1258062023
Short name T679
Test name
Test status
Simulation time 2559562429 ps
CPU time 35.3 seconds
Started Jun 30 06:37:47 PM PDT 24
Finished Jun 30 06:38:22 PM PDT 24
Peak memory 200444 kb
Host smart-f7480286-5fe9-4d22-962c-c44455e6c7f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258062023 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_long_msg.1258062023
Directory /workspace/47.hmac_long_msg/latest

Test location /workspace/coverage/default/47.hmac_smoke.4111235705
Short name T169
Test name
Test status
Simulation time 465511637 ps
CPU time 3.78 seconds
Started Jun 30 06:37:46 PM PDT 24
Finished Jun 30 06:37:50 PM PDT 24
Peak memory 200296 kb
Host smart-647536cb-9122-4a65-91d1-6ca2204bce70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111235705 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_smoke.4111235705
Directory /workspace/47.hmac_smoke/latest

Test location /workspace/coverage/default/47.hmac_stress_all.801709683
Short name T159
Test name
Test status
Simulation time 8592062870 ps
CPU time 618.66 seconds
Started Jun 30 06:37:53 PM PDT 24
Finished Jun 30 06:48:13 PM PDT 24
Peak memory 613656 kb
Host smart-080f765f-5c81-45eb-acc6-d02ed22cc182
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801709683 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 47.hmac_stress_all.801709683
Directory /workspace/47.hmac_stress_all/latest

Test location /workspace/coverage/default/47.hmac_test_hmac256_vectors.481676185
Short name T254
Test name
Test status
Simulation time 2373947079 ps
CPU time 29.73 seconds
Started Jun 30 06:37:55 PM PDT 24
Finished Jun 30 06:38:25 PM PDT 24
Peak memory 200384 kb
Host smart-1712564c-7452-4eb4-916b-bb144c7763a6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=481676185 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_test_hmac256_vectors.481676185
Directory /workspace/47.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/47.hmac_test_hmac384_vectors.2246966943
Short name T691
Test name
Test status
Simulation time 28224754385 ps
CPU time 92.62 seconds
Started Jun 30 06:37:54 PM PDT 24
Finished Jun 30 06:39:27 PM PDT 24
Peak memory 200352 kb
Host smart-1bcc347b-f17e-425d-8fac-5b7f8aa662ba
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2246966943 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_test_hmac384_vectors.2246966943
Directory /workspace/47.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/47.hmac_test_hmac512_vectors.1587012392
Short name T709
Test name
Test status
Simulation time 4538054984 ps
CPU time 71.89 seconds
Started Jun 30 06:37:52 PM PDT 24
Finished Jun 30 06:39:05 PM PDT 24
Peak memory 200368 kb
Host smart-3c10849a-0cb5-4655-bb9a-ee009dab088a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1587012392 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_test_hmac512_vectors.1587012392
Directory /workspace/47.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/47.hmac_test_sha256_vectors.4070043916
Short name T570
Test name
Test status
Simulation time 138060091499 ps
CPU time 448.9 seconds
Started Jun 30 06:37:53 PM PDT 24
Finished Jun 30 06:45:23 PM PDT 24
Peak memory 200284 kb
Host smart-34346507-7aa9-4d00-a17f-9017dd6c73a6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=4070043916 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_test_sha256_vectors.4070043916
Directory /workspace/47.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/47.hmac_test_sha384_vectors.3097344128
Short name T489
Test name
Test status
Simulation time 330209818374 ps
CPU time 1842.24 seconds
Started Jun 30 06:37:53 PM PDT 24
Finished Jun 30 07:08:37 PM PDT 24
Peak memory 216204 kb
Host smart-3cae0ed1-0416-4084-8a0d-0dda8cddfdcd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3097344128 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_test_sha384_vectors.3097344128
Directory /workspace/47.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/47.hmac_wipe_secret.1830561222
Short name T115
Test name
Test status
Simulation time 1986379145 ps
CPU time 75.34 seconds
Started Jun 30 06:37:52 PM PDT 24
Finished Jun 30 06:39:07 PM PDT 24
Peak memory 200320 kb
Host smart-a6129170-e3d3-449b-ac26-1bf5c7080ca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830561222 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_wipe_secret.1830561222
Directory /workspace/47.hmac_wipe_secret/latest

Test location /workspace/coverage/default/48.hmac_alert_test.4101470514
Short name T82
Test name
Test status
Simulation time 20175702 ps
CPU time 0.6 seconds
Started Jun 30 06:37:58 PM PDT 24
Finished Jun 30 06:37:59 PM PDT 24
Peak memory 197020 kb
Host smart-71f49aec-e020-40e0-a5aa-956f9884b84a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101470514 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_alert_test.4101470514
Directory /workspace/48.hmac_alert_test/latest

Test location /workspace/coverage/default/48.hmac_back_pressure.2797081984
Short name T409
Test name
Test status
Simulation time 3315631756 ps
CPU time 41.87 seconds
Started Jun 30 06:37:57 PM PDT 24
Finished Jun 30 06:38:40 PM PDT 24
Peak memory 200548 kb
Host smart-ea9a029a-0c3f-494f-b935-8b8ecf47ae22
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2797081984 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_back_pressure.2797081984
Directory /workspace/48.hmac_back_pressure/latest

Test location /workspace/coverage/default/48.hmac_burst_wr.2371623346
Short name T688
Test name
Test status
Simulation time 742803415 ps
CPU time 14.2 seconds
Started Jun 30 06:37:57 PM PDT 24
Finished Jun 30 06:38:11 PM PDT 24
Peak memory 200232 kb
Host smart-f7d324a6-58d3-400c-ac98-9898e6cc7c7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371623346 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_burst_wr.2371623346
Directory /workspace/48.hmac_burst_wr/latest

Test location /workspace/coverage/default/48.hmac_datapath_stress.754985055
Short name T729
Test name
Test status
Simulation time 1548511162 ps
CPU time 298.77 seconds
Started Jun 30 06:38:02 PM PDT 24
Finished Jun 30 06:43:02 PM PDT 24
Peak memory 505700 kb
Host smart-f4865c05-1613-4d81-9500-472ab5f2dc8f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=754985055 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_datapath_stress.754985055
Directory /workspace/48.hmac_datapath_stress/latest

Test location /workspace/coverage/default/48.hmac_error.2495980639
Short name T749
Test name
Test status
Simulation time 3731487050 ps
CPU time 23.42 seconds
Started Jun 30 06:37:57 PM PDT 24
Finished Jun 30 06:38:21 PM PDT 24
Peak memory 200320 kb
Host smart-9eaa8634-0a79-48c6-8ef6-0ea274d72b36
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495980639 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_error.2495980639
Directory /workspace/48.hmac_error/latest

Test location /workspace/coverage/default/48.hmac_long_msg.1494115759
Short name T445
Test name
Test status
Simulation time 17944051521 ps
CPU time 122.54 seconds
Started Jun 30 06:37:59 PM PDT 24
Finished Jun 30 06:40:02 PM PDT 24
Peak memory 216752 kb
Host smart-3f2acad4-c09e-424a-b941-17778a302c4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494115759 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_long_msg.1494115759
Directory /workspace/48.hmac_long_msg/latest

Test location /workspace/coverage/default/48.hmac_smoke.3494858202
Short name T733
Test name
Test status
Simulation time 116336267 ps
CPU time 2.58 seconds
Started Jun 30 06:37:54 PM PDT 24
Finished Jun 30 06:37:57 PM PDT 24
Peak memory 200360 kb
Host smart-95b76074-ae3b-4ca7-ac56-761f13f4fcdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494858202 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_smoke.3494858202
Directory /workspace/48.hmac_smoke/latest

Test location /workspace/coverage/default/48.hmac_stress_all.1659980922
Short name T384
Test name
Test status
Simulation time 16446518068 ps
CPU time 85.61 seconds
Started Jun 30 06:37:58 PM PDT 24
Finished Jun 30 06:39:24 PM PDT 24
Peak memory 200340 kb
Host smart-ac3bc64a-56de-4534-aa7b-58ba07d5c069
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659980922 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.hmac_stress_all.1659980922
Directory /workspace/48.hmac_stress_all/latest

Test location /workspace/coverage/default/48.hmac_test_hmac256_vectors.203514865
Short name T301
Test name
Test status
Simulation time 3659689929 ps
CPU time 32 seconds
Started Jun 30 06:37:57 PM PDT 24
Finished Jun 30 06:38:30 PM PDT 24
Peak memory 200616 kb
Host smart-281dce05-a7da-4421-bf2a-52036d9b29ce
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=203514865 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_test_hmac256_vectors.203514865
Directory /workspace/48.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/48.hmac_test_hmac384_vectors.94624698
Short name T252
Test name
Test status
Simulation time 1534495704 ps
CPU time 46.98 seconds
Started Jun 30 06:37:57 PM PDT 24
Finished Jun 30 06:38:45 PM PDT 24
Peak memory 200288 kb
Host smart-d43f3b96-19d9-4d6e-8692-a5959c97b6a4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=94624698 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_test_hmac384_vectors.94624698
Directory /workspace/48.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/48.hmac_test_hmac512_vectors.1583923313
Short name T203
Test name
Test status
Simulation time 15822171043 ps
CPU time 117.92 seconds
Started Jun 30 06:37:58 PM PDT 24
Finished Jun 30 06:39:56 PM PDT 24
Peak memory 200352 kb
Host smart-fc166eed-1294-469d-be48-9e83aa7e9462
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1583923313 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_test_hmac512_vectors.1583923313
Directory /workspace/48.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/48.hmac_test_sha256_vectors.2268058744
Short name T435
Test name
Test status
Simulation time 28807548675 ps
CPU time 491.07 seconds
Started Jun 30 06:38:03 PM PDT 24
Finished Jun 30 06:46:14 PM PDT 24
Peak memory 199720 kb
Host smart-e20ce0b9-7d14-4ab1-9f93-c85839045197
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2268058744 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_test_sha256_vectors.2268058744
Directory /workspace/48.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/48.hmac_test_sha384_vectors.3557049104
Short name T152
Test name
Test status
Simulation time 119347150339 ps
CPU time 1670.49 seconds
Started Jun 30 06:37:57 PM PDT 24
Finished Jun 30 07:05:48 PM PDT 24
Peak memory 216712 kb
Host smart-0d296f90-5f6b-4dae-a7e7-8330a884518a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3557049104 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_test_sha384_vectors.3557049104
Directory /workspace/48.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/48.hmac_test_sha512_vectors.39316027
Short name T350
Test name
Test status
Simulation time 151671793534 ps
CPU time 1958.09 seconds
Started Jun 30 06:37:58 PM PDT 24
Finished Jun 30 07:10:37 PM PDT 24
Peak memory 216140 kb
Host smart-62df52b9-ce88-4a1e-96a9-1fdd7865caad
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=39316027 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_test_sha512_vectors.39316027
Directory /workspace/48.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/48.hmac_wipe_secret.2869870094
Short name T564
Test name
Test status
Simulation time 10309299478 ps
CPU time 48.41 seconds
Started Jun 30 06:37:59 PM PDT 24
Finished Jun 30 06:38:48 PM PDT 24
Peak memory 200356 kb
Host smart-a5c04b33-8433-49b1-b045-35df6bb19b94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869870094 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_wipe_secret.2869870094
Directory /workspace/48.hmac_wipe_secret/latest

Test location /workspace/coverage/default/49.hmac_alert_test.3147058654
Short name T432
Test name
Test status
Simulation time 15412218 ps
CPU time 0.59 seconds
Started Jun 30 06:38:10 PM PDT 24
Finished Jun 30 06:38:11 PM PDT 24
Peak memory 195232 kb
Host smart-3688bb8a-786d-4f86-ad87-fdc6e9944340
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147058654 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_alert_test.3147058654
Directory /workspace/49.hmac_alert_test/latest

Test location /workspace/coverage/default/49.hmac_back_pressure.701859007
Short name T771
Test name
Test status
Simulation time 530786774 ps
CPU time 25.88 seconds
Started Jun 30 06:38:03 PM PDT 24
Finished Jun 30 06:38:29 PM PDT 24
Peak memory 200316 kb
Host smart-0cd94147-fb63-4aff-8c05-6ddfa725170b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=701859007 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_back_pressure.701859007
Directory /workspace/49.hmac_back_pressure/latest

Test location /workspace/coverage/default/49.hmac_burst_wr.1337444759
Short name T542
Test name
Test status
Simulation time 5727338006 ps
CPU time 65.13 seconds
Started Jun 30 06:38:02 PM PDT 24
Finished Jun 30 06:39:08 PM PDT 24
Peak memory 200396 kb
Host smart-dc89d2f0-eefd-4a6d-9dbd-3035bed375d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337444759 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_burst_wr.1337444759
Directory /workspace/49.hmac_burst_wr/latest

Test location /workspace/coverage/default/49.hmac_datapath_stress.448481899
Short name T693
Test name
Test status
Simulation time 2900195788 ps
CPU time 707 seconds
Started Jun 30 06:38:04 PM PDT 24
Finished Jun 30 06:49:51 PM PDT 24
Peak memory 724536 kb
Host smart-80305203-fb06-4125-8fa0-b42a729f6b8e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=448481899 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_datapath_stress.448481899
Directory /workspace/49.hmac_datapath_stress/latest

Test location /workspace/coverage/default/49.hmac_error.2383105619
Short name T84
Test name
Test status
Simulation time 20062622798 ps
CPU time 123.3 seconds
Started Jun 30 06:38:03 PM PDT 24
Finished Jun 30 06:40:07 PM PDT 24
Peak memory 200328 kb
Host smart-c8ff99b1-ae7a-4e56-8c04-75215aeb8d46
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383105619 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_error.2383105619
Directory /workspace/49.hmac_error/latest

Test location /workspace/coverage/default/49.hmac_long_msg.93381375
Short name T623
Test name
Test status
Simulation time 1623415366 ps
CPU time 98.49 seconds
Started Jun 30 06:38:04 PM PDT 24
Finished Jun 30 06:39:43 PM PDT 24
Peak memory 200300 kb
Host smart-50e5276a-1e82-4ad0-b951-a1cd2cb97b27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93381375 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_long_msg.93381375
Directory /workspace/49.hmac_long_msg/latest

Test location /workspace/coverage/default/49.hmac_smoke.2673209758
Short name T698
Test name
Test status
Simulation time 47020663 ps
CPU time 2.49 seconds
Started Jun 30 06:38:03 PM PDT 24
Finished Jun 30 06:38:05 PM PDT 24
Peak memory 199596 kb
Host smart-4104e624-97be-4542-b947-54e529b5adc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673209758 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_smoke.2673209758
Directory /workspace/49.hmac_smoke/latest

Test location /workspace/coverage/default/49.hmac_stress_all.1552100387
Short name T116
Test name
Test status
Simulation time 85188998614 ps
CPU time 5065.8 seconds
Started Jun 30 06:38:04 PM PDT 24
Finished Jun 30 08:02:31 PM PDT 24
Peak memory 216752 kb
Host smart-55c7766d-c037-467a-a742-a8b3de2b3f53
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552100387 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.hmac_stress_all.1552100387
Directory /workspace/49.hmac_stress_all/latest

Test location /workspace/coverage/default/49.hmac_test_hmac256_vectors.1680130035
Short name T190
Test name
Test status
Simulation time 6078822476 ps
CPU time 41.2 seconds
Started Jun 30 06:38:03 PM PDT 24
Finished Jun 30 06:38:45 PM PDT 24
Peak memory 200400 kb
Host smart-243c0c65-876c-4727-889b-9f76812a0193
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1680130035 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_test_hmac256_vectors.1680130035
Directory /workspace/49.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/49.hmac_test_hmac384_vectors.527332553
Short name T776
Test name
Test status
Simulation time 8984546372 ps
CPU time 83.24 seconds
Started Jun 30 06:38:03 PM PDT 24
Finished Jun 30 06:39:26 PM PDT 24
Peak memory 200368 kb
Host smart-7460d872-94bd-4b7c-97bf-24d25c2d47fb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=527332553 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_test_hmac384_vectors.527332553
Directory /workspace/49.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/49.hmac_test_hmac512_vectors.460899742
Short name T511
Test name
Test status
Simulation time 1988532818 ps
CPU time 62.94 seconds
Started Jun 30 06:38:04 PM PDT 24
Finished Jun 30 06:39:07 PM PDT 24
Peak memory 200352 kb
Host smart-a7de6ac7-63b6-49da-b0e7-72f6db8a28fd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=460899742 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_test_hmac512_vectors.460899742
Directory /workspace/49.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/49.hmac_test_sha256_vectors.3234635637
Short name T294
Test name
Test status
Simulation time 16336015473 ps
CPU time 452.65 seconds
Started Jun 30 06:38:07 PM PDT 24
Finished Jun 30 06:45:40 PM PDT 24
Peak memory 200276 kb
Host smart-a070d112-5d94-41b3-bb71-710ee58b4fa1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3234635637 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_test_sha256_vectors.3234635637
Directory /workspace/49.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/49.hmac_test_sha384_vectors.1680875125
Short name T229
Test name
Test status
Simulation time 65431640799 ps
CPU time 1788.44 seconds
Started Jun 30 06:38:03 PM PDT 24
Finished Jun 30 07:07:53 PM PDT 24
Peak memory 216364 kb
Host smart-199df33e-02ef-4e1a-821a-a27d1228fdbd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1680875125 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_test_sha384_vectors.1680875125
Directory /workspace/49.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/49.hmac_test_sha512_vectors.100960859
Short name T322
Test name
Test status
Simulation time 261270410775 ps
CPU time 1788.41 seconds
Started Jun 30 06:38:05 PM PDT 24
Finished Jun 30 07:07:54 PM PDT 24
Peak memory 216712 kb
Host smart-53057a50-d0ab-4be9-8f55-2cb54c6e1834
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=100960859 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_test_sha512_vectors.100960859
Directory /workspace/49.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/49.hmac_wipe_secret.1432050079
Short name T251
Test name
Test status
Simulation time 9832185735 ps
CPU time 46.03 seconds
Started Jun 30 06:38:05 PM PDT 24
Finished Jun 30 06:38:51 PM PDT 24
Peak memory 200380 kb
Host smart-d74f5820-6cbd-4ff4-af89-1160b3ba4e6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432050079 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_wipe_secret.1432050079
Directory /workspace/49.hmac_wipe_secret/latest

Test location /workspace/coverage/default/5.hmac_alert_test.2412293213
Short name T62
Test name
Test status
Simulation time 43216677 ps
CPU time 0.57 seconds
Started Jun 30 06:34:24 PM PDT 24
Finished Jun 30 06:34:25 PM PDT 24
Peak memory 196276 kb
Host smart-6bd4e8c9-c4d9-48c4-948a-f0e6fca7a298
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412293213 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_alert_test.2412293213
Directory /workspace/5.hmac_alert_test/latest

Test location /workspace/coverage/default/5.hmac_back_pressure.2071152128
Short name T300
Test name
Test status
Simulation time 1117372338 ps
CPU time 51.04 seconds
Started Jun 30 06:34:20 PM PDT 24
Finished Jun 30 06:35:11 PM PDT 24
Peak memory 200312 kb
Host smart-a6395dc5-aa89-45bf-96f3-88443eef7bf5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2071152128 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_back_pressure.2071152128
Directory /workspace/5.hmac_back_pressure/latest

Test location /workspace/coverage/default/5.hmac_burst_wr.3463006107
Short name T134
Test name
Test status
Simulation time 4475354676 ps
CPU time 60.79 seconds
Started Jun 30 06:34:28 PM PDT 24
Finished Jun 30 06:35:30 PM PDT 24
Peak memory 200232 kb
Host smart-bb110195-e641-4c2d-b1ee-c3f24b156a6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463006107 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_burst_wr.3463006107
Directory /workspace/5.hmac_burst_wr/latest

Test location /workspace/coverage/default/5.hmac_datapath_stress.3057183244
Short name T431
Test name
Test status
Simulation time 2889305313 ps
CPU time 348.68 seconds
Started Jun 30 06:34:20 PM PDT 24
Finished Jun 30 06:40:10 PM PDT 24
Peak memory 648200 kb
Host smart-409c86b6-51aa-47cd-a1be-88c40e03d1ea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3057183244 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_datapath_stress.3057183244
Directory /workspace/5.hmac_datapath_stress/latest

Test location /workspace/coverage/default/5.hmac_error.1822490949
Short name T529
Test name
Test status
Simulation time 4355359993 ps
CPU time 106.45 seconds
Started Jun 30 06:34:24 PM PDT 24
Finished Jun 30 06:36:11 PM PDT 24
Peak memory 200308 kb
Host smart-d382601e-d577-49a4-913d-35cbf310fe36
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822490949 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_error.1822490949
Directory /workspace/5.hmac_error/latest

Test location /workspace/coverage/default/5.hmac_long_msg.1794547987
Short name T666
Test name
Test status
Simulation time 5034986432 ps
CPU time 89.97 seconds
Started Jun 30 06:34:24 PM PDT 24
Finished Jun 30 06:35:55 PM PDT 24
Peak memory 200396 kb
Host smart-2425decc-be7a-4879-9057-87e4a06050bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794547987 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_long_msg.1794547987
Directory /workspace/5.hmac_long_msg/latest

Test location /workspace/coverage/default/5.hmac_smoke.4222544232
Short name T651
Test name
Test status
Simulation time 195027701 ps
CPU time 9.21 seconds
Started Jun 30 06:34:21 PM PDT 24
Finished Jun 30 06:34:31 PM PDT 24
Peak memory 200308 kb
Host smart-12396834-d5bf-4f27-abc0-b8926851e545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222544232 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_smoke.4222544232
Directory /workspace/5.hmac_smoke/latest

Test location /workspace/coverage/default/5.hmac_stress_all.3518456406
Short name T65
Test name
Test status
Simulation time 3623716403314 ps
CPU time 3804.54 seconds
Started Jun 30 06:34:23 PM PDT 24
Finished Jun 30 07:37:48 PM PDT 24
Peak memory 724300 kb
Host smart-9dd73255-7966-4214-bf74-8cb96a703d91
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518456406 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all.3518456406
Directory /workspace/5.hmac_stress_all/latest

Test location /workspace/coverage/default/5.hmac_test_hmac256_vectors.1461168926
Short name T265
Test name
Test status
Simulation time 21576181033 ps
CPU time 64.62 seconds
Started Jun 30 06:34:21 PM PDT 24
Finished Jun 30 06:35:27 PM PDT 24
Peak memory 200368 kb
Host smart-5f3a3cb3-6dc3-4eaa-8a13-9906970f8126
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1461168926 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_test_hmac256_vectors.1461168926
Directory /workspace/5.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/5.hmac_test_hmac384_vectors.3318759539
Short name T558
Test name
Test status
Simulation time 3947890633 ps
CPU time 44.91 seconds
Started Jun 30 06:34:19 PM PDT 24
Finished Jun 30 06:35:04 PM PDT 24
Peak memory 200344 kb
Host smart-632f845c-56e0-4136-8f92-21a2c3d489a7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3318759539 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_test_hmac384_vectors.3318759539
Directory /workspace/5.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/5.hmac_test_hmac512_vectors.3312150803
Short name T680
Test name
Test status
Simulation time 7866047748 ps
CPU time 59.94 seconds
Started Jun 30 06:34:22 PM PDT 24
Finished Jun 30 06:35:23 PM PDT 24
Peak memory 200284 kb
Host smart-29733d99-93de-4bbc-ad6b-bcd4470e64c7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3312150803 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_test_hmac512_vectors.3312150803
Directory /workspace/5.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/5.hmac_test_sha256_vectors.413281619
Short name T304
Test name
Test status
Simulation time 38583007229 ps
CPU time 478.33 seconds
Started Jun 30 06:34:23 PM PDT 24
Finished Jun 30 06:42:22 PM PDT 24
Peak memory 200312 kb
Host smart-bdb77d3b-2e49-4367-bf96-2268ed061742
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=413281619 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_test_sha256_vectors.413281619
Directory /workspace/5.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/5.hmac_test_sha384_vectors.2314099460
Short name T61
Test name
Test status
Simulation time 164911132881 ps
CPU time 2125.75 seconds
Started Jun 30 06:34:23 PM PDT 24
Finished Jun 30 07:09:49 PM PDT 24
Peak memory 215864 kb
Host smart-f9da1484-383d-4dbd-9edf-5322c9327beb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2314099460 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_test_sha384_vectors.2314099460
Directory /workspace/5.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/5.hmac_test_sha512_vectors.1431227277
Short name T720
Test name
Test status
Simulation time 107206646210 ps
CPU time 1824.76 seconds
Started Jun 30 06:34:21 PM PDT 24
Finished Jun 30 07:04:47 PM PDT 24
Peak memory 215740 kb
Host smart-4f63d825-28b2-4254-8105-d4190c0220a0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1431227277 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_test_sha512_vectors.1431227277
Directory /workspace/5.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/5.hmac_wipe_secret.3051454133
Short name T408
Test name
Test status
Simulation time 4497760277 ps
CPU time 66.33 seconds
Started Jun 30 06:34:21 PM PDT 24
Finished Jun 30 06:35:28 PM PDT 24
Peak memory 200368 kb
Host smart-53bcfc31-f3ed-48eb-ab40-6b2530487187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051454133 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_wipe_secret.3051454133
Directory /workspace/5.hmac_wipe_secret/latest

Test location /workspace/coverage/default/6.hmac_alert_test.85747405
Short name T181
Test name
Test status
Simulation time 12602905 ps
CPU time 0.58 seconds
Started Jun 30 06:34:23 PM PDT 24
Finished Jun 30 06:34:24 PM PDT 24
Peak memory 196292 kb
Host smart-a429ad48-d29c-4673-acb0-e7e62b57baf9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85747405 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_alert_test.85747405
Directory /workspace/6.hmac_alert_test/latest

Test location /workspace/coverage/default/6.hmac_back_pressure.3436391954
Short name T26
Test name
Test status
Simulation time 529895292 ps
CPU time 24.25 seconds
Started Jun 30 06:34:20 PM PDT 24
Finished Jun 30 06:34:45 PM PDT 24
Peak memory 200220 kb
Host smart-76ffe33c-7fe5-44a9-98fa-ba930698b106
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3436391954 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_back_pressure.3436391954
Directory /workspace/6.hmac_back_pressure/latest

Test location /workspace/coverage/default/6.hmac_burst_wr.531718288
Short name T189
Test name
Test status
Simulation time 206389770 ps
CPU time 4.34 seconds
Started Jun 30 06:34:23 PM PDT 24
Finished Jun 30 06:34:27 PM PDT 24
Peak memory 200460 kb
Host smart-3b9c2173-64ec-465f-a729-22a27aae967f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531718288 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_burst_wr.531718288
Directory /workspace/6.hmac_burst_wr/latest

Test location /workspace/coverage/default/6.hmac_datapath_stress.1548331202
Short name T388
Test name
Test status
Simulation time 1346192470 ps
CPU time 145.21 seconds
Started Jun 30 06:34:27 PM PDT 24
Finished Jun 30 06:36:53 PM PDT 24
Peak memory 440312 kb
Host smart-80b6bf75-dc8c-4dcb-b522-ca8af5bb162f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1548331202 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_datapath_stress.1548331202
Directory /workspace/6.hmac_datapath_stress/latest

Test location /workspace/coverage/default/6.hmac_error.3365336823
Short name T127
Test name
Test status
Simulation time 42780612443 ps
CPU time 120.62 seconds
Started Jun 30 06:34:20 PM PDT 24
Finished Jun 30 06:36:21 PM PDT 24
Peak memory 200372 kb
Host smart-7efc8425-e380-4e04-8a96-0d075cdd3a28
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365336823 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_error.3365336823
Directory /workspace/6.hmac_error/latest

Test location /workspace/coverage/default/6.hmac_long_msg.977584430
Short name T465
Test name
Test status
Simulation time 30352271535 ps
CPU time 34.07 seconds
Started Jun 30 06:34:21 PM PDT 24
Finished Jun 30 06:34:56 PM PDT 24
Peak memory 200340 kb
Host smart-c6074039-a755-46a8-addb-1a9f1b34143f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977584430 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_long_msg.977584430
Directory /workspace/6.hmac_long_msg/latest

Test location /workspace/coverage/default/6.hmac_smoke.2241850730
Short name T584
Test name
Test status
Simulation time 725436325 ps
CPU time 8.77 seconds
Started Jun 30 06:34:21 PM PDT 24
Finished Jun 30 06:34:30 PM PDT 24
Peak memory 200328 kb
Host smart-bb6d2cb7-cfb0-4c55-801e-54d4e5f77117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2241850730 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_smoke.2241850730
Directory /workspace/6.hmac_smoke/latest

Test location /workspace/coverage/default/6.hmac_stress_all.363607654
Short name T728
Test name
Test status
Simulation time 121721058350 ps
CPU time 338.47 seconds
Started Jun 30 06:34:24 PM PDT 24
Finished Jun 30 06:40:03 PM PDT 24
Peak memory 200388 kb
Host smart-340db66a-dcf1-416c-8557-6b34753ba68f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363607654 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all.363607654
Directory /workspace/6.hmac_stress_all/latest

Test location /workspace/coverage/default/6.hmac_test_hmac256_vectors.118905779
Short name T218
Test name
Test status
Simulation time 12610022756 ps
CPU time 55.83 seconds
Started Jun 30 06:34:22 PM PDT 24
Finished Jun 30 06:35:19 PM PDT 24
Peak memory 200376 kb
Host smart-bed49e27-1b6a-4fe1-9458-b6a386708bb6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=118905779 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_test_hmac256_vectors.118905779
Directory /workspace/6.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/6.hmac_test_hmac384_vectors.184957412
Short name T276
Test name
Test status
Simulation time 6347497164 ps
CPU time 49.46 seconds
Started Jun 30 06:34:24 PM PDT 24
Finished Jun 30 06:35:14 PM PDT 24
Peak memory 200356 kb
Host smart-7db69871-faf5-49c5-9efb-4b826d99dbba
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=184957412 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_test_hmac384_vectors.184957412
Directory /workspace/6.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/6.hmac_test_hmac512_vectors.1875237344
Short name T759
Test name
Test status
Simulation time 10676118148 ps
CPU time 58.21 seconds
Started Jun 30 06:34:20 PM PDT 24
Finished Jun 30 06:35:19 PM PDT 24
Peak memory 200372 kb
Host smart-9c08eb34-512e-496b-bac7-55b1c09a4a34
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1875237344 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_test_hmac512_vectors.1875237344
Directory /workspace/6.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/6.hmac_test_sha256_vectors.3799944831
Short name T192
Test name
Test status
Simulation time 47392571125 ps
CPU time 442.93 seconds
Started Jun 30 06:34:22 PM PDT 24
Finished Jun 30 06:41:46 PM PDT 24
Peak memory 200220 kb
Host smart-4345b49c-0c1d-4848-bd5a-14567eccfe09
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3799944831 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_test_sha256_vectors.3799944831
Directory /workspace/6.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/6.hmac_test_sha384_vectors.150509183
Short name T434
Test name
Test status
Simulation time 211181141478 ps
CPU time 1932.86 seconds
Started Jun 30 06:34:19 PM PDT 24
Finished Jun 30 07:06:33 PM PDT 24
Peak memory 216728 kb
Host smart-eda342de-5167-4f6d-8928-c56006aeebd7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=150509183 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_test_sha384_vectors.150509183
Directory /workspace/6.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/6.hmac_test_sha512_vectors.42732730
Short name T303
Test name
Test status
Simulation time 107015319938 ps
CPU time 1935.45 seconds
Started Jun 30 06:34:22 PM PDT 24
Finished Jun 30 07:06:38 PM PDT 24
Peak memory 216176 kb
Host smart-8f649563-1680-439c-927d-60a404514afb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=42732730 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_test_sha512_vectors.42732730
Directory /workspace/6.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/6.hmac_wipe_secret.4167149282
Short name T523
Test name
Test status
Simulation time 2662388917 ps
CPU time 34.75 seconds
Started Jun 30 06:34:23 PM PDT 24
Finished Jun 30 06:34:58 PM PDT 24
Peak memory 200428 kb
Host smart-dcf901d2-d11f-4fe3-9dcb-4a77680eb88d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167149282 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_wipe_secret.4167149282
Directory /workspace/6.hmac_wipe_secret/latest

Test location /workspace/coverage/default/7.hmac_alert_test.589734964
Short name T377
Test name
Test status
Simulation time 13461177 ps
CPU time 0.57 seconds
Started Jun 30 06:34:26 PM PDT 24
Finished Jun 30 06:34:27 PM PDT 24
Peak memory 197000 kb
Host smart-113912e8-f3de-4634-aaaa-49c6abfea2bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589734964 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_alert_test.589734964
Directory /workspace/7.hmac_alert_test/latest

Test location /workspace/coverage/default/7.hmac_back_pressure.4054963727
Short name T545
Test name
Test status
Simulation time 1601364784 ps
CPU time 11.35 seconds
Started Jun 30 06:34:21 PM PDT 24
Finished Jun 30 06:34:33 PM PDT 24
Peak memory 200252 kb
Host smart-1dbcf797-9b40-4c88-bb3f-2a6d8634e05a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4054963727 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_back_pressure.4054963727
Directory /workspace/7.hmac_back_pressure/latest

Test location /workspace/coverage/default/7.hmac_burst_wr.3142828662
Short name T347
Test name
Test status
Simulation time 1666978437 ps
CPU time 7.78 seconds
Started Jun 30 06:34:27 PM PDT 24
Finished Jun 30 06:34:35 PM PDT 24
Peak memory 200268 kb
Host smart-3b240356-66c6-4531-8be7-a8e2c3623ca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142828662 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_burst_wr.3142828662
Directory /workspace/7.hmac_burst_wr/latest

Test location /workspace/coverage/default/7.hmac_datapath_stress.733931513
Short name T321
Test name
Test status
Simulation time 9074224913 ps
CPU time 554.58 seconds
Started Jun 30 06:34:34 PM PDT 24
Finished Jun 30 06:43:49 PM PDT 24
Peak memory 678624 kb
Host smart-4f88ddde-c078-4fea-8087-160b3565b16e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=733931513 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_datapath_stress.733931513
Directory /workspace/7.hmac_datapath_stress/latest

Test location /workspace/coverage/default/7.hmac_error.2060462850
Short name T120
Test name
Test status
Simulation time 5112522566 ps
CPU time 86.17 seconds
Started Jun 30 06:34:26 PM PDT 24
Finished Jun 30 06:35:53 PM PDT 24
Peak memory 200412 kb
Host smart-3caf719e-3acf-40ae-9c71-c3cdb844f2bb
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060462850 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_error.2060462850
Directory /workspace/7.hmac_error/latest

Test location /workspace/coverage/default/7.hmac_long_msg.2746129852
Short name T272
Test name
Test status
Simulation time 462906790 ps
CPU time 4.97 seconds
Started Jun 30 06:34:19 PM PDT 24
Finished Jun 30 06:34:25 PM PDT 24
Peak memory 200348 kb
Host smart-242e14f2-a7e5-4a0c-b1e7-c2987aa72948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746129852 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_long_msg.2746129852
Directory /workspace/7.hmac_long_msg/latest

Test location /workspace/coverage/default/7.hmac_smoke.2858655119
Short name T699
Test name
Test status
Simulation time 3871108271 ps
CPU time 17.42 seconds
Started Jun 30 06:34:27 PM PDT 24
Finished Jun 30 06:34:45 PM PDT 24
Peak memory 200224 kb
Host smart-e82fc74f-dc47-45da-bdc2-7d784d264ca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858655119 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_smoke.2858655119
Directory /workspace/7.hmac_smoke/latest

Test location /workspace/coverage/default/7.hmac_stress_all.1594654916
Short name T135
Test name
Test status
Simulation time 150442299263 ps
CPU time 3984.98 seconds
Started Jun 30 06:34:24 PM PDT 24
Finished Jun 30 07:40:50 PM PDT 24
Peak memory 831564 kb
Host smart-45abb92a-9db4-4470-b79a-d1861272a2c7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594654916 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all.1594654916
Directory /workspace/7.hmac_stress_all/latest

Test location /workspace/coverage/default/7.hmac_test_hmac256_vectors.861319546
Short name T783
Test name
Test status
Simulation time 4518412165 ps
CPU time 36.69 seconds
Started Jun 30 06:34:32 PM PDT 24
Finished Jun 30 06:35:09 PM PDT 24
Peak memory 200364 kb
Host smart-663b97ba-1d7a-4bf6-b0a5-bb5ffe05a1dc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=861319546 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_test_hmac256_vectors.861319546
Directory /workspace/7.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/7.hmac_test_hmac384_vectors.1537220347
Short name T592
Test name
Test status
Simulation time 4662339142 ps
CPU time 73.86 seconds
Started Jun 30 06:34:27 PM PDT 24
Finished Jun 30 06:35:42 PM PDT 24
Peak memory 200312 kb
Host smart-bc5dbfb9-2763-4024-a89f-f3749eb6a6cd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1537220347 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_test_hmac384_vectors.1537220347
Directory /workspace/7.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/7.hmac_test_hmac512_vectors.414494255
Short name T77
Test name
Test status
Simulation time 7337073605 ps
CPU time 50.34 seconds
Started Jun 30 06:34:30 PM PDT 24
Finished Jun 30 06:35:21 PM PDT 24
Peak memory 200216 kb
Host smart-60a0e49f-0e6a-4c22-bbe4-4cd6e86f38cc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=414494255 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_test_hmac512_vectors.414494255
Directory /workspace/7.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/7.hmac_test_sha256_vectors.1878221988
Short name T791
Test name
Test status
Simulation time 27700609433 ps
CPU time 483.63 seconds
Started Jun 30 06:34:25 PM PDT 24
Finished Jun 30 06:42:29 PM PDT 24
Peak memory 200328 kb
Host smart-87265c40-ebba-41a1-9227-08b72fc7a399
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1878221988 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_test_sha256_vectors.1878221988
Directory /workspace/7.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/7.hmac_test_sha384_vectors.2889113600
Short name T269
Test name
Test status
Simulation time 150860140387 ps
CPU time 2004.59 seconds
Started Jun 30 06:34:29 PM PDT 24
Finished Jun 30 07:07:55 PM PDT 24
Peak memory 216552 kb
Host smart-bf7c2d08-fcd0-4914-87ee-405147b0a309
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2889113600 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_test_sha384_vectors.2889113600
Directory /workspace/7.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/7.hmac_test_sha512_vectors.3437965248
Short name T316
Test name
Test status
Simulation time 416499156613 ps
CPU time 1838.3 seconds
Started Jun 30 06:34:28 PM PDT 24
Finished Jun 30 07:05:07 PM PDT 24
Peak memory 216692 kb
Host smart-4e8033aa-708f-4a73-a750-bb5cc6e081d3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3437965248 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_test_sha512_vectors.3437965248
Directory /workspace/7.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/7.hmac_wipe_secret.2565105723
Short name T487
Test name
Test status
Simulation time 6028974771 ps
CPU time 42.62 seconds
Started Jun 30 06:34:25 PM PDT 24
Finished Jun 30 06:35:08 PM PDT 24
Peak memory 200328 kb
Host smart-5e84bd7e-7e06-47c6-9c1e-d869a3245d35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565105723 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_wipe_secret.2565105723
Directory /workspace/7.hmac_wipe_secret/latest

Test location /workspace/coverage/default/8.hmac_alert_test.2587136374
Short name T711
Test name
Test status
Simulation time 43810494 ps
CPU time 0.61 seconds
Started Jun 30 06:34:30 PM PDT 24
Finished Jun 30 06:34:31 PM PDT 24
Peak memory 196288 kb
Host smart-e00d41a6-266d-478e-a021-45f4f1486155
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587136374 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_alert_test.2587136374
Directory /workspace/8.hmac_alert_test/latest

Test location /workspace/coverage/default/8.hmac_back_pressure.960566159
Short name T402
Test name
Test status
Simulation time 3097789236 ps
CPU time 39.18 seconds
Started Jun 30 06:34:25 PM PDT 24
Finished Jun 30 06:35:05 PM PDT 24
Peak memory 200460 kb
Host smart-70e76942-fd0e-4465-813c-e6932aa9843a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=960566159 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_back_pressure.960566159
Directory /workspace/8.hmac_back_pressure/latest

Test location /workspace/coverage/default/8.hmac_burst_wr.3115038743
Short name T583
Test name
Test status
Simulation time 543365163 ps
CPU time 27.64 seconds
Started Jun 30 06:34:27 PM PDT 24
Finished Jun 30 06:34:56 PM PDT 24
Peak memory 200316 kb
Host smart-44227ca6-e095-4ee4-a0d0-f6c365c0eb84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3115038743 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_burst_wr.3115038743
Directory /workspace/8.hmac_burst_wr/latest

Test location /workspace/coverage/default/8.hmac_datapath_stress.259029885
Short name T621
Test name
Test status
Simulation time 1354789229 ps
CPU time 268.58 seconds
Started Jun 30 06:34:31 PM PDT 24
Finished Jun 30 06:39:00 PM PDT 24
Peak memory 445220 kb
Host smart-29b3ccb6-c0e1-4ce1-81e2-d796a4941c31
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=259029885 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_datapath_stress.259029885
Directory /workspace/8.hmac_datapath_stress/latest

Test location /workspace/coverage/default/8.hmac_error.166444120
Short name T498
Test name
Test status
Simulation time 4785245725 ps
CPU time 60.84 seconds
Started Jun 30 06:34:25 PM PDT 24
Finished Jun 30 06:35:26 PM PDT 24
Peak memory 200320 kb
Host smart-ba2658e7-04de-4073-924b-b3b2ac1d560e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166444120 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_error.166444120
Directory /workspace/8.hmac_error/latest

Test location /workspace/coverage/default/8.hmac_long_msg.2316207134
Short name T714
Test name
Test status
Simulation time 40183286251 ps
CPU time 71.24 seconds
Started Jun 30 06:34:26 PM PDT 24
Finished Jun 30 06:35:37 PM PDT 24
Peak memory 216700 kb
Host smart-ed6347cd-2f52-4f07-ad6b-ca9250042298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316207134 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_long_msg.2316207134
Directory /workspace/8.hmac_long_msg/latest

Test location /workspace/coverage/default/8.hmac_smoke.3979163356
Short name T356
Test name
Test status
Simulation time 712792739 ps
CPU time 10.49 seconds
Started Jun 30 06:34:31 PM PDT 24
Finished Jun 30 06:34:42 PM PDT 24
Peak memory 200328 kb
Host smart-6cf5edca-c1d5-4661-94c1-e571d6dea831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979163356 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_smoke.3979163356
Directory /workspace/8.hmac_smoke/latest

Test location /workspace/coverage/default/8.hmac_stress_all.3336177547
Short name T49
Test name
Test status
Simulation time 52531721383 ps
CPU time 1901.39 seconds
Started Jun 30 06:34:27 PM PDT 24
Finished Jun 30 07:06:10 PM PDT 24
Peak memory 741552 kb
Host smart-f35e36ac-19a0-4977-a39a-c3f8576dc50d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336177547 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all.3336177547
Directory /workspace/8.hmac_stress_all/latest

Test location /workspace/coverage/default/8.hmac_test_hmac256_vectors.18268349
Short name T78
Test name
Test status
Simulation time 4152214325 ps
CPU time 33.21 seconds
Started Jun 30 06:34:28 PM PDT 24
Finished Jun 30 06:35:02 PM PDT 24
Peak memory 200340 kb
Host smart-3a4801a5-8bdb-4969-aec9-56a176cc242c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=18268349 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_test_hmac256_vectors.18268349
Directory /workspace/8.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/8.hmac_test_hmac384_vectors.2329287708
Short name T202
Test name
Test status
Simulation time 23107650394 ps
CPU time 54.61 seconds
Started Jun 30 06:34:29 PM PDT 24
Finished Jun 30 06:35:24 PM PDT 24
Peak memory 200340 kb
Host smart-9cea4935-3b09-420d-b749-088295d0925f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2329287708 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_test_hmac384_vectors.2329287708
Directory /workspace/8.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/8.hmac_test_hmac512_vectors.2736008624
Short name T637
Test name
Test status
Simulation time 1804345247 ps
CPU time 51.33 seconds
Started Jun 30 06:34:29 PM PDT 24
Finished Jun 30 06:35:21 PM PDT 24
Peak memory 200320 kb
Host smart-7953a119-d2be-4510-80b1-10eca320ec86
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2736008624 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_test_hmac512_vectors.2736008624
Directory /workspace/8.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/8.hmac_test_sha256_vectors.1061988973
Short name T787
Test name
Test status
Simulation time 171343203481 ps
CPU time 531.73 seconds
Started Jun 30 06:34:24 PM PDT 24
Finished Jun 30 06:43:16 PM PDT 24
Peak memory 200292 kb
Host smart-c74be783-0a98-4803-95b5-0a3b95ce1c09
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1061988973 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_test_sha256_vectors.1061988973
Directory /workspace/8.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/8.hmac_test_sha384_vectors.606740653
Short name T547
Test name
Test status
Simulation time 133550252226 ps
CPU time 1872.09 seconds
Started Jun 30 06:34:30 PM PDT 24
Finished Jun 30 07:05:43 PM PDT 24
Peak memory 216240 kb
Host smart-d760a1f1-1049-4516-9caa-0345dc84786f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=606740653 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_test_sha384_vectors.606740653
Directory /workspace/8.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/8.hmac_test_sha512_vectors.2193900992
Short name T247
Test name
Test status
Simulation time 108819399312 ps
CPU time 1884.72 seconds
Started Jun 30 06:34:34 PM PDT 24
Finished Jun 30 07:06:00 PM PDT 24
Peak memory 216692 kb
Host smart-44f909d4-f56e-4084-927e-13f733b03fa2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2193900992 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_test_sha512_vectors.2193900992
Directory /workspace/8.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/8.hmac_wipe_secret.3805056239
Short name T753
Test name
Test status
Simulation time 8163947635 ps
CPU time 79.08 seconds
Started Jun 30 06:34:25 PM PDT 24
Finished Jun 30 06:35:45 PM PDT 24
Peak memory 200372 kb
Host smart-d8d04bf4-f557-4c8e-bd6b-a622aa2f56b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805056239 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_wipe_secret.3805056239
Directory /workspace/8.hmac_wipe_secret/latest

Test location /workspace/coverage/default/9.hmac_alert_test.2878487427
Short name T205
Test name
Test status
Simulation time 12592795 ps
CPU time 0.58 seconds
Started Jun 30 06:34:31 PM PDT 24
Finished Jun 30 06:34:32 PM PDT 24
Peak memory 195928 kb
Host smart-69eb7c9e-fd8e-4378-a6eb-bf6365cd19ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878487427 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_alert_test.2878487427
Directory /workspace/9.hmac_alert_test/latest

Test location /workspace/coverage/default/9.hmac_back_pressure.968234462
Short name T24
Test name
Test status
Simulation time 469919268 ps
CPU time 22.11 seconds
Started Jun 30 06:34:25 PM PDT 24
Finished Jun 30 06:34:48 PM PDT 24
Peak memory 200336 kb
Host smart-c68a3789-5e7c-4a77-9224-b1f2dd72e0ac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=968234462 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_back_pressure.968234462
Directory /workspace/9.hmac_back_pressure/latest

Test location /workspace/coverage/default/9.hmac_burst_wr.1252422387
Short name T672
Test name
Test status
Simulation time 3255399495 ps
CPU time 29.4 seconds
Started Jun 30 06:34:23 PM PDT 24
Finished Jun 30 06:34:53 PM PDT 24
Peak memory 200388 kb
Host smart-2544fca0-f826-4b95-a68a-2cff96e648f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252422387 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_burst_wr.1252422387
Directory /workspace/9.hmac_burst_wr/latest

Test location /workspace/coverage/default/9.hmac_datapath_stress.3639902726
Short name T723
Test name
Test status
Simulation time 5484464385 ps
CPU time 1049.49 seconds
Started Jun 30 06:34:32 PM PDT 24
Finished Jun 30 06:52:02 PM PDT 24
Peak memory 694080 kb
Host smart-2f4a7292-52e7-47a1-bce2-cdf0db9ca3cc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3639902726 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_datapath_stress.3639902726
Directory /workspace/9.hmac_datapath_stress/latest

Test location /workspace/coverage/default/9.hmac_error.747762144
Short name T586
Test name
Test status
Simulation time 1551287621 ps
CPU time 87.48 seconds
Started Jun 30 06:34:26 PM PDT 24
Finished Jun 30 06:35:54 PM PDT 24
Peak memory 200320 kb
Host smart-ae54d0ce-6432-4e1a-b1f4-262f5af5760e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747762144 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_error.747762144
Directory /workspace/9.hmac_error/latest

Test location /workspace/coverage/default/9.hmac_long_msg.1458155387
Short name T209
Test name
Test status
Simulation time 6603589822 ps
CPU time 98.8 seconds
Started Jun 30 06:34:27 PM PDT 24
Finished Jun 30 06:36:07 PM PDT 24
Peak memory 200404 kb
Host smart-9c5aedf7-1d31-476a-b2c3-c5618b7ccc31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458155387 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_long_msg.1458155387
Directory /workspace/9.hmac_long_msg/latest

Test location /workspace/coverage/default/9.hmac_smoke.3320527772
Short name T559
Test name
Test status
Simulation time 513462752 ps
CPU time 9.16 seconds
Started Jun 30 06:34:29 PM PDT 24
Finished Jun 30 06:34:39 PM PDT 24
Peak memory 200320 kb
Host smart-cb45b6dc-da8a-486b-9ef4-c55a8f70de68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320527772 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_smoke.3320527772
Directory /workspace/9.hmac_smoke/latest

Test location /workspace/coverage/default/9.hmac_stress_all.934500650
Short name T397
Test name
Test status
Simulation time 1735015994 ps
CPU time 105.14 seconds
Started Jun 30 06:34:29 PM PDT 24
Finished Jun 30 06:36:15 PM PDT 24
Peak memory 200304 kb
Host smart-ba921876-6a6f-4af3-ac09-6052e47cb9b8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934500650 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all.934500650
Directory /workspace/9.hmac_stress_all/latest

Test location /workspace/coverage/default/9.hmac_test_hmac256_vectors.3917169230
Short name T419
Test name
Test status
Simulation time 23800917112 ps
CPU time 75.22 seconds
Started Jun 30 06:34:32 PM PDT 24
Finished Jun 30 06:35:48 PM PDT 24
Peak memory 200368 kb
Host smart-9d6b905c-d50c-4779-a9b2-cb4fc25c8d52
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3917169230 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_test_hmac256_vectors.3917169230
Directory /workspace/9.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/9.hmac_test_hmac384_vectors.3191656086
Short name T755
Test name
Test status
Simulation time 2999401219 ps
CPU time 42.93 seconds
Started Jun 30 06:34:30 PM PDT 24
Finished Jun 30 06:35:14 PM PDT 24
Peak memory 200408 kb
Host smart-849ae982-e0de-4074-b2c0-05747a9543a5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3191656086 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_test_hmac384_vectors.3191656086
Directory /workspace/9.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/9.hmac_test_hmac512_vectors.1537517626
Short name T292
Test name
Test status
Simulation time 7241773301 ps
CPU time 59.36 seconds
Started Jun 30 06:34:30 PM PDT 24
Finished Jun 30 06:35:30 PM PDT 24
Peak memory 200376 kb
Host smart-723ab416-a64f-42c8-a4d9-19f33106e334
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1537517626 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_test_hmac512_vectors.1537517626
Directory /workspace/9.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/9.hmac_test_sha256_vectors.708547974
Short name T524
Test name
Test status
Simulation time 25687292741 ps
CPU time 416.86 seconds
Started Jun 30 06:34:31 PM PDT 24
Finished Jun 30 06:41:29 PM PDT 24
Peak memory 200312 kb
Host smart-ec246494-49b7-4041-ad33-1fdc55cb54f4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=708547974 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_test_sha256_vectors.708547974
Directory /workspace/9.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/9.hmac_test_sha384_vectors.2027833346
Short name T29
Test name
Test status
Simulation time 308595902912 ps
CPU time 1797.5 seconds
Started Jun 30 06:34:29 PM PDT 24
Finished Jun 30 07:04:28 PM PDT 24
Peak memory 215896 kb
Host smart-88d83194-a5d7-48c7-bac3-daf8619aaf64
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2027833346 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_test_sha384_vectors.2027833346
Directory /workspace/9.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/9.hmac_test_sha512_vectors.2827273042
Short name T735
Test name
Test status
Simulation time 472900056766 ps
CPU time 2071.3 seconds
Started Jun 30 06:34:33 PM PDT 24
Finished Jun 30 07:09:05 PM PDT 24
Peak memory 216552 kb
Host smart-09cbd777-dd25-4402-b47e-f24cd8bc21f6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2827273042 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_test_sha512_vectors.2827273042
Directory /workspace/9.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/9.hmac_wipe_secret.2870038655
Short name T195
Test name
Test status
Simulation time 17806705884 ps
CPU time 85.72 seconds
Started Jun 30 06:34:34 PM PDT 24
Finished Jun 30 06:36:00 PM PDT 24
Peak memory 200352 kb
Host smart-4434c693-3685-4c08-9610-65d6272e2213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870038655 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_wipe_secret.2870038655
Directory /workspace/9.hmac_wipe_secret/latest
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