Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	19227044	1			T1	26443		T2	15749		T3	436
all_values[1]	19227044	1			T1	26443		T2	15749		T3	436
all_values[2]	19227044	1			T1	26443		T2	15749		T3	436

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

246030

1

T3

4

T12

467

T5

158

auto[1]

57435102

1

T1

79329

T2

47247

T3

1304

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

49012855

1

T1

70975

T2

42131

T3

1148

auto[1]

8668277

1

T1

8354

T2

5116

T3

160

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	92664	1			T3	2		T12	465		T5	113
all_values[0]	auto[0]	auto[1]	415	1			T12	2		T5	2		T6	1
all_values[0]	auto[1]	auto[0]	19112685	1			T1	26415		T2	15730		T3	431
all_values[0]	auto[1]	auto[1]	21280	1			T1	28		T2	19		T3	3
all_values[1]	auto[0]	auto[0]	52556	1			T3	2		T5	43		T8	28
all_values[1]	auto[0]	auto[1]	262	1			T28	1		T29	5		T25	3
all_values[1]	auto[1]	auto[0]	19173731	1			T1	26443		T2	15749		T3	434
all_values[1]	auto[1]	auto[1]	495	1			T6	3		T28	4		T29	1
all_values[2]	auto[0]	auto[0]	46936	1			T7	2		T6	1		T28	505
all_values[2]	auto[0]	auto[1]	53197	1			T7	2		T6	2		T28	641
all_values[2]	auto[1]	auto[0]	10534283	1			T1	18117		T2	10652		T3	279
all_values[2]	auto[1]	auto[1]	8592628	1			T1	8326		T2	5097		T3	157