Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::msg_len_cg

Group : hmac_env_pkg::hmac_env_cov::msg_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
52.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	8	10	55.56
Crosses	32	16	16	50.00

Variables for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
hmac_en	2	0	2	100.00	100	1	1	2
msg_len_lower_cp	15	7	8	53.33	100	1	1	0
msg_len_upper_cp	1	1	0	0.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
msg_len_lower_cross	30	14	16	53.33	100	1	1	0
msg_len_upper_cross	2	2	0	0.00	100	1	1	0

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

160264

1

T1

38

T2

30

T3

2

auto[1]

164928

1

T1

30

T2

22

T3

4

---

Summary for Variable msg_len_lower_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	7	8	53.33

User Defined Bins for msg_len_lower_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
len_2049	0	1	1
len_2047	0	1	1
len_1025	0	1	1
len_1023	0	1	1
len_513	0	1	1
len_511	0	1	1
len_1	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_2050_plus	125414	1			T1	29		T2	21		T12	188
len_1026_2046	9934	1			T3	2		T12	4		T4	6
len_514_1022	5103	1			T12	1		T4	9		T5	32
len_2_510	6654	1			T12	1		T4	2		T18	3
len_2048	456	1			T4	1		T5	6		T8	2
len_1024	1814	1			T4	5		T5	4		T28	2
len_512	393	1			T4	2		T5	3		T8	3
len_0	12828	1			T1	5		T2	5		T3	1

---

Summary for Variable msg_len_upper_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	1	0	0.00

User Defined Bins for msg_len_upper_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
len_upper	0	1	1

---

Summary for Cross msg_len_lower_cross

Samples crossed: hmac_en msg_len_lower_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	14	16	53.33	14

Automatically Generated Cross Bins for msg_len_lower_cross

Element holes

hmac_en	msg_len_lower_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[len_2049]	--	--	2
*	[len_2047 , len_1025]	--	--	4
*	[len_1023 , len_513]	--	--	4
*	[len_511 , len_1]	--	--	4

Covered bins

hmac_en	msg_len_lower_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	len_2050_plus	62981	1			T1	16		T2	15		T12	149
auto[0]	len_1026_2046	4356	1			T3	1		T12	1		T4	2
auto[0]	len_514_1022	3207	1			T12	1		T4	3		T5	28
auto[0]	len_2_510	2688	1			T12	1		T4	2		T18	2
auto[0]	len_2048	200	1			T4	1		T5	5		T8	2
auto[0]	len_1024	290	1			T4	2		T5	3		T28	2
auto[0]	len_512	227	1			T4	1		T5	2		T8	3
auto[0]	len_0	6183	1			T1	3		T12	54		T4	2
auto[1]	len_2050_plus	62433	1			T1	13		T2	6		T12	39
auto[1]	len_1026_2046	5578	1			T3	1		T12	3		T4	4
auto[1]	len_514_1022	1896	1			T4	6		T5	4		T8	2
auto[1]	len_2_510	3966	1			T18	1		T5	12		T7	8
auto[1]	len_2048	256	1			T5	1		T6	2		T26	1
auto[1]	len_1024	1524	1			T4	3		T5	1		T29	1
auto[1]	len_512	166	1			T4	1		T5	1		T6	3
auto[1]	len_0	6645	1			T1	2		T2	5		T3	1

---

Summary for Cross msg_len_upper_cross

Samples crossed: hmac_en msg_len_upper_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	2	2	0	0.00	2

Automatically Generated Cross Bins for msg_len_upper_cross

Uncovered bins

hmac_en	msg_len_upper_cp	COUNT	AT LEAST	NUMBER	STATUS
*	*	--	--	2