Group : hmac_env_pkg::hmac_env_cov::status_cg
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Group : hmac_env_pkg::hmac_env_cov::status_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv


Summary for Group hmac_env_pkg::hmac_env_cov::status_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 20 0 20 100.00
Crosses 192 0 192 100.00


Variables for Group hmac_env_pkg::hmac_env_cov::status_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
digest_swap 2 0 2 100.00 100 1 1 2
endian_swap 2 0 2 100.00 100 1 1 2
hmac_en 2 0 2 100.00 100 1 1 2
key_swap 2 0 2 100.00 100 1 1 2
sta_fifo_depth 8 0 8 100.00 100 1 1 0
sta_fifo_empty 2 0 2 100.00 100 1 1 2
sta_fifo_full 2 0 2 100.00 100 1 1 2


Crosses for Group hmac_env_pkg::hmac_env_cov::status_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
fifo_empty_cross 32 0 32 100.00 100 1 1 0
fifo_full_cross 32 0 32 100.00 100 1 1 0
fifo_depth_cross 128 0 128 100.00 100 1 1 0


Summary for Variable digest_swap

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for digest_swap

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 4776853 1 T1 7340 T2 3381 T3 171
auto[1] 3319521 1 T1 5775 T2 4480 T3 49


Summary for Variable endian_swap

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for endian_swap

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3246241 1 T1 7067 T2 3357 T3 92
auto[1] 4850133 1 T1 6048 T2 4504 T3 128


Summary for Variable hmac_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for hmac_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3567505 1 T1 6838 T2 4186 T3 91
auto[1] 4528869 1 T1 6277 T2 3675 T3 129


Summary for Variable key_swap

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for key_swap

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 4819260 1 T1 6922 T2 3987 T3 161
auto[1] 3277114 1 T1 6193 T2 3874 T3 59


Summary for Variable sta_fifo_depth

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 8 0 8 100.00


User Defined Bins for sta_fifo_depth

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
fifo_depth[0] 7172296 1 T1 10883 T2 7746 T3 216
fifo_depth[1] 134203 1 T1 414 T2 90 T3 3
fifo_depth[2] 108177 1 T1 381 T2 23 T3 1
fifo_depth[3] 86827 1 T1 362 T2 2 T12 18
fifo_depth[4] 80950 1 T1 351 T12 18 T5 41
fifo_depth[5] 62260 1 T1 299 T12 7 T5 4
fifo_depth[6] 51103 1 T1 206 T12 3 T5 6
fifo_depth[7] 34004 1 T1 125 T5 3 T7 128


Summary for Variable sta_fifo_empty

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sta_fifo_empty

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 924078 1 T1 2232 T2 115 T3 4
auto[1] 7172296 1 T1 10883 T2 7746 T3 216


Summary for Variable sta_fifo_full

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sta_fifo_full

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 8078785 1 T1 13115 T2 7861 T3 220
auto[1] 17589 1 T25 320 T20 440 T94 542


Summary for Cross fifo_empty_cross

Samples crossed: sta_fifo_empty hmac_en endian_swap digest_swap key_swap
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 32 0 32 100.00


Automatically Generated Cross Bins for fifo_empty_cross

Bins
sta_fifo_emptyhmac_enendian_swapdigest_swapkey_swapCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] 50699 1 T3 1 T4 1 T8 3
auto[0] auto[0] auto[0] auto[0] auto[1] 45216 1 T1 101 T2 7 T5 25
auto[0] auto[0] auto[0] auto[1] auto[0] 39591 1 T1 391 T2 13 T12 102
auto[0] auto[0] auto[0] auto[1] auto[1] 44358 1 T1 270 T2 17 T4 2
auto[0] auto[0] auto[1] auto[0] auto[0] 182678 1 T2 14 T5 27 T136 1
auto[0] auto[0] auto[1] auto[0] auto[1] 45093 1 T1 179 T2 9 T5 61
auto[0] auto[0] auto[1] auto[1] auto[0] 51148 1 T1 58 T13 82 T28 99
auto[0] auto[0] auto[1] auto[1] auto[1] 48285 1 T1 131 T2 20 T5 1
auto[0] auto[1] auto[0] auto[0] auto[0] 47631 1 T1 381 T2 15 T4 5
auto[0] auto[1] auto[0] auto[0] auto[1] 44743 1 T5 6 T6 3 T13 172
auto[0] auto[1] auto[0] auto[1] auto[0] 55590 1 T1 144 T18 1 T5 40
auto[0] auto[1] auto[0] auto[1] auto[1] 53954 1 T12 10 T8 3 T13 136
auto[0] auto[1] auto[1] auto[0] auto[0] 58973 1 T1 209 T3 3 T4 4
auto[0] auto[1] auto[1] auto[0] auto[1] 54258 1 T1 259 T2 5 T4 6
auto[0] auto[1] auto[1] auto[1] auto[0] 50495 1 T1 109 T2 15 T4 8
auto[0] auto[1] auto[1] auto[1] auto[1] 51366 1 T4 1 T5 4 T8 5
auto[1] auto[0] auto[0] auto[0] auto[0] 202247 1 T1 349 T2 1 T3 42
auto[1] auto[0] auto[0] auto[0] auto[1] 212922 1 T1 388 T2 408 T4 12
auto[1] auto[0] auto[0] auto[1] auto[0] 189810 1 T1 719 T2 469 T12 503
auto[1] auto[0] auto[0] auto[1] auto[1] 224624 1 T1 1769 T2 1063 T4 44
auto[1] auto[0] auto[1] auto[0] auto[0] 1582416 1 T1 345 T2 674 T3 48
auto[1] auto[0] auto[1] auto[0] auto[1] 200832 1 T1 1147 T2 815 T4 41
auto[1] auto[0] auto[1] auto[1] auto[0] 217116 1 T1 221 T4 93 T5 35
auto[1] auto[0] auto[1] auto[1] auto[1] 230470 1 T1 770 T2 676 T12 216
auto[1] auto[1] auto[0] auto[0] auto[0] 482400 1 T1 2057 T2 954 T4 109
auto[1] auto[1] auto[0] auto[0] auto[1] 488166 1 T3 1 T4 3 T5 92
auto[1] auto[1] auto[0] auto[1] auto[0] 525614 1 T1 276 T2 405 T12 68
auto[1] auto[1] auto[0] auto[1] auto[1] 538676 1 T1 222 T2 5 T3 48
auto[1] auto[1] auto[1] auto[0] auto[0] 579815 1 T1 968 T2 306 T3 67
auto[1] auto[1] auto[1] auto[0] auto[1] 498764 1 T1 957 T2 173 T3 9
auto[1] auto[1] auto[1] auto[1] auto[0] 503037 1 T1 695 T2 1121 T4 170
auto[1] auto[1] auto[1] auto[1] auto[1] 495387 1 T2 676 T3 1 T12 72


Summary for Cross fifo_full_cross

Samples crossed: sta_fifo_full hmac_en endian_swap digest_swap key_swap
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 32 0 32 100.00


Automatically Generated Cross Bins for fifo_full_cross

Bins
sta_fifo_fullhmac_enendian_swapdigest_swapkey_swapCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] 251626 1 T1 349 T2 1 T3 43
auto[0] auto[0] auto[0] auto[0] auto[1] 256432 1 T1 489 T2 415 T4 12
auto[0] auto[0] auto[0] auto[1] auto[0] 228669 1 T1 1110 T2 482 T12 605
auto[0] auto[0] auto[0] auto[1] auto[1] 267394 1 T1 2039 T2 1080 T4 46
auto[0] auto[0] auto[1] auto[0] auto[0] 1762326 1 T1 345 T2 688 T3 48
auto[0] auto[0] auto[1] auto[0] auto[1] 244836 1 T1 1326 T2 824 T4 41
auto[0] auto[0] auto[1] auto[1] auto[0] 266973 1 T1 279 T4 93 T5 35
auto[0] auto[0] auto[1] auto[1] auto[1] 277357 1 T1 901 T2 696 T12 216
auto[0] auto[1] auto[0] auto[0] auto[0] 528745 1 T1 2438 T2 969 T4 114
auto[0] auto[1] auto[0] auto[0] auto[1] 531866 1 T3 1 T4 3 T5 98
auto[0] auto[1] auto[0] auto[1] auto[0] 580312 1 T1 420 T2 405 T12 68
auto[0] auto[1] auto[0] auto[1] auto[1] 592068 1 T1 222 T2 5 T3 48
auto[0] auto[1] auto[1] auto[0] auto[0] 638274 1 T1 1177 T2 306 T3 70
auto[0] auto[1] auto[1] auto[0] auto[1] 552804 1 T1 1216 T2 178 T3 9
auto[0] auto[1] auto[1] auto[1] auto[0] 552612 1 T1 804 T2 1136 T4 178
auto[0] auto[1] auto[1] auto[1] auto[1] 546491 1 T2 676 T3 1 T12 72
auto[1] auto[0] auto[0] auto[0] auto[0] 1320 1 T25 104 T20 92 T94 1
auto[1] auto[0] auto[0] auto[0] auto[1] 1706 1 T25 24 T20 1 T94 305
auto[1] auto[0] auto[0] auto[1] auto[0] 732 1 T25 2 T20 14 T94 153
auto[1] auto[0] auto[0] auto[1] auto[1] 1588 1 T25 31 T20 49 T38 2
auto[1] auto[0] auto[1] auto[0] auto[0] 2768 1 T20 6 T94 20 T9 103
auto[1] auto[0] auto[1] auto[0] auto[1] 1089 1 T25 12 T20 89 T137 30
auto[1] auto[0] auto[1] auto[1] auto[0] 1291 1 T25 24 T20 11 T137 15
auto[1] auto[0] auto[1] auto[1] auto[1] 1398 1 T25 23 T20 7 T94 37
auto[1] auto[1] auto[0] auto[0] auto[0] 1286 1 T20 1 T9 27 T138 1
auto[1] auto[1] auto[0] auto[0] auto[1] 1043 1 T20 3 T38 72 T139 24
auto[1] auto[1] auto[0] auto[1] auto[0] 892 1 T25 3 T94 14 T137 4
auto[1] auto[1] auto[0] auto[1] auto[1] 562 1 T25 61 T20 10 T94 12
auto[1] auto[1] auto[1] auto[0] auto[0] 514 1 T25 6 T20 62 T137 26
auto[1] auto[1] auto[1] auto[0] auto[1] 218 1 T20 5 T9 35 T138 84
auto[1] auto[1] auto[1] auto[1] auto[0] 920 1 T25 3 T9 15 T140 42
auto[1] auto[1] auto[1] auto[1] auto[1] 262 1 T25 27 T20 90 T137 23


Summary for Cross fifo_depth_cross

Samples crossed: sta_fifo_depth hmac_en endian_swap digest_swap key_swap
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 128 0 128 100.00


Automatically Generated Cross Bins for fifo_depth_cross

Bins
sta_fifo_depthhmac_enendian_swapdigest_swapkey_swapCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
fifo_depth[0] auto[0] auto[0] auto[0] auto[0] 202247 1 T1 349 T2 1 T3 42
fifo_depth[0] auto[0] auto[0] auto[0] auto[1] 212922 1 T1 388 T2 408 T4 12
fifo_depth[0] auto[0] auto[0] auto[1] auto[0] 189810 1 T1 719 T2 469 T12 503
fifo_depth[0] auto[0] auto[0] auto[1] auto[1] 224624 1 T1 1769 T2 1063 T4 44
fifo_depth[0] auto[0] auto[1] auto[0] auto[0] 1582416 1 T1 345 T2 674 T3 48
fifo_depth[0] auto[0] auto[1] auto[0] auto[1] 200832 1 T1 1147 T2 815 T4 41
fifo_depth[0] auto[0] auto[1] auto[1] auto[0] 217116 1 T1 221 T4 93 T5 35
fifo_depth[0] auto[0] auto[1] auto[1] auto[1] 230470 1 T1 770 T2 676 T12 216
fifo_depth[0] auto[1] auto[0] auto[0] auto[0] 482400 1 T1 2057 T2 954 T4 109
fifo_depth[0] auto[1] auto[0] auto[0] auto[1] 488166 1 T3 1 T4 3 T5 92
fifo_depth[0] auto[1] auto[0] auto[1] auto[0] 525614 1 T1 276 T2 405 T12 68
fifo_depth[0] auto[1] auto[0] auto[1] auto[1] 538676 1 T1 222 T2 5 T3 48
fifo_depth[0] auto[1] auto[1] auto[0] auto[0] 579815 1 T1 968 T2 306 T3 67
fifo_depth[0] auto[1] auto[1] auto[0] auto[1] 498764 1 T1 957 T2 173 T3 9
fifo_depth[0] auto[1] auto[1] auto[1] auto[0] 503037 1 T1 695 T2 1121 T4 170
fifo_depth[0] auto[1] auto[1] auto[1] auto[1] 495387 1 T2 676 T3 1 T12 72
fifo_depth[1] auto[0] auto[0] auto[0] auto[0] 4411 1 T3 1 T4 1 T8 3
fifo_depth[1] auto[0] auto[0] auto[0] auto[1] 4617 1 T1 9 T2 6 T5 9
fifo_depth[1] auto[0] auto[0] auto[1] auto[0] 3926 1 T1 80 T2 8 T12 34
fifo_depth[1] auto[0] auto[0] auto[1] auto[1] 5030 1 T1 45 T2 13 T4 1
fifo_depth[1] auto[0] auto[1] auto[0] auto[0] 44586 1 T2 10 T5 15 T13 41
fifo_depth[1] auto[0] auto[1] auto[0] auto[1] 4436 1 T1 29 T2 9 T5 35
fifo_depth[1] auto[0] auto[1] auto[1] auto[0] 4267 1 T1 12 T13 11 T28 68
fifo_depth[1] auto[0] auto[1] auto[1] auto[1] 4732 1 T1 32 T2 16 T13 114
fifo_depth[1] auto[1] auto[0] auto[0] auto[0] 6689 1 T1 80 T2 12 T4 3
fifo_depth[1] auto[1] auto[0] auto[0] auto[1] 6744 1 T6 2 T13 28 T26 3
fifo_depth[1] auto[1] auto[0] auto[1] auto[0] 7376 1 T1 29 T5 21 T7 100
fifo_depth[1] auto[1] auto[0] auto[1] auto[1] 7420 1 T8 2 T13 22 T28 47
fifo_depth[1] auto[1] auto[1] auto[0] auto[0] 8029 1 T1 39 T3 2 T4 2
fifo_depth[1] auto[1] auto[1] auto[0] auto[1] 7944 1 T1 42 T2 2 T4 4
fifo_depth[1] auto[1] auto[1] auto[1] auto[0] 7213 1 T1 17 T2 14 T4 6
fifo_depth[1] auto[1] auto[1] auto[1] auto[1] 6783 1 T8 1 T136 1 T28 93
fifo_depth[2] auto[0] auto[0] auto[0] auto[0] 3542 1 T13 27 T28 32 T29 10
fifo_depth[2] auto[0] auto[0] auto[0] auto[1] 4028 1 T1 20 T2 1 T5 7
fifo_depth[2] auto[0] auto[0] auto[1] auto[0] 3412 1 T1 67 T2 5 T12 28
fifo_depth[2] auto[0] auto[0] auto[1] auto[1] 4146 1 T1 51 T2 4 T4 1
fifo_depth[2] auto[0] auto[1] auto[0] auto[0] 33080 1 T2 3 T5 12 T13 48
fifo_depth[2] auto[0] auto[1] auto[0] auto[1] 3498 1 T1 31 T5 8 T13 95
fifo_depth[2] auto[0] auto[1] auto[1] auto[0] 3339 1 T1 7 T13 13 T28 24
fifo_depth[2] auto[0] auto[1] auto[1] auto[1] 3674 1 T1 15 T2 4 T5 1
fifo_depth[2] auto[1] auto[0] auto[0] auto[0] 5818 1 T1 59 T2 3 T4 1
fifo_depth[2] auto[1] auto[0] auto[0] auto[1] 5624 1 T5 4 T6 1 T13 38
fifo_depth[2] auto[1] auto[0] auto[1] auto[0] 6305 1 T1 30 T5 17 T7 87
fifo_depth[2] auto[1] auto[0] auto[1] auto[1] 6378 1 T12 4 T8 1 T13 23
fifo_depth[2] auto[1] auto[1] auto[0] auto[0] 6308 1 T1 31 T3 1 T4 2
fifo_depth[2] auto[1] auto[1] auto[0] auto[1] 6695 1 T1 55 T2 2 T4 2
fifo_depth[2] auto[1] auto[1] auto[1] auto[0] 6309 1 T1 15 T2 1 T4 2
fifo_depth[2] auto[1] auto[1] auto[1] auto[1] 6021 1 T4 1 T8 2 T6 1
fifo_depth[3] auto[0] auto[0] auto[0] auto[0] 2792 1 T6 1 T13 28 T28 9
fifo_depth[3] auto[0] auto[0] auto[0] auto[1] 2968 1 T1 13 T5 3 T13 115
fifo_depth[3] auto[0] auto[0] auto[1] auto[0] 2522 1 T1 57 T12 18 T5 1
fifo_depth[3] auto[0] auto[0] auto[1] auto[1] 3037 1 T1 42 T18 1 T13 25
fifo_depth[3] auto[0] auto[1] auto[0] auto[0] 25271 1 T2 1 T13 48 T28 5
fifo_depth[3] auto[0] auto[1] auto[0] auto[1] 2640 1 T1 28 T5 8 T13 94
fifo_depth[3] auto[0] auto[1] auto[1] auto[0] 2414 1 T1 11 T13 8 T28 6
fifo_depth[3] auto[0] auto[1] auto[1] auto[1] 2789 1 T1 26 T13 105 T28 11
fifo_depth[3] auto[1] auto[0] auto[0] auto[0] 5002 1 T1 55 T4 1 T6 1
fifo_depth[3] auto[1] auto[0] auto[0] auto[1] 4776 1 T13 35 T28 4 T29 10
fifo_depth[3] auto[1] auto[0] auto[1] auto[0] 5514 1 T1 22 T18 1 T5 2
fifo_depth[3] auto[1] auto[0] auto[1] auto[1] 5594 1 T13 22 T28 12 T31 216
fifo_depth[3] auto[1] auto[1] auto[0] auto[0] 5238 1 T1 42 T7 40 T13 22
fifo_depth[3] auto[1] auto[1] auto[0] auto[1] 5689 1 T1 49 T2 1 T5 8
fifo_depth[3] auto[1] auto[1] auto[1] auto[0] 5416 1 T1 17 T7 106 T13 58
fifo_depth[3] auto[1] auto[1] auto[1] auto[1] 5165 1 T8 2 T6 1 T28 7
fifo_depth[4] auto[0] auto[0] auto[0] auto[0] 2810 1 T13 28 T29 1 T25 51
fifo_depth[4] auto[0] auto[0] auto[0] auto[1] 3350 1 T1 17 T5 2 T13 139
fifo_depth[4] auto[0] auto[0] auto[1] auto[0] 2648 1 T1 67 T12 14 T5 16
fifo_depth[4] auto[0] auto[0] auto[1] auto[1] 3412 1 T1 48 T5 5 T13 25
fifo_depth[4] auto[0] auto[1] auto[0] auto[0] 19320 1 T13 46 T29 2 T25 66
fifo_depth[4] auto[0] auto[1] auto[0] auto[1] 2998 1 T1 18 T5 7 T136 1
fifo_depth[4] auto[0] auto[1] auto[1] auto[0] 2779 1 T1 8 T13 13 T28 1
fifo_depth[4] auto[0] auto[1] auto[1] auto[1] 2793 1 T1 29 T13 107 T28 3
fifo_depth[4] auto[1] auto[0] auto[0] auto[0] 4737 1 T1 54 T28 2 T29 8
fifo_depth[4] auto[1] auto[0] auto[0] auto[1] 4391 1 T5 2 T13 26 T29 9
fifo_depth[4] auto[1] auto[0] auto[1] auto[0] 5337 1 T1 26 T7 107 T13 48
fifo_depth[4] auto[1] auto[0] auto[1] auto[1] 5372 1 T12 4 T13 25 T28 1
fifo_depth[4] auto[1] auto[1] auto[0] auto[0] 4851 1 T1 33 T7 44 T13 18
fifo_depth[4] auto[1] auto[1] auto[0] auto[1] 5462 1 T1 36 T5 8 T28 2
fifo_depth[4] auto[1] auto[1] auto[1] auto[0] 5223 1 T1 15 T7 95 T13 63
fifo_depth[4] auto[1] auto[1] auto[1] auto[1] 5467 1 T5 1 T28 2 T29 2
fifo_depth[5] auto[0] auto[0] auto[0] auto[0] 2110 1 T13 25 T25 31 T81 1
fifo_depth[5] auto[0] auto[0] auto[0] auto[1] 2279 1 T1 15 T5 1 T13 82
fifo_depth[5] auto[0] auto[0] auto[1] auto[0] 1972 1 T1 61 T12 6 T13 5
fifo_depth[5] auto[0] auto[0] auto[1] auto[1] 2234 1 T1 37 T13 22 T29 1
fifo_depth[5] auto[0] auto[1] auto[0] auto[0] 13710 1 T13 23 T25 59 T20 54
fifo_depth[5] auto[0] auto[1] auto[0] auto[1] 2136 1 T1 22 T5 2 T13 80
fifo_depth[5] auto[0] auto[1] auto[1] auto[0] 1854 1 T1 5 T13 9 T29 7
fifo_depth[5] auto[0] auto[1] auto[1] auto[1] 2137 1 T1 15 T13 83 T28 1
fifo_depth[5] auto[1] auto[0] auto[0] auto[0] 4122 1 T1 57 T28 1 T29 5
fifo_depth[5] auto[1] auto[0] auto[0] auto[1] 3519 1 T13 24 T28 2 T29 2
fifo_depth[5] auto[1] auto[0] auto[1] auto[0] 4603 1 T1 16 T7 81 T13 37
fifo_depth[5] auto[1] auto[0] auto[1] auto[1] 4714 1 T12 1 T13 22 T31 214
fifo_depth[5] auto[1] auto[1] auto[0] auto[0] 3871 1 T1 25 T7 38 T13 16
fifo_depth[5] auto[1] auto[1] auto[0] auto[1] 4390 1 T1 35 T13 1 T29 2
fifo_depth[5] auto[1] auto[1] auto[1] auto[0] 4308 1 T1 11 T7 88 T13 52
fifo_depth[5] auto[1] auto[1] auto[1] auto[1] 4301 1 T5 1 T28 2 T25 106
fifo_depth[6] auto[0] auto[0] auto[0] auto[0] 1665 1 T13 15 T25 23 T20 99
fifo_depth[6] auto[0] auto[0] auto[0] auto[1] 2099 1 T1 11 T5 1 T13 52
fifo_depth[6] auto[0] auto[0] auto[1] auto[0] 1707 1 T1 31 T12 2 T5 4
fifo_depth[6] auto[0] auto[0] auto[1] auto[1] 2128 1 T1 22 T13 10 T25 95
fifo_depth[6] auto[0] auto[1] auto[0] auto[0] 9704 1 T13 12 T25 46 T20 36
fifo_depth[6] auto[0] auto[1] auto[0] auto[1] 2049 1 T1 26 T5 1 T13 49
fifo_depth[6] auto[0] auto[1] auto[1] auto[0] 1997 1 T1 6 T13 10 T29 12
fifo_depth[6] auto[0] auto[1] auto[1] auto[1] 1807 1 T1 6 T13 63 T25 130
fifo_depth[6] auto[1] auto[0] auto[0] auto[0] 3275 1 T1 32 T29 3 T25 41
fifo_depth[6] auto[1] auto[0] auto[0] auto[1] 2696 1 T13 14 T29 2 T25 111
fifo_depth[6] auto[1] auto[0] auto[1] auto[0] 3875 1 T1 12 T7 56 T13 25
fifo_depth[6] auto[1] auto[0] auto[1] auto[1] 3806 1 T12 1 T13 17 T31 176
fifo_depth[6] auto[1] auto[1] auto[0] auto[0] 3340 1 T1 18 T7 24 T13 16
fifo_depth[6] auto[1] auto[1] auto[0] auto[1] 3601 1 T1 27 T13 1 T29 2
fifo_depth[6] auto[1] auto[1] auto[1] auto[0] 3547 1 T1 15 T7 72 T13 44
fifo_depth[6] auto[1] auto[1] auto[1] auto[1] 3807 1 T28 2 T25 86 T20 24
fifo_depth[7] auto[0] auto[0] auto[0] auto[0] 1215 1 T13 12 T25 21 T20 80
fifo_depth[7] auto[0] auto[0] auto[0] auto[1] 1219 1 T1 10 T5 2 T13 33
fifo_depth[7] auto[0] auto[0] auto[1] auto[0] 1109 1 T1 21 T13 4 T28 1
fifo_depth[7] auto[0] auto[0] auto[1] auto[1] 1381 1 T1 10 T13 8 T25 89
fifo_depth[7] auto[0] auto[1] auto[0] auto[0] 5985 1 T136 1 T13 7 T25 37
fifo_depth[7] auto[0] auto[1] auto[0] auto[1] 1238 1 T1 16 T13 43 T29 1
fifo_depth[7] auto[0] auto[1] auto[1] auto[0] 1361 1 T1 7 T13 9 T29 1
fifo_depth[7] auto[0] auto[1] auto[1] auto[1] 1345 1 T1 5 T13 49 T25 96
fifo_depth[7] auto[1] auto[0] auto[0] auto[0] 2240 1 T1 23 T29 2 T25 20
fifo_depth[7] auto[1] auto[0] auto[0] auto[1] 1937 1 T13 7 T25 67 T72 1
fifo_depth[7] auto[1] auto[0] auto[1] auto[0] 2675 1 T1 6 T7 61 T13 19
fifo_depth[7] auto[1] auto[0] auto[1] auto[1] 2771 1 T13 4 T31 121 T25 86
fifo_depth[7] auto[1] auto[1] auto[0] auto[0] 2321 1 T1 8 T7 17 T13 14
fifo_depth[7] auto[1] auto[1] auto[0] auto[1] 2304 1 T1 9 T29 3 T25 85
fifo_depth[7] auto[1] auto[1] auto[1] auto[0] 2431 1 T1 10 T7 50 T13 28
fifo_depth[7] auto[1] auto[1] auto[1] auto[1] 2472 1 T5 1 T28 2 T25 62

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