Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	19227044	1			T1	26443		T2	15749		T3	436
all_pins[1]	19227044	1			T1	26443		T2	15749		T3	436
all_pins[2]	19227044	1			T1	26443		T2	15749		T3	436

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	49065747	1			T1	70973		T2	42130		T3	1148
values[0x1]	8615385	1			T1	8356		T2	5117		T3	160
transitions[0x0=>0x1]	8615160	1			T1	8356		T2	5117		T3	160
transitions[0x1=>0x0]	8615172	1			T1	8356		T2	5117		T3	160

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	19204840	1			T1	26413		T2	15729		T3	433
all_pins[0]	values[0x1]	22204	1			T1	30		T2	20		T3	3
all_pins[0]	transitions[0x0=>0x1]	22123	1			T1	30		T2	20		T3	3
all_pins[0]	transitions[0x1=>0x0]	8592559	1			T1	8326		T2	5097		T3	157
all_pins[1]	values[0x0]	19226491	1			T1	26443		T2	15749		T3	436
all_pins[1]	values[0x1]	553	1			T6	3		T28	4		T29	1
all_pins[1]	transitions[0x0=>0x1]	487	1			T6	3		T28	4		T29	1
all_pins[1]	transitions[0x1=>0x0]	22138	1			T1	30		T2	20		T3	3
all_pins[2]	values[0x0]	10634416	1			T1	18117		T2	10652		T3	279
all_pins[2]	values[0x1]	8592628	1			T1	8326		T2	5097		T3	157
all_pins[2]	transitions[0x0=>0x1]	8592550	1			T1	8326		T2	5097		T3	157
all_pins[2]	transitions[0x1=>0x0]	475	1			T6	1		T28	3		T25	12