Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 0 18 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 0 18 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 1241 1 T6 7 T28 11 T29 17
all_values[1] 1241 1 T6 7 T28 11 T29 17
all_values[2] 1241 1 T6 7 T28 11 T29 17


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1831 1 T6 8 T28 11 T29 20
auto[1] 1892 1 T6 13 T28 22 T29 31


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1336 1 T6 7 T28 14 T29 20
auto[1] 2387 1 T6 14 T28 19 T29 31


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 2116 1 T6 11 T28 21 T29 33
auto[1] 1607 1 T6 10 T28 12 T29 18


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 0 18 100.00
Automatically Generated Cross Bins 18 0 18 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 252 1 T6 3 T28 1 T29 6
all_values[0] auto[0] auto[0] auto[1] 119 1 T28 1 T29 1 T72 3
all_values[0] auto[0] auto[1] auto[0] 231 1 T6 1 T28 4 T29 3
all_values[0] auto[0] auto[1] auto[1] 118 1 T28 1 T29 3 T25 6
all_values[0] auto[1] auto[0] auto[1] 258 1 T6 1 T28 1 T29 2
all_values[0] auto[1] auto[1] auto[1] 263 1 T6 2 T28 3 T29 2
all_values[1] auto[0] auto[0] auto[0] 176 1 T6 1 T28 1 T29 2
all_values[1] auto[0] auto[0] auto[1] 158 1 T28 1 T29 2 T25 4
all_values[1] auto[0] auto[1] auto[0] 214 1 T6 1 T28 3 T29 4
all_values[1] auto[0] auto[1] auto[1] 163 1 T6 2 T28 1 T29 3
all_values[1] auto[1] auto[0] auto[1] 260 1 T6 1 T28 2 T29 4
all_values[1] auto[1] auto[1] auto[1] 270 1 T6 2 T28 3 T29 2
all_values[2] auto[0] auto[0] auto[0] 226 1 T28 2 T25 2 T72 2
all_values[2] auto[0] auto[0] auto[1] 107 1 T6 1 T28 1 T29 1
all_values[2] auto[0] auto[1] auto[0] 237 1 T6 1 T28 3 T29 5
all_values[2] auto[0] auto[1] auto[1] 115 1 T6 1 T28 2 T29 3
all_values[2] auto[1] auto[0] auto[1] 275 1 T6 1 T28 1 T29 2
all_values[2] auto[1] auto[1] auto[1] 281 1 T6 3 T28 2 T29 6


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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