Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::cfg_cg

Group : hmac_env_pkg::hmac_env_cov::cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	90	0	90	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_size	5	0	5	100.00	100	1	1	0
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	0
key_length	7	0	7	100.00	100	1	1	0
key_swap	2	0	2	100.00	100	1	1	2
sha_en	2	0	2	100.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cfg_cross	16	0	16	100.00	100	1	1	0
hmac_dis_x_sha_en	4	0	4	100.00	100	1	1	0
key_x_digest_mismatch	35	0	35	100.00	100	1	1	0
key_length_x_digest_size	35	0	35	100.00	100	1	1	0

Summary for Variable digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for digest_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sha2_invalid	5106	1			T1	7		T2	9		T3	1
sha2_none	4786	1			T1	8		T2	6		T3	3
sha2_512	7982	1			T1	5		T2	7		T3	2
sha2_384	8129	1			T1	10		T2	7		T3	1
sha2_256	7057	1			T1	11		T2	6		T3	1

---

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20018

1

T1

24

T2

16

T3

6

auto[1]

13486

1

T1

18

T2

21

T3

2

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

13158

1

T1

24

T2

17

T3

3

auto[1]

20346

1

T1

18

T2

20

T3

5

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

17476

1

T1

19

T2

19

T3

6

disabled

16028

1

T1

23

T2

18

T3

2

---

Summary for Variable key_length

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for key_length

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	5489	1			T1	7		T2	5		T3	3
key_none	7864	1			T1	6		T2	2		T4	3
key_1024	4830	1			T1	6		T2	11		T3	1
key_512	4267	1			T1	3		T2	9		T12	1
key_384	3884	1			T1	10		T3	2		T4	12
key_256	3600	1			T1	4		T2	2		T3	1
key_128	3468	1			T1	6		T2	8		T3	1

---

Summary for Variable key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for key_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20407

1

T1

22

T2

16

T3

4

auto[1]

13097

1

T1

20

T2

21

T3

4

---

Summary for Variable sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

33254

1

T1

42

T2

37

T3

8

disabled

250

1

T13

4

T28

6

T29

4

---

Summary for Cross cfg_cross

Samples crossed: hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cfg_cross

Bins

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

auto[0]

auto[0]

auto[0]

1795

1

T1

7

T2

3

T4

6

enabled

auto[0]

auto[0]

auto[1]

1795

1

T3

1

T4

3

T5

2

enabled

auto[0]

auto[1]

auto[0]

1870

1

T1

2

T2

3

T12

1

enabled

auto[0]

auto[1]

auto[1]

1865

1

T1

1

T2

1

T3

1

enabled

auto[1]

auto[0]

auto[0]

4489

1

T1

3

T2

2

T3

2

enabled

auto[1]

auto[0]

auto[1]

1805

1

T1

4

T2

2

T3

1

enabled

auto[1]

auto[1]

auto[0]

2059

1

T1

2

T2

4

T4

5

enabled

auto[1]

auto[1]

auto[1]

1798

1

T2

4

T3

1

T12

1

disabled

auto[0]

auto[0]

auto[0]

1460

1

T1

3

T2

1

T3

1

disabled

auto[0]

auto[0]

auto[1]

1447

1

T1

1

T2

3

T4

2

disabled

auto[0]

auto[1]

auto[0]

1447

1

T1

3

T2

1

T12

1

disabled

auto[0]

auto[1]

auto[1]

1479

1

T1

7

T2

5

T4

1

disabled

auto[1]

auto[0]

auto[0]

5857

1

T1

1

T2

2

T3

1

disabled

auto[1]

auto[0]

auto[1]

1370

1

T1

5

T2

3

T4

2

disabled

auto[1]

auto[1]

auto[0]

1430

1

T1

1

T4

2

T5

3

disabled

auto[1]

auto[1]

auto[1]

1538

1

T1

2

T2

3

T12

1

---

Summary for Cross hmac_dis_x_sha_en

Samples crossed: hmac_en sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	3	0	3	100.00
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for hmac_dis_x_sha_en

Bins

hmac_en

sha_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

enabled

17380

1

T1

19

T2

19

T3

6

enabled

disabled

96

1

T13

1

T28

3

T29

4

disabled

disabled

154

1

T13

3

T28

3

T72

7

User Defined Cross Bins for hmac_dis_x_sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

15874

1

T1

23

T2

18

T3

2

---

Summary for Cross key_x_digest_mismatch

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	35	0	35	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for key_x_digest_mismatch

Bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	sha2_invalid	1336	1			T1	2		T2	1		T3	1
key_invalid	sha2_none	962	1			T1	2		T2	1		T12	1
key_invalid	sha2_512	1019	1			T1	1		T2	1		T3	1
key_invalid	sha2_384	1028	1			T1	2		T2	2		T4	3
key_invalid	sha2_256	1023	1			T3	1		T12	1		T4	2
key_none	sha2_invalid	618	1			T1	2		T2	1		T4	1
key_none	sha2_none	572	1			T1	1		T4	1		T5	1
key_none	sha2_512	2234	1			T1	1		T4	1		T5	4
key_none	sha2_384	2690	1			T1	1		T5	1		T7	1
key_none	sha2_256	1688	1			T1	1		T2	1		T5	1
key_1024	sha2_invalid	629	1			T2	3		T4	2		T5	1
key_1024	sha2_none	645	1			T1	1		T2	1		T4	2
key_1024	sha2_512	1832	1			T2	3		T12	1		T4	2
key_1024	sha2_384	1011	1			T1	4		T2	2		T3	1
key_512	sha2_invalid	604	1			T4	1		T5	2		T8	3
key_512	sha2_none	657	1			T2	1		T12	1		T4	1
key_512	sha2_512	740	1			T1	1		T2	3		T8	1
key_512	sha2_384	1262	1			T2	2		T4	2		T5	1
key_512	sha2_256	955	1			T1	2		T2	2		T4	4
key_384	sha2_invalid	639	1			T1	1		T4	1		T5	2
key_384	sha2_none	665	1			T1	3		T3	2		T4	4
key_384	sha2_512	713	1			T1	1		T4	4		T7	2
key_384	sha2_384	687	1			T1	2		T4	2		T7	3
key_384	sha2_256	1119	1			T1	3		T4	1		T18	1
key_256	sha2_invalid	612	1			T2	2		T4	1		T18	1
key_256	sha2_none	669	1			T3	1		T4	2		T18	1
key_256	sha2_512	700	1			T6	2		T13	1		T28	4
key_256	sha2_384	711	1			T4	1		T18	1		T7	1
key_256	sha2_256	862	1			T1	3		T4	1		T5	3
key_128	sha2_invalid	648	1			T1	2		T2	2		T4	1
key_128	sha2_none	601	1			T1	1		T2	3		T12	1
key_128	sha2_512	721	1			T1	1		T3	1		T4	1
key_128	sha2_384	722	1			T1	1		T2	1		T5	2
key_128	sha2_256	724	1			T1	1		T2	1		T4	2

User Defined Cross Bins for key_x_digest_mismatch

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

663

1

T1

1

T2

2

T4

2

---

Summary for Cross key_length_x_digest_size

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	35	0	35	100.00

Automatically Generated Cross Bins for key_length_x_digest_size

Bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	sha2_invalid	1336	1			T1	2		T2	1		T3	1
key_invalid	sha2_none	962	1			T1	2		T2	1		T12	1
key_invalid	sha2_512	1019	1			T1	1		T2	1		T3	1
key_invalid	sha2_384	1028	1			T1	2		T2	2		T4	3
key_invalid	sha2_256	1023	1			T3	1		T12	1		T4	2
key_none	sha2_invalid	618	1			T1	2		T2	1		T4	1
key_none	sha2_none	572	1			T1	1		T4	1		T5	1
key_none	sha2_512	2234	1			T1	1		T4	1		T5	4
key_none	sha2_384	2690	1			T1	1		T5	1		T7	1
key_none	sha2_256	1688	1			T1	1		T2	1		T5	1
key_1024	sha2_invalid	629	1			T2	3		T4	2		T5	1
key_1024	sha2_none	645	1			T1	1		T2	1		T4	2
key_1024	sha2_512	1832	1			T2	3		T12	1		T4	2
key_1024	sha2_384	1011	1			T1	4		T2	2		T3	1
key_1024	sha2_256	663	1			T1	1		T2	2		T4	2
key_512	sha2_invalid	604	1			T4	1		T5	2		T8	3
key_512	sha2_none	657	1			T2	1		T12	1		T4	1
key_512	sha2_512	740	1			T1	1		T2	3		T8	1
key_512	sha2_384	1262	1			T2	2		T4	2		T5	1
key_512	sha2_256	955	1			T1	2		T2	2		T4	4
key_384	sha2_invalid	639	1			T1	1		T4	1		T5	2
key_384	sha2_none	665	1			T1	3		T3	2		T4	4
key_384	sha2_512	713	1			T1	1		T4	4		T7	2
key_384	sha2_384	687	1			T1	2		T4	2		T7	3
key_384	sha2_256	1119	1			T1	3		T4	1		T18	1
key_256	sha2_invalid	612	1			T2	2		T4	1		T18	1
key_256	sha2_none	669	1			T3	1		T4	2		T18	1
key_256	sha2_512	700	1			T6	2		T13	1		T28	4
key_256	sha2_384	711	1			T4	1		T18	1		T7	1
key_256	sha2_256	862	1			T1	3		T4	1		T5	3
key_128	sha2_invalid	648	1			T1	2		T2	2		T4	1
key_128	sha2_none	601	1			T1	1		T2	3		T12	1
key_128	sha2_512	721	1			T1	1		T3	1		T4	1
key_128	sha2_384	722	1			T1	1		T2	1		T5	2
key_128	sha2_256	724	1			T1	1		T2	1		T4	2