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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.09 95.95 94.35 100.00 87.18 92.33 99.49 96.35


Total test records in report: 659
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T118 /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.110402651 Jul 01 10:39:45 AM PDT 24 Jul 01 10:39:49 AM PDT 24 197909120 ps
T536 /workspace/coverage/cover_reg_top/6.hmac_intr_test.1312367117 Jul 01 10:39:57 AM PDT 24 Jul 01 10:39:58 AM PDT 24 25757383 ps
T101 /workspace/coverage/cover_reg_top/13.hmac_csr_rw.3742931239 Jul 01 10:39:36 AM PDT 24 Jul 01 10:39:44 AM PDT 24 20821101 ps
T102 /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.3536320958 Jul 01 10:39:40 AM PDT 24 Jul 01 10:39:50 AM PDT 24 218785287 ps
T537 /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.350266623 Jul 01 10:39:38 AM PDT 24 Jul 01 10:39:58 AM PDT 24 5237953365 ps
T538 /workspace/coverage/cover_reg_top/1.hmac_tl_errors.3962278905 Jul 01 10:39:39 AM PDT 24 Jul 01 10:39:45 AM PDT 24 31691461 ps
T539 /workspace/coverage/cover_reg_top/11.hmac_intr_test.1891775798 Jul 01 10:39:38 AM PDT 24 Jul 01 10:39:44 AM PDT 24 31208918 ps
T540 /workspace/coverage/cover_reg_top/3.hmac_tl_errors.1329495621 Jul 01 10:40:04 AM PDT 24 Jul 01 10:40:07 AM PDT 24 125112890 ps
T541 /workspace/coverage/cover_reg_top/8.hmac_csr_rw.2357941964 Jul 01 10:39:36 AM PDT 24 Jul 01 10:39:41 AM PDT 24 24385827 ps
T542 /workspace/coverage/cover_reg_top/26.hmac_intr_test.1409952773 Jul 01 10:39:39 AM PDT 24 Jul 01 10:39:44 AM PDT 24 72616980 ps
T103 /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.1727759673 Jul 01 10:39:34 AM PDT 24 Jul 01 10:39:38 AM PDT 24 27475044 ps
T543 /workspace/coverage/cover_reg_top/2.hmac_intr_test.86820349 Jul 01 10:39:33 AM PDT 24 Jul 01 10:39:36 AM PDT 24 11681579 ps
T78 /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.3269117312 Jul 01 10:39:37 AM PDT 24 Jul 01 10:39:44 AM PDT 24 611194116 ps
T58 /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.2368264701 Jul 01 10:39:43 AM PDT 24 Jul 01 10:39:50 AM PDT 24 639758171 ps
T544 /workspace/coverage/cover_reg_top/14.hmac_tl_errors.2086572384 Jul 01 10:39:54 AM PDT 24 Jul 01 10:39:56 AM PDT 24 58113047 ps
T104 /workspace/coverage/cover_reg_top/17.hmac_csr_rw.2996054691 Jul 01 10:39:51 AM PDT 24 Jul 01 10:39:53 AM PDT 24 31876223 ps
T79 /workspace/coverage/cover_reg_top/33.hmac_intr_test.941960148 Jul 01 10:39:35 AM PDT 24 Jul 01 10:39:39 AM PDT 24 32989681 ps
T105 /workspace/coverage/cover_reg_top/6.hmac_csr_rw.4174486215 Jul 01 10:39:40 AM PDT 24 Jul 01 10:39:45 AM PDT 24 35957532 ps
T119 /workspace/coverage/cover_reg_top/5.hmac_csr_rw.2228532955 Jul 01 10:39:22 AM PDT 24 Jul 01 10:39:24 AM PDT 24 126778510 ps
T126 /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.3478540606 Jul 01 10:39:38 AM PDT 24 Jul 01 10:39:47 AM PDT 24 540996328 ps
T545 /workspace/coverage/cover_reg_top/14.hmac_intr_test.3975588217 Jul 01 10:39:45 AM PDT 24 Jul 01 10:39:48 AM PDT 24 50360061 ps
T546 /workspace/coverage/cover_reg_top/34.hmac_intr_test.2750323169 Jul 01 10:39:36 AM PDT 24 Jul 01 10:39:41 AM PDT 24 42203221 ps
T129 /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.942399313 Jul 01 10:39:37 AM PDT 24 Jul 01 10:39:43 AM PDT 24 728837493 ps
T547 /workspace/coverage/cover_reg_top/10.hmac_intr_test.3171944759 Jul 01 10:40:05 AM PDT 24 Jul 01 10:40:07 AM PDT 24 45618120 ps
T548 /workspace/coverage/cover_reg_top/11.hmac_tl_errors.4101453400 Jul 01 10:39:44 AM PDT 24 Jul 01 10:39:51 AM PDT 24 411718754 ps
T549 /workspace/coverage/cover_reg_top/23.hmac_intr_test.2834205458 Jul 01 10:39:49 AM PDT 24 Jul 01 10:39:52 AM PDT 24 23302529 ps
T550 /workspace/coverage/cover_reg_top/6.hmac_tl_errors.56484753 Jul 01 10:39:34 AM PDT 24 Jul 01 10:39:41 AM PDT 24 207028843 ps
T551 /workspace/coverage/cover_reg_top/18.hmac_tl_errors.3081156445 Jul 01 10:39:41 AM PDT 24 Jul 01 10:39:47 AM PDT 24 96157672 ps
T552 /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.986785205 Jul 01 10:40:08 AM PDT 24 Jul 01 10:40:17 AM PDT 24 319776093 ps
T110 /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.2237115303 Jul 01 10:39:47 AM PDT 24 Jul 01 10:39:55 AM PDT 24 567711624 ps
T134 /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.1204038126 Jul 01 10:40:32 AM PDT 24 Jul 01 10:40:36 AM PDT 24 391534333 ps
T553 /workspace/coverage/cover_reg_top/9.hmac_intr_test.1345881076 Jul 01 10:39:40 AM PDT 24 Jul 01 10:39:45 AM PDT 24 133781636 ps
T120 /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.364701901 Jul 01 10:39:36 AM PDT 24 Jul 01 10:39:43 AM PDT 24 296980800 ps
T121 /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.3383264285 Jul 01 10:39:34 AM PDT 24 Jul 01 10:39:44 AM PDT 24 264165889 ps
T106 /workspace/coverage/cover_reg_top/3.hmac_csr_rw.4079846217 Jul 01 10:39:32 AM PDT 24 Jul 01 10:39:35 AM PDT 24 642766271 ps
T554 /workspace/coverage/cover_reg_top/32.hmac_intr_test.826631104 Jul 01 10:39:39 AM PDT 24 Jul 01 10:39:44 AM PDT 24 98336059 ps
T555 /workspace/coverage/cover_reg_top/8.hmac_tl_errors.1702879219 Jul 01 10:39:33 AM PDT 24 Jul 01 10:39:39 AM PDT 24 1132059593 ps
T556 /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.3082508173 Jul 01 10:39:43 AM PDT 24 Jul 01 10:39:49 AM PDT 24 101313556 ps
T557 /workspace/coverage/cover_reg_top/0.hmac_tl_errors.2558328742 Jul 01 10:39:34 AM PDT 24 Jul 01 10:39:38 AM PDT 24 128770520 ps
T122 /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.4154507982 Jul 01 10:39:34 AM PDT 24 Jul 01 10:39:37 AM PDT 24 187890596 ps
T123 /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.1011685749 Jul 01 10:39:50 AM PDT 24 Jul 01 10:39:53 AM PDT 24 214251638 ps
T130 /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.3930175080 Jul 01 10:40:17 AM PDT 24 Jul 01 10:40:24 AM PDT 24 166502086 ps
T558 /workspace/coverage/cover_reg_top/35.hmac_intr_test.1910760679 Jul 01 10:39:40 AM PDT 24 Jul 01 10:39:45 AM PDT 24 31378706 ps
T559 /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.875288172 Jul 01 10:39:36 AM PDT 24 Jul 01 10:39:41 AM PDT 24 213273188 ps
T560 /workspace/coverage/cover_reg_top/1.hmac_intr_test.3046820900 Jul 01 10:40:01 AM PDT 24 Jul 01 10:40:02 AM PDT 24 14870362 ps
T561 /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.1466608253 Jul 01 10:39:34 AM PDT 24 Jul 01 10:39:39 AM PDT 24 68648992 ps
T59 /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.2048090093 Jul 01 10:39:34 AM PDT 24 Jul 01 10:39:40 AM PDT 24 196053706 ps
T562 /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.3386765005 Jul 01 10:39:30 AM PDT 24 Jul 01 10:56:09 AM PDT 24 66093477906 ps
T563 /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.74483328 Jul 01 10:39:30 AM PDT 24 Jul 01 10:39:34 AM PDT 24 38410533 ps
T564 /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.3753761782 Jul 01 10:39:35 AM PDT 24 Jul 01 10:39:40 AM PDT 24 64041461 ps
T565 /workspace/coverage/cover_reg_top/41.hmac_intr_test.1482905385 Jul 01 10:40:19 AM PDT 24 Jul 01 10:40:23 AM PDT 24 11744640 ps
T566 /workspace/coverage/cover_reg_top/18.hmac_intr_test.2431339316 Jul 01 10:39:47 AM PDT 24 Jul 01 10:39:50 AM PDT 24 85531448 ps
T107 /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.1173347818 Jul 01 10:40:18 AM PDT 24 Jul 01 10:40:23 AM PDT 24 66336664 ps
T567 /workspace/coverage/cover_reg_top/42.hmac_intr_test.121202064 Jul 01 10:39:43 AM PDT 24 Jul 01 10:39:47 AM PDT 24 14181357 ps
T568 /workspace/coverage/cover_reg_top/12.hmac_csr_rw.3924422635 Jul 01 10:39:52 AM PDT 24 Jul 01 10:39:54 AM PDT 24 95027587 ps
T132 /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.4120884368 Jul 01 10:39:33 AM PDT 24 Jul 01 10:39:39 AM PDT 24 862546981 ps
T569 /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.2997583776 Jul 01 10:39:37 AM PDT 24 Jul 01 10:39:44 AM PDT 24 1407355143 ps
T131 /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.1612553206 Jul 01 10:39:47 AM PDT 24 Jul 01 10:39:51 AM PDT 24 97574152 ps
T570 /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.838951625 Jul 01 10:39:31 AM PDT 24 Jul 01 10:45:09 AM PDT 24 22753829928 ps
T571 /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.1889311461 Jul 01 10:39:19 AM PDT 24 Jul 01 10:39:21 AM PDT 24 138839288 ps
T572 /workspace/coverage/cover_reg_top/4.hmac_tl_errors.3452670718 Jul 01 10:40:14 AM PDT 24 Jul 01 10:40:18 AM PDT 24 291048770 ps
T573 /workspace/coverage/cover_reg_top/38.hmac_intr_test.2457502756 Jul 01 10:40:23 AM PDT 24 Jul 01 10:40:29 AM PDT 24 34673566 ps
T574 /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.1992948814 Jul 01 10:39:38 AM PDT 24 Jul 01 10:39:45 AM PDT 24 97244202 ps
T575 /workspace/coverage/cover_reg_top/4.hmac_csr_rw.1074335874 Jul 01 10:40:12 AM PDT 24 Jul 01 10:40:20 AM PDT 24 17430054 ps
T576 /workspace/coverage/cover_reg_top/7.hmac_intr_test.460669145 Jul 01 10:39:40 AM PDT 24 Jul 01 10:39:47 AM PDT 24 21415245 ps
T577 /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.2007647139 Jul 01 10:39:55 AM PDT 24 Jul 01 10:39:59 AM PDT 24 691572627 ps
T578 /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.672373239 Jul 01 10:40:11 AM PDT 24 Jul 01 10:43:50 AM PDT 24 27891115927 ps
T127 /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.1805122952 Jul 01 10:39:41 AM PDT 24 Jul 01 10:39:50 AM PDT 24 806890857 ps
T579 /workspace/coverage/cover_reg_top/0.hmac_intr_test.1008566217 Jul 01 10:39:34 AM PDT 24 Jul 01 10:39:38 AM PDT 24 36231793 ps
T580 /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.3824967289 Jul 01 10:40:07 AM PDT 24 Jul 01 10:40:10 AM PDT 24 96386280 ps
T581 /workspace/coverage/cover_reg_top/13.hmac_intr_test.2510121801 Jul 01 10:39:30 AM PDT 24 Jul 01 10:39:33 AM PDT 24 26783086 ps
T582 /workspace/coverage/cover_reg_top/29.hmac_intr_test.412730654 Jul 01 10:40:03 AM PDT 24 Jul 01 10:40:05 AM PDT 24 33992269 ps
T583 /workspace/coverage/cover_reg_top/39.hmac_intr_test.3422073287 Jul 01 10:40:08 AM PDT 24 Jul 01 10:40:09 AM PDT 24 37617708 ps
T108 /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.1072521735 Jul 01 10:39:39 AM PDT 24 Jul 01 10:39:57 AM PDT 24 1232020000 ps
T584 /workspace/coverage/cover_reg_top/2.hmac_tl_errors.3053334424 Jul 01 10:40:15 AM PDT 24 Jul 01 10:40:19 AM PDT 24 55647604 ps
T585 /workspace/coverage/cover_reg_top/22.hmac_intr_test.558323175 Jul 01 10:39:38 AM PDT 24 Jul 01 10:39:44 AM PDT 24 33634086 ps
T133 /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.3014691385 Jul 01 10:39:35 AM PDT 24 Jul 01 10:39:45 AM PDT 24 159278231 ps
T586 /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.1856181115 Jul 01 10:39:35 AM PDT 24 Jul 01 10:39:40 AM PDT 24 442924337 ps
T587 /workspace/coverage/cover_reg_top/31.hmac_intr_test.704711054 Jul 01 10:39:41 AM PDT 24 Jul 01 10:39:46 AM PDT 24 19128941 ps
T109 /workspace/coverage/cover_reg_top/19.hmac_csr_rw.146397021 Jul 01 10:39:42 AM PDT 24 Jul 01 10:39:46 AM PDT 24 26274944 ps
T588 /workspace/coverage/cover_reg_top/12.hmac_intr_test.2193766346 Jul 01 10:39:38 AM PDT 24 Jul 01 10:39:43 AM PDT 24 40283379 ps
T589 /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.2717463292 Jul 01 10:39:34 AM PDT 24 Jul 01 10:39:40 AM PDT 24 194446578 ps
T590 /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.1628800675 Jul 01 10:39:38 AM PDT 24 Jul 01 10:39:45 AM PDT 24 171959729 ps
T591 /workspace/coverage/cover_reg_top/4.hmac_intr_test.1321212944 Jul 01 10:40:20 AM PDT 24 Jul 01 10:40:24 AM PDT 24 12741089 ps
T592 /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.770426333 Jul 01 10:39:38 AM PDT 24 Jul 01 10:40:56 AM PDT 24 6751044464 ps
T593 /workspace/coverage/cover_reg_top/46.hmac_intr_test.1827184792 Jul 01 10:39:55 AM PDT 24 Jul 01 10:39:56 AM PDT 24 163117418 ps
T594 /workspace/coverage/cover_reg_top/10.hmac_csr_rw.787430563 Jul 01 10:39:52 AM PDT 24 Jul 01 10:39:54 AM PDT 24 16805602 ps
T595 /workspace/coverage/cover_reg_top/19.hmac_intr_test.3568907985 Jul 01 10:39:43 AM PDT 24 Jul 01 10:39:49 AM PDT 24 20968376 ps
T596 /workspace/coverage/cover_reg_top/18.hmac_csr_rw.2560810522 Jul 01 10:39:36 AM PDT 24 Jul 01 10:39:40 AM PDT 24 31794320 ps
T597 /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.1417336879 Jul 01 10:39:31 AM PDT 24 Jul 01 10:39:35 AM PDT 24 39062382 ps
T598 /workspace/coverage/cover_reg_top/27.hmac_intr_test.1273392897 Jul 01 10:40:22 AM PDT 24 Jul 01 10:40:28 AM PDT 24 16075799 ps
T599 /workspace/coverage/cover_reg_top/30.hmac_intr_test.2996890944 Jul 01 10:40:33 AM PDT 24 Jul 01 10:40:36 AM PDT 24 61563504 ps
T111 /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.2740501586 Jul 01 10:39:34 AM PDT 24 Jul 01 10:39:46 AM PDT 24 855712225 ps
T600 /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.2794599790 Jul 01 10:39:35 AM PDT 24 Jul 01 10:39:41 AM PDT 24 163251380 ps
T601 /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.4214899347 Jul 01 10:40:10 AM PDT 24 Jul 01 10:40:13 AM PDT 24 524527146 ps
T602 /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.13872423 Jul 01 10:39:40 AM PDT 24 Jul 01 10:39:47 AM PDT 24 148267432 ps
T603 /workspace/coverage/cover_reg_top/15.hmac_tl_errors.2233117899 Jul 01 10:39:42 AM PDT 24 Jul 01 10:39:49 AM PDT 24 1804244171 ps
T604 /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.36614716 Jul 01 10:39:46 AM PDT 24 Jul 01 10:39:50 AM PDT 24 25232568 ps
T605 /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.2017459787 Jul 01 10:39:38 AM PDT 24 Jul 01 10:39:46 AM PDT 24 721477032 ps
T606 /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.977883616 Jul 01 10:39:46 AM PDT 24 Jul 01 10:39:51 AM PDT 24 84637344 ps
T607 /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.1187967654 Jul 01 10:39:25 AM PDT 24 Jul 01 10:39:28 AM PDT 24 226782301 ps
T608 /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.235238645 Jul 01 10:39:37 AM PDT 24 Jul 01 10:39:42 AM PDT 24 33686325 ps
T609 /workspace/coverage/cover_reg_top/16.hmac_tl_errors.2135565325 Jul 01 10:40:06 AM PDT 24 Jul 01 10:40:09 AM PDT 24 91706303 ps
T115 /workspace/coverage/cover_reg_top/9.hmac_csr_rw.2660269559 Jul 01 10:39:37 AM PDT 24 Jul 01 10:39:42 AM PDT 24 59278381 ps
T112 /workspace/coverage/cover_reg_top/15.hmac_csr_rw.2024266729 Jul 01 10:39:43 AM PDT 24 Jul 01 10:39:48 AM PDT 24 77993390 ps
T610 /workspace/coverage/cover_reg_top/7.hmac_tl_errors.1365572167 Jul 01 10:39:32 AM PDT 24 Jul 01 10:39:36 AM PDT 24 86563991 ps
T611 /workspace/coverage/cover_reg_top/13.hmac_tl_errors.46952032 Jul 01 10:39:38 AM PDT 24 Jul 01 10:39:49 AM PDT 24 178917314 ps
T612 /workspace/coverage/cover_reg_top/20.hmac_intr_test.2469597233 Jul 01 10:39:40 AM PDT 24 Jul 01 10:39:45 AM PDT 24 32856243 ps
T613 /workspace/coverage/cover_reg_top/17.hmac_intr_test.1173407812 Jul 01 10:39:39 AM PDT 24 Jul 01 10:39:44 AM PDT 24 52856478 ps
T614 /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.1730203535 Jul 01 10:39:57 AM PDT 24 Jul 01 10:40:02 AM PDT 24 992042749 ps
T615 /workspace/coverage/cover_reg_top/8.hmac_intr_test.437016035 Jul 01 10:39:29 AM PDT 24 Jul 01 10:39:31 AM PDT 24 14947029 ps
T113 /workspace/coverage/cover_reg_top/11.hmac_csr_rw.1004331583 Jul 01 10:39:28 AM PDT 24 Jul 01 10:39:30 AM PDT 24 34840305 ps
T616 /workspace/coverage/cover_reg_top/48.hmac_intr_test.275947206 Jul 01 10:39:50 AM PDT 24 Jul 01 10:39:53 AM PDT 24 37023404 ps
T617 /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.2933295819 Jul 01 10:39:58 AM PDT 24 Jul 01 10:40:00 AM PDT 24 32359913 ps
T618 /workspace/coverage/cover_reg_top/25.hmac_intr_test.4188994032 Jul 01 10:39:43 AM PDT 24 Jul 01 10:39:47 AM PDT 24 32805796 ps
T619 /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.399227948 Jul 01 10:39:57 AM PDT 24 Jul 01 10:39:59 AM PDT 24 125707968 ps
T620 /workspace/coverage/cover_reg_top/5.hmac_tl_errors.2731110071 Jul 01 10:39:34 AM PDT 24 Jul 01 10:39:39 AM PDT 24 67907593 ps
T621 /workspace/coverage/cover_reg_top/19.hmac_tl_errors.3704128536 Jul 01 10:39:48 AM PDT 24 Jul 01 10:39:52 AM PDT 24 67191989 ps
T622 /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.2081687927 Jul 01 10:40:04 AM PDT 24 Jul 01 10:40:09 AM PDT 24 304740478 ps
T623 /workspace/coverage/cover_reg_top/28.hmac_intr_test.1314133831 Jul 01 10:40:27 AM PDT 24 Jul 01 10:40:30 AM PDT 24 85609968 ps
T624 /workspace/coverage/cover_reg_top/21.hmac_intr_test.2309425717 Jul 01 10:39:51 AM PDT 24 Jul 01 10:39:53 AM PDT 24 40352969 ps
T625 /workspace/coverage/cover_reg_top/45.hmac_intr_test.1344753976 Jul 01 10:39:43 AM PDT 24 Jul 01 10:39:47 AM PDT 24 38341531 ps
T626 /workspace/coverage/cover_reg_top/37.hmac_intr_test.2186832569 Jul 01 10:40:12 AM PDT 24 Jul 01 10:40:15 AM PDT 24 13740754 ps
T114 /workspace/coverage/cover_reg_top/0.hmac_csr_rw.476014139 Jul 01 10:39:38 AM PDT 24 Jul 01 10:39:43 AM PDT 24 14107646 ps
T627 /workspace/coverage/cover_reg_top/43.hmac_intr_test.2721937076 Jul 01 10:40:23 AM PDT 24 Jul 01 10:40:26 AM PDT 24 17559411 ps
T628 /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.284896704 Jul 01 10:39:45 AM PDT 24 Jul 01 10:39:51 AM PDT 24 95514561 ps
T629 /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.4135891908 Jul 01 10:39:31 AM PDT 24 Jul 01 10:39:34 AM PDT 24 130136357 ps
T630 /workspace/coverage/cover_reg_top/9.hmac_tl_errors.47617303 Jul 01 10:39:37 AM PDT 24 Jul 01 10:39:42 AM PDT 24 48532251 ps
T631 /workspace/coverage/cover_reg_top/44.hmac_intr_test.4134987153 Jul 01 10:39:35 AM PDT 24 Jul 01 10:39:41 AM PDT 24 70753190 ps
T632 /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.3299898999 Jul 01 10:39:38 AM PDT 24 Jul 01 10:39:45 AM PDT 24 73714788 ps
T633 /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.1609608497 Jul 01 10:40:21 AM PDT 24 Jul 01 10:40:26 AM PDT 24 107371817 ps
T634 /workspace/coverage/cover_reg_top/47.hmac_intr_test.450510886 Jul 01 10:40:30 AM PDT 24 Jul 01 10:40:32 AM PDT 24 23301056 ps
T635 /workspace/coverage/cover_reg_top/17.hmac_tl_errors.2748388445 Jul 01 10:39:46 AM PDT 24 Jul 01 10:39:51 AM PDT 24 623052042 ps
T636 /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.3767793986 Jul 01 10:39:36 AM PDT 24 Jul 01 10:39:42 AM PDT 24 111504511 ps
T637 /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.3773668771 Jul 01 10:39:39 AM PDT 24 Jul 01 10:39:46 AM PDT 24 475198015 ps
T638 /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.4220192016 Jul 01 10:39:34 AM PDT 24 Jul 01 10:39:39 AM PDT 24 60708980 ps
T639 /workspace/coverage/cover_reg_top/24.hmac_intr_test.2839556491 Jul 01 10:39:43 AM PDT 24 Jul 01 10:39:47 AM PDT 24 35649097 ps
T116 /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.475317880 Jul 01 10:40:09 AM PDT 24 Jul 01 10:40:18 AM PDT 24 1847940252 ps
T640 /workspace/coverage/cover_reg_top/16.hmac_intr_test.691405043 Jul 01 10:39:36 AM PDT 24 Jul 01 10:39:41 AM PDT 24 32675209 ps
T641 /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.1566443816 Jul 01 10:39:37 AM PDT 24 Jul 01 10:39:44 AM PDT 24 416888579 ps
T642 /workspace/coverage/cover_reg_top/12.hmac_tl_errors.3699861893 Jul 01 10:39:42 AM PDT 24 Jul 01 10:39:48 AM PDT 24 97366332 ps
T643 /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.3346893625 Jul 01 10:40:07 AM PDT 24 Jul 01 10:40:19 AM PDT 24 5556625631 ps
T644 /workspace/coverage/cover_reg_top/2.hmac_csr_rw.2816960010 Jul 01 10:39:39 AM PDT 24 Jul 01 10:39:49 AM PDT 24 57210910 ps
T645 /workspace/coverage/cover_reg_top/36.hmac_intr_test.1968102860 Jul 01 10:39:51 AM PDT 24 Jul 01 10:39:53 AM PDT 24 10989541 ps
T646 /workspace/coverage/cover_reg_top/5.hmac_intr_test.3884195809 Jul 01 10:39:37 AM PDT 24 Jul 01 10:39:42 AM PDT 24 31486429 ps
T647 /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.3136074894 Jul 01 10:39:33 AM PDT 24 Jul 01 10:39:38 AM PDT 24 101772749 ps
T648 /workspace/coverage/cover_reg_top/1.hmac_csr_rw.3109368394 Jul 01 10:39:34 AM PDT 24 Jul 01 10:39:38 AM PDT 24 37101700 ps
T649 /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.4077830482 Jul 01 10:39:36 AM PDT 24 Jul 01 10:39:44 AM PDT 24 303440430 ps
T650 /workspace/coverage/cover_reg_top/7.hmac_csr_rw.1811225798 Jul 01 10:39:36 AM PDT 24 Jul 01 10:39:41 AM PDT 24 103317026 ps
T651 /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.2797892375 Jul 01 10:39:34 AM PDT 24 Jul 01 10:39:43 AM PDT 24 106885834 ps
T652 /workspace/coverage/cover_reg_top/49.hmac_intr_test.2067333957 Jul 01 10:40:09 AM PDT 24 Jul 01 10:40:12 AM PDT 24 17923737 ps
T653 /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.496768766 Jul 01 10:40:04 AM PDT 24 Jul 01 10:40:20 AM PDT 24 620529346 ps
T654 /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.4056205801 Jul 01 10:40:14 AM PDT 24 Jul 01 10:40:24 AM PDT 24 100799689 ps
T655 /workspace/coverage/cover_reg_top/10.hmac_tl_errors.1165451584 Jul 01 10:39:37 AM PDT 24 Jul 01 10:39:44 AM PDT 24 420911570 ps
T656 /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.709325040 Jul 01 10:39:29 AM PDT 24 Jul 01 10:39:32 AM PDT 24 96087034 ps
T657 /workspace/coverage/cover_reg_top/14.hmac_csr_rw.294391961 Jul 01 10:39:49 AM PDT 24 Jul 01 10:39:52 AM PDT 24 35388193 ps
T128 /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.2179504066 Jul 01 10:40:02 AM PDT 24 Jul 01 10:40:07 AM PDT 24 479340191 ps
T658 /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.2863806919 Jul 01 10:39:41 AM PDT 24 Jul 01 10:39:50 AM PDT 24 1922234712 ps
T659 /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.4117866922 Jul 01 10:39:41 AM PDT 24 Jul 01 10:39:47 AM PDT 24 410103612 ps

Test location /workspace/coverage/default/5.hmac_smoke.3794133566
Short name T4
Test name
Test status
Simulation time 928471455 ps
CPU time 15.48 seconds
Started Jul 01 10:40:43 AM PDT 24
Finished Jul 01 10:41:00 AM PDT 24
Peak memory 200232 kb
Host smart-4cf090f5-cf7d-45b8-80b1-d0405a51f0fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3794133566 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_smoke.3794133566
Directory /workspace/5.hmac_smoke/latest

Test location /workspace/coverage/default/44.hmac_stress_all.1261484932
Short name T20
Test name
Test status
Simulation time 39981904282 ps
CPU time 1345.99 seconds
Started Jul 01 10:41:39 AM PDT 24
Finished Jul 01 11:04:06 AM PDT 24
Peak memory 670864 kb
Host smart-de17b019-1d4d-4af7-99bd-cdd4704c02a6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261484932 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.hmac_stress_all.1261484932
Directory /workspace/44.hmac_stress_all/latest

Test location /workspace/coverage/default/8.hmac_stress_all_with_rand_reset.2901761012
Short name T22
Test name
Test status
Simulation time 212489350715 ps
CPU time 5388.15 seconds
Started Jul 01 10:41:01 AM PDT 24
Finished Jul 01 12:10:50 PM PDT 24
Peak memory 841396 kb
Host smart-cc094db6-bfd1-42df-86f9-f249ba8019f4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2901761012 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all_with_rand_reset.2901761012
Directory /workspace/8.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.hmac_stress_all.1262710056
Short name T13
Test name
Test status
Simulation time 32814162060 ps
CPU time 437.64 seconds
Started Jul 01 10:41:10 AM PDT 24
Finished Jul 01 10:48:28 AM PDT 24
Peak memory 200324 kb
Host smart-23ca42f1-7572-4202-b392-0bb27a1b4dc2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262710056 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.hmac_stress_all.1262710056
Directory /workspace/28.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.2095172301
Short name T56
Test name
Test status
Simulation time 235293144 ps
CPU time 3.85 seconds
Started Jul 01 10:39:38 AM PDT 24
Finished Jul 01 10:39:46 AM PDT 24
Peak memory 199416 kb
Host smart-deffb898-41e9-4bbd-8d7c-6c494141e5af
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095172301 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_intg_err.2095172301
Directory /workspace/19.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/9.hmac_stress_all_with_rand_reset.3668264115
Short name T9
Test name
Test status
Simulation time 115293123704 ps
CPU time 9268.61 seconds
Started Jul 01 10:41:10 AM PDT 24
Finished Jul 01 01:15:41 PM PDT 24
Peak memory 930312 kb
Host smart-eca6d652-78d8-4c18-9b09-5ede21bcb90d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3668264115 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all_with_rand_reset.3668264115
Directory /workspace/9.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.hmac_sec_cm.3759737890
Short name T42
Test name
Test status
Simulation time 33118963 ps
CPU time 0.78 seconds
Started Jul 01 10:40:43 AM PDT 24
Finished Jul 01 10:40:45 AM PDT 24
Peak memory 218772 kb
Host smart-533bc10d-f44c-4644-9135-d4c73b2ae026
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759737890 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_sec_cm.3759737890
Directory /workspace/0.hmac_sec_cm/latest

Test location /workspace/coverage/default/46.hmac_stress_all.1335905218
Short name T72
Test name
Test status
Simulation time 83851735364 ps
CPU time 1818.44 seconds
Started Jul 01 10:41:25 AM PDT 24
Finished Jul 01 11:11:45 AM PDT 24
Peak memory 724060 kb
Host smart-6a881a52-23e6-4472-bded-9337a655da00
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335905218 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.hmac_stress_all.1335905218
Directory /workspace/46.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_rw.2996054691
Short name T104
Test name
Test status
Simulation time 31876223 ps
CPU time 0.92 seconds
Started Jul 01 10:39:51 AM PDT 24
Finished Jul 01 10:39:53 AM PDT 24
Peak memory 198624 kb
Host smart-7d38979f-7d7d-4c15-88a5-a7be830f029a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996054691 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_rw.2996054691
Directory /workspace/17.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.3930175080
Short name T130
Test name
Test status
Simulation time 166502086 ps
CPU time 4.07 seconds
Started Jul 01 10:40:17 AM PDT 24
Finished Jul 01 10:40:24 AM PDT 24
Peak memory 199416 kb
Host smart-33133262-7777-48a0-8804-7a49301ba27d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930175080 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_intg_err.3930175080
Directory /workspace/17.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/13.hmac_alert_test.651762701
Short name T177
Test name
Test status
Simulation time 15327142 ps
CPU time 0.63 seconds
Started Jul 01 10:40:54 AM PDT 24
Finished Jul 01 10:40:56 AM PDT 24
Peak memory 196736 kb
Host smart-661ddfdf-ecec-4efe-9cc6-68e03b5707a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651762701 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_alert_test.651762701
Directory /workspace/13.hmac_alert_test/latest

Test location /workspace/coverage/default/33.hmac_stress_all.2890285239
Short name T29
Test name
Test status
Simulation time 366307248464 ps
CPU time 967.07 seconds
Started Jul 01 10:41:22 AM PDT 24
Finished Jul 01 10:57:31 AM PDT 24
Peak memory 694024 kb
Host smart-7e567302-e5ea-41d9-affc-8b40b63d4358
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890285239 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.hmac_stress_all.2890285239
Directory /workspace/33.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.2179504066
Short name T128
Test name
Test status
Simulation time 479340191 ps
CPU time 3.88 seconds
Started Jul 01 10:40:02 AM PDT 24
Finished Jul 01 10:40:07 AM PDT 24
Peak memory 199440 kb
Host smart-5cd5d4c3-f719-4df2-90a9-a4843aaaab2f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179504066 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_intg_err.2179504066
Directory /workspace/1.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.2048090093
Short name T59
Test name
Test status
Simulation time 196053706 ps
CPU time 3.18 seconds
Started Jul 01 10:39:34 AM PDT 24
Finished Jul 01 10:39:40 AM PDT 24
Peak memory 199408 kb
Host smart-47b0fbd9-721f-4066-9717-8c78e60775af
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048090093 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_intg_err.2048090093
Directory /workspace/10.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/2.hmac_stress_all_with_rand_reset.1278771993
Short name T16
Test name
Test status
Simulation time 647792098772 ps
CPU time 1794.32 seconds
Started Jul 01 10:41:02 AM PDT 24
Finished Jul 01 11:10:57 AM PDT 24
Peak memory 645252 kb
Host smart-6e00dbe2-9657-40e0-aec4-7c6ab3579b29
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1278771993 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all_with_rand_reset.1278771993
Directory /workspace/2.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.986785205
Short name T552
Test name
Test status
Simulation time 319776093 ps
CPU time 8.25 seconds
Started Jul 01 10:40:08 AM PDT 24
Finished Jul 01 10:40:17 AM PDT 24
Peak memory 199340 kb
Host smart-37601269-fce3-4d7d-852e-a9016c5b0caa
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986785205 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_aliasing.986785205
Directory /workspace/0.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.1072521735
Short name T108
Test name
Test status
Simulation time 1232020000 ps
CPU time 13.89 seconds
Started Jul 01 10:39:39 AM PDT 24
Finished Jul 01 10:39:57 AM PDT 24
Peak memory 198460 kb
Host smart-6be615dc-659c-48ea-8e4c-0ad899fc3968
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072521735 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_bit_bash.1072521735
Directory /workspace/0.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.235238645
Short name T608
Test name
Test status
Simulation time 33686325 ps
CPU time 0.98 seconds
Started Jul 01 10:39:37 AM PDT 24
Finished Jul 01 10:39:42 AM PDT 24
Peak memory 199316 kb
Host smart-aa221c3e-a62a-4a91-9a8b-b8929cf48e8a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235238645 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_hw_reset.235238645
Directory /workspace/0.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.770426333
Short name T592
Test name
Test status
Simulation time 6751044464 ps
CPU time 73.47 seconds
Started Jul 01 10:39:38 AM PDT 24
Finished Jul 01 10:40:56 AM PDT 24
Peak memory 215716 kb
Host smart-006fa8a0-b94e-4f6e-a81f-33b417de1024
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770426333 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.hmac_csr_mem_rw_with_rand_reset.770426333
Directory /workspace/0.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_rw.476014139
Short name T114
Test name
Test status
Simulation time 14107646 ps
CPU time 0.79 seconds
Started Jul 01 10:39:38 AM PDT 24
Finished Jul 01 10:39:43 AM PDT 24
Peak memory 199044 kb
Host smart-fbd7c1b9-966f-4a24-96ba-bb2bd7c26a1f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476014139 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_rw.476014139
Directory /workspace/0.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_intr_test.1008566217
Short name T579
Test name
Test status
Simulation time 36231793 ps
CPU time 0.57 seconds
Started Jul 01 10:39:34 AM PDT 24
Finished Jul 01 10:39:38 AM PDT 24
Peak memory 193992 kb
Host smart-ef39a5eb-392f-493b-92bd-254b4bee1809
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008566217 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_intr_test.1008566217
Directory /workspace/0.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.1609608497
Short name T633
Test name
Test status
Simulation time 107371817 ps
CPU time 1.8 seconds
Started Jul 01 10:40:21 AM PDT 24
Finished Jul 01 10:40:26 AM PDT 24
Peak memory 199176 kb
Host smart-30b7871c-4f0f-4030-a2a7-fca3ca8ca0c7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609608497 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_same_csr
_outstanding.1609608497
Directory /workspace/0.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_errors.2558328742
Short name T557
Test name
Test status
Simulation time 128770520 ps
CPU time 1.84 seconds
Started Jul 01 10:39:34 AM PDT 24
Finished Jul 01 10:39:38 AM PDT 24
Peak memory 199416 kb
Host smart-03d94f85-bde8-4225-8ae0-818e317e8c4c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558328742 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_errors.2558328742
Directory /workspace/0.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.852604861
Short name T57
Test name
Test status
Simulation time 345328290 ps
CPU time 2.92 seconds
Started Jul 01 10:39:39 AM PDT 24
Finished Jul 01 10:39:47 AM PDT 24
Peak memory 199484 kb
Host smart-dd2d57d1-63bc-4cf4-aea9-f05fc1b5af02
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852604861 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_intg_err.852604861
Directory /workspace/0.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.2740501586
Short name T111
Test name
Test status
Simulation time 855712225 ps
CPU time 8.86 seconds
Started Jul 01 10:39:34 AM PDT 24
Finished Jul 01 10:39:46 AM PDT 24
Peak memory 199116 kb
Host smart-8dd7c483-5fba-48c5-9e70-de8acc7f23ca
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740501586 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_aliasing.2740501586
Directory /workspace/1.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.496768766
Short name T653
Test name
Test status
Simulation time 620529346 ps
CPU time 14.37 seconds
Started Jul 01 10:40:04 AM PDT 24
Finished Jul 01 10:40:20 AM PDT 24
Peak memory 199224 kb
Host smart-f436b1c3-16ff-445a-bf13-14e146db4195
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496768766 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_bit_bash.496768766
Directory /workspace/1.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.875288172
Short name T559
Test name
Test status
Simulation time 213273188 ps
CPU time 0.72 seconds
Started Jul 01 10:39:36 AM PDT 24
Finished Jul 01 10:39:41 AM PDT 24
Peak memory 197324 kb
Host smart-e3d2b203-b5df-4e26-9021-9b926942ef3a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875288172 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_hw_reset.875288172
Directory /workspace/1.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.709325040
Short name T656
Test name
Test status
Simulation time 96087034 ps
CPU time 1.8 seconds
Started Jul 01 10:39:29 AM PDT 24
Finished Jul 01 10:39:32 AM PDT 24
Peak memory 199476 kb
Host smart-7a6d17bb-a152-40a7-b255-0aeca0bcbfb2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709325040 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.hmac_csr_mem_rw_with_rand_reset.709325040
Directory /workspace/1.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_rw.3109368394
Short name T648
Test name
Test status
Simulation time 37101700 ps
CPU time 0.92 seconds
Started Jul 01 10:39:34 AM PDT 24
Finished Jul 01 10:39:38 AM PDT 24
Peak memory 198720 kb
Host smart-c95d9480-dfbd-4765-b616-961ba8740e29
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109368394 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_rw.3109368394
Directory /workspace/1.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_intr_test.3046820900
Short name T560
Test name
Test status
Simulation time 14870362 ps
CPU time 0.59 seconds
Started Jul 01 10:40:01 AM PDT 24
Finished Jul 01 10:40:02 AM PDT 24
Peak memory 194488 kb
Host smart-1370ed31-7678-4f33-9d3b-f84d0025e3aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046820900 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_intr_test.3046820900
Directory /workspace/1.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.1992948814
Short name T574
Test name
Test status
Simulation time 97244202 ps
CPU time 1.67 seconds
Started Jul 01 10:39:38 AM PDT 24
Finished Jul 01 10:39:45 AM PDT 24
Peak memory 199416 kb
Host smart-810f02c4-403f-4bdb-9804-e6a7507953c8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992948814 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_same_csr
_outstanding.1992948814
Directory /workspace/1.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_errors.3962278905
Short name T538
Test name
Test status
Simulation time 31691461 ps
CPU time 1.53 seconds
Started Jul 01 10:39:39 AM PDT 24
Finished Jul 01 10:39:45 AM PDT 24
Peak memory 199500 kb
Host smart-a830dc29-771c-4a9f-9065-3b6f2a5f2a10
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962278905 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_errors.3962278905
Directory /workspace/1.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.4135891908
Short name T629
Test name
Test status
Simulation time 130136357 ps
CPU time 1.13 seconds
Started Jul 01 10:39:31 AM PDT 24
Finished Jul 01 10:39:34 AM PDT 24
Peak memory 199336 kb
Host smart-7b8a7a89-4acf-4fea-8a20-3c3e3f0551e5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135891908 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.hmac_csr_mem_rw_with_rand_reset.4135891908
Directory /workspace/10.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_rw.787430563
Short name T594
Test name
Test status
Simulation time 16805602 ps
CPU time 0.68 seconds
Started Jul 01 10:39:52 AM PDT 24
Finished Jul 01 10:39:54 AM PDT 24
Peak memory 197300 kb
Host smart-3dd16d3f-bf54-4013-8888-6a7c51116b3d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787430563 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_rw.787430563
Directory /workspace/10.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_intr_test.3171944759
Short name T547
Test name
Test status
Simulation time 45618120 ps
CPU time 0.59 seconds
Started Jul 01 10:40:05 AM PDT 24
Finished Jul 01 10:40:07 AM PDT 24
Peak memory 194328 kb
Host smart-c2eeba3b-912d-4bfd-ba28-39a1ecb50f66
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171944759 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_intr_test.3171944759
Directory /workspace/10.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.364701901
Short name T120
Test name
Test status
Simulation time 296980800 ps
CPU time 2.46 seconds
Started Jul 01 10:39:36 AM PDT 24
Finished Jul 01 10:39:43 AM PDT 24
Peak memory 199368 kb
Host smart-0969f15a-7b10-43a5-bb15-2dfb3f05eb27
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364701901 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_same_csr
_outstanding.364701901
Directory /workspace/10.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_errors.1165451584
Short name T655
Test name
Test status
Simulation time 420911570 ps
CPU time 2.16 seconds
Started Jul 01 10:39:37 AM PDT 24
Finished Jul 01 10:39:44 AM PDT 24
Peak memory 199416 kb
Host smart-496e8f7d-62a1-4c8b-9201-a44be8540a02
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165451584 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_errors.1165451584
Directory /workspace/10.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.74483328
Short name T563
Test name
Test status
Simulation time 38410533 ps
CPU time 2.51 seconds
Started Jul 01 10:39:30 AM PDT 24
Finished Jul 01 10:39:34 AM PDT 24
Peak memory 199536 kb
Host smart-cf17356c-2753-43c3-8541-6109a3e430ef
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74483328 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 11.hmac_csr_mem_rw_with_rand_reset.74483328
Directory /workspace/11.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_rw.1004331583
Short name T113
Test name
Test status
Simulation time 34840305 ps
CPU time 0.95 seconds
Started Jul 01 10:39:28 AM PDT 24
Finished Jul 01 10:39:30 AM PDT 24
Peak memory 199092 kb
Host smart-22de841a-b0a9-4840-939c-76d027d461f5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004331583 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_rw.1004331583
Directory /workspace/11.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_intr_test.1891775798
Short name T539
Test name
Test status
Simulation time 31208918 ps
CPU time 0.61 seconds
Started Jul 01 10:39:38 AM PDT 24
Finished Jul 01 10:39:44 AM PDT 24
Peak memory 194548 kb
Host smart-0714b7a8-ae87-44ea-9d3b-a00199b9e3a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891775798 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_intr_test.1891775798
Directory /workspace/11.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.3753761782
Short name T564
Test name
Test status
Simulation time 64041461 ps
CPU time 1.54 seconds
Started Jul 01 10:39:35 AM PDT 24
Finished Jul 01 10:39:40 AM PDT 24
Peak memory 199392 kb
Host smart-0e59da88-5d3f-446c-adf5-df2e14eeaec4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753761782 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_same_cs
r_outstanding.3753761782
Directory /workspace/11.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_errors.4101453400
Short name T548
Test name
Test status
Simulation time 411718754 ps
CPU time 4.06 seconds
Started Jul 01 10:39:44 AM PDT 24
Finished Jul 01 10:39:51 AM PDT 24
Peak memory 199488 kb
Host smart-64391ed7-5194-404e-bbe6-b1093b28166a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101453400 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_errors.4101453400
Directory /workspace/11.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.4120884368
Short name T132
Test name
Test status
Simulation time 862546981 ps
CPU time 3.15 seconds
Started Jul 01 10:39:33 AM PDT 24
Finished Jul 01 10:39:39 AM PDT 24
Peak memory 199364 kb
Host smart-b3fef642-3698-42d9-a818-2c84700b1989
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120884368 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_intg_err.4120884368
Directory /workspace/11.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.3299898999
Short name T632
Test name
Test status
Simulation time 73714788 ps
CPU time 1.78 seconds
Started Jul 01 10:39:38 AM PDT 24
Finished Jul 01 10:39:45 AM PDT 24
Peak memory 199392 kb
Host smart-df6e7041-e407-4129-9f5d-2ce5239d40bd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299898999 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.hmac_csr_mem_rw_with_rand_reset.3299898999
Directory /workspace/12.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_rw.3924422635
Short name T568
Test name
Test status
Simulation time 95027587 ps
CPU time 0.66 seconds
Started Jul 01 10:39:52 AM PDT 24
Finished Jul 01 10:39:54 AM PDT 24
Peak memory 197344 kb
Host smart-4a10a69f-4ca7-49a8-a63e-d6cbafe7687a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924422635 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_rw.3924422635
Directory /workspace/12.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_intr_test.2193766346
Short name T588
Test name
Test status
Simulation time 40283379 ps
CPU time 0.6 seconds
Started Jul 01 10:39:38 AM PDT 24
Finished Jul 01 10:39:43 AM PDT 24
Peak memory 194504 kb
Host smart-aac2a753-0d54-4353-b268-7abecb50e10e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193766346 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_intr_test.2193766346
Directory /workspace/12.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.1466608253
Short name T561
Test name
Test status
Simulation time 68648992 ps
CPU time 1.52 seconds
Started Jul 01 10:39:34 AM PDT 24
Finished Jul 01 10:39:39 AM PDT 24
Peak memory 199368 kb
Host smart-dbc95d9c-4da3-4f08-bf01-dd9d2cea3583
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466608253 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_same_cs
r_outstanding.1466608253
Directory /workspace/12.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_errors.3699861893
Short name T642
Test name
Test status
Simulation time 97366332 ps
CPU time 1.89 seconds
Started Jul 01 10:39:42 AM PDT 24
Finished Jul 01 10:39:48 AM PDT 24
Peak memory 199440 kb
Host smart-008bb8ef-22b2-45da-866b-526582b4ec52
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699861893 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_errors.3699861893
Directory /workspace/12.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.1805122952
Short name T127
Test name
Test status
Simulation time 806890857 ps
CPU time 4.29 seconds
Started Jul 01 10:39:41 AM PDT 24
Finished Jul 01 10:39:50 AM PDT 24
Peak memory 199412 kb
Host smart-879d6b75-8fa0-4e15-96c8-c8109dcf8191
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805122952 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_intg_err.1805122952
Directory /workspace/12.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.3082508173
Short name T556
Test name
Test status
Simulation time 101313556 ps
CPU time 2.32 seconds
Started Jul 01 10:39:43 AM PDT 24
Finished Jul 01 10:39:49 AM PDT 24
Peak memory 199544 kb
Host smart-ec988d1c-262b-4e09-8a8f-04b6eee72843
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082508173 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.hmac_csr_mem_rw_with_rand_reset.3082508173
Directory /workspace/13.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_rw.3742931239
Short name T101
Test name
Test status
Simulation time 20821101 ps
CPU time 0.73 seconds
Started Jul 01 10:39:36 AM PDT 24
Finished Jul 01 10:39:44 AM PDT 24
Peak memory 197848 kb
Host smart-37fbe780-f2f3-4b76-a945-80b937519bf8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742931239 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_rw.3742931239
Directory /workspace/13.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_intr_test.2510121801
Short name T581
Test name
Test status
Simulation time 26783086 ps
CPU time 0.61 seconds
Started Jul 01 10:39:30 AM PDT 24
Finished Jul 01 10:39:33 AM PDT 24
Peak memory 194404 kb
Host smart-b90763af-7192-4fa6-b493-a97c6d00f397
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510121801 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_intr_test.2510121801
Directory /workspace/13.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.13872423
Short name T602
Test name
Test status
Simulation time 148267432 ps
CPU time 2.12 seconds
Started Jul 01 10:39:40 AM PDT 24
Finished Jul 01 10:39:47 AM PDT 24
Peak memory 199452 kb
Host smart-4b8d2168-6d25-4622-8d76-14e64b4c2f13
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13872423 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_same_csr_
outstanding.13872423
Directory /workspace/13.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_errors.46952032
Short name T611
Test name
Test status
Simulation time 178917314 ps
CPU time 2.24 seconds
Started Jul 01 10:39:38 AM PDT 24
Finished Jul 01 10:39:49 AM PDT 24
Peak memory 199412 kb
Host smart-7bd4ecc0-acb0-41a1-9387-c719a0a0f7b9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46952032 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_errors.46952032
Directory /workspace/13.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.2863806919
Short name T658
Test name
Test status
Simulation time 1922234712 ps
CPU time 3.98 seconds
Started Jul 01 10:39:41 AM PDT 24
Finished Jul 01 10:39:50 AM PDT 24
Peak memory 199392 kb
Host smart-27556c57-e86b-4900-8fd7-1a2337f13c85
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863806919 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_intg_err.2863806919
Directory /workspace/13.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.2717463292
Short name T589
Test name
Test status
Simulation time 194446578 ps
CPU time 3.42 seconds
Started Jul 01 10:39:34 AM PDT 24
Finished Jul 01 10:39:40 AM PDT 24
Peak memory 214972 kb
Host smart-530437b7-e699-4732-b4c8-680842cef84f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717463292 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.hmac_csr_mem_rw_with_rand_reset.2717463292
Directory /workspace/14.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_rw.294391961
Short name T657
Test name
Test status
Simulation time 35388193 ps
CPU time 0.72 seconds
Started Jul 01 10:39:49 AM PDT 24
Finished Jul 01 10:39:52 AM PDT 24
Peak memory 197400 kb
Host smart-5ec26acc-6df3-4eb6-8da6-973ede797f3e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294391961 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_rw.294391961
Directory /workspace/14.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_intr_test.3975588217
Short name T545
Test name
Test status
Simulation time 50360061 ps
CPU time 0.58 seconds
Started Jul 01 10:39:45 AM PDT 24
Finished Jul 01 10:39:48 AM PDT 24
Peak memory 194260 kb
Host smart-46de225e-22e2-4379-888f-1a773e42cb63
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975588217 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_intr_test.3975588217
Directory /workspace/14.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.3269117312
Short name T78
Test name
Test status
Simulation time 611194116 ps
CPU time 2.49 seconds
Started Jul 01 10:39:37 AM PDT 24
Finished Jul 01 10:39:44 AM PDT 24
Peak memory 199368 kb
Host smart-24f969ff-3cf8-4693-b92e-08fcba89aa48
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269117312 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_same_cs
r_outstanding.3269117312
Directory /workspace/14.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_errors.2086572384
Short name T544
Test name
Test status
Simulation time 58113047 ps
CPU time 1.36 seconds
Started Jul 01 10:39:54 AM PDT 24
Finished Jul 01 10:39:56 AM PDT 24
Peak memory 199484 kb
Host smart-3a12f059-cd20-4ce3-a79b-3d5a110e282e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086572384 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_errors.2086572384
Directory /workspace/14.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.2368264701
Short name T58
Test name
Test status
Simulation time 639758171 ps
CPU time 3.13 seconds
Started Jul 01 10:39:43 AM PDT 24
Finished Jul 01 10:39:50 AM PDT 24
Peak memory 199432 kb
Host smart-43c2dc8b-0d16-4ac9-acb5-732e7a672cbb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368264701 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_intg_err.2368264701
Directory /workspace/14.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.3767793986
Short name T636
Test name
Test status
Simulation time 111504511 ps
CPU time 1.67 seconds
Started Jul 01 10:39:36 AM PDT 24
Finished Jul 01 10:39:42 AM PDT 24
Peak memory 199492 kb
Host smart-281094e7-0fd7-49a4-b7dd-ee3b003cc93a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767793986 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.hmac_csr_mem_rw_with_rand_reset.3767793986
Directory /workspace/15.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_rw.2024266729
Short name T112
Test name
Test status
Simulation time 77993390 ps
CPU time 0.82 seconds
Started Jul 01 10:39:43 AM PDT 24
Finished Jul 01 10:39:48 AM PDT 24
Peak memory 199292 kb
Host smart-776d7794-ae26-4d7e-b9b6-ce851b1eb858
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024266729 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_rw.2024266729
Directory /workspace/15.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_intr_test.2571248004
Short name T533
Test name
Test status
Simulation time 13405800 ps
CPU time 0.61 seconds
Started Jul 01 10:40:03 AM PDT 24
Finished Jul 01 10:40:04 AM PDT 24
Peak memory 194484 kb
Host smart-767a53a1-157c-4934-8c58-6b5c03a37e56
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571248004 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_intr_test.2571248004
Directory /workspace/15.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.1011685749
Short name T123
Test name
Test status
Simulation time 214251638 ps
CPU time 1.15 seconds
Started Jul 01 10:39:50 AM PDT 24
Finished Jul 01 10:39:53 AM PDT 24
Peak memory 198120 kb
Host smart-7e409240-fc11-4ad2-98a8-91403fe59f83
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011685749 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_same_cs
r_outstanding.1011685749
Directory /workspace/15.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_errors.2233117899
Short name T603
Test name
Test status
Simulation time 1804244171 ps
CPU time 3.17 seconds
Started Jul 01 10:39:42 AM PDT 24
Finished Jul 01 10:39:49 AM PDT 24
Peak memory 199396 kb
Host smart-e242bf51-e74c-4048-b578-74300b3fe476
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233117899 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_errors.2233117899
Directory /workspace/15.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.2081687927
Short name T622
Test name
Test status
Simulation time 304740478 ps
CPU time 3.17 seconds
Started Jul 01 10:40:04 AM PDT 24
Finished Jul 01 10:40:09 AM PDT 24
Peak memory 199384 kb
Host smart-fe267368-4547-4e08-8acd-d0cb76f95226
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081687927 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_intg_err.2081687927
Directory /workspace/15.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.1628800675
Short name T590
Test name
Test status
Simulation time 171959729 ps
CPU time 2.65 seconds
Started Jul 01 10:39:38 AM PDT 24
Finished Jul 01 10:39:45 AM PDT 24
Peak memory 207660 kb
Host smart-ce12bd2c-97f6-42ae-aaf5-1b7a6571a184
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628800675 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.hmac_csr_mem_rw_with_rand_reset.1628800675
Directory /workspace/16.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_rw.2017239405
Short name T117
Test name
Test status
Simulation time 41662817 ps
CPU time 0.75 seconds
Started Jul 01 10:39:44 AM PDT 24
Finished Jul 01 10:39:52 AM PDT 24
Peak memory 197412 kb
Host smart-e794a369-5954-4399-9e37-762edd587828
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017239405 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_rw.2017239405
Directory /workspace/16.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_intr_test.691405043
Short name T640
Test name
Test status
Simulation time 32675209 ps
CPU time 0.62 seconds
Started Jul 01 10:39:36 AM PDT 24
Finished Jul 01 10:39:41 AM PDT 24
Peak memory 194484 kb
Host smart-e9abb985-b3d3-4d4d-9cb1-471be583d9dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691405043 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_intr_test.691405043
Directory /workspace/16.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.110402651
Short name T118
Test name
Test status
Simulation time 197909120 ps
CPU time 1.17 seconds
Started Jul 01 10:39:45 AM PDT 24
Finished Jul 01 10:39:49 AM PDT 24
Peak memory 199004 kb
Host smart-0c2bce55-2467-490e-8ea6-ad0b74e2a534
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110402651 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_same_csr
_outstanding.110402651
Directory /workspace/16.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_errors.2135565325
Short name T609
Test name
Test status
Simulation time 91706303 ps
CPU time 2.07 seconds
Started Jul 01 10:40:06 AM PDT 24
Finished Jul 01 10:40:09 AM PDT 24
Peak memory 199376 kb
Host smart-2e9804c6-7ab4-4633-bad5-485c492683a9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135565325 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_errors.2135565325
Directory /workspace/16.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.3478540606
Short name T126
Test name
Test status
Simulation time 540996328 ps
CPU time 4.01 seconds
Started Jul 01 10:39:38 AM PDT 24
Finished Jul 01 10:39:47 AM PDT 24
Peak memory 199424 kb
Host smart-7103f7c4-55e0-4465-ad14-9eaf0a5486ed
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478540606 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_intg_err.3478540606
Directory /workspace/16.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.36614716
Short name T604
Test name
Test status
Simulation time 25232568 ps
CPU time 1.59 seconds
Started Jul 01 10:39:46 AM PDT 24
Finished Jul 01 10:39:50 AM PDT 24
Peak memory 199528 kb
Host smart-4eaf13b9-c365-4e30-af4d-5f93f356623c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36614716 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.hmac_csr_mem_rw_with_rand_reset.36614716
Directory /workspace/17.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_intr_test.1173407812
Short name T613
Test name
Test status
Simulation time 52856478 ps
CPU time 0.58 seconds
Started Jul 01 10:39:39 AM PDT 24
Finished Jul 01 10:39:44 AM PDT 24
Peak memory 194340 kb
Host smart-4ea5c421-9649-4b5a-b063-db74ad67a470
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173407812 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_intr_test.1173407812
Directory /workspace/17.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.4117866922
Short name T659
Test name
Test status
Simulation time 410103612 ps
CPU time 2.17 seconds
Started Jul 01 10:39:41 AM PDT 24
Finished Jul 01 10:39:47 AM PDT 24
Peak memory 199380 kb
Host smart-5728cb81-6c6e-4e59-b07f-f753aefaa8fa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117866922 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_same_cs
r_outstanding.4117866922
Directory /workspace/17.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_errors.2748388445
Short name T635
Test name
Test status
Simulation time 623052042 ps
CPU time 2.82 seconds
Started Jul 01 10:39:46 AM PDT 24
Finished Jul 01 10:39:51 AM PDT 24
Peak memory 199404 kb
Host smart-3a8464ed-dd05-4d43-9cf8-720ed3348a12
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748388445 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_errors.2748388445
Directory /workspace/17.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.672373239
Short name T578
Test name
Test status
Simulation time 27891115927 ps
CPU time 216.92 seconds
Started Jul 01 10:40:11 AM PDT 24
Finished Jul 01 10:43:50 AM PDT 24
Peak memory 215508 kb
Host smart-15cd294d-734f-4492-87db-c9530aabf19e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672373239 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.hmac_csr_mem_rw_with_rand_reset.672373239
Directory /workspace/18.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_rw.2560810522
Short name T596
Test name
Test status
Simulation time 31794320 ps
CPU time 0.91 seconds
Started Jul 01 10:39:36 AM PDT 24
Finished Jul 01 10:39:40 AM PDT 24
Peak memory 198976 kb
Host smart-a23c857f-ba1e-4730-8202-b4d34ebf5469
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560810522 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_rw.2560810522
Directory /workspace/18.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_intr_test.2431339316
Short name T566
Test name
Test status
Simulation time 85531448 ps
CPU time 0.6 seconds
Started Jul 01 10:39:47 AM PDT 24
Finished Jul 01 10:39:50 AM PDT 24
Peak memory 194468 kb
Host smart-b7d29a64-bcbd-4164-91b3-2dc4aada9f79
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431339316 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_intr_test.2431339316
Directory /workspace/18.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.2933295819
Short name T617
Test name
Test status
Simulation time 32359913 ps
CPU time 1.59 seconds
Started Jul 01 10:39:58 AM PDT 24
Finished Jul 01 10:40:00 AM PDT 24
Peak memory 199396 kb
Host smart-bc687f6f-1341-44d0-b609-fb155c80454a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933295819 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_same_cs
r_outstanding.2933295819
Directory /workspace/18.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_errors.3081156445
Short name T551
Test name
Test status
Simulation time 96157672 ps
CPU time 1.37 seconds
Started Jul 01 10:39:41 AM PDT 24
Finished Jul 01 10:39:47 AM PDT 24
Peak memory 199428 kb
Host smart-6752544b-3043-418c-af75-108c55333aa0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081156445 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_errors.3081156445
Directory /workspace/18.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.1612553206
Short name T131
Test name
Test status
Simulation time 97574152 ps
CPU time 1.94 seconds
Started Jul 01 10:39:47 AM PDT 24
Finished Jul 01 10:39:51 AM PDT 24
Peak memory 199436 kb
Host smart-14720be1-e20e-44bf-a3ae-6d19438e5687
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612553206 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_intg_err.1612553206
Directory /workspace/18.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.838951625
Short name T570
Test name
Test status
Simulation time 22753829928 ps
CPU time 335.92 seconds
Started Jul 01 10:39:31 AM PDT 24
Finished Jul 01 10:45:09 AM PDT 24
Peak memory 214972 kb
Host smart-7264698b-f63c-418a-86ca-15bebb2cfaa5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838951625 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.hmac_csr_mem_rw_with_rand_reset.838951625
Directory /workspace/19.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_rw.146397021
Short name T109
Test name
Test status
Simulation time 26274944 ps
CPU time 0.7 seconds
Started Jul 01 10:39:42 AM PDT 24
Finished Jul 01 10:39:46 AM PDT 24
Peak memory 197220 kb
Host smart-fdc036e9-611b-4c2b-ae42-c03b816f627c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146397021 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_rw.146397021
Directory /workspace/19.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_intr_test.3568907985
Short name T595
Test name
Test status
Simulation time 20968376 ps
CPU time 0.62 seconds
Started Jul 01 10:39:43 AM PDT 24
Finished Jul 01 10:39:49 AM PDT 24
Peak memory 194352 kb
Host smart-495b7ab6-c828-4da9-8911-b4cf2da6f448
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568907985 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_intr_test.3568907985
Directory /workspace/19.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.2007647139
Short name T577
Test name
Test status
Simulation time 691572627 ps
CPU time 2.44 seconds
Started Jul 01 10:39:55 AM PDT 24
Finished Jul 01 10:39:59 AM PDT 24
Peak memory 199732 kb
Host smart-a43475f6-d62f-4792-9741-00c91ed9c99c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007647139 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_same_cs
r_outstanding.2007647139
Directory /workspace/19.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_errors.3704128536
Short name T621
Test name
Test status
Simulation time 67191989 ps
CPU time 1.68 seconds
Started Jul 01 10:39:48 AM PDT 24
Finished Jul 01 10:39:52 AM PDT 24
Peak memory 199484 kb
Host smart-3eb02a75-dabb-4696-9664-094668b1dbb3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704128536 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_errors.3704128536
Directory /workspace/19.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.3536320958
Short name T102
Test name
Test status
Simulation time 218785287 ps
CPU time 5.42 seconds
Started Jul 01 10:39:40 AM PDT 24
Finished Jul 01 10:39:50 AM PDT 24
Peak memory 199412 kb
Host smart-266535ac-50c5-4b98-a573-b452a7f0cd57
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536320958 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_aliasing.3536320958
Directory /workspace/2.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.2237115303
Short name T110
Test name
Test status
Simulation time 567711624 ps
CPU time 5.22 seconds
Started Jul 01 10:39:47 AM PDT 24
Finished Jul 01 10:39:55 AM PDT 24
Peak memory 199432 kb
Host smart-ae95e820-db35-437c-af65-09cdc32348dc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237115303 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_bit_bash.2237115303
Directory /workspace/2.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.1173347818
Short name T107
Test name
Test status
Simulation time 66336664 ps
CPU time 0.93 seconds
Started Jul 01 10:40:18 AM PDT 24
Finished Jul 01 10:40:23 AM PDT 24
Peak memory 199348 kb
Host smart-24fe1fc8-c0c5-471c-85cb-bc04bcebf7d0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173347818 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_hw_reset.1173347818
Directory /workspace/2.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.4220192016
Short name T638
Test name
Test status
Simulation time 60708980 ps
CPU time 1.61 seconds
Started Jul 01 10:39:34 AM PDT 24
Finished Jul 01 10:39:39 AM PDT 24
Peak memory 199564 kb
Host smart-2ffe44bc-ca8e-43cf-966f-56968629c8be
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220192016 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.hmac_csr_mem_rw_with_rand_reset.4220192016
Directory /workspace/2.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_rw.2816960010
Short name T644
Test name
Test status
Simulation time 57210910 ps
CPU time 0.92 seconds
Started Jul 01 10:39:39 AM PDT 24
Finished Jul 01 10:39:49 AM PDT 24
Peak memory 199300 kb
Host smart-ef533488-df95-4cbe-8560-8b40d525894c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816960010 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_rw.2816960010
Directory /workspace/2.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_intr_test.86820349
Short name T543
Test name
Test status
Simulation time 11681579 ps
CPU time 0.59 seconds
Started Jul 01 10:39:33 AM PDT 24
Finished Jul 01 10:39:36 AM PDT 24
Peak memory 194368 kb
Host smart-2da1f821-cf82-46f7-be0e-7fc86bb54745
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86820349 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_intr_test.86820349
Directory /workspace/2.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.1856181115
Short name T586
Test name
Test status
Simulation time 442924337 ps
CPU time 2.19 seconds
Started Jul 01 10:39:35 AM PDT 24
Finished Jul 01 10:39:40 AM PDT 24
Peak memory 199368 kb
Host smart-355ee477-bec1-456e-bf0d-69ef7721f01e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856181115 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_same_csr
_outstanding.1856181115
Directory /workspace/2.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_errors.3053334424
Short name T584
Test name
Test status
Simulation time 55647604 ps
CPU time 1.43 seconds
Started Jul 01 10:40:15 AM PDT 24
Finished Jul 01 10:40:19 AM PDT 24
Peak memory 199444 kb
Host smart-96046063-fae8-4bbd-8882-57405b5ee3f3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053334424 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_errors.3053334424
Directory /workspace/2.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.4214899347
Short name T601
Test name
Test status
Simulation time 524527146 ps
CPU time 1.89 seconds
Started Jul 01 10:40:10 AM PDT 24
Finished Jul 01 10:40:13 AM PDT 24
Peak memory 199364 kb
Host smart-b2cabdd8-4aaa-4c53-8e3e-de6f9ebc58fb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214899347 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_intg_err.4214899347
Directory /workspace/2.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.hmac_intr_test.2469597233
Short name T612
Test name
Test status
Simulation time 32856243 ps
CPU time 0.56 seconds
Started Jul 01 10:39:40 AM PDT 24
Finished Jul 01 10:39:45 AM PDT 24
Peak memory 194340 kb
Host smart-f88ed041-9e5c-4977-a912-bbdd72c85acd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469597233 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.hmac_intr_test.2469597233
Directory /workspace/20.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.hmac_intr_test.2309425717
Short name T624
Test name
Test status
Simulation time 40352969 ps
CPU time 0.6 seconds
Started Jul 01 10:39:51 AM PDT 24
Finished Jul 01 10:39:53 AM PDT 24
Peak memory 194404 kb
Host smart-479400f8-d0ed-493d-b51a-9c01d29eb18b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309425717 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.hmac_intr_test.2309425717
Directory /workspace/21.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.hmac_intr_test.558323175
Short name T585
Test name
Test status
Simulation time 33634086 ps
CPU time 0.59 seconds
Started Jul 01 10:39:38 AM PDT 24
Finished Jul 01 10:39:44 AM PDT 24
Peak memory 194444 kb
Host smart-e5ce89d7-0272-483d-88a8-a988cc7365b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558323175 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.hmac_intr_test.558323175
Directory /workspace/22.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.hmac_intr_test.2834205458
Short name T549
Test name
Test status
Simulation time 23302529 ps
CPU time 0.57 seconds
Started Jul 01 10:39:49 AM PDT 24
Finished Jul 01 10:39:52 AM PDT 24
Peak memory 194312 kb
Host smart-267fb251-e7fa-4642-aa9e-2cfdde521763
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834205458 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.hmac_intr_test.2834205458
Directory /workspace/23.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.hmac_intr_test.2839556491
Short name T639
Test name
Test status
Simulation time 35649097 ps
CPU time 0.68 seconds
Started Jul 01 10:39:43 AM PDT 24
Finished Jul 01 10:39:47 AM PDT 24
Peak memory 194396 kb
Host smart-bed08e1c-9d5c-41d1-92df-d54cd0939d8e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839556491 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.hmac_intr_test.2839556491
Directory /workspace/24.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.hmac_intr_test.4188994032
Short name T618
Test name
Test status
Simulation time 32805796 ps
CPU time 0.56 seconds
Started Jul 01 10:39:43 AM PDT 24
Finished Jul 01 10:39:47 AM PDT 24
Peak memory 194428 kb
Host smart-8b163779-8f0d-4b25-ab9f-6d81efd70844
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188994032 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.hmac_intr_test.4188994032
Directory /workspace/25.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.hmac_intr_test.1409952773
Short name T542
Test name
Test status
Simulation time 72616980 ps
CPU time 0.62 seconds
Started Jul 01 10:39:39 AM PDT 24
Finished Jul 01 10:39:44 AM PDT 24
Peak memory 194460 kb
Host smart-ead0124d-5346-4bf2-9f18-bad5a64e43c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409952773 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.hmac_intr_test.1409952773
Directory /workspace/26.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.hmac_intr_test.1273392897
Short name T598
Test name
Test status
Simulation time 16075799 ps
CPU time 0.63 seconds
Started Jul 01 10:40:22 AM PDT 24
Finished Jul 01 10:40:28 AM PDT 24
Peak memory 194500 kb
Host smart-cc5670bc-b885-415c-8ac6-a74e75e5e26c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273392897 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.hmac_intr_test.1273392897
Directory /workspace/27.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.hmac_intr_test.1314133831
Short name T623
Test name
Test status
Simulation time 85609968 ps
CPU time 0.65 seconds
Started Jul 01 10:40:27 AM PDT 24
Finished Jul 01 10:40:30 AM PDT 24
Peak memory 194728 kb
Host smart-9eb35ec1-9813-4017-bcf0-a5863a36dc4e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314133831 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.hmac_intr_test.1314133831
Directory /workspace/28.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.hmac_intr_test.412730654
Short name T582
Test name
Test status
Simulation time 33992269 ps
CPU time 0.56 seconds
Started Jul 01 10:40:03 AM PDT 24
Finished Jul 01 10:40:05 AM PDT 24
Peak memory 194348 kb
Host smart-67c8d314-325f-4b0d-8ad4-11cc3d1262f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412730654 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.hmac_intr_test.412730654
Directory /workspace/29.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.475317880
Short name T116
Test name
Test status
Simulation time 1847940252 ps
CPU time 6.08 seconds
Started Jul 01 10:40:09 AM PDT 24
Finished Jul 01 10:40:18 AM PDT 24
Peak memory 199340 kb
Host smart-a2e8c497-4a6e-47b4-9714-8b2200246858
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475317880 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_aliasing.475317880
Directory /workspace/3.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.3346893625
Short name T643
Test name
Test status
Simulation time 5556625631 ps
CPU time 10.81 seconds
Started Jul 01 10:40:07 AM PDT 24
Finished Jul 01 10:40:19 AM PDT 24
Peak memory 198916 kb
Host smart-05db67a6-e104-4f07-b827-a96d93bc353a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346893625 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_bit_bash.3346893625
Directory /workspace/3.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.1889311461
Short name T571
Test name
Test status
Simulation time 138839288 ps
CPU time 0.71 seconds
Started Jul 01 10:39:19 AM PDT 24
Finished Jul 01 10:39:21 AM PDT 24
Peak memory 197140 kb
Host smart-6263b7b3-2fcb-47b5-b73f-14c4babb5193
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889311461 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_hw_reset.1889311461
Directory /workspace/3.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.284896704
Short name T628
Test name
Test status
Simulation time 95514561 ps
CPU time 2.86 seconds
Started Jul 01 10:39:45 AM PDT 24
Finished Jul 01 10:39:51 AM PDT 24
Peak memory 199504 kb
Host smart-e441c748-e1ea-4717-99a4-b7b2abc3bbd1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284896704 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.hmac_csr_mem_rw_with_rand_reset.284896704
Directory /workspace/3.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_rw.4079846217
Short name T106
Test name
Test status
Simulation time 642766271 ps
CPU time 0.96 seconds
Started Jul 01 10:39:32 AM PDT 24
Finished Jul 01 10:39:35 AM PDT 24
Peak memory 199324 kb
Host smart-749d9e4d-8e9e-4ebb-a583-d00e69303342
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079846217 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_rw.4079846217
Directory /workspace/3.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_intr_test.2559977999
Short name T535
Test name
Test status
Simulation time 150950666 ps
CPU time 0.61 seconds
Started Jul 01 10:40:27 AM PDT 24
Finished Jul 01 10:40:30 AM PDT 24
Peak memory 194384 kb
Host smart-e2089240-4bb6-46a8-95dd-9e664a0be64c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559977999 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_intr_test.2559977999
Directory /workspace/3.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.399227948
Short name T619
Test name
Test status
Simulation time 125707968 ps
CPU time 1.18 seconds
Started Jul 01 10:39:57 AM PDT 24
Finished Jul 01 10:39:59 AM PDT 24
Peak memory 199284 kb
Host smart-5d9f1ea3-8c62-45b0-96a6-1f655afb064f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399227948 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_same_csr_
outstanding.399227948
Directory /workspace/3.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_errors.1329495621
Short name T540
Test name
Test status
Simulation time 125112890 ps
CPU time 1.59 seconds
Started Jul 01 10:40:04 AM PDT 24
Finished Jul 01 10:40:07 AM PDT 24
Peak memory 199420 kb
Host smart-b4dc8ba2-82ae-46fa-863f-82cf54dcbb85
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329495621 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_errors.1329495621
Directory /workspace/3.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.1204038126
Short name T134
Test name
Test status
Simulation time 391534333 ps
CPU time 2.03 seconds
Started Jul 01 10:40:32 AM PDT 24
Finished Jul 01 10:40:36 AM PDT 24
Peak memory 199484 kb
Host smart-48dfed12-f5bb-4264-9c73-dbe78183eef8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204038126 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_intg_err.1204038126
Directory /workspace/3.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.hmac_intr_test.2996890944
Short name T599
Test name
Test status
Simulation time 61563504 ps
CPU time 0.62 seconds
Started Jul 01 10:40:33 AM PDT 24
Finished Jul 01 10:40:36 AM PDT 24
Peak memory 194468 kb
Host smart-05e9248b-c958-4f26-9448-3ed7347853af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996890944 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.hmac_intr_test.2996890944
Directory /workspace/30.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.hmac_intr_test.704711054
Short name T587
Test name
Test status
Simulation time 19128941 ps
CPU time 0.59 seconds
Started Jul 01 10:39:41 AM PDT 24
Finished Jul 01 10:39:46 AM PDT 24
Peak memory 194364 kb
Host smart-009deea9-0d43-4b5c-a6dd-f562073d5937
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704711054 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.hmac_intr_test.704711054
Directory /workspace/31.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.hmac_intr_test.826631104
Short name T554
Test name
Test status
Simulation time 98336059 ps
CPU time 0.63 seconds
Started Jul 01 10:39:39 AM PDT 24
Finished Jul 01 10:39:44 AM PDT 24
Peak memory 194500 kb
Host smart-444fbda9-f138-4028-9915-5b024f9615e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826631104 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.hmac_intr_test.826631104
Directory /workspace/32.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.hmac_intr_test.941960148
Short name T79
Test name
Test status
Simulation time 32989681 ps
CPU time 0.63 seconds
Started Jul 01 10:39:35 AM PDT 24
Finished Jul 01 10:39:39 AM PDT 24
Peak memory 194452 kb
Host smart-5dd32765-a561-4822-8c46-94a6a5385b08
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941960148 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.hmac_intr_test.941960148
Directory /workspace/33.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.hmac_intr_test.2750323169
Short name T546
Test name
Test status
Simulation time 42203221 ps
CPU time 0.62 seconds
Started Jul 01 10:39:36 AM PDT 24
Finished Jul 01 10:39:41 AM PDT 24
Peak memory 194424 kb
Host smart-0ea42cd6-45c8-4ae2-96c1-ba910ac26c25
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750323169 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.hmac_intr_test.2750323169
Directory /workspace/34.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.hmac_intr_test.1910760679
Short name T558
Test name
Test status
Simulation time 31378706 ps
CPU time 0.7 seconds
Started Jul 01 10:39:40 AM PDT 24
Finished Jul 01 10:39:45 AM PDT 24
Peak memory 194536 kb
Host smart-7df8089b-b40b-44e0-b074-56082540a561
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910760679 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.hmac_intr_test.1910760679
Directory /workspace/35.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.hmac_intr_test.1968102860
Short name T645
Test name
Test status
Simulation time 10989541 ps
CPU time 0.6 seconds
Started Jul 01 10:39:51 AM PDT 24
Finished Jul 01 10:39:53 AM PDT 24
Peak memory 194408 kb
Host smart-2d9b9fc3-3006-472a-93d4-ed9225ece93d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968102860 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.hmac_intr_test.1968102860
Directory /workspace/36.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.hmac_intr_test.2186832569
Short name T626
Test name
Test status
Simulation time 13740754 ps
CPU time 0.6 seconds
Started Jul 01 10:40:12 AM PDT 24
Finished Jul 01 10:40:15 AM PDT 24
Peak memory 194480 kb
Host smart-0db9c22a-96c3-4c9c-ac18-bee0f2b11488
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186832569 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.hmac_intr_test.2186832569
Directory /workspace/37.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.hmac_intr_test.2457502756
Short name T573
Test name
Test status
Simulation time 34673566 ps
CPU time 0.61 seconds
Started Jul 01 10:40:23 AM PDT 24
Finished Jul 01 10:40:29 AM PDT 24
Peak memory 194412 kb
Host smart-fdae748a-ffad-47f3-a11e-24754f5e0398
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457502756 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.hmac_intr_test.2457502756
Directory /workspace/38.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.hmac_intr_test.3422073287
Short name T583
Test name
Test status
Simulation time 37617708 ps
CPU time 0.6 seconds
Started Jul 01 10:40:08 AM PDT 24
Finished Jul 01 10:40:09 AM PDT 24
Peak memory 194404 kb
Host smart-7252e662-ae86-45f1-b286-dcf2ff741f10
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422073287 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.hmac_intr_test.3422073287
Directory /workspace/39.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.2797892375
Short name T651
Test name
Test status
Simulation time 106885834 ps
CPU time 5.55 seconds
Started Jul 01 10:39:34 AM PDT 24
Finished Jul 01 10:39:43 AM PDT 24
Peak memory 199316 kb
Host smart-a4d360db-a542-409f-ac1c-68dd106e44c2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797892375 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_aliasing.2797892375
Directory /workspace/4.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.350266623
Short name T537
Test name
Test status
Simulation time 5237953365 ps
CPU time 15.37 seconds
Started Jul 01 10:39:38 AM PDT 24
Finished Jul 01 10:39:58 AM PDT 24
Peak memory 199596 kb
Host smart-4e86e1fb-f46c-415d-b1eb-5565c03016d2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350266623 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_bit_bash.350266623
Directory /workspace/4.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.1727759673
Short name T103
Test name
Test status
Simulation time 27475044 ps
CPU time 0.84 seconds
Started Jul 01 10:39:34 AM PDT 24
Finished Jul 01 10:39:38 AM PDT 24
Peak memory 198568 kb
Host smart-5bb8e2b0-9107-4af1-a26f-38d7c51d0014
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727759673 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_hw_reset.1727759673
Directory /workspace/4.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.3824967289
Short name T580
Test name
Test status
Simulation time 96386280 ps
CPU time 2.42 seconds
Started Jul 01 10:40:07 AM PDT 24
Finished Jul 01 10:40:10 AM PDT 24
Peak memory 199552 kb
Host smart-1ca3cc7f-e69d-49dd-b5d6-28830fc412ed
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824967289 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.hmac_csr_mem_rw_with_rand_reset.3824967289
Directory /workspace/4.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_rw.1074335874
Short name T575
Test name
Test status
Simulation time 17430054 ps
CPU time 0.68 seconds
Started Jul 01 10:40:12 AM PDT 24
Finished Jul 01 10:40:20 AM PDT 24
Peak memory 197472 kb
Host smart-35aedac9-66b3-46ac-8722-ba19976cc3a4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074335874 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_rw.1074335874
Directory /workspace/4.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_intr_test.1321212944
Short name T591
Test name
Test status
Simulation time 12741089 ps
CPU time 0.62 seconds
Started Jul 01 10:40:20 AM PDT 24
Finished Jul 01 10:40:24 AM PDT 24
Peak memory 194496 kb
Host smart-721d9dcf-ba17-4681-b671-2514c3e14652
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321212944 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_intr_test.1321212944
Directory /workspace/4.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.3773668771
Short name T637
Test name
Test status
Simulation time 475198015 ps
CPU time 2.3 seconds
Started Jul 01 10:39:39 AM PDT 24
Finished Jul 01 10:39:46 AM PDT 24
Peak memory 199408 kb
Host smart-ef796b81-4c23-43c2-947b-bc16b6a9d951
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773668771 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_same_csr
_outstanding.3773668771
Directory /workspace/4.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_errors.3452670718
Short name T572
Test name
Test status
Simulation time 291048770 ps
CPU time 2.61 seconds
Started Jul 01 10:40:14 AM PDT 24
Finished Jul 01 10:40:18 AM PDT 24
Peak memory 199404 kb
Host smart-1c91b1de-07df-4aae-acd7-d6b1fe423b97
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452670718 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_errors.3452670718
Directory /workspace/4.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.3014691385
Short name T133
Test name
Test status
Simulation time 159278231 ps
CPU time 4 seconds
Started Jul 01 10:39:35 AM PDT 24
Finished Jul 01 10:39:45 AM PDT 24
Peak memory 199440 kb
Host smart-f19d08a8-2c29-4eec-ada8-87dfcf17a0a9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014691385 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_intg_err.3014691385
Directory /workspace/4.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.hmac_intr_test.2259326289
Short name T534
Test name
Test status
Simulation time 39883080 ps
CPU time 0.58 seconds
Started Jul 01 10:39:41 AM PDT 24
Finished Jul 01 10:39:50 AM PDT 24
Peak memory 194372 kb
Host smart-1019a115-b395-4443-8eb2-edb44ff4ab35
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259326289 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.hmac_intr_test.2259326289
Directory /workspace/40.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.hmac_intr_test.1482905385
Short name T565
Test name
Test status
Simulation time 11744640 ps
CPU time 0.7 seconds
Started Jul 01 10:40:19 AM PDT 24
Finished Jul 01 10:40:23 AM PDT 24
Peak memory 194452 kb
Host smart-96c5449e-f305-4f0e-835b-0ca4b27decd0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482905385 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.hmac_intr_test.1482905385
Directory /workspace/41.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.hmac_intr_test.121202064
Short name T567
Test name
Test status
Simulation time 14181357 ps
CPU time 0.59 seconds
Started Jul 01 10:39:43 AM PDT 24
Finished Jul 01 10:39:47 AM PDT 24
Peak memory 194488 kb
Host smart-19555696-0ac8-4136-8092-75b36aa2a412
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121202064 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.hmac_intr_test.121202064
Directory /workspace/42.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.hmac_intr_test.2721937076
Short name T627
Test name
Test status
Simulation time 17559411 ps
CPU time 0.61 seconds
Started Jul 01 10:40:23 AM PDT 24
Finished Jul 01 10:40:26 AM PDT 24
Peak memory 194420 kb
Host smart-c56cb15c-4941-466e-97e1-4acbee587e52
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721937076 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.hmac_intr_test.2721937076
Directory /workspace/43.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.hmac_intr_test.4134987153
Short name T631
Test name
Test status
Simulation time 70753190 ps
CPU time 0.59 seconds
Started Jul 01 10:39:35 AM PDT 24
Finished Jul 01 10:39:41 AM PDT 24
Peak memory 194464 kb
Host smart-6edd04d4-1b2d-447f-981a-0294460f6c21
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134987153 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.hmac_intr_test.4134987153
Directory /workspace/44.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.hmac_intr_test.1344753976
Short name T625
Test name
Test status
Simulation time 38341531 ps
CPU time 0.56 seconds
Started Jul 01 10:39:43 AM PDT 24
Finished Jul 01 10:39:47 AM PDT 24
Peak memory 194332 kb
Host smart-a0ee85ec-b95e-4903-80df-901e1ddf5b1e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344753976 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.hmac_intr_test.1344753976
Directory /workspace/45.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.hmac_intr_test.1827184792
Short name T593
Test name
Test status
Simulation time 163117418 ps
CPU time 0.61 seconds
Started Jul 01 10:39:55 AM PDT 24
Finished Jul 01 10:39:56 AM PDT 24
Peak memory 194392 kb
Host smart-b8967a1a-0a43-46b6-8d8e-5b8eb9a1979e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827184792 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.hmac_intr_test.1827184792
Directory /workspace/46.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.hmac_intr_test.450510886
Short name T634
Test name
Test status
Simulation time 23301056 ps
CPU time 0.6 seconds
Started Jul 01 10:40:30 AM PDT 24
Finished Jul 01 10:40:32 AM PDT 24
Peak memory 194516 kb
Host smart-f79e2852-4fe9-4217-ad23-e92070f7a1fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450510886 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.hmac_intr_test.450510886
Directory /workspace/47.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.hmac_intr_test.275947206
Short name T616
Test name
Test status
Simulation time 37023404 ps
CPU time 0.58 seconds
Started Jul 01 10:39:50 AM PDT 24
Finished Jul 01 10:39:53 AM PDT 24
Peak memory 194464 kb
Host smart-aea29565-e061-4c8d-ab80-9871e7e99de3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275947206 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.hmac_intr_test.275947206
Directory /workspace/48.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.hmac_intr_test.2067333957
Short name T652
Test name
Test status
Simulation time 17923737 ps
CPU time 0.6 seconds
Started Jul 01 10:40:09 AM PDT 24
Finished Jul 01 10:40:12 AM PDT 24
Peak memory 194428 kb
Host smart-aefac27e-0567-4686-84c7-339152b307ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067333957 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.hmac_intr_test.2067333957
Directory /workspace/49.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.1566443816
Short name T641
Test name
Test status
Simulation time 416888579 ps
CPU time 2.37 seconds
Started Jul 01 10:39:37 AM PDT 24
Finished Jul 01 10:39:44 AM PDT 24
Peak memory 199528 kb
Host smart-d6889876-73ba-40f2-b839-a80e9ba13823
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566443816 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.hmac_csr_mem_rw_with_rand_reset.1566443816
Directory /workspace/5.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_rw.2228532955
Short name T119
Test name
Test status
Simulation time 126778510 ps
CPU time 0.96 seconds
Started Jul 01 10:39:22 AM PDT 24
Finished Jul 01 10:39:24 AM PDT 24
Peak memory 199276 kb
Host smart-9b002929-9cf6-4a3e-9fdd-7289f6f0ba5b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228532955 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_rw.2228532955
Directory /workspace/5.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_intr_test.3884195809
Short name T646
Test name
Test status
Simulation time 31486429 ps
CPU time 0.58 seconds
Started Jul 01 10:39:37 AM PDT 24
Finished Jul 01 10:39:42 AM PDT 24
Peak memory 194344 kb
Host smart-d327a41c-e1fe-43ff-a31a-cff1fec2ebcd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884195809 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_intr_test.3884195809
Directory /workspace/5.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.1417336879
Short name T597
Test name
Test status
Simulation time 39062382 ps
CPU time 1.02 seconds
Started Jul 01 10:39:31 AM PDT 24
Finished Jul 01 10:39:35 AM PDT 24
Peak memory 197888 kb
Host smart-3fbea1ce-54b7-4000-8dd7-447a93f5d06c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417336879 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_same_csr
_outstanding.1417336879
Directory /workspace/5.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_errors.2731110071
Short name T620
Test name
Test status
Simulation time 67907593 ps
CPU time 1.52 seconds
Started Jul 01 10:39:34 AM PDT 24
Finished Jul 01 10:39:39 AM PDT 24
Peak memory 199424 kb
Host smart-45205cba-3204-4e0a-a5f2-a7692ff883e7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731110071 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_errors.2731110071
Directory /workspace/5.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.4077830482
Short name T649
Test name
Test status
Simulation time 303440430 ps
CPU time 3.8 seconds
Started Jul 01 10:39:36 AM PDT 24
Finished Jul 01 10:39:44 AM PDT 24
Peak memory 199408 kb
Host smart-63caf051-46fc-407f-8880-edbbd94cdeef
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077830482 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_intg_err.4077830482
Directory /workspace/5.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.3136074894
Short name T647
Test name
Test status
Simulation time 101772749 ps
CPU time 2.32 seconds
Started Jul 01 10:39:33 AM PDT 24
Finished Jul 01 10:39:38 AM PDT 24
Peak memory 199480 kb
Host smart-3f9ba8e2-bbb7-41f9-8c13-ecc94bf1abb6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136074894 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.hmac_csr_mem_rw_with_rand_reset.3136074894
Directory /workspace/6.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_rw.4174486215
Short name T105
Test name
Test status
Simulation time 35957532 ps
CPU time 0.95 seconds
Started Jul 01 10:39:40 AM PDT 24
Finished Jul 01 10:39:45 AM PDT 24
Peak memory 199324 kb
Host smart-71d93ecc-edc9-4fdc-9705-3dcaac44441b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174486215 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_rw.4174486215
Directory /workspace/6.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_intr_test.1312367117
Short name T536
Test name
Test status
Simulation time 25757383 ps
CPU time 0.62 seconds
Started Jul 01 10:39:57 AM PDT 24
Finished Jul 01 10:39:58 AM PDT 24
Peak memory 194504 kb
Host smart-26cd19ae-a20e-46d3-9923-390c7dd12d67
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312367117 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_intr_test.1312367117
Directory /workspace/6.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.2794599790
Short name T600
Test name
Test status
Simulation time 163251380 ps
CPU time 2.42 seconds
Started Jul 01 10:39:35 AM PDT 24
Finished Jul 01 10:39:41 AM PDT 24
Peak memory 199400 kb
Host smart-3fa032f7-7a12-435c-bd45-49b4e971b44b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794599790 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_same_csr
_outstanding.2794599790
Directory /workspace/6.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_errors.56484753
Short name T550
Test name
Test status
Simulation time 207028843 ps
CPU time 4.07 seconds
Started Jul 01 10:39:34 AM PDT 24
Finished Jul 01 10:39:41 AM PDT 24
Peak memory 199428 kb
Host smart-9cd01220-9af3-4ba2-a125-5e0da1b2e981
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56484753 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_errors.56484753
Directory /workspace/6.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.1730203535
Short name T614
Test name
Test status
Simulation time 992042749 ps
CPU time 4.28 seconds
Started Jul 01 10:39:57 AM PDT 24
Finished Jul 01 10:40:02 AM PDT 24
Peak memory 199488 kb
Host smart-1b8410f3-9a6f-4302-914b-45b602a8feee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730203535 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_intg_err.1730203535
Directory /workspace/6.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.4056205801
Short name T654
Test name
Test status
Simulation time 100799689 ps
CPU time 1.35 seconds
Started Jul 01 10:40:14 AM PDT 24
Finished Jul 01 10:40:24 AM PDT 24
Peak memory 199408 kb
Host smart-5c4c173b-11e1-441f-9d70-e04a45d3054b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056205801 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.hmac_csr_mem_rw_with_rand_reset.4056205801
Directory /workspace/7.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_rw.1811225798
Short name T650
Test name
Test status
Simulation time 103317026 ps
CPU time 0.88 seconds
Started Jul 01 10:39:36 AM PDT 24
Finished Jul 01 10:39:41 AM PDT 24
Peak memory 198956 kb
Host smart-4af9b95b-2724-4a43-aa2d-3a1183602828
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811225798 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_rw.1811225798
Directory /workspace/7.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_intr_test.460669145
Short name T576
Test name
Test status
Simulation time 21415245 ps
CPU time 0.61 seconds
Started Jul 01 10:39:40 AM PDT 24
Finished Jul 01 10:39:47 AM PDT 24
Peak memory 194460 kb
Host smart-0e0cd12a-0637-4e9c-b87b-e0cb69690a8e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460669145 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_intr_test.460669145
Directory /workspace/7.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.3383264285
Short name T121
Test name
Test status
Simulation time 264165889 ps
CPU time 1.21 seconds
Started Jul 01 10:39:34 AM PDT 24
Finished Jul 01 10:39:44 AM PDT 24
Peak memory 197824 kb
Host smart-d9cf13bd-b337-46f7-ae8b-b0c2e174fc3c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383264285 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_same_csr
_outstanding.3383264285
Directory /workspace/7.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_errors.1365572167
Short name T610
Test name
Test status
Simulation time 86563991 ps
CPU time 1.75 seconds
Started Jul 01 10:39:32 AM PDT 24
Finished Jul 01 10:39:36 AM PDT 24
Peak memory 199424 kb
Host smart-caec0163-4d4c-44b8-bdcb-bb6ca41ac487
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365572167 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_errors.1365572167
Directory /workspace/7.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.942399313
Short name T129
Test name
Test status
Simulation time 728837493 ps
CPU time 1.88 seconds
Started Jul 01 10:39:37 AM PDT 24
Finished Jul 01 10:39:43 AM PDT 24
Peak memory 199416 kb
Host smart-b24ac3b1-df01-44b6-a7b1-5f440bea0d54
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942399313 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_intg_err.942399313
Directory /workspace/7.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.2997583776
Short name T569
Test name
Test status
Simulation time 1407355143 ps
CPU time 2.3 seconds
Started Jul 01 10:39:37 AM PDT 24
Finished Jul 01 10:39:44 AM PDT 24
Peak memory 199380 kb
Host smart-b432ee3a-ec66-4d97-ba76-9195c7c8130f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997583776 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.hmac_csr_mem_rw_with_rand_reset.2997583776
Directory /workspace/8.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_rw.2357941964
Short name T541
Test name
Test status
Simulation time 24385827 ps
CPU time 0.66 seconds
Started Jul 01 10:39:36 AM PDT 24
Finished Jul 01 10:39:41 AM PDT 24
Peak memory 197476 kb
Host smart-dae83f5e-cd9c-4ea9-83d2-31284dc3b412
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357941964 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_rw.2357941964
Directory /workspace/8.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_intr_test.437016035
Short name T615
Test name
Test status
Simulation time 14947029 ps
CPU time 0.65 seconds
Started Jul 01 10:39:29 AM PDT 24
Finished Jul 01 10:39:31 AM PDT 24
Peak memory 194368 kb
Host smart-dd1b11ec-67ef-40c4-8b07-4b81d6392abb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437016035 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_intr_test.437016035
Directory /workspace/8.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.1187967654
Short name T607
Test name
Test status
Simulation time 226782301 ps
CPU time 2.3 seconds
Started Jul 01 10:39:25 AM PDT 24
Finished Jul 01 10:39:28 AM PDT 24
Peak memory 199456 kb
Host smart-564caaf1-d9e0-4465-8994-3a8a60f4701d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187967654 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_same_csr
_outstanding.1187967654
Directory /workspace/8.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_errors.1702879219
Short name T555
Test name
Test status
Simulation time 1132059593 ps
CPU time 3.49 seconds
Started Jul 01 10:39:33 AM PDT 24
Finished Jul 01 10:39:39 AM PDT 24
Peak memory 199416 kb
Host smart-1fdde269-175c-428a-8158-726e84670826
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702879219 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_errors.1702879219
Directory /workspace/8.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.977883616
Short name T606
Test name
Test status
Simulation time 84637344 ps
CPU time 2.77 seconds
Started Jul 01 10:39:46 AM PDT 24
Finished Jul 01 10:39:51 AM PDT 24
Peak memory 199412 kb
Host smart-76045eef-81ff-47a6-89ac-b17cb53525bd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977883616 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_intg_err.977883616
Directory /workspace/8.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.3386765005
Short name T562
Test name
Test status
Simulation time 66093477906 ps
CPU time 997.97 seconds
Started Jul 01 10:39:30 AM PDT 24
Finished Jul 01 10:56:09 AM PDT 24
Peak memory 224132 kb
Host smart-0b56787e-d2e1-45d5-aea0-86504b2e109e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386765005 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.hmac_csr_mem_rw_with_rand_reset.3386765005
Directory /workspace/9.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_rw.2660269559
Short name T115
Test name
Test status
Simulation time 59278381 ps
CPU time 0.77 seconds
Started Jul 01 10:39:37 AM PDT 24
Finished Jul 01 10:39:42 AM PDT 24
Peak memory 198888 kb
Host smart-cc162dec-6b28-4aea-9ca0-ec9afe33dbe8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660269559 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_rw.2660269559
Directory /workspace/9.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_intr_test.1345881076
Short name T553
Test name
Test status
Simulation time 133781636 ps
CPU time 0.6 seconds
Started Jul 01 10:39:40 AM PDT 24
Finished Jul 01 10:39:45 AM PDT 24
Peak memory 194456 kb
Host smart-19c4ee93-fdba-4dff-92c4-601d14e73b89
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345881076 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_intr_test.1345881076
Directory /workspace/9.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.4154507982
Short name T122
Test name
Test status
Simulation time 187890596 ps
CPU time 1.08 seconds
Started Jul 01 10:39:34 AM PDT 24
Finished Jul 01 10:39:37 AM PDT 24
Peak memory 198076 kb
Host smart-6cfd761f-62b6-42fd-aecd-27774fe24aaf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154507982 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_same_csr
_outstanding.4154507982
Directory /workspace/9.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_errors.47617303
Short name T630
Test name
Test status
Simulation time 48532251 ps
CPU time 1.5 seconds
Started Jul 01 10:39:37 AM PDT 24
Finished Jul 01 10:39:42 AM PDT 24
Peak memory 199416 kb
Host smart-9b3cf480-67df-4fee-895b-da30355d4670
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47617303 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_errors.47617303
Directory /workspace/9.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.2017459787
Short name T605
Test name
Test status
Simulation time 721477032 ps
CPU time 3.19 seconds
Started Jul 01 10:39:38 AM PDT 24
Finished Jul 01 10:39:46 AM PDT 24
Peak memory 199420 kb
Host smart-f88d8500-53fe-40e3-81f8-c8f3b5556f58
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017459787 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_intg_err.2017459787
Directory /workspace/9.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.hmac_alert_test.1633511757
Short name T203
Test name
Test status
Simulation time 14750495 ps
CPU time 0.58 seconds
Started Jul 01 10:40:44 AM PDT 24
Finished Jul 01 10:40:45 AM PDT 24
Peak memory 195876 kb
Host smart-9e897f60-2e89-40f6-8886-f45e6ad80123
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633511757 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_alert_test.1633511757
Directory /workspace/0.hmac_alert_test/latest

Test location /workspace/coverage/default/0.hmac_back_pressure.314428646
Short name T331
Test name
Test status
Simulation time 82318536 ps
CPU time 2.3 seconds
Started Jul 01 10:40:46 AM PDT 24
Finished Jul 01 10:40:49 AM PDT 24
Peak memory 200292 kb
Host smart-c9266e8c-397d-4802-a843-13209705e208
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=314428646 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_back_pressure.314428646
Directory /workspace/0.hmac_back_pressure/latest

Test location /workspace/coverage/default/0.hmac_burst_wr.513521418
Short name T135
Test name
Test status
Simulation time 4424410529 ps
CPU time 53.94 seconds
Started Jul 01 10:40:33 AM PDT 24
Finished Jul 01 10:41:28 AM PDT 24
Peak memory 200384 kb
Host smart-32dea143-f7c5-43e0-8aaf-8c78713e7577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513521418 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_burst_wr.513521418
Directory /workspace/0.hmac_burst_wr/latest

Test location /workspace/coverage/default/0.hmac_datapath_stress.1543468617
Short name T515
Test name
Test status
Simulation time 11646286410 ps
CPU time 1239.99 seconds
Started Jul 01 10:41:06 AM PDT 24
Finished Jul 01 11:01:47 AM PDT 24
Peak memory 758036 kb
Host smart-bbbcedf1-18aa-4386-b89b-e9ec16ba7cd7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1543468617 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_datapath_stress.1543468617
Directory /workspace/0.hmac_datapath_stress/latest

Test location /workspace/coverage/default/0.hmac_error.1541318830
Short name T256
Test name
Test status
Simulation time 2035958912 ps
CPU time 25.98 seconds
Started Jul 01 10:40:47 AM PDT 24
Finished Jul 01 10:41:14 AM PDT 24
Peak memory 200100 kb
Host smart-9372f8c3-3070-4b4b-b9db-0b68164d9f96
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541318830 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_error.1541318830
Directory /workspace/0.hmac_error/latest

Test location /workspace/coverage/default/0.hmac_long_msg.4121337529
Short name T454
Test name
Test status
Simulation time 48262768720 ps
CPU time 63.14 seconds
Started Jul 01 10:40:42 AM PDT 24
Finished Jul 01 10:41:46 AM PDT 24
Peak memory 200388 kb
Host smart-2d62b7d9-3308-4630-9d2b-dd160d9d3779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121337529 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_long_msg.4121337529
Directory /workspace/0.hmac_long_msg/latest

Test location /workspace/coverage/default/0.hmac_smoke.1721502579
Short name T196
Test name
Test status
Simulation time 477645508 ps
CPU time 14.66 seconds
Started Jul 01 10:40:43 AM PDT 24
Finished Jul 01 10:40:59 AM PDT 24
Peak memory 200244 kb
Host smart-fde0fab9-9aea-42d9-87a6-7533a5365a90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721502579 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_smoke.1721502579
Directory /workspace/0.hmac_smoke/latest

Test location /workspace/coverage/default/0.hmac_stress_all.447313329
Short name T305
Test name
Test status
Simulation time 50118826516 ps
CPU time 1150.58 seconds
Started Jul 01 10:40:44 AM PDT 24
Finished Jul 01 10:59:56 AM PDT 24
Peak memory 636780 kb
Host smart-d91cb0f6-30e3-4b9d-9b86-df24f5b20372
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447313329 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all.447313329
Directory /workspace/0.hmac_stress_all/latest

Test location /workspace/coverage/default/0.hmac_stress_all_with_rand_reset.812716163
Short name T60
Test name
Test status
Simulation time 12685032769 ps
CPU time 291.07 seconds
Started Jul 01 10:40:31 AM PDT 24
Finished Jul 01 10:45:28 AM PDT 24
Peak memory 372048 kb
Host smart-04c544ee-4836-4c62-b920-4f74f30cdd34
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=812716163 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all_with_rand_reset.812716163
Directory /workspace/0.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.hmac_test_hmac256_vectors.409477032
Short name T351
Test name
Test status
Simulation time 1533070748 ps
CPU time 60.77 seconds
Started Jul 01 10:42:06 AM PDT 24
Finished Jul 01 10:43:09 AM PDT 24
Peak memory 200028 kb
Host smart-447f9d8f-acf3-4aba-b88b-d17664a099ce
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=409477032 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac256_vectors.409477032
Directory /workspace/0.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_hmac384_vectors.4045420243
Short name T151
Test name
Test status
Simulation time 21022461559 ps
CPU time 62.64 seconds
Started Jul 01 10:40:46 AM PDT 24
Finished Jul 01 10:41:50 AM PDT 24
Peak memory 200376 kb
Host smart-bbe94afd-aa7a-4578-aa12-ce59cf860e78
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4045420243 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac384_vectors.4045420243
Directory /workspace/0.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_hmac512_vectors.2850037466
Short name T386
Test name
Test status
Simulation time 28069684319 ps
CPU time 78.37 seconds
Started Jul 01 10:40:42 AM PDT 24
Finished Jul 01 10:42:02 AM PDT 24
Peak memory 200284 kb
Host smart-c0e3c6a3-0a1e-4a2f-9a04-7aba03c8b82f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2850037466 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac512_vectors.2850037466
Directory /workspace/0.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha256_vectors.2277898764
Short name T502
Test name
Test status
Simulation time 34306102933 ps
CPU time 597.73 seconds
Started Jul 01 10:40:40 AM PDT 24
Finished Jul 01 10:50:38 AM PDT 24
Peak memory 200288 kb
Host smart-6cf30dc1-8259-4b8c-82c1-026fa2371d4b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2277898764 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha256_vectors.2277898764
Directory /workspace/0.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha384_vectors.462261614
Short name T272
Test name
Test status
Simulation time 41271365681 ps
CPU time 2062.46 seconds
Started Jul 01 10:40:47 AM PDT 24
Finished Jul 01 11:15:11 AM PDT 24
Peak memory 215848 kb
Host smart-91eb2ec4-db6f-4bda-93ae-2ebccfeec8fd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=462261614 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha384_vectors.462261614
Directory /workspace/0.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha512_vectors.2608349606
Short name T451
Test name
Test status
Simulation time 198060844440 ps
CPU time 2330.98 seconds
Started Jul 01 10:42:00 AM PDT 24
Finished Jul 01 11:20:53 AM PDT 24
Peak memory 215344 kb
Host smart-f93de72c-c920-4ded-b508-355c77e1abb2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_200_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2608349606 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha512_vectors.2608349606
Directory /workspace/0.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/0.hmac_wipe_secret.2165029878
Short name T248
Test name
Test status
Simulation time 261818210 ps
CPU time 13.36 seconds
Started Jul 01 10:40:44 AM PDT 24
Finished Jul 01 10:40:58 AM PDT 24
Peak memory 200208 kb
Host smart-8cfc0c65-93ff-41ad-9611-01cc5b7df194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165029878 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_wipe_secret.2165029878
Directory /workspace/0.hmac_wipe_secret/latest

Test location /workspace/coverage/default/1.hmac_alert_test.52736314
Short name T361
Test name
Test status
Simulation time 24707388 ps
CPU time 0.62 seconds
Started Jul 01 10:40:56 AM PDT 24
Finished Jul 01 10:40:57 AM PDT 24
Peak memory 196744 kb
Host smart-bdb2138d-362a-44b9-a6f5-7622b89315a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52736314 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_alert_test.52736314
Directory /workspace/1.hmac_alert_test/latest

Test location /workspace/coverage/default/1.hmac_back_pressure.711718746
Short name T461
Test name
Test status
Simulation time 1921517168 ps
CPU time 52.54 seconds
Started Jul 01 10:40:42 AM PDT 24
Finished Jul 01 10:41:37 AM PDT 24
Peak memory 200168 kb
Host smart-ab405d4f-8845-48c0-9996-080b55dc60e1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=711718746 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_back_pressure.711718746
Directory /workspace/1.hmac_back_pressure/latest

Test location /workspace/coverage/default/1.hmac_burst_wr.3714081010
Short name T82
Test name
Test status
Simulation time 1387331349 ps
CPU time 5.41 seconds
Started Jul 01 10:40:57 AM PDT 24
Finished Jul 01 10:41:08 AM PDT 24
Peak memory 200268 kb
Host smart-c408a18c-a5fe-4db6-b019-3221f629869e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714081010 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_burst_wr.3714081010
Directory /workspace/1.hmac_burst_wr/latest

Test location /workspace/coverage/default/1.hmac_datapath_stress.2758228106
Short name T66
Test name
Test status
Simulation time 3896659222 ps
CPU time 330.32 seconds
Started Jul 01 10:40:32 AM PDT 24
Finished Jul 01 10:46:04 AM PDT 24
Peak memory 454872 kb
Host smart-fbee9da5-c4a1-4622-8da5-b52f9115043a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2758228106 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_datapath_stress.2758228106
Directory /workspace/1.hmac_datapath_stress/latest

Test location /workspace/coverage/default/1.hmac_error.754497941
Short name T185
Test name
Test status
Simulation time 16324615023 ps
CPU time 56.79 seconds
Started Jul 01 10:40:36 AM PDT 24
Finished Jul 01 10:41:33 AM PDT 24
Peak memory 200284 kb
Host smart-88a62fc2-1f11-4429-8ddd-7b06df136cbf
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754497941 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_error.754497941
Directory /workspace/1.hmac_error/latest

Test location /workspace/coverage/default/1.hmac_long_msg.2732799360
Short name T145
Test name
Test status
Simulation time 1197891222 ps
CPU time 14.65 seconds
Started Jul 01 10:42:02 AM PDT 24
Finished Jul 01 10:42:18 AM PDT 24
Peak memory 199808 kb
Host smart-2d3598b2-dcaa-4b2c-8f83-7d7ba1014803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2732799360 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_long_msg.2732799360
Directory /workspace/1.hmac_long_msg/latest

Test location /workspace/coverage/default/1.hmac_sec_cm.3944752343
Short name T44
Test name
Test status
Simulation time 82834620 ps
CPU time 0.87 seconds
Started Jul 01 10:40:40 AM PDT 24
Finished Jul 01 10:40:42 AM PDT 24
Peak memory 219512 kb
Host smart-fb80e875-6fd4-45c8-bc26-26494b6ce192
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944752343 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_sec_cm.3944752343
Directory /workspace/1.hmac_sec_cm/latest

Test location /workspace/coverage/default/1.hmac_smoke.862614025
Short name T271
Test name
Test status
Simulation time 4227092605 ps
CPU time 13.29 seconds
Started Jul 01 10:41:55 AM PDT 24
Finished Jul 01 10:42:11 AM PDT 24
Peak memory 199928 kb
Host smart-f3b31503-2c66-4c9f-8244-3b58608c0a3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862614025 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_smoke.862614025
Directory /workspace/1.hmac_smoke/latest

Test location /workspace/coverage/default/1.hmac_stress_all.2475666290
Short name T73
Test name
Test status
Simulation time 34241119988 ps
CPU time 806.83 seconds
Started Jul 01 10:42:10 AM PDT 24
Finished Jul 01 10:55:40 AM PDT 24
Peak memory 682876 kb
Host smart-778d5653-9d2d-4f77-8f35-5f15a26b8068
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475666290 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all.2475666290
Directory /workspace/1.hmac_stress_all/latest

Test location /workspace/coverage/default/1.hmac_stress_all_with_rand_reset.3394322502
Short name T24
Test name
Test status
Simulation time 21338461244 ps
CPU time 378.44 seconds
Started Jul 01 10:40:39 AM PDT 24
Finished Jul 01 10:46:58 AM PDT 24
Peak memory 255808 kb
Host smart-cc76693e-5ca6-473c-a702-96ed5d582222
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3394322502 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all_with_rand_reset.3394322502
Directory /workspace/1.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.hmac_test_hmac256_vectors.3843805218
Short name T233
Test name
Test status
Simulation time 1065688883 ps
CPU time 38.11 seconds
Started Jul 01 10:40:40 AM PDT 24
Finished Jul 01 10:41:19 AM PDT 24
Peak memory 200196 kb
Host smart-d4d6804c-eb0f-4b9a-8970-748fb7afa9e7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3843805218 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac256_vectors.3843805218
Directory /workspace/1.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_hmac384_vectors.2433643715
Short name T319
Test name
Test status
Simulation time 20969567255 ps
CPU time 60.13 seconds
Started Jul 01 10:41:01 AM PDT 24
Finished Jul 01 10:42:02 AM PDT 24
Peak memory 200324 kb
Host smart-9ac99f26-ec59-4ef0-a9ba-b21652adc50c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2433643715 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac384_vectors.2433643715
Directory /workspace/1.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_hmac512_vectors.15370611
Short name T88
Test name
Test status
Simulation time 6232658839 ps
CPU time 119.83 seconds
Started Jul 01 10:42:04 AM PDT 24
Finished Jul 01 10:44:05 AM PDT 24
Peak memory 200024 kb
Host smart-eb6dd7a1-7d25-4d0b-b57c-84e3d8f400fd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=15370611 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac512_vectors.15370611
Directory /workspace/1.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha256_vectors.3996090006
Short name T339
Test name
Test status
Simulation time 74525681226 ps
CPU time 497.29 seconds
Started Jul 01 10:41:00 AM PDT 24
Finished Jul 01 10:49:18 AM PDT 24
Peak memory 200308 kb
Host smart-6049e1a4-7841-4e41-9589-f22143a2da82
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3996090006 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha256_vectors.3996090006
Directory /workspace/1.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha384_vectors.3540096163
Short name T210
Test name
Test status
Simulation time 141557921779 ps
CPU time 2373.19 seconds
Started Jul 01 10:40:35 AM PDT 24
Finished Jul 01 11:20:10 AM PDT 24
Peak memory 216284 kb
Host smart-83e0857b-bf67-4735-b910-70dce71b1e3b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3540096163 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha384_vectors.3540096163
Directory /workspace/1.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha512_vectors.509177821
Short name T91
Test name
Test status
Simulation time 156052136345 ps
CPU time 1981.38 seconds
Started Jul 01 10:42:00 AM PDT 24
Finished Jul 01 11:15:03 AM PDT 24
Peak memory 215960 kb
Host smart-2f4c2db1-5599-4ce6-ad42-b33647f128a0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_200_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=509177821 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha512_vectors.509177821
Directory /workspace/1.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/1.hmac_wipe_secret.1101628283
Short name T472
Test name
Test status
Simulation time 2111488954 ps
CPU time 27.7 seconds
Started Jul 01 10:41:56 AM PDT 24
Finished Jul 01 10:42:26 AM PDT 24
Peak memory 199848 kb
Host smart-c5a78aee-3684-4dab-9189-3e9b9d5faece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101628283 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_wipe_secret.1101628283
Directory /workspace/1.hmac_wipe_secret/latest

Test location /workspace/coverage/default/10.hmac_alert_test.3211411105
Short name T325
Test name
Test status
Simulation time 39696495 ps
CPU time 0.57 seconds
Started Jul 01 10:41:13 AM PDT 24
Finished Jul 01 10:41:14 AM PDT 24
Peak memory 195732 kb
Host smart-3ab3d663-360e-4fdb-99d6-a28c789f5436
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211411105 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_alert_test.3211411105
Directory /workspace/10.hmac_alert_test/latest

Test location /workspace/coverage/default/10.hmac_back_pressure.3982066556
Short name T246
Test name
Test status
Simulation time 1321097944 ps
CPU time 34.94 seconds
Started Jul 01 10:41:06 AM PDT 24
Finished Jul 01 10:41:41 AM PDT 24
Peak memory 200212 kb
Host smart-a49f1337-0ea2-43df-88f2-0ba94625ac9b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3982066556 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_back_pressure.3982066556
Directory /workspace/10.hmac_back_pressure/latest

Test location /workspace/coverage/default/10.hmac_burst_wr.2063767862
Short name T34
Test name
Test status
Simulation time 1828313435 ps
CPU time 14.23 seconds
Started Jul 01 10:40:50 AM PDT 24
Finished Jul 01 10:41:05 AM PDT 24
Peak memory 200188 kb
Host smart-1e949d34-b1ed-4616-a2a9-e6dc1f032cab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063767862 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_burst_wr.2063767862
Directory /workspace/10.hmac_burst_wr/latest

Test location /workspace/coverage/default/10.hmac_datapath_stress.457163654
Short name T242
Test name
Test status
Simulation time 2944679478 ps
CPU time 496.29 seconds
Started Jul 01 10:40:55 AM PDT 24
Finished Jul 01 10:49:12 AM PDT 24
Peak memory 673952 kb
Host smart-acb5502f-0a97-4d81-ace6-86f8a5709dd7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=457163654 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_datapath_stress.457163654
Directory /workspace/10.hmac_datapath_stress/latest

Test location /workspace/coverage/default/10.hmac_error.2873238006
Short name T50
Test name
Test status
Simulation time 8674505259 ps
CPU time 37.4 seconds
Started Jul 01 10:40:46 AM PDT 24
Finished Jul 01 10:41:24 AM PDT 24
Peak memory 200192 kb
Host smart-188592e3-56b5-4f5a-831f-9dc47abd4137
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873238006 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_error.2873238006
Directory /workspace/10.hmac_error/latest

Test location /workspace/coverage/default/10.hmac_long_msg.3859395689
Short name T466
Test name
Test status
Simulation time 27721907808 ps
CPU time 87.8 seconds
Started Jul 01 10:40:57 AM PDT 24
Finished Jul 01 10:42:26 AM PDT 24
Peak memory 200404 kb
Host smart-ce94e482-73b2-4bac-a894-0480c6608141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859395689 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_long_msg.3859395689
Directory /workspace/10.hmac_long_msg/latest

Test location /workspace/coverage/default/10.hmac_smoke.20988566
Short name T189
Test name
Test status
Simulation time 75375885 ps
CPU time 3.35 seconds
Started Jul 01 10:41:07 AM PDT 24
Finished Jul 01 10:41:11 AM PDT 24
Peak memory 200152 kb
Host smart-62b36e3b-4d2f-4871-ba2b-ce4bc8d2b408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20988566 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_smoke.20988566
Directory /workspace/10.hmac_smoke/latest

Test location /workspace/coverage/default/10.hmac_stress_all.3453930773
Short name T479
Test name
Test status
Simulation time 567606451865 ps
CPU time 3604.4 seconds
Started Jul 01 10:41:05 AM PDT 24
Finished Jul 01 11:41:10 AM PDT 24
Peak memory 807620 kb
Host smart-1c3e24c7-4139-401f-bd6e-2d20fe969066
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453930773 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.hmac_stress_all.3453930773
Directory /workspace/10.hmac_stress_all/latest

Test location /workspace/coverage/default/10.hmac_wipe_secret.3778872970
Short name T96
Test name
Test status
Simulation time 4287339428 ps
CPU time 54.72 seconds
Started Jul 01 10:40:34 AM PDT 24
Finished Jul 01 10:41:30 AM PDT 24
Peak memory 200248 kb
Host smart-b087ad81-8048-4563-b736-e465c2b4d098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778872970 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_wipe_secret.3778872970
Directory /workspace/10.hmac_wipe_secret/latest

Test location /workspace/coverage/default/11.hmac_alert_test.3350463139
Short name T408
Test name
Test status
Simulation time 13065317 ps
CPU time 0.59 seconds
Started Jul 01 10:41:02 AM PDT 24
Finished Jul 01 10:41:03 AM PDT 24
Peak memory 195060 kb
Host smart-661e666d-f838-40b3-a64a-c56a31d982c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350463139 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_alert_test.3350463139
Directory /workspace/11.hmac_alert_test/latest

Test location /workspace/coverage/default/11.hmac_back_pressure.3910045070
Short name T153
Test name
Test status
Simulation time 3061892109 ps
CPU time 86.42 seconds
Started Jul 01 10:40:54 AM PDT 24
Finished Jul 01 10:42:22 AM PDT 24
Peak memory 200224 kb
Host smart-c199844d-691e-4554-ab5d-e0e767ec3ab2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3910045070 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_back_pressure.3910045070
Directory /workspace/11.hmac_back_pressure/latest

Test location /workspace/coverage/default/11.hmac_burst_wr.1613404783
Short name T244
Test name
Test status
Simulation time 8372492049 ps
CPU time 33.15 seconds
Started Jul 01 10:40:55 AM PDT 24
Finished Jul 01 10:41:29 AM PDT 24
Peak memory 200416 kb
Host smart-1328e4fe-93ae-402e-8b24-a9af786ec48e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613404783 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_burst_wr.1613404783
Directory /workspace/11.hmac_burst_wr/latest

Test location /workspace/coverage/default/11.hmac_datapath_stress.2125792575
Short name T206
Test name
Test status
Simulation time 5783791416 ps
CPU time 386.23 seconds
Started Jul 01 10:40:46 AM PDT 24
Finished Jul 01 10:47:13 AM PDT 24
Peak memory 497972 kb
Host smart-97452cbf-6b5e-47f3-ba0d-ebd41a3cf747
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2125792575 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_datapath_stress.2125792575
Directory /workspace/11.hmac_datapath_stress/latest

Test location /workspace/coverage/default/11.hmac_error.3032673709
Short name T282
Test name
Test status
Simulation time 3561457727 ps
CPU time 193.08 seconds
Started Jul 01 10:40:47 AM PDT 24
Finished Jul 01 10:44:02 AM PDT 24
Peak memory 200296 kb
Host smart-7ec89169-4f7a-4a41-9cd5-b8bca9bc6455
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032673709 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_error.3032673709
Directory /workspace/11.hmac_error/latest

Test location /workspace/coverage/default/11.hmac_long_msg.1285560137
Short name T150
Test name
Test status
Simulation time 8269836679 ps
CPU time 105.29 seconds
Started Jul 01 10:40:50 AM PDT 24
Finished Jul 01 10:42:36 AM PDT 24
Peak memory 200332 kb
Host smart-289112ed-e652-41b0-94e4-359772d0a226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285560137 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_long_msg.1285560137
Directory /workspace/11.hmac_long_msg/latest

Test location /workspace/coverage/default/11.hmac_smoke.767166572
Short name T8
Test name
Test status
Simulation time 3383347973 ps
CPU time 12.32 seconds
Started Jul 01 10:41:11 AM PDT 24
Finished Jul 01 10:41:24 AM PDT 24
Peak memory 200280 kb
Host smart-3f878a21-a037-4571-a280-18a14e62b449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767166572 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_smoke.767166572
Directory /workspace/11.hmac_smoke/latest

Test location /workspace/coverage/default/11.hmac_stress_all.426883237
Short name T349
Test name
Test status
Simulation time 59770517641 ps
CPU time 1138.75 seconds
Started Jul 01 10:40:47 AM PDT 24
Finished Jul 01 10:59:47 AM PDT 24
Peak memory 470892 kb
Host smart-35a1ed4c-c587-4fde-a081-fdf53c38e83b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426883237 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 11.hmac_stress_all.426883237
Directory /workspace/11.hmac_stress_all/latest

Test location /workspace/coverage/default/11.hmac_wipe_secret.4133970638
Short name T223
Test name
Test status
Simulation time 6709163276 ps
CPU time 22.92 seconds
Started Jul 01 10:41:06 AM PDT 24
Finished Jul 01 10:41:29 AM PDT 24
Peak memory 200320 kb
Host smart-b253277f-642a-4b95-b47a-0caffe8cc86c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133970638 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_wipe_secret.4133970638
Directory /workspace/11.hmac_wipe_secret/latest

Test location /workspace/coverage/default/12.hmac_alert_test.2479451118
Short name T276
Test name
Test status
Simulation time 29715465 ps
CPU time 0.58 seconds
Started Jul 01 10:40:53 AM PDT 24
Finished Jul 01 10:40:55 AM PDT 24
Peak memory 195728 kb
Host smart-68eae28f-9278-4d94-aeb5-e56ee02de819
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479451118 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_alert_test.2479451118
Directory /workspace/12.hmac_alert_test/latest

Test location /workspace/coverage/default/12.hmac_back_pressure.2593451401
Short name T149
Test name
Test status
Simulation time 1400277839 ps
CPU time 83.57 seconds
Started Jul 01 10:40:36 AM PDT 24
Finished Jul 01 10:42:01 AM PDT 24
Peak memory 200132 kb
Host smart-a7b593f7-c345-4e19-92de-8ce7da406ba8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2593451401 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_back_pressure.2593451401
Directory /workspace/12.hmac_back_pressure/latest

Test location /workspace/coverage/default/12.hmac_burst_wr.3938364512
Short name T173
Test name
Test status
Simulation time 1410680302 ps
CPU time 18.64 seconds
Started Jul 01 10:40:58 AM PDT 24
Finished Jul 01 10:41:17 AM PDT 24
Peak memory 200212 kb
Host smart-b5695585-75b7-4752-8d68-906d29a0eef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938364512 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_burst_wr.3938364512
Directory /workspace/12.hmac_burst_wr/latest

Test location /workspace/coverage/default/12.hmac_datapath_stress.871541670
Short name T283
Test name
Test status
Simulation time 6449447610 ps
CPU time 1526.19 seconds
Started Jul 01 10:40:42 AM PDT 24
Finished Jul 01 11:06:10 AM PDT 24
Peak memory 757772 kb
Host smart-fe806601-c8da-465f-a167-4a95dc32d96d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=871541670 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_datapath_stress.871541670
Directory /workspace/12.hmac_datapath_stress/latest

Test location /workspace/coverage/default/12.hmac_error.1259106246
Short name T166
Test name
Test status
Simulation time 5669784829 ps
CPU time 48.5 seconds
Started Jul 01 10:41:16 AM PDT 24
Finished Jul 01 10:42:07 AM PDT 24
Peak memory 200256 kb
Host smart-8ee13c7b-b1b3-4614-9229-8cce475079f0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259106246 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_error.1259106246
Directory /workspace/12.hmac_error/latest

Test location /workspace/coverage/default/12.hmac_long_msg.768284541
Short name T268
Test name
Test status
Simulation time 18343633091 ps
CPU time 169.32 seconds
Started Jul 01 10:41:08 AM PDT 24
Finished Jul 01 10:43:58 AM PDT 24
Peak memory 216688 kb
Host smart-4311a5e1-caf1-4e7b-bb7a-ec156b62c200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768284541 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_long_msg.768284541
Directory /workspace/12.hmac_long_msg/latest

Test location /workspace/coverage/default/12.hmac_smoke.1408668005
Short name T81
Test name
Test status
Simulation time 192264871 ps
CPU time 7.01 seconds
Started Jul 01 10:40:51 AM PDT 24
Finished Jul 01 10:41:00 AM PDT 24
Peak memory 200188 kb
Host smart-016c2be9-c324-426e-b197-e66f31ae51d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408668005 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_smoke.1408668005
Directory /workspace/12.hmac_smoke/latest

Test location /workspace/coverage/default/12.hmac_stress_all.3788826494
Short name T523
Test name
Test status
Simulation time 55532907479 ps
CPU time 480.42 seconds
Started Jul 01 10:41:13 AM PDT 24
Finished Jul 01 10:49:14 AM PDT 24
Peak memory 208472 kb
Host smart-a0b8fd9c-194c-4a96-9ba9-0ea49d9059fb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788826494 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.hmac_stress_all.3788826494
Directory /workspace/12.hmac_stress_all/latest

Test location /workspace/coverage/default/12.hmac_wipe_secret.3452902267
Short name T262
Test name
Test status
Simulation time 27003486067 ps
CPU time 82.46 seconds
Started Jul 01 10:40:54 AM PDT 24
Finished Jul 01 10:42:18 AM PDT 24
Peak memory 200344 kb
Host smart-38f4a076-42af-4eee-af97-d905ba987eff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452902267 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_wipe_secret.3452902267
Directory /workspace/12.hmac_wipe_secret/latest

Test location /workspace/coverage/default/13.hmac_back_pressure.2201956875
Short name T293
Test name
Test status
Simulation time 144658483 ps
CPU time 2.16 seconds
Started Jul 01 10:40:51 AM PDT 24
Finished Jul 01 10:40:59 AM PDT 24
Peak memory 200148 kb
Host smart-590f0181-ec69-423d-bf37-1d4e87094267
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2201956875 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_back_pressure.2201956875
Directory /workspace/13.hmac_back_pressure/latest

Test location /workspace/coverage/default/13.hmac_burst_wr.1262509014
Short name T385
Test name
Test status
Simulation time 3356574148 ps
CPU time 41.99 seconds
Started Jul 01 10:40:44 AM PDT 24
Finished Jul 01 10:41:27 AM PDT 24
Peak memory 200212 kb
Host smart-d8d505d0-fa45-4208-94e9-7850c7adcedb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262509014 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_burst_wr.1262509014
Directory /workspace/13.hmac_burst_wr/latest

Test location /workspace/coverage/default/13.hmac_datapath_stress.4169074604
Short name T366
Test name
Test status
Simulation time 1332925785 ps
CPU time 262.49 seconds
Started Jul 01 10:41:14 AM PDT 24
Finished Jul 01 10:45:38 AM PDT 24
Peak memory 455640 kb
Host smart-340c13e3-8842-435c-8f68-91e86bd1c191
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4169074604 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_datapath_stress.4169074604
Directory /workspace/13.hmac_datapath_stress/latest

Test location /workspace/coverage/default/13.hmac_error.2027621302
Short name T368
Test name
Test status
Simulation time 66242589492 ps
CPU time 241.72 seconds
Started Jul 01 10:40:46 AM PDT 24
Finished Jul 01 10:44:49 AM PDT 24
Peak memory 200244 kb
Host smart-eb574b6c-a1e6-4ac3-88e0-32fffe6546b6
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027621302 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_error.2027621302
Directory /workspace/13.hmac_error/latest

Test location /workspace/coverage/default/13.hmac_long_msg.2479563957
Short name T259
Test name
Test status
Simulation time 15506258937 ps
CPU time 66.55 seconds
Started Jul 01 10:40:41 AM PDT 24
Finished Jul 01 10:41:48 AM PDT 24
Peak memory 200296 kb
Host smart-9e098aa0-6bc0-4380-9f34-2cd4ad72e4fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479563957 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_long_msg.2479563957
Directory /workspace/13.hmac_long_msg/latest

Test location /workspace/coverage/default/13.hmac_smoke.1205629564
Short name T70
Test name
Test status
Simulation time 1099880666 ps
CPU time 13.33 seconds
Started Jul 01 10:40:47 AM PDT 24
Finished Jul 01 10:41:02 AM PDT 24
Peak memory 200240 kb
Host smart-563f3bb1-8817-4b4c-9cbe-24dafb241019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205629564 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_smoke.1205629564
Directory /workspace/13.hmac_smoke/latest

Test location /workspace/coverage/default/13.hmac_stress_all.3835491258
Short name T200
Test name
Test status
Simulation time 9022525030 ps
CPU time 498.06 seconds
Started Jul 01 10:40:44 AM PDT 24
Finished Jul 01 10:49:03 AM PDT 24
Peak memory 200348 kb
Host smart-a05ebb2e-a092-4f0d-a711-8c7c6a9070ab
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835491258 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.hmac_stress_all.3835491258
Directory /workspace/13.hmac_stress_all/latest

Test location /workspace/coverage/default/13.hmac_wipe_secret.340945219
Short name T486
Test name
Test status
Simulation time 18172844269 ps
CPU time 55.51 seconds
Started Jul 01 10:40:54 AM PDT 24
Finished Jul 01 10:41:51 AM PDT 24
Peak memory 200344 kb
Host smart-90aeb635-e606-4452-a59b-c4cdc50952a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340945219 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_wipe_secret.340945219
Directory /workspace/13.hmac_wipe_secret/latest

Test location /workspace/coverage/default/14.hmac_alert_test.695684420
Short name T49
Test name
Test status
Simulation time 32061073 ps
CPU time 0.62 seconds
Started Jul 01 10:40:50 AM PDT 24
Finished Jul 01 10:40:51 AM PDT 24
Peak memory 196148 kb
Host smart-493b3be0-3e58-44f2-9f57-60d97aae8dda
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695684420 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_alert_test.695684420
Directory /workspace/14.hmac_alert_test/latest

Test location /workspace/coverage/default/14.hmac_back_pressure.586274949
Short name T93
Test name
Test status
Simulation time 731162278 ps
CPU time 10.55 seconds
Started Jul 01 10:40:42 AM PDT 24
Finished Jul 01 10:40:54 AM PDT 24
Peak memory 200240 kb
Host smart-dd66c647-20c5-4fd3-a12a-351a49cfa2bb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=586274949 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_back_pressure.586274949
Directory /workspace/14.hmac_back_pressure/latest

Test location /workspace/coverage/default/14.hmac_burst_wr.3558050842
Short name T139
Test name
Test status
Simulation time 732618225 ps
CPU time 42.82 seconds
Started Jul 01 10:41:12 AM PDT 24
Finished Jul 01 10:41:56 AM PDT 24
Peak memory 200204 kb
Host smart-143c786c-68db-448c-b7a4-6ac2a81270ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558050842 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_burst_wr.3558050842
Directory /workspace/14.hmac_burst_wr/latest

Test location /workspace/coverage/default/14.hmac_datapath_stress.2405233700
Short name T527
Test name
Test status
Simulation time 1062197206 ps
CPU time 82.15 seconds
Started Jul 01 10:41:05 AM PDT 24
Finished Jul 01 10:42:28 AM PDT 24
Peak memory 328196 kb
Host smart-45e6ad59-2672-4dd0-a63c-55db5862c150
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2405233700 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_datapath_stress.2405233700
Directory /workspace/14.hmac_datapath_stress/latest

Test location /workspace/coverage/default/14.hmac_error.3659697795
Short name T337
Test name
Test status
Simulation time 14440042383 ps
CPU time 38.98 seconds
Started Jul 01 10:41:05 AM PDT 24
Finished Jul 01 10:41:45 AM PDT 24
Peak memory 200216 kb
Host smart-71bc9224-e51f-43a0-83ad-c2fe18853967
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659697795 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_error.3659697795
Directory /workspace/14.hmac_error/latest

Test location /workspace/coverage/default/14.hmac_long_msg.3559854936
Short name T165
Test name
Test status
Simulation time 5800061230 ps
CPU time 77.65 seconds
Started Jul 01 10:40:48 AM PDT 24
Finished Jul 01 10:42:07 AM PDT 24
Peak memory 200424 kb
Host smart-d1527a07-d32f-4156-8015-4477a384566f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559854936 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_long_msg.3559854936
Directory /workspace/14.hmac_long_msg/latest

Test location /workspace/coverage/default/14.hmac_smoke.579593666
Short name T332
Test name
Test status
Simulation time 13838675808 ps
CPU time 8.75 seconds
Started Jul 01 10:40:46 AM PDT 24
Finished Jul 01 10:40:58 AM PDT 24
Peak memory 200372 kb
Host smart-59c97b0c-6ada-40b1-81bf-60e088f50140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579593666 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_smoke.579593666
Directory /workspace/14.hmac_smoke/latest

Test location /workspace/coverage/default/14.hmac_stress_all.4216107884
Short name T137
Test name
Test status
Simulation time 66365195858 ps
CPU time 1598.93 seconds
Started Jul 01 10:40:49 AM PDT 24
Finished Jul 01 11:07:29 AM PDT 24
Peak memory 735864 kb
Host smart-e3e080c1-8796-45fc-bbea-f5cb58700dbc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216107884 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.hmac_stress_all.4216107884
Directory /workspace/14.hmac_stress_all/latest

Test location /workspace/coverage/default/14.hmac_wipe_secret.2070553660
Short name T478
Test name
Test status
Simulation time 6046226285 ps
CPU time 105.06 seconds
Started Jul 01 10:40:54 AM PDT 24
Finished Jul 01 10:42:40 AM PDT 24
Peak memory 200332 kb
Host smart-8f40e827-803e-4887-a239-1c26ea1cafe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070553660 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_wipe_secret.2070553660
Directory /workspace/14.hmac_wipe_secret/latest

Test location /workspace/coverage/default/15.hmac_alert_test.498321997
Short name T526
Test name
Test status
Simulation time 15797879 ps
CPU time 0.59 seconds
Started Jul 01 10:41:00 AM PDT 24
Finished Jul 01 10:41:01 AM PDT 24
Peak memory 195068 kb
Host smart-dbd25746-515d-4e14-b691-dc4417e5b184
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498321997 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_alert_test.498321997
Directory /workspace/15.hmac_alert_test/latest

Test location /workspace/coverage/default/15.hmac_back_pressure.3684418088
Short name T513
Test name
Test status
Simulation time 5599493402 ps
CPU time 70.95 seconds
Started Jul 01 10:40:49 AM PDT 24
Finished Jul 01 10:42:01 AM PDT 24
Peak memory 200532 kb
Host smart-482a86d1-9e69-4977-b9d2-6f846cbdaed6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3684418088 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_back_pressure.3684418088
Directory /workspace/15.hmac_back_pressure/latest

Test location /workspace/coverage/default/15.hmac_burst_wr.2564166354
Short name T438
Test name
Test status
Simulation time 1591988896 ps
CPU time 44.18 seconds
Started Jul 01 10:41:12 AM PDT 24
Finished Jul 01 10:41:57 AM PDT 24
Peak memory 200368 kb
Host smart-a4accf16-29b5-4783-9532-5c19fca698c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564166354 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_burst_wr.2564166354
Directory /workspace/15.hmac_burst_wr/latest

Test location /workspace/coverage/default/15.hmac_datapath_stress.1437214248
Short name T439
Test name
Test status
Simulation time 5897919821 ps
CPU time 282.46 seconds
Started Jul 01 10:40:54 AM PDT 24
Finished Jul 01 10:45:37 AM PDT 24
Peak memory 663312 kb
Host smart-8cdc2e04-9476-485c-a696-b2c5d08e98b8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1437214248 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_datapath_stress.1437214248
Directory /workspace/15.hmac_datapath_stress/latest

Test location /workspace/coverage/default/15.hmac_error.3765850477
Short name T444
Test name
Test status
Simulation time 13038518462 ps
CPU time 54.11 seconds
Started Jul 01 10:40:48 AM PDT 24
Finished Jul 01 10:41:43 AM PDT 24
Peak memory 200292 kb
Host smart-9c1f3482-9e40-4c11-a088-3ea0ca3a8b37
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765850477 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_error.3765850477
Directory /workspace/15.hmac_error/latest

Test location /workspace/coverage/default/15.hmac_long_msg.2174978085
Short name T356
Test name
Test status
Simulation time 36203784762 ps
CPU time 126.72 seconds
Started Jul 01 10:41:07 AM PDT 24
Finished Jul 01 10:43:14 AM PDT 24
Peak memory 200600 kb
Host smart-9716ca80-2072-4c93-8d51-dcac3ee779db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174978085 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_long_msg.2174978085
Directory /workspace/15.hmac_long_msg/latest

Test location /workspace/coverage/default/15.hmac_smoke.1352637387
Short name T367
Test name
Test status
Simulation time 988367022 ps
CPU time 5.86 seconds
Started Jul 01 10:40:54 AM PDT 24
Finished Jul 01 10:41:06 AM PDT 24
Peak memory 200260 kb
Host smart-b2d22eef-ac60-4cd0-849f-bb941b82b048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352637387 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_smoke.1352637387
Directory /workspace/15.hmac_smoke/latest

Test location /workspace/coverage/default/15.hmac_stress_all.2920301952
Short name T125
Test name
Test status
Simulation time 73069169489 ps
CPU time 1974.44 seconds
Started Jul 01 10:40:50 AM PDT 24
Finished Jul 01 11:13:46 AM PDT 24
Peak memory 660508 kb
Host smart-061ad30a-4233-4ceb-b61f-8ac3fc75a1a3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920301952 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.hmac_stress_all.2920301952
Directory /workspace/15.hmac_stress_all/latest

Test location /workspace/coverage/default/15.hmac_wipe_secret.1098749587
Short name T363
Test name
Test status
Simulation time 27851629190 ps
CPU time 121.03 seconds
Started Jul 01 10:41:13 AM PDT 24
Finished Jul 01 10:43:15 AM PDT 24
Peak memory 200364 kb
Host smart-a598f5ee-9456-439c-80eb-4d0f2fd537f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098749587 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_wipe_secret.1098749587
Directory /workspace/15.hmac_wipe_secret/latest

Test location /workspace/coverage/default/16.hmac_alert_test.4017460854
Short name T441
Test name
Test status
Simulation time 43844398 ps
CPU time 0.61 seconds
Started Jul 01 10:40:45 AM PDT 24
Finished Jul 01 10:40:47 AM PDT 24
Peak memory 196104 kb
Host smart-27c2da2b-b41f-47a2-aed9-ea707b110ecc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017460854 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_alert_test.4017460854
Directory /workspace/16.hmac_alert_test/latest

Test location /workspace/coverage/default/16.hmac_back_pressure.185222647
Short name T37
Test name
Test status
Simulation time 1142438543 ps
CPU time 63.92 seconds
Started Jul 01 10:41:10 AM PDT 24
Finished Jul 01 10:42:14 AM PDT 24
Peak memory 200200 kb
Host smart-77224415-c57f-47ba-b244-8cfd96ce620a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=185222647 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_back_pressure.185222647
Directory /workspace/16.hmac_back_pressure/latest

Test location /workspace/coverage/default/16.hmac_burst_wr.1184889962
Short name T213
Test name
Test status
Simulation time 3450497270 ps
CPU time 68.39 seconds
Started Jul 01 10:40:46 AM PDT 24
Finished Jul 01 10:41:56 AM PDT 24
Peak memory 200248 kb
Host smart-de872f08-95f9-4110-98f2-fb4933a67ab9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184889962 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_burst_wr.1184889962
Directory /workspace/16.hmac_burst_wr/latest

Test location /workspace/coverage/default/16.hmac_datapath_stress.3462086325
Short name T299
Test name
Test status
Simulation time 8547327795 ps
CPU time 262.76 seconds
Started Jul 01 10:40:57 AM PDT 24
Finished Jul 01 10:45:21 AM PDT 24
Peak memory 463232 kb
Host smart-6a72a4c9-c40b-4412-acc2-f3232b670930
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3462086325 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_datapath_stress.3462086325
Directory /workspace/16.hmac_datapath_stress/latest

Test location /workspace/coverage/default/16.hmac_error.1382119123
Short name T456
Test name
Test status
Simulation time 22620917949 ps
CPU time 256.89 seconds
Started Jul 01 10:41:04 AM PDT 24
Finished Jul 01 10:45:22 AM PDT 24
Peak memory 200332 kb
Host smart-5682fd67-53e4-44ce-860c-d9db6267c1ca
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382119123 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_error.1382119123
Directory /workspace/16.hmac_error/latest

Test location /workspace/coverage/default/16.hmac_long_msg.3596734671
Short name T380
Test name
Test status
Simulation time 6407099494 ps
CPU time 83.79 seconds
Started Jul 01 10:41:08 AM PDT 24
Finished Jul 01 10:42:32 AM PDT 24
Peak memory 200284 kb
Host smart-c29d345c-a8f5-434a-a3e8-07543b63e34b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596734671 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_long_msg.3596734671
Directory /workspace/16.hmac_long_msg/latest

Test location /workspace/coverage/default/16.hmac_smoke.3616233545
Short name T172
Test name
Test status
Simulation time 352755815 ps
CPU time 5.09 seconds
Started Jul 01 10:41:08 AM PDT 24
Finished Jul 01 10:41:14 AM PDT 24
Peak memory 200216 kb
Host smart-52d94b89-2001-4fc5-8ecd-a444743e4fc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3616233545 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_smoke.3616233545
Directory /workspace/16.hmac_smoke/latest

Test location /workspace/coverage/default/16.hmac_stress_all.3780151596
Short name T463
Test name
Test status
Simulation time 35353840459 ps
CPU time 469.37 seconds
Started Jul 01 10:41:08 AM PDT 24
Finished Jul 01 10:48:58 AM PDT 24
Peak memory 200320 kb
Host smart-ee9c0d19-7dcc-4220-9dc4-fdba08b5ceec
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780151596 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.hmac_stress_all.3780151596
Directory /workspace/16.hmac_stress_all/latest

Test location /workspace/coverage/default/16.hmac_wipe_secret.2815903938
Short name T482
Test name
Test status
Simulation time 2950944647 ps
CPU time 24.74 seconds
Started Jul 01 10:41:10 AM PDT 24
Finished Jul 01 10:41:35 AM PDT 24
Peak memory 200376 kb
Host smart-eca0286b-e0d7-41b5-9bc5-35790b68bbc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815903938 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_wipe_secret.2815903938
Directory /workspace/16.hmac_wipe_secret/latest

Test location /workspace/coverage/default/17.hmac_alert_test.3524537104
Short name T275
Test name
Test status
Simulation time 11684129 ps
CPU time 0.61 seconds
Started Jul 01 10:40:57 AM PDT 24
Finished Jul 01 10:40:59 AM PDT 24
Peak memory 196128 kb
Host smart-a1e8c40f-eb50-4d58-8ad4-e8708c1cc381
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524537104 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_alert_test.3524537104
Directory /workspace/17.hmac_alert_test/latest

Test location /workspace/coverage/default/17.hmac_back_pressure.3510820569
Short name T485
Test name
Test status
Simulation time 7373156617 ps
CPU time 46.54 seconds
Started Jul 01 10:40:45 AM PDT 24
Finished Jul 01 10:41:32 AM PDT 24
Peak memory 200316 kb
Host smart-76601745-d8e8-4bc8-b869-e5364a861f65
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3510820569 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_back_pressure.3510820569
Directory /workspace/17.hmac_back_pressure/latest

Test location /workspace/coverage/default/17.hmac_burst_wr.3689867626
Short name T5
Test name
Test status
Simulation time 32913839782 ps
CPU time 103.47 seconds
Started Jul 01 10:40:53 AM PDT 24
Finished Jul 01 10:42:37 AM PDT 24
Peak memory 200264 kb
Host smart-466d8e2d-e602-450c-bc11-da6ed66474fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689867626 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_burst_wr.3689867626
Directory /workspace/17.hmac_burst_wr/latest

Test location /workspace/coverage/default/17.hmac_datapath_stress.702819390
Short name T347
Test name
Test status
Simulation time 6207693225 ps
CPU time 1249.37 seconds
Started Jul 01 10:40:55 AM PDT 24
Finished Jul 01 11:01:45 AM PDT 24
Peak memory 732240 kb
Host smart-46c0248c-3d51-4dc0-a674-7d6976928188
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=702819390 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_datapath_stress.702819390
Directory /workspace/17.hmac_datapath_stress/latest

Test location /workspace/coverage/default/17.hmac_error.1853984618
Short name T251
Test name
Test status
Simulation time 55374352059 ps
CPU time 152.62 seconds
Started Jul 01 10:41:10 AM PDT 24
Finished Jul 01 10:43:44 AM PDT 24
Peak memory 200616 kb
Host smart-78abb3da-6508-4e8b-901d-d6d55fa85674
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853984618 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_error.1853984618
Directory /workspace/17.hmac_error/latest

Test location /workspace/coverage/default/17.hmac_long_msg.1210182161
Short name T447
Test name
Test status
Simulation time 17719163662 ps
CPU time 183.64 seconds
Started Jul 01 10:41:13 AM PDT 24
Finished Jul 01 10:44:18 AM PDT 24
Peak memory 200464 kb
Host smart-d0956d28-47e9-4e9a-9554-c756f90063a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210182161 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_long_msg.1210182161
Directory /workspace/17.hmac_long_msg/latest

Test location /workspace/coverage/default/17.hmac_smoke.2339329360
Short name T186
Test name
Test status
Simulation time 235759528 ps
CPU time 3.1 seconds
Started Jul 01 10:41:13 AM PDT 24
Finished Jul 01 10:41:18 AM PDT 24
Peak memory 200232 kb
Host smart-ce45c68e-e9c7-4e24-b025-1e0dbdaa5bb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339329360 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_smoke.2339329360
Directory /workspace/17.hmac_smoke/latest

Test location /workspace/coverage/default/17.hmac_stress_all.4125586760
Short name T74
Test name
Test status
Simulation time 34555483076 ps
CPU time 400.54 seconds
Started Jul 01 10:41:12 AM PDT 24
Finished Jul 01 10:47:53 AM PDT 24
Peak memory 200260 kb
Host smart-2fc28838-d1b3-422f-badb-3163be4312a2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125586760 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.hmac_stress_all.4125586760
Directory /workspace/17.hmac_stress_all/latest

Test location /workspace/coverage/default/17.hmac_wipe_secret.980633262
Short name T294
Test name
Test status
Simulation time 466583736 ps
CPU time 20.81 seconds
Started Jul 01 10:41:09 AM PDT 24
Finished Jul 01 10:41:31 AM PDT 24
Peak memory 200212 kb
Host smart-f0136af9-8966-477b-8fa4-947ac6597217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980633262 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_wipe_secret.980633262
Directory /workspace/17.hmac_wipe_secret/latest

Test location /workspace/coverage/default/18.hmac_alert_test.2275569625
Short name T221
Test name
Test status
Simulation time 13024224 ps
CPU time 0.61 seconds
Started Jul 01 10:41:15 AM PDT 24
Finished Jul 01 10:41:17 AM PDT 24
Peak memory 196816 kb
Host smart-c5a01417-a622-4173-b164-aec2080507b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275569625 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_alert_test.2275569625
Directory /workspace/18.hmac_alert_test/latest

Test location /workspace/coverage/default/18.hmac_back_pressure.1396839537
Short name T301
Test name
Test status
Simulation time 953729951 ps
CPU time 48.36 seconds
Started Jul 01 10:41:18 AM PDT 24
Finished Jul 01 10:42:09 AM PDT 24
Peak memory 200100 kb
Host smart-5dcafc8e-1784-4cc2-a94e-5791c529a601
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1396839537 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_back_pressure.1396839537
Directory /workspace/18.hmac_back_pressure/latest

Test location /workspace/coverage/default/18.hmac_burst_wr.3156904578
Short name T193
Test name
Test status
Simulation time 2358733894 ps
CPU time 30.92 seconds
Started Jul 01 10:41:12 AM PDT 24
Finished Jul 01 10:41:44 AM PDT 24
Peak memory 200236 kb
Host smart-f26a65ef-e738-4491-9962-3844c80dd706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156904578 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_burst_wr.3156904578
Directory /workspace/18.hmac_burst_wr/latest

Test location /workspace/coverage/default/18.hmac_datapath_stress.2577131437
Short name T446
Test name
Test status
Simulation time 989945063 ps
CPU time 129.43 seconds
Started Jul 01 10:41:12 AM PDT 24
Finished Jul 01 10:43:23 AM PDT 24
Peak memory 432580 kb
Host smart-67b9407a-bece-4b8f-a64e-e2571200aae2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2577131437 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_datapath_stress.2577131437
Directory /workspace/18.hmac_datapath_stress/latest

Test location /workspace/coverage/default/18.hmac_error.3892115591
Short name T433
Test name
Test status
Simulation time 18862188855 ps
CPU time 41.98 seconds
Started Jul 01 10:40:49 AM PDT 24
Finished Jul 01 10:41:32 AM PDT 24
Peak memory 200288 kb
Host smart-61a5058b-e5b5-4650-9737-3df75cad5aba
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892115591 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_error.3892115591
Directory /workspace/18.hmac_error/latest

Test location /workspace/coverage/default/18.hmac_long_msg.1014161371
Short name T163
Test name
Test status
Simulation time 26872557700 ps
CPU time 145.93 seconds
Started Jul 01 10:40:51 AM PDT 24
Finished Jul 01 10:43:19 AM PDT 24
Peak memory 200612 kb
Host smart-44e491ea-6f26-4c60-a008-6f3e3b95d82f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014161371 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_long_msg.1014161371
Directory /workspace/18.hmac_long_msg/latest

Test location /workspace/coverage/default/18.hmac_smoke.3570603588
Short name T322
Test name
Test status
Simulation time 146166012 ps
CPU time 5.56 seconds
Started Jul 01 10:40:47 AM PDT 24
Finished Jul 01 10:40:54 AM PDT 24
Peak memory 200244 kb
Host smart-aaffa637-045a-4b96-b149-0db6fdb7911d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570603588 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_smoke.3570603588
Directory /workspace/18.hmac_smoke/latest

Test location /workspace/coverage/default/18.hmac_stress_all.4118395876
Short name T425
Test name
Test status
Simulation time 42072950145 ps
CPU time 167.51 seconds
Started Jul 01 10:40:59 AM PDT 24
Finished Jul 01 10:43:47 AM PDT 24
Peak memory 200508 kb
Host smart-fdff58ab-2a9f-42d3-b175-44dac10c78ca
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118395876 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.hmac_stress_all.4118395876
Directory /workspace/18.hmac_stress_all/latest

Test location /workspace/coverage/default/18.hmac_wipe_secret.1861803737
Short name T247
Test name
Test status
Simulation time 108032904 ps
CPU time 6.28 seconds
Started Jul 01 10:41:15 AM PDT 24
Finished Jul 01 10:41:27 AM PDT 24
Peak memory 200264 kb
Host smart-a68f5a61-f2e8-466a-bdec-aa94cbc0256f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861803737 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_wipe_secret.1861803737
Directory /workspace/18.hmac_wipe_secret/latest

Test location /workspace/coverage/default/19.hmac_alert_test.4091313178
Short name T510
Test name
Test status
Simulation time 18440574 ps
CPU time 0.59 seconds
Started Jul 01 10:41:06 AM PDT 24
Finished Jul 01 10:41:07 AM PDT 24
Peak memory 196084 kb
Host smart-d91e8aad-11d2-4acb-9955-26f4a35e02db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091313178 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_alert_test.4091313178
Directory /workspace/19.hmac_alert_test/latest

Test location /workspace/coverage/default/19.hmac_back_pressure.152618306
Short name T407
Test name
Test status
Simulation time 1121424823 ps
CPU time 59.26 seconds
Started Jul 01 10:40:59 AM PDT 24
Finished Jul 01 10:41:59 AM PDT 24
Peak memory 200212 kb
Host smart-c914da8f-5aa9-43ca-b78c-8da7a09bedcc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=152618306 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_back_pressure.152618306
Directory /workspace/19.hmac_back_pressure/latest

Test location /workspace/coverage/default/19.hmac_burst_wr.255664694
Short name T483
Test name
Test status
Simulation time 2411355824 ps
CPU time 34.28 seconds
Started Jul 01 10:41:07 AM PDT 24
Finished Jul 01 10:41:42 AM PDT 24
Peak memory 200360 kb
Host smart-c211a808-f5f7-4c69-80e9-89ee8eb33049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255664694 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_burst_wr.255664694
Directory /workspace/19.hmac_burst_wr/latest

Test location /workspace/coverage/default/19.hmac_datapath_stress.3445134840
Short name T289
Test name
Test status
Simulation time 6827825428 ps
CPU time 555.74 seconds
Started Jul 01 10:41:00 AM PDT 24
Finished Jul 01 10:50:17 AM PDT 24
Peak memory 677460 kb
Host smart-99dc0bb4-3011-48e2-a5cd-f02b4e85468c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3445134840 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_datapath_stress.3445134840
Directory /workspace/19.hmac_datapath_stress/latest

Test location /workspace/coverage/default/19.hmac_error.36208756
Short name T285
Test name
Test status
Simulation time 34741433598 ps
CPU time 80.11 seconds
Started Jul 01 10:41:16 AM PDT 24
Finished Jul 01 10:42:40 AM PDT 24
Peak memory 200152 kb
Host smart-c85bf049-6e34-4dc4-ab9b-34ed6a2a7f16
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36208756 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_error.36208756
Directory /workspace/19.hmac_error/latest

Test location /workspace/coverage/default/19.hmac_long_msg.2915560209
Short name T418
Test name
Test status
Simulation time 539663650 ps
CPU time 15.12 seconds
Started Jul 01 10:41:12 AM PDT 24
Finished Jul 01 10:41:28 AM PDT 24
Peak memory 200268 kb
Host smart-8bb78cb9-f009-4525-b937-a25be84f4dfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915560209 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_long_msg.2915560209
Directory /workspace/19.hmac_long_msg/latest

Test location /workspace/coverage/default/19.hmac_smoke.2566423465
Short name T309
Test name
Test status
Simulation time 162122083 ps
CPU time 8.03 seconds
Started Jul 01 10:40:53 AM PDT 24
Finished Jul 01 10:41:02 AM PDT 24
Peak memory 200204 kb
Host smart-46d55955-8f6a-4925-ae75-874cc88abf33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566423465 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_smoke.2566423465
Directory /workspace/19.hmac_smoke/latest

Test location /workspace/coverage/default/19.hmac_stress_all.63060293
Short name T499
Test name
Test status
Simulation time 5737336284 ps
CPU time 307.49 seconds
Started Jul 01 10:40:53 AM PDT 24
Finished Jul 01 10:46:02 AM PDT 24
Peak memory 208588 kb
Host smart-2a15a640-dcba-41e0-9086-2c92ab7b3440
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63060293 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 19.hmac_stress_all.63060293
Directory /workspace/19.hmac_stress_all/latest

Test location /workspace/coverage/default/19.hmac_wipe_secret.3189947977
Short name T55
Test name
Test status
Simulation time 894147927 ps
CPU time 24.29 seconds
Started Jul 01 10:41:13 AM PDT 24
Finished Jul 01 10:41:38 AM PDT 24
Peak memory 200200 kb
Host smart-a9e77277-b8dd-4fd9-b7b7-6e35514d6fde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189947977 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_wipe_secret.3189947977
Directory /workspace/19.hmac_wipe_secret/latest

Test location /workspace/coverage/default/2.hmac_alert_test.512165830
Short name T493
Test name
Test status
Simulation time 22551169 ps
CPU time 0.58 seconds
Started Jul 01 10:41:14 AM PDT 24
Finished Jul 01 10:41:22 AM PDT 24
Peak memory 195096 kb
Host smart-a4fd0c00-6133-43dc-a165-60eb7dbe7030
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512165830 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_alert_test.512165830
Directory /workspace/2.hmac_alert_test/latest

Test location /workspace/coverage/default/2.hmac_back_pressure.129693540
Short name T32
Test name
Test status
Simulation time 4807745004 ps
CPU time 70.66 seconds
Started Jul 01 10:40:39 AM PDT 24
Finished Jul 01 10:41:50 AM PDT 24
Peak memory 216548 kb
Host smart-0362eb18-4dba-4428-834f-a56b428b889a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=129693540 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_back_pressure.129693540
Directory /workspace/2.hmac_back_pressure/latest

Test location /workspace/coverage/default/2.hmac_burst_wr.3397715363
Short name T295
Test name
Test status
Simulation time 16612008430 ps
CPU time 39.29 seconds
Started Jul 01 10:40:49 AM PDT 24
Finished Jul 01 10:41:29 AM PDT 24
Peak memory 200388 kb
Host smart-8c04ad4b-5d5a-4955-9e53-917c4cfd0810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397715363 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_burst_wr.3397715363
Directory /workspace/2.hmac_burst_wr/latest

Test location /workspace/coverage/default/2.hmac_datapath_stress.728438790
Short name T255
Test name
Test status
Simulation time 37241065052 ps
CPU time 818.15 seconds
Started Jul 01 10:41:37 AM PDT 24
Finished Jul 01 10:55:16 AM PDT 24
Peak memory 611256 kb
Host smart-9c60ea50-e9bf-4021-b4e1-0bee7d013fad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=728438790 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_datapath_stress.728438790
Directory /workspace/2.hmac_datapath_stress/latest

Test location /workspace/coverage/default/2.hmac_error.2894577140
Short name T154
Test name
Test status
Simulation time 18838310307 ps
CPU time 60.59 seconds
Started Jul 01 10:41:40 AM PDT 24
Finished Jul 01 10:42:42 AM PDT 24
Peak memory 198660 kb
Host smart-6b878b82-8d6b-4c0b-8d8f-d100fb840c59
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894577140 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_error.2894577140
Directory /workspace/2.hmac_error/latest

Test location /workspace/coverage/default/2.hmac_long_msg.3076448728
Short name T430
Test name
Test status
Simulation time 42023822929 ps
CPU time 124.5 seconds
Started Jul 01 10:41:04 AM PDT 24
Finished Jul 01 10:43:09 AM PDT 24
Peak memory 200460 kb
Host smart-75c797dd-990e-43bf-9572-c8d994a71778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3076448728 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_long_msg.3076448728
Directory /workspace/2.hmac_long_msg/latest

Test location /workspace/coverage/default/2.hmac_sec_cm.104863249
Short name T45
Test name
Test status
Simulation time 314862755 ps
CPU time 1 seconds
Started Jul 01 10:40:42 AM PDT 24
Finished Jul 01 10:40:43 AM PDT 24
Peak memory 219604 kb
Host smart-a4631eae-3cb0-4d7e-8b90-115bdf6e52db
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104863249 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_sec_cm.104863249
Directory /workspace/2.hmac_sec_cm/latest

Test location /workspace/coverage/default/2.hmac_smoke.4149773290
Short name T530
Test name
Test status
Simulation time 28242790 ps
CPU time 0.88 seconds
Started Jul 01 10:40:43 AM PDT 24
Finished Jul 01 10:40:46 AM PDT 24
Peak memory 199972 kb
Host smart-05900fa5-51b2-4d21-9a21-1ff1c837652b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149773290 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_smoke.4149773290
Directory /workspace/2.hmac_smoke/latest

Test location /workspace/coverage/default/2.hmac_stress_all.412868991
Short name T100
Test name
Test status
Simulation time 26623868397 ps
CPU time 2439.22 seconds
Started Jul 01 10:40:33 AM PDT 24
Finished Jul 01 11:21:14 AM PDT 24
Peak memory 770196 kb
Host smart-53cc013d-f710-4354-9b16-e185256728cc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412868991 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all.412868991
Directory /workspace/2.hmac_stress_all/latest

Test location /workspace/coverage/default/2.hmac_test_hmac256_vectors.4245097824
Short name T270
Test name
Test status
Simulation time 2664796909 ps
CPU time 41.97 seconds
Started Jul 01 10:40:36 AM PDT 24
Finished Jul 01 10:41:19 AM PDT 24
Peak memory 200224 kb
Host smart-39931f1a-87d1-4517-b4c2-ec849d9f6465
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4245097824 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac256_vectors.4245097824
Directory /workspace/2.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_hmac384_vectors.622851819
Short name T292
Test name
Test status
Simulation time 7867284534 ps
CPU time 89.11 seconds
Started Jul 01 10:41:40 AM PDT 24
Finished Jul 01 10:43:11 AM PDT 24
Peak memory 198652 kb
Host smart-653de016-eb1c-406d-9a91-a32de4f26c0d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=622851819 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac384_vectors.622851819
Directory /workspace/2.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_hmac512_vectors.3814119173
Short name T162
Test name
Test status
Simulation time 9928799809 ps
CPU time 76.05 seconds
Started Jul 01 10:40:36 AM PDT 24
Finished Jul 01 10:41:52 AM PDT 24
Peak memory 200300 kb
Host smart-25127828-7faf-47da-a9b7-6d77c988439f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3814119173 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac512_vectors.3814119173
Directory /workspace/2.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha256_vectors.3238147032
Short name T267
Test name
Test status
Simulation time 32954368450 ps
CPU time 558.15 seconds
Started Jul 01 10:40:54 AM PDT 24
Finished Jul 01 10:50:13 AM PDT 24
Peak memory 200324 kb
Host smart-6e13f488-f664-4ea4-9539-404c54e322ec
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3238147032 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha256_vectors.3238147032
Directory /workspace/2.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha384_vectors.700597233
Short name T324
Test name
Test status
Simulation time 340243219907 ps
CPU time 2170.43 seconds
Started Jul 01 10:42:00 AM PDT 24
Finished Jul 01 11:18:12 AM PDT 24
Peak memory 215364 kb
Host smart-4f7a0e5a-2e5f-4393-b108-509ad159eee6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=700597233 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha384_vectors.700597233
Directory /workspace/2.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha512_vectors.3808358191
Short name T509
Test name
Test status
Simulation time 182640564126 ps
CPU time 2362.03 seconds
Started Jul 01 10:40:49 AM PDT 24
Finished Jul 01 11:20:12 AM PDT 24
Peak memory 216708 kb
Host smart-115d0b85-822f-4975-bd7d-19db516c89e8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_200_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3808358191 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha512_vectors.3808358191
Directory /workspace/2.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/2.hmac_wipe_secret.3240993553
Short name T303
Test name
Test status
Simulation time 2224824742 ps
CPU time 29.33 seconds
Started Jul 01 10:42:02 AM PDT 24
Finished Jul 01 10:42:32 AM PDT 24
Peak memory 199852 kb
Host smart-aaa2a741-6518-4ed1-9608-7271d4fd81cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3240993553 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_wipe_secret.3240993553
Directory /workspace/2.hmac_wipe_secret/latest

Test location /workspace/coverage/default/20.hmac_alert_test.182383416
Short name T41
Test name
Test status
Simulation time 18639068 ps
CPU time 0.61 seconds
Started Jul 01 10:41:14 AM PDT 24
Finished Jul 01 10:41:16 AM PDT 24
Peak memory 196816 kb
Host smart-6746031d-d11b-4c0b-8020-6be78183be63
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182383416 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_alert_test.182383416
Directory /workspace/20.hmac_alert_test/latest

Test location /workspace/coverage/default/20.hmac_back_pressure.537557449
Short name T227
Test name
Test status
Simulation time 812756063 ps
CPU time 45.16 seconds
Started Jul 01 10:41:17 AM PDT 24
Finished Jul 01 10:42:06 AM PDT 24
Peak memory 200200 kb
Host smart-8a0928bd-cc06-40c4-9daf-d3a3cefce2bf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=537557449 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_back_pressure.537557449
Directory /workspace/20.hmac_back_pressure/latest

Test location /workspace/coverage/default/20.hmac_burst_wr.4081123305
Short name T195
Test name
Test status
Simulation time 2134522070 ps
CPU time 30.32 seconds
Started Jul 01 10:40:50 AM PDT 24
Finished Jul 01 10:41:21 AM PDT 24
Peak memory 200220 kb
Host smart-7070ab17-720c-4292-8a84-4d59f0652498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081123305 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_burst_wr.4081123305
Directory /workspace/20.hmac_burst_wr/latest

Test location /workspace/coverage/default/20.hmac_datapath_stress.1222833053
Short name T507
Test name
Test status
Simulation time 4726413559 ps
CPU time 271.33 seconds
Started Jul 01 10:41:14 AM PDT 24
Finished Jul 01 10:45:48 AM PDT 24
Peak memory 461436 kb
Host smart-9a37da3b-4f1c-408a-a42e-b0109528b386
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1222833053 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_datapath_stress.1222833053
Directory /workspace/20.hmac_datapath_stress/latest

Test location /workspace/coverage/default/20.hmac_error.2489686355
Short name T336
Test name
Test status
Simulation time 92708605 ps
CPU time 5.03 seconds
Started Jul 01 10:40:59 AM PDT 24
Finished Jul 01 10:41:04 AM PDT 24
Peak memory 200072 kb
Host smart-0a3de4e9-cb6c-4b83-9dd7-252018c05e7d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489686355 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_error.2489686355
Directory /workspace/20.hmac_error/latest

Test location /workspace/coverage/default/20.hmac_long_msg.145748572
Short name T399
Test name
Test status
Simulation time 28439766883 ps
CPU time 89.5 seconds
Started Jul 01 10:40:51 AM PDT 24
Finished Jul 01 10:42:22 AM PDT 24
Peak memory 208540 kb
Host smart-490f1084-5710-48bc-ac1d-58d794489601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145748572 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_long_msg.145748572
Directory /workspace/20.hmac_long_msg/latest

Test location /workspace/coverage/default/20.hmac_smoke.2722629606
Short name T3
Test name
Test status
Simulation time 239666740 ps
CPU time 3.65 seconds
Started Jul 01 10:40:51 AM PDT 24
Finished Jul 01 10:40:56 AM PDT 24
Peak memory 200192 kb
Host smart-2a9715ba-90ad-45e8-9385-aaa0f5418a8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722629606 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_smoke.2722629606
Directory /workspace/20.hmac_smoke/latest

Test location /workspace/coverage/default/20.hmac_stress_all.2764668476
Short name T124
Test name
Test status
Simulation time 179762184938 ps
CPU time 810.65 seconds
Started Jul 01 10:41:15 AM PDT 24
Finished Jul 01 10:54:48 AM PDT 24
Peak memory 216716 kb
Host smart-a19a9d1b-8537-4c1f-991f-85285ae7922c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764668476 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.hmac_stress_all.2764668476
Directory /workspace/20.hmac_stress_all/latest

Test location /workspace/coverage/default/20.hmac_wipe_secret.3203021576
Short name T314
Test name
Test status
Simulation time 705182565 ps
CPU time 31.35 seconds
Started Jul 01 10:41:02 AM PDT 24
Finished Jul 01 10:41:34 AM PDT 24
Peak memory 200212 kb
Host smart-8a465eb0-33f5-43d6-8d7b-4a2ee6f1b4bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203021576 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_wipe_secret.3203021576
Directory /workspace/20.hmac_wipe_secret/latest

Test location /workspace/coverage/default/21.hmac_alert_test.4037258406
Short name T71
Test name
Test status
Simulation time 71411193 ps
CPU time 0.61 seconds
Started Jul 01 10:41:03 AM PDT 24
Finished Jul 01 10:41:04 AM PDT 24
Peak memory 196072 kb
Host smart-89010ba2-268f-448e-8fd5-43c5ee587662
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037258406 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_alert_test.4037258406
Directory /workspace/21.hmac_alert_test/latest

Test location /workspace/coverage/default/21.hmac_back_pressure.1513113361
Short name T229
Test name
Test status
Simulation time 1336563063 ps
CPU time 58.93 seconds
Started Jul 01 10:41:16 AM PDT 24
Finished Jul 01 10:42:19 AM PDT 24
Peak memory 200244 kb
Host smart-f19334c2-fab8-497e-a213-8fd9156cc6a9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1513113361 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_back_pressure.1513113361
Directory /workspace/21.hmac_back_pressure/latest

Test location /workspace/coverage/default/21.hmac_burst_wr.1404491519
Short name T377
Test name
Test status
Simulation time 9728014645 ps
CPU time 33.94 seconds
Started Jul 01 10:41:16 AM PDT 24
Finished Jul 01 10:41:54 AM PDT 24
Peak memory 200352 kb
Host smart-943158ed-2180-4533-8cac-0be13f0e1237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404491519 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_burst_wr.1404491519
Directory /workspace/21.hmac_burst_wr/latest

Test location /workspace/coverage/default/21.hmac_datapath_stress.1449006209
Short name T341
Test name
Test status
Simulation time 8262942308 ps
CPU time 328.33 seconds
Started Jul 01 10:41:16 AM PDT 24
Finished Jul 01 10:46:48 AM PDT 24
Peak memory 618408 kb
Host smart-9151bc98-2849-4f02-8168-e3cd090b407a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1449006209 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_datapath_stress.1449006209
Directory /workspace/21.hmac_datapath_stress/latest

Test location /workspace/coverage/default/21.hmac_error.28178904
Short name T373
Test name
Test status
Simulation time 318834848 ps
CPU time 4.57 seconds
Started Jul 01 10:41:09 AM PDT 24
Finished Jul 01 10:41:14 AM PDT 24
Peak memory 200064 kb
Host smart-7a89a716-15da-4fdd-9720-e72a70241fbf
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28178904 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_error.28178904
Directory /workspace/21.hmac_error/latest

Test location /workspace/coverage/default/21.hmac_long_msg.2764828218
Short name T217
Test name
Test status
Simulation time 17422330708 ps
CPU time 41.56 seconds
Started Jul 01 10:41:14 AM PDT 24
Finished Jul 01 10:41:58 AM PDT 24
Peak memory 200340 kb
Host smart-55278866-8c94-4ed0-9b0d-11775b883224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764828218 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_long_msg.2764828218
Directory /workspace/21.hmac_long_msg/latest

Test location /workspace/coverage/default/21.hmac_smoke.3562151639
Short name T284
Test name
Test status
Simulation time 1003750191 ps
CPU time 11.52 seconds
Started Jul 01 10:41:10 AM PDT 24
Finished Jul 01 10:41:22 AM PDT 24
Peak memory 200180 kb
Host smart-2d16ac3b-4d6b-478e-84b0-551d1358cd70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562151639 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_smoke.3562151639
Directory /workspace/21.hmac_smoke/latest

Test location /workspace/coverage/default/21.hmac_stress_all.1709844805
Short name T263
Test name
Test status
Simulation time 56698620314 ps
CPU time 995.24 seconds
Started Jul 01 10:41:02 AM PDT 24
Finished Jul 01 10:57:38 AM PDT 24
Peak memory 200288 kb
Host smart-e43e25de-3be8-42ea-bb5f-ee48d565246c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709844805 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.hmac_stress_all.1709844805
Directory /workspace/21.hmac_stress_all/latest

Test location /workspace/coverage/default/21.hmac_wipe_secret.3373839101
Short name T389
Test name
Test status
Simulation time 10759752130 ps
CPU time 47.52 seconds
Started Jul 01 10:40:52 AM PDT 24
Finished Jul 01 10:41:41 AM PDT 24
Peak memory 200340 kb
Host smart-710e985f-0e15-4056-bc58-dab28f5b2415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373839101 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_wipe_secret.3373839101
Directory /workspace/21.hmac_wipe_secret/latest

Test location /workspace/coverage/default/22.hmac_alert_test.2236095836
Short name T497
Test name
Test status
Simulation time 28061100 ps
CPU time 0.58 seconds
Started Jul 01 10:41:12 AM PDT 24
Finished Jul 01 10:41:14 AM PDT 24
Peak memory 196092 kb
Host smart-26e9dc5f-b396-44fa-905e-495eab442aa9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236095836 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_alert_test.2236095836
Directory /workspace/22.hmac_alert_test/latest

Test location /workspace/coverage/default/22.hmac_back_pressure.2501682552
Short name T158
Test name
Test status
Simulation time 5729428155 ps
CPU time 32.9 seconds
Started Jul 01 10:40:56 AM PDT 24
Finished Jul 01 10:41:30 AM PDT 24
Peak memory 200460 kb
Host smart-31af9688-3f2c-493d-8c1e-7d5bd7036de2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2501682552 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_back_pressure.2501682552
Directory /workspace/22.hmac_back_pressure/latest

Test location /workspace/coverage/default/22.hmac_burst_wr.1181909851
Short name T36
Test name
Test status
Simulation time 4145721393 ps
CPU time 49.9 seconds
Started Jul 01 10:41:00 AM PDT 24
Finished Jul 01 10:41:50 AM PDT 24
Peak memory 200312 kb
Host smart-35b5c1b7-cf47-447a-b599-3d732aef0496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181909851 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_burst_wr.1181909851
Directory /workspace/22.hmac_burst_wr/latest

Test location /workspace/coverage/default/22.hmac_datapath_stress.3181834489
Short name T501
Test name
Test status
Simulation time 2121440406 ps
CPU time 386.61 seconds
Started Jul 01 10:41:05 AM PDT 24
Finished Jul 01 10:47:32 AM PDT 24
Peak memory 626488 kb
Host smart-5d907784-3e0b-47d9-a7a2-0ca94ac19be2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3181834489 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_datapath_stress.3181834489
Directory /workspace/22.hmac_datapath_stress/latest

Test location /workspace/coverage/default/22.hmac_error.2040397578
Short name T224
Test name
Test status
Simulation time 14187100110 ps
CPU time 63.01 seconds
Started Jul 01 10:41:16 AM PDT 24
Finished Jul 01 10:42:31 AM PDT 24
Peak memory 200308 kb
Host smart-9584bfb0-db9e-4bcd-b68e-78266aed0f86
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040397578 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_error.2040397578
Directory /workspace/22.hmac_error/latest

Test location /workspace/coverage/default/22.hmac_long_msg.3121646391
Short name T48
Test name
Test status
Simulation time 3895003315 ps
CPU time 67.21 seconds
Started Jul 01 10:41:15 AM PDT 24
Finished Jul 01 10:42:28 AM PDT 24
Peak memory 200092 kb
Host smart-e8640b81-91fc-48a9-a7b5-9ee6dffc5e17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121646391 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_long_msg.3121646391
Directory /workspace/22.hmac_long_msg/latest

Test location /workspace/coverage/default/22.hmac_smoke.1501891300
Short name T33
Test name
Test status
Simulation time 217687121 ps
CPU time 3.93 seconds
Started Jul 01 10:40:51 AM PDT 24
Finished Jul 01 10:40:56 AM PDT 24
Peak memory 200204 kb
Host smart-392a2980-c56c-4a80-9233-d5c5b83d624e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501891300 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_smoke.1501891300
Directory /workspace/22.hmac_smoke/latest

Test location /workspace/coverage/default/22.hmac_stress_all.3475185899
Short name T6
Test name
Test status
Simulation time 4689544319 ps
CPU time 159.07 seconds
Started Jul 01 10:41:13 AM PDT 24
Finished Jul 01 10:43:54 AM PDT 24
Peak memory 453272 kb
Host smart-34b38273-4061-4dad-a2b7-cfe6d27a3dc9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475185899 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.hmac_stress_all.3475185899
Directory /workspace/22.hmac_stress_all/latest

Test location /workspace/coverage/default/22.hmac_wipe_secret.2570809681
Short name T370
Test name
Test status
Simulation time 2271174764 ps
CPU time 99.02 seconds
Started Jul 01 10:41:13 AM PDT 24
Finished Jul 01 10:42:53 AM PDT 24
Peak memory 200248 kb
Host smart-9e553e7e-75a8-4021-b44b-4bde068db6b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570809681 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_wipe_secret.2570809681
Directory /workspace/22.hmac_wipe_secret/latest

Test location /workspace/coverage/default/23.hmac_alert_test.2313072586
Short name T287
Test name
Test status
Simulation time 39666177 ps
CPU time 0.58 seconds
Started Jul 01 10:41:16 AM PDT 24
Finished Jul 01 10:41:19 AM PDT 24
Peak memory 195100 kb
Host smart-ec2066e0-c134-43bf-9258-eb3040fecb35
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313072586 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_alert_test.2313072586
Directory /workspace/23.hmac_alert_test/latest

Test location /workspace/coverage/default/23.hmac_back_pressure.1862307570
Short name T136
Test name
Test status
Simulation time 3459971296 ps
CPU time 12.15 seconds
Started Jul 01 10:41:16 AM PDT 24
Finished Jul 01 10:41:32 AM PDT 24
Peak memory 200236 kb
Host smart-d4b64958-06a8-4b05-8047-e15031ec7e1d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1862307570 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_back_pressure.1862307570
Directory /workspace/23.hmac_back_pressure/latest

Test location /workspace/coverage/default/23.hmac_burst_wr.1308976361
Short name T296
Test name
Test status
Simulation time 1345481485 ps
CPU time 34.44 seconds
Started Jul 01 10:41:12 AM PDT 24
Finished Jul 01 10:41:47 AM PDT 24
Peak memory 200272 kb
Host smart-742054fb-9e76-41d3-910f-e4321371884e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308976361 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_burst_wr.1308976361
Directory /workspace/23.hmac_burst_wr/latest

Test location /workspace/coverage/default/23.hmac_datapath_stress.1931342379
Short name T201
Test name
Test status
Simulation time 8181562887 ps
CPU time 1729.48 seconds
Started Jul 01 10:41:18 AM PDT 24
Finished Jul 01 11:10:11 AM PDT 24
Peak memory 776380 kb
Host smart-2aa21190-3607-4963-bbab-32627a662c1f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1931342379 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_datapath_stress.1931342379
Directory /workspace/23.hmac_datapath_stress/latest

Test location /workspace/coverage/default/23.hmac_error.2452983645
Short name T311
Test name
Test status
Simulation time 21530826285 ps
CPU time 109.5 seconds
Started Jul 01 10:41:11 AM PDT 24
Finished Jul 01 10:43:01 AM PDT 24
Peak memory 200276 kb
Host smart-c4ffb8f0-188a-433f-95e6-d5c148492615
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452983645 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_error.2452983645
Directory /workspace/23.hmac_error/latest

Test location /workspace/coverage/default/23.hmac_long_msg.3940258189
Short name T208
Test name
Test status
Simulation time 1116221315 ps
CPU time 5.67 seconds
Started Jul 01 10:41:20 AM PDT 24
Finished Jul 01 10:41:29 AM PDT 24
Peak memory 200148 kb
Host smart-ecc81114-16c3-48c7-9c13-afea5d1e2d1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940258189 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_long_msg.3940258189
Directory /workspace/23.hmac_long_msg/latest

Test location /workspace/coverage/default/23.hmac_smoke.595365611
Short name T531
Test name
Test status
Simulation time 238934372 ps
CPU time 3.37 seconds
Started Jul 01 10:41:08 AM PDT 24
Finished Jul 01 10:41:12 AM PDT 24
Peak memory 200136 kb
Host smart-16429ba3-e138-4853-9389-23989992f4b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595365611 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_smoke.595365611
Directory /workspace/23.hmac_smoke/latest

Test location /workspace/coverage/default/23.hmac_stress_all.227931134
Short name T500
Test name
Test status
Simulation time 175978444695 ps
CPU time 1335.05 seconds
Started Jul 01 10:40:57 AM PDT 24
Finished Jul 01 11:03:13 AM PDT 24
Peak memory 617728 kb
Host smart-0e4033ae-33df-4b96-a26b-0ea68374d341
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227931134 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 23.hmac_stress_all.227931134
Directory /workspace/23.hmac_stress_all/latest

Test location /workspace/coverage/default/23.hmac_wipe_secret.1258650401
Short name T254
Test name
Test status
Simulation time 2037209017 ps
CPU time 47.25 seconds
Started Jul 01 10:41:01 AM PDT 24
Finished Jul 01 10:41:49 AM PDT 24
Peak memory 200240 kb
Host smart-da184ddb-4d3f-4654-802a-2ea9fe149f9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258650401 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_wipe_secret.1258650401
Directory /workspace/23.hmac_wipe_secret/latest

Test location /workspace/coverage/default/24.hmac_alert_test.3618798137
Short name T39
Test name
Test status
Simulation time 17522377 ps
CPU time 0.57 seconds
Started Jul 01 10:41:13 AM PDT 24
Finished Jul 01 10:41:15 AM PDT 24
Peak memory 196148 kb
Host smart-80cafb86-ce19-4ae2-9fde-d7325a592377
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618798137 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_alert_test.3618798137
Directory /workspace/24.hmac_alert_test/latest

Test location /workspace/coverage/default/24.hmac_back_pressure.826123814
Short name T417
Test name
Test status
Simulation time 495331174 ps
CPU time 26.6 seconds
Started Jul 01 10:41:18 AM PDT 24
Finished Jul 01 10:41:48 AM PDT 24
Peak memory 200200 kb
Host smart-b8331f08-be60-4b80-855a-8f35b6aed136
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=826123814 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_back_pressure.826123814
Directory /workspace/24.hmac_back_pressure/latest

Test location /workspace/coverage/default/24.hmac_burst_wr.1533810272
Short name T355
Test name
Test status
Simulation time 5306949185 ps
CPU time 58.28 seconds
Started Jul 01 10:41:24 AM PDT 24
Finished Jul 01 10:42:29 AM PDT 24
Peak memory 200448 kb
Host smart-b291f432-0e68-4102-9cbe-baef029e36a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533810272 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_burst_wr.1533810272
Directory /workspace/24.hmac_burst_wr/latest

Test location /workspace/coverage/default/24.hmac_datapath_stress.94885081
Short name T525
Test name
Test status
Simulation time 27915504700 ps
CPU time 568.03 seconds
Started Jul 01 10:41:00 AM PDT 24
Finished Jul 01 10:50:28 AM PDT 24
Peak memory 637712 kb
Host smart-99ec56d8-5b92-4f48-b7b0-442b10176624
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=94885081 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_datapath_stress.94885081
Directory /workspace/24.hmac_datapath_stress/latest

Test location /workspace/coverage/default/24.hmac_error.1408401108
Short name T144
Test name
Test status
Simulation time 830382121 ps
CPU time 15 seconds
Started Jul 01 10:41:07 AM PDT 24
Finished Jul 01 10:41:23 AM PDT 24
Peak memory 200240 kb
Host smart-56da124f-a4ae-45f5-b68b-4cbc0dfe48a4
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408401108 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_error.1408401108
Directory /workspace/24.hmac_error/latest

Test location /workspace/coverage/default/24.hmac_long_msg.3338794945
Short name T277
Test name
Test status
Simulation time 1599624259 ps
CPU time 86.21 seconds
Started Jul 01 10:41:09 AM PDT 24
Finished Jul 01 10:42:36 AM PDT 24
Peak memory 200268 kb
Host smart-a13f0838-84a2-4bfc-9010-713cdc22fff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338794945 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_long_msg.3338794945
Directory /workspace/24.hmac_long_msg/latest

Test location /workspace/coverage/default/24.hmac_smoke.3137385099
Short name T253
Test name
Test status
Simulation time 271156337 ps
CPU time 3.89 seconds
Started Jul 01 10:41:23 AM PDT 24
Finished Jul 01 10:41:29 AM PDT 24
Peak memory 200132 kb
Host smart-63a88240-517d-44ca-97fc-a9ae72c3856b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137385099 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_smoke.3137385099
Directory /workspace/24.hmac_smoke/latest

Test location /workspace/coverage/default/24.hmac_stress_all.881360132
Short name T327
Test name
Test status
Simulation time 29367013224 ps
CPU time 924.18 seconds
Started Jul 01 10:41:07 AM PDT 24
Finished Jul 01 10:56:32 AM PDT 24
Peak memory 632808 kb
Host smart-e85fc8f2-f8fa-4d0b-a01c-72ffb8727ad9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881360132 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 24.hmac_stress_all.881360132
Directory /workspace/24.hmac_stress_all/latest

Test location /workspace/coverage/default/24.hmac_wipe_secret.2099058618
Short name T98
Test name
Test status
Simulation time 5000918539 ps
CPU time 63.38 seconds
Started Jul 01 10:41:13 AM PDT 24
Finished Jul 01 10:42:18 AM PDT 24
Peak memory 200320 kb
Host smart-13478073-ceaa-4507-b1b1-f35f4f11c6c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099058618 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_wipe_secret.2099058618
Directory /workspace/24.hmac_wipe_secret/latest

Test location /workspace/coverage/default/25.hmac_alert_test.1918959470
Short name T335
Test name
Test status
Simulation time 15963311 ps
CPU time 0.59 seconds
Started Jul 01 10:41:09 AM PDT 24
Finished Jul 01 10:41:10 AM PDT 24
Peak memory 196808 kb
Host smart-b232cf4f-cbb6-4bba-94fd-6951aae031e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918959470 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_alert_test.1918959470
Directory /workspace/25.hmac_alert_test/latest

Test location /workspace/coverage/default/25.hmac_back_pressure.2400237916
Short name T470
Test name
Test status
Simulation time 1048754127 ps
CPU time 58.6 seconds
Started Jul 01 10:41:15 AM PDT 24
Finished Jul 01 10:42:16 AM PDT 24
Peak memory 200252 kb
Host smart-d07c83be-ebea-46f1-972e-e2806766f4ef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2400237916 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_back_pressure.2400237916
Directory /workspace/25.hmac_back_pressure/latest

Test location /workspace/coverage/default/25.hmac_burst_wr.2995890274
Short name T194
Test name
Test status
Simulation time 6221736578 ps
CPU time 32.35 seconds
Started Jul 01 10:41:19 AM PDT 24
Finished Jul 01 10:41:55 AM PDT 24
Peak memory 200296 kb
Host smart-6405ade0-7b8d-459c-a7b4-4ec26f3f0145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995890274 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_burst_wr.2995890274
Directory /workspace/25.hmac_burst_wr/latest

Test location /workspace/coverage/default/25.hmac_datapath_stress.1676547579
Short name T84
Test name
Test status
Simulation time 23927780133 ps
CPU time 823.84 seconds
Started Jul 01 10:41:01 AM PDT 24
Finished Jul 01 10:54:45 AM PDT 24
Peak memory 756404 kb
Host smart-c377c608-0fed-4125-9807-177df428769b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1676547579 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_datapath_stress.1676547579
Directory /workspace/25.hmac_datapath_stress/latest

Test location /workspace/coverage/default/25.hmac_error.4149176842
Short name T291
Test name
Test status
Simulation time 8949002210 ps
CPU time 152.29 seconds
Started Jul 01 10:41:16 AM PDT 24
Finished Jul 01 10:43:52 AM PDT 24
Peak memory 200316 kb
Host smart-3ff465bb-22b1-4030-b964-435575b9e7f5
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149176842 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_error.4149176842
Directory /workspace/25.hmac_error/latest

Test location /workspace/coverage/default/25.hmac_long_msg.3560226125
Short name T524
Test name
Test status
Simulation time 2557629375 ps
CPU time 37.01 seconds
Started Jul 01 10:41:16 AM PDT 24
Finished Jul 01 10:41:56 AM PDT 24
Peak memory 200268 kb
Host smart-67bc5f54-b898-4624-b8be-70d93399e3f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560226125 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_long_msg.3560226125
Directory /workspace/25.hmac_long_msg/latest

Test location /workspace/coverage/default/25.hmac_smoke.3752697156
Short name T343
Test name
Test status
Simulation time 297173308 ps
CPU time 13.27 seconds
Started Jul 01 10:40:54 AM PDT 24
Finished Jul 01 10:41:08 AM PDT 24
Peak memory 200204 kb
Host smart-c7034639-86db-46a1-b714-56fb2b4077c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752697156 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_smoke.3752697156
Directory /workspace/25.hmac_smoke/latest

Test location /workspace/coverage/default/25.hmac_stress_all.3418019318
Short name T140
Test name
Test status
Simulation time 19958332290 ps
CPU time 710.15 seconds
Started Jul 01 10:40:54 AM PDT 24
Finished Jul 01 10:52:45 AM PDT 24
Peak memory 642492 kb
Host smart-18129ace-b597-4a27-a535-f4ff219345e3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418019318 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.hmac_stress_all.3418019318
Directory /workspace/25.hmac_stress_all/latest

Test location /workspace/coverage/default/25.hmac_wipe_secret.510880175
Short name T209
Test name
Test status
Simulation time 401223280 ps
CPU time 11.5 seconds
Started Jul 01 10:41:11 AM PDT 24
Finished Jul 01 10:41:24 AM PDT 24
Peak memory 200252 kb
Host smart-af3f042f-26d1-4b87-a003-945e9e5c1dfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510880175 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_wipe_secret.510880175
Directory /workspace/25.hmac_wipe_secret/latest

Test location /workspace/coverage/default/26.hmac_alert_test.3985229571
Short name T317
Test name
Test status
Simulation time 14499119 ps
CPU time 0.54 seconds
Started Jul 01 10:41:15 AM PDT 24
Finished Jul 01 10:41:17 AM PDT 24
Peak memory 196036 kb
Host smart-3ec8358e-6330-4d8e-9368-736ea61cc49a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985229571 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_alert_test.3985229571
Directory /workspace/26.hmac_alert_test/latest

Test location /workspace/coverage/default/26.hmac_back_pressure.3849304357
Short name T376
Test name
Test status
Simulation time 1364945437 ps
CPU time 58.56 seconds
Started Jul 01 10:41:14 AM PDT 24
Finished Jul 01 10:42:15 AM PDT 24
Peak memory 200196 kb
Host smart-5fdbb85a-2e95-4dfb-8b54-6053dd09fb3f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3849304357 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_back_pressure.3849304357
Directory /workspace/26.hmac_back_pressure/latest

Test location /workspace/coverage/default/26.hmac_burst_wr.1253389163
Short name T382
Test name
Test status
Simulation time 466893084 ps
CPU time 25.99 seconds
Started Jul 01 10:41:02 AM PDT 24
Finished Jul 01 10:41:29 AM PDT 24
Peak memory 200252 kb
Host smart-ae2b576f-9035-4e8b-9f21-4bf1c7b955d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253389163 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_burst_wr.1253389163
Directory /workspace/26.hmac_burst_wr/latest

Test location /workspace/coverage/default/26.hmac_datapath_stress.1550427331
Short name T431
Test name
Test status
Simulation time 1955271311 ps
CPU time 328.57 seconds
Started Jul 01 10:41:18 AM PDT 24
Finished Jul 01 10:46:50 AM PDT 24
Peak memory 489616 kb
Host smart-050fcb07-449d-40ff-b788-bf75b449ef6a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1550427331 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_datapath_stress.1550427331
Directory /workspace/26.hmac_datapath_stress/latest

Test location /workspace/coverage/default/26.hmac_error.1941977059
Short name T375
Test name
Test status
Simulation time 37438264769 ps
CPU time 146.8 seconds
Started Jul 01 10:41:14 AM PDT 24
Finished Jul 01 10:43:42 AM PDT 24
Peak memory 200284 kb
Host smart-f05b2e00-0654-44bb-8b77-151953f53f97
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941977059 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_error.1941977059
Directory /workspace/26.hmac_error/latest

Test location /workspace/coverage/default/26.hmac_long_msg.4179778579
Short name T435
Test name
Test status
Simulation time 123123099 ps
CPU time 6.64 seconds
Started Jul 01 10:41:15 AM PDT 24
Finished Jul 01 10:41:23 AM PDT 24
Peak memory 200264 kb
Host smart-9090a5b4-8ecc-423c-9f14-065bb1cacc3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179778579 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_long_msg.4179778579
Directory /workspace/26.hmac_long_msg/latest

Test location /workspace/coverage/default/26.hmac_smoke.493230046
Short name T274
Test name
Test status
Simulation time 8018248090 ps
CPU time 10.45 seconds
Started Jul 01 10:41:14 AM PDT 24
Finished Jul 01 10:41:25 AM PDT 24
Peak memory 200392 kb
Host smart-a6c64af5-ed67-4598-9abc-d97dd820db11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493230046 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_smoke.493230046
Directory /workspace/26.hmac_smoke/latest

Test location /workspace/coverage/default/26.hmac_stress_all.1052840867
Short name T222
Test name
Test status
Simulation time 243968295233 ps
CPU time 1839.27 seconds
Started Jul 01 10:41:16 AM PDT 24
Finished Jul 01 11:11:58 AM PDT 24
Peak memory 766756 kb
Host smart-19cd6ccf-bc4e-4978-9605-b13fb4efc46c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052840867 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.hmac_stress_all.1052840867
Directory /workspace/26.hmac_stress_all/latest

Test location /workspace/coverage/default/26.hmac_wipe_secret.2942790195
Short name T449
Test name
Test status
Simulation time 16734462966 ps
CPU time 46.8 seconds
Started Jul 01 10:41:17 AM PDT 24
Finished Jul 01 10:42:08 AM PDT 24
Peak memory 200348 kb
Host smart-e0215f32-1e30-4c4e-9acb-b99de05ca2d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942790195 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_wipe_secret.2942790195
Directory /workspace/26.hmac_wipe_secret/latest

Test location /workspace/coverage/default/27.hmac_alert_test.1281021837
Short name T390
Test name
Test status
Simulation time 47370129 ps
CPU time 0.58 seconds
Started Jul 01 10:41:17 AM PDT 24
Finished Jul 01 10:41:21 AM PDT 24
Peak memory 196808 kb
Host smart-e29a449c-2c53-43e8-bdef-5621b0a8c387
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281021837 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_alert_test.1281021837
Directory /workspace/27.hmac_alert_test/latest

Test location /workspace/coverage/default/27.hmac_back_pressure.1062749065
Short name T152
Test name
Test status
Simulation time 582326892 ps
CPU time 15.88 seconds
Started Jul 01 10:41:15 AM PDT 24
Finished Jul 01 10:41:32 AM PDT 24
Peak memory 200148 kb
Host smart-dd64d619-ed9f-4b77-bef7-71ce0009cad4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1062749065 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_back_pressure.1062749065
Directory /workspace/27.hmac_back_pressure/latest

Test location /workspace/coverage/default/27.hmac_burst_wr.1018223556
Short name T452
Test name
Test status
Simulation time 1125505387 ps
CPU time 14.87 seconds
Started Jul 01 10:41:17 AM PDT 24
Finished Jul 01 10:41:36 AM PDT 24
Peak memory 200228 kb
Host smart-fccf2fbe-e2b7-41b7-bdd0-2079ca5fe1b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018223556 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_burst_wr.1018223556
Directory /workspace/27.hmac_burst_wr/latest

Test location /workspace/coverage/default/27.hmac_datapath_stress.1401660827
Short name T315
Test name
Test status
Simulation time 7310941553 ps
CPU time 1472.36 seconds
Started Jul 01 10:41:14 AM PDT 24
Finished Jul 01 11:05:48 AM PDT 24
Peak memory 797104 kb
Host smart-d2863a5a-e092-41e3-969e-bda531e761db
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1401660827 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_datapath_stress.1401660827
Directory /workspace/27.hmac_datapath_stress/latest

Test location /workspace/coverage/default/27.hmac_error.3736936425
Short name T437
Test name
Test status
Simulation time 25418892193 ps
CPU time 105.83 seconds
Started Jul 01 10:41:14 AM PDT 24
Finished Jul 01 10:43:01 AM PDT 24
Peak memory 200256 kb
Host smart-83053570-e0e1-4198-948e-0739c9cfb089
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736936425 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_error.3736936425
Directory /workspace/27.hmac_error/latest

Test location /workspace/coverage/default/27.hmac_long_msg.3032359684
Short name T508
Test name
Test status
Simulation time 4135763428 ps
CPU time 26.25 seconds
Started Jul 01 10:41:18 AM PDT 24
Finished Jul 01 10:41:48 AM PDT 24
Peak memory 199668 kb
Host smart-390e0ee4-85c5-4025-932d-140af25918e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032359684 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_long_msg.3032359684
Directory /workspace/27.hmac_long_msg/latest

Test location /workspace/coverage/default/27.hmac_smoke.2658639853
Short name T426
Test name
Test status
Simulation time 1147110195 ps
CPU time 10.33 seconds
Started Jul 01 10:41:19 AM PDT 24
Finished Jul 01 10:41:32 AM PDT 24
Peak memory 200184 kb
Host smart-a36f1d8e-1640-4a8a-9de8-fa0c86190cb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658639853 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_smoke.2658639853
Directory /workspace/27.hmac_smoke/latest

Test location /workspace/coverage/default/27.hmac_stress_all.3049029889
Short name T138
Test name
Test status
Simulation time 27705422332 ps
CPU time 1613.24 seconds
Started Jul 01 10:41:12 AM PDT 24
Finished Jul 01 11:08:06 AM PDT 24
Peak memory 711656 kb
Host smart-484aa689-ae5a-4b60-801e-b00414a9b8f2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049029889 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.hmac_stress_all.3049029889
Directory /workspace/27.hmac_stress_all/latest

Test location /workspace/coverage/default/27.hmac_wipe_secret.2367132430
Short name T87
Test name
Test status
Simulation time 1369247922 ps
CPU time 4.81 seconds
Started Jul 01 10:41:06 AM PDT 24
Finished Jul 01 10:41:12 AM PDT 24
Peak memory 200212 kb
Host smart-134cf6f1-a3f7-456d-bc25-2b0ca3412694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367132430 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_wipe_secret.2367132430
Directory /workspace/27.hmac_wipe_secret/latest

Test location /workspace/coverage/default/28.hmac_alert_test.930760508
Short name T318
Test name
Test status
Simulation time 17091493 ps
CPU time 0.66 seconds
Started Jul 01 10:41:15 AM PDT 24
Finished Jul 01 10:41:17 AM PDT 24
Peak memory 195084 kb
Host smart-a22798bb-5ff7-44b2-94cb-7389ee6d9c67
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930760508 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_alert_test.930760508
Directory /workspace/28.hmac_alert_test/latest

Test location /workspace/coverage/default/28.hmac_back_pressure.282127424
Short name T35
Test name
Test status
Simulation time 6340923497 ps
CPU time 73.13 seconds
Started Jul 01 10:41:06 AM PDT 24
Finished Jul 01 10:42:20 AM PDT 24
Peak memory 200252 kb
Host smart-2e6cd132-6407-4465-8bda-1baa8a485d29
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=282127424 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_back_pressure.282127424
Directory /workspace/28.hmac_back_pressure/latest

Test location /workspace/coverage/default/28.hmac_burst_wr.541744347
Short name T348
Test name
Test status
Simulation time 2503810539 ps
CPU time 35.08 seconds
Started Jul 01 10:40:55 AM PDT 24
Finished Jul 01 10:41:31 AM PDT 24
Peak memory 200288 kb
Host smart-9a2277d5-5e53-428a-98e2-7dbcbdc76725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541744347 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_burst_wr.541744347
Directory /workspace/28.hmac_burst_wr/latest

Test location /workspace/coverage/default/28.hmac_datapath_stress.3755349591
Short name T395
Test name
Test status
Simulation time 5030865702 ps
CPU time 437.83 seconds
Started Jul 01 10:41:03 AM PDT 24
Finished Jul 01 10:48:21 AM PDT 24
Peak memory 692780 kb
Host smart-d0960f3c-dfa1-4efe-afd0-897910c24785
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3755349591 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_datapath_stress.3755349591
Directory /workspace/28.hmac_datapath_stress/latest

Test location /workspace/coverage/default/28.hmac_error.287065122
Short name T249
Test name
Test status
Simulation time 36683489869 ps
CPU time 90.97 seconds
Started Jul 01 10:41:18 AM PDT 24
Finished Jul 01 10:42:53 AM PDT 24
Peak memory 200300 kb
Host smart-10a96db9-d05c-46f0-86a2-4645f7b368cc
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287065122 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_error.287065122
Directory /workspace/28.hmac_error/latest

Test location /workspace/coverage/default/28.hmac_long_msg.1166802242
Short name T392
Test name
Test status
Simulation time 1256019387 ps
CPU time 35.46 seconds
Started Jul 01 10:41:16 AM PDT 24
Finished Jul 01 10:41:56 AM PDT 24
Peak memory 200264 kb
Host smart-88c8f685-1486-45ce-9a96-b920a1d7b187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166802242 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_long_msg.1166802242
Directory /workspace/28.hmac_long_msg/latest

Test location /workspace/coverage/default/28.hmac_smoke.1835061727
Short name T228
Test name
Test status
Simulation time 4839519049 ps
CPU time 14.07 seconds
Started Jul 01 10:41:17 AM PDT 24
Finished Jul 01 10:41:34 AM PDT 24
Peak memory 200300 kb
Host smart-9cd35f86-51b9-4ee6-b129-19aa1b64ddaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835061727 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_smoke.1835061727
Directory /workspace/28.hmac_smoke/latest

Test location /workspace/coverage/default/28.hmac_wipe_secret.4005985468
Short name T178
Test name
Test status
Simulation time 7757436266 ps
CPU time 78.34 seconds
Started Jul 01 10:41:01 AM PDT 24
Finished Jul 01 10:42:20 AM PDT 24
Peak memory 200356 kb
Host smart-9368f145-3b83-4bbf-9f00-482933828a0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005985468 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_wipe_secret.4005985468
Directory /workspace/28.hmac_wipe_secret/latest

Test location /workspace/coverage/default/29.hmac_alert_test.3824614743
Short name T40
Test name
Test status
Simulation time 11183361 ps
CPU time 0.57 seconds
Started Jul 01 10:41:13 AM PDT 24
Finished Jul 01 10:41:15 AM PDT 24
Peak memory 195060 kb
Host smart-fbcc85e1-9d41-4e16-912e-16657bed1dfa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824614743 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_alert_test.3824614743
Directory /workspace/29.hmac_alert_test/latest

Test location /workspace/coverage/default/29.hmac_back_pressure.121241041
Short name T371
Test name
Test status
Simulation time 1961830096 ps
CPU time 55.21 seconds
Started Jul 01 10:41:19 AM PDT 24
Finished Jul 01 10:42:18 AM PDT 24
Peak memory 200128 kb
Host smart-d55cbd6a-a4be-4a6e-87b6-4f615662ddf7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=121241041 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_back_pressure.121241041
Directory /workspace/29.hmac_back_pressure/latest

Test location /workspace/coverage/default/29.hmac_burst_wr.2260524019
Short name T401
Test name
Test status
Simulation time 70214685 ps
CPU time 3.43 seconds
Started Jul 01 10:41:22 AM PDT 24
Finished Jul 01 10:41:28 AM PDT 24
Peak memory 200264 kb
Host smart-372c2d79-b7af-4b0c-b434-023649d12e19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260524019 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_burst_wr.2260524019
Directory /workspace/29.hmac_burst_wr/latest

Test location /workspace/coverage/default/29.hmac_datapath_stress.4043669166
Short name T199
Test name
Test status
Simulation time 3831191832 ps
CPU time 536.23 seconds
Started Jul 01 10:41:16 AM PDT 24
Finished Jul 01 10:50:15 AM PDT 24
Peak memory 696768 kb
Host smart-b7091276-8d61-49c9-9e47-e56c795bd8df
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4043669166 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_datapath_stress.4043669166
Directory /workspace/29.hmac_datapath_stress/latest

Test location /workspace/coverage/default/29.hmac_error.2266527632
Short name T269
Test name
Test status
Simulation time 707011358 ps
CPU time 39.31 seconds
Started Jul 01 10:41:17 AM PDT 24
Finished Jul 01 10:42:00 AM PDT 24
Peak memory 200248 kb
Host smart-3332c0a8-e676-4626-b130-4f22b72b0348
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266527632 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_error.2266527632
Directory /workspace/29.hmac_error/latest

Test location /workspace/coverage/default/29.hmac_long_msg.3290711501
Short name T442
Test name
Test status
Simulation time 1433057421 ps
CPU time 75.32 seconds
Started Jul 01 10:41:16 AM PDT 24
Finished Jul 01 10:42:35 AM PDT 24
Peak memory 200204 kb
Host smart-dd7ddae8-097e-416f-829e-3bed018eadea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290711501 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_long_msg.3290711501
Directory /workspace/29.hmac_long_msg/latest

Test location /workspace/coverage/default/29.hmac_smoke.3355580264
Short name T384
Test name
Test status
Simulation time 488639945 ps
CPU time 8.29 seconds
Started Jul 01 10:41:14 AM PDT 24
Finished Jul 01 10:41:24 AM PDT 24
Peak memory 200180 kb
Host smart-116f4f83-8169-4f19-90e5-1b5d90a5c3fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355580264 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_smoke.3355580264
Directory /workspace/29.hmac_smoke/latest

Test location /workspace/coverage/default/29.hmac_stress_all.1862850078
Short name T77
Test name
Test status
Simulation time 103526842824 ps
CPU time 2658.41 seconds
Started Jul 01 10:41:32 AM PDT 24
Finished Jul 01 11:25:52 AM PDT 24
Peak memory 817164 kb
Host smart-86c1c2d0-dda6-4d85-96fd-1832701dbe56
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862850078 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.hmac_stress_all.1862850078
Directory /workspace/29.hmac_stress_all/latest

Test location /workspace/coverage/default/29.hmac_wipe_secret.1542012130
Short name T429
Test name
Test status
Simulation time 12490395365 ps
CPU time 105.44 seconds
Started Jul 01 10:41:25 AM PDT 24
Finished Jul 01 10:43:12 AM PDT 24
Peak memory 200284 kb
Host smart-d127ae21-d8a9-484a-a760-a36118802a6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542012130 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_wipe_secret.1542012130
Directory /workspace/29.hmac_wipe_secret/latest

Test location /workspace/coverage/default/3.hmac_alert_test.3536511698
Short name T402
Test name
Test status
Simulation time 68171737 ps
CPU time 0.56 seconds
Started Jul 01 10:40:36 AM PDT 24
Finished Jul 01 10:40:38 AM PDT 24
Peak memory 195764 kb
Host smart-6ff11025-bc0a-4e5d-8136-646b638d7278
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536511698 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_alert_test.3536511698
Directory /workspace/3.hmac_alert_test/latest

Test location /workspace/coverage/default/3.hmac_back_pressure.856168996
Short name T459
Test name
Test status
Simulation time 1455032097 ps
CPU time 44.7 seconds
Started Jul 01 10:40:44 AM PDT 24
Finished Jul 01 10:41:30 AM PDT 24
Peak memory 200184 kb
Host smart-db314059-6ee7-48aa-937a-bb9463de51c6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=856168996 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_back_pressure.856168996
Directory /workspace/3.hmac_back_pressure/latest

Test location /workspace/coverage/default/3.hmac_burst_wr.931700161
Short name T481
Test name
Test status
Simulation time 502524340 ps
CPU time 26.5 seconds
Started Jul 01 10:40:39 AM PDT 24
Finished Jul 01 10:41:05 AM PDT 24
Peak memory 200228 kb
Host smart-f4675e18-4b81-4d73-8cd6-604fdba83fe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=931700161 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_burst_wr.931700161
Directory /workspace/3.hmac_burst_wr/latest

Test location /workspace/coverage/default/3.hmac_datapath_stress.3268621823
Short name T169
Test name
Test status
Simulation time 22798787693 ps
CPU time 949.54 seconds
Started Jul 01 10:42:02 AM PDT 24
Finished Jul 01 10:57:52 AM PDT 24
Peak memory 720416 kb
Host smart-358f0450-e9db-405a-89ff-0ad54e276708
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3268621823 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_datapath_stress.3268621823
Directory /workspace/3.hmac_datapath_stress/latest

Test location /workspace/coverage/default/3.hmac_error.3310861791
Short name T316
Test name
Test status
Simulation time 22000825355 ps
CPU time 258.56 seconds
Started Jul 01 10:41:01 AM PDT 24
Finished Jul 01 10:45:20 AM PDT 24
Peak memory 200300 kb
Host smart-a551a54c-becf-4283-a379-ca95f3279462
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310861791 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_error.3310861791
Directory /workspace/3.hmac_error/latest

Test location /workspace/coverage/default/3.hmac_long_msg.271427118
Short name T180
Test name
Test status
Simulation time 152142139552 ps
CPU time 223.03 seconds
Started Jul 01 10:41:01 AM PDT 24
Finished Jul 01 10:44:44 AM PDT 24
Peak memory 200728 kb
Host smart-a3978fc8-82c6-4635-aadc-f3b8463f8593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271427118 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_long_msg.271427118
Directory /workspace/3.hmac_long_msg/latest

Test location /workspace/coverage/default/3.hmac_sec_cm.854929788
Short name T46
Test name
Test status
Simulation time 135021852 ps
CPU time 1 seconds
Started Jul 01 10:40:44 AM PDT 24
Finished Jul 01 10:40:46 AM PDT 24
Peak memory 218620 kb
Host smart-5c46e4f1-c4f1-4080-837f-30195d0f6083
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854929788 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_sec_cm.854929788
Directory /workspace/3.hmac_sec_cm/latest

Test location /workspace/coverage/default/3.hmac_smoke.920550504
Short name T164
Test name
Test status
Simulation time 1503142218 ps
CPU time 10.88 seconds
Started Jul 01 10:40:48 AM PDT 24
Finished Jul 01 10:41:00 AM PDT 24
Peak memory 200272 kb
Host smart-54bf6b7b-0143-4d28-a9ca-fa1ef10c0ec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920550504 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_smoke.920550504
Directory /workspace/3.hmac_smoke/latest

Test location /workspace/coverage/default/3.hmac_stress_all.1946074910
Short name T406
Test name
Test status
Simulation time 99548978647 ps
CPU time 1072.47 seconds
Started Jul 01 10:40:51 AM PDT 24
Finished Jul 01 10:58:45 AM PDT 24
Peak memory 745252 kb
Host smart-a3bcc19e-f689-4c0b-a613-bb3b18fb96f7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946074910 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all.1946074910
Directory /workspace/3.hmac_stress_all/latest

Test location /workspace/coverage/default/3.hmac_stress_all_with_rand_reset.2263784124
Short name T10
Test name
Test status
Simulation time 73923454257 ps
CPU time 1586.05 seconds
Started Jul 01 10:40:44 AM PDT 24
Finished Jul 01 11:07:11 AM PDT 24
Peak memory 563920 kb
Host smart-e0d5c607-d99a-43fe-a866-62514f186fd1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2263784124 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all_with_rand_reset.2263784124
Directory /workspace/3.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.hmac_test_hmac256_vectors.1848648708
Short name T170
Test name
Test status
Simulation time 4539989361 ps
CPU time 48.32 seconds
Started Jul 01 10:42:05 AM PDT 24
Finished Jul 01 10:42:55 AM PDT 24
Peak memory 200068 kb
Host smart-e0a5edc3-2431-42ed-9532-271d6c54d15a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1848648708 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac256_vectors.1848648708
Directory /workspace/3.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_hmac384_vectors.3768673337
Short name T464
Test name
Test status
Simulation time 35755475007 ps
CPU time 93.94 seconds
Started Jul 01 10:40:59 AM PDT 24
Finished Jul 01 10:42:34 AM PDT 24
Peak memory 200304 kb
Host smart-5823d45c-d73a-4b7d-94aa-d3b976119208
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3768673337 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac384_vectors.3768673337
Directory /workspace/3.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_hmac512_vectors.2089687235
Short name T215
Test name
Test status
Simulation time 192871674007 ps
CPU time 121.61 seconds
Started Jul 01 10:40:44 AM PDT 24
Finished Jul 01 10:42:51 AM PDT 24
Peak memory 200324 kb
Host smart-a2369886-68f7-4a5f-84ab-958d7280ef7c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2089687235 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac512_vectors.2089687235
Directory /workspace/3.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha256_vectors.1404202101
Short name T187
Test name
Test status
Simulation time 18132697417 ps
CPU time 508.89 seconds
Started Jul 01 10:40:43 AM PDT 24
Finished Jul 01 10:49:13 AM PDT 24
Peak memory 200308 kb
Host smart-67fe22a5-9dd5-4610-983f-c3737e787945
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1404202101 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha256_vectors.1404202101
Directory /workspace/3.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha384_vectors.1775380855
Short name T257
Test name
Test status
Simulation time 100863180357 ps
CPU time 2176.17 seconds
Started Jul 01 10:40:51 AM PDT 24
Finished Jul 01 11:17:08 AM PDT 24
Peak memory 216520 kb
Host smart-a9e744a3-2ee6-49ca-8e3d-13c649896f14
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1775380855 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha384_vectors.1775380855
Directory /workspace/3.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/3.hmac_wipe_secret.3523716411
Short name T372
Test name
Test status
Simulation time 706054890 ps
CPU time 10.47 seconds
Started Jul 01 10:41:53 AM PDT 24
Finished Jul 01 10:42:06 AM PDT 24
Peak memory 199836 kb
Host smart-5ef1f62a-fecd-4e5c-8da9-740ef7de8483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523716411 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_wipe_secret.3523716411
Directory /workspace/3.hmac_wipe_secret/latest

Test location /workspace/coverage/default/30.hmac_alert_test.296150724
Short name T273
Test name
Test status
Simulation time 36966842 ps
CPU time 0.58 seconds
Started Jul 01 10:41:15 AM PDT 24
Finished Jul 01 10:41:18 AM PDT 24
Peak memory 196120 kb
Host smart-29a4001a-8d98-433b-9053-3d1bc27c52dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296150724 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_alert_test.296150724
Directory /workspace/30.hmac_alert_test/latest

Test location /workspace/coverage/default/30.hmac_back_pressure.2357728138
Short name T161
Test name
Test status
Simulation time 413588785 ps
CPU time 22.14 seconds
Started Jul 01 10:41:14 AM PDT 24
Finished Jul 01 10:41:38 AM PDT 24
Peak memory 200156 kb
Host smart-3fc243e4-3cde-4e52-97cc-42350379c2dd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2357728138 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_back_pressure.2357728138
Directory /workspace/30.hmac_back_pressure/latest

Test location /workspace/coverage/default/30.hmac_burst_wr.1904143891
Short name T310
Test name
Test status
Simulation time 629458973 ps
CPU time 33.66 seconds
Started Jul 01 10:41:26 AM PDT 24
Finished Jul 01 10:42:01 AM PDT 24
Peak memory 200292 kb
Host smart-b6579c7d-6816-4ead-85d2-d18a8aeca457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904143891 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_burst_wr.1904143891
Directory /workspace/30.hmac_burst_wr/latest

Test location /workspace/coverage/default/30.hmac_datapath_stress.3221643531
Short name T245
Test name
Test status
Simulation time 4469984794 ps
CPU time 815.2 seconds
Started Jul 01 10:41:19 AM PDT 24
Finished Jul 01 10:54:58 AM PDT 24
Peak memory 727340 kb
Host smart-9e931cb2-10aa-4bd6-88a4-65f6512ef2c6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3221643531 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_datapath_stress.3221643531
Directory /workspace/30.hmac_datapath_stress/latest

Test location /workspace/coverage/default/30.hmac_error.903743229
Short name T520
Test name
Test status
Simulation time 1216679608 ps
CPU time 63.31 seconds
Started Jul 01 10:41:20 AM PDT 24
Finished Jul 01 10:42:27 AM PDT 24
Peak memory 200156 kb
Host smart-86e48531-9c8f-4353-938e-2a587bdf9778
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903743229 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_error.903743229
Directory /workspace/30.hmac_error/latest

Test location /workspace/coverage/default/30.hmac_long_msg.767280176
Short name T393
Test name
Test status
Simulation time 24963994527 ps
CPU time 98.86 seconds
Started Jul 01 10:41:21 AM PDT 24
Finished Jul 01 10:43:03 AM PDT 24
Peak memory 200396 kb
Host smart-42c7e164-022e-4421-84e7-0f3740cf2b24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767280176 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_long_msg.767280176
Directory /workspace/30.hmac_long_msg/latest

Test location /workspace/coverage/default/30.hmac_smoke.1810590759
Short name T350
Test name
Test status
Simulation time 44692628 ps
CPU time 1.38 seconds
Started Jul 01 10:41:17 AM PDT 24
Finished Jul 01 10:41:22 AM PDT 24
Peak memory 200236 kb
Host smart-595b5c77-835f-425b-8aef-824b13194c16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810590759 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_smoke.1810590759
Directory /workspace/30.hmac_smoke/latest

Test location /workspace/coverage/default/30.hmac_stress_all.949586540
Short name T365
Test name
Test status
Simulation time 12049707308 ps
CPU time 163.5 seconds
Started Jul 01 10:41:16 AM PDT 24
Finished Jul 01 10:44:03 AM PDT 24
Peak memory 208464 kb
Host smart-c00cead1-4e68-47f0-8455-a166a43a7a33
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949586540 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 30.hmac_stress_all.949586540
Directory /workspace/30.hmac_stress_all/latest

Test location /workspace/coverage/default/30.hmac_wipe_secret.3022789994
Short name T190
Test name
Test status
Simulation time 3347965272 ps
CPU time 42.46 seconds
Started Jul 01 10:41:17 AM PDT 24
Finished Jul 01 10:42:03 AM PDT 24
Peak memory 200392 kb
Host smart-0ed5865b-d9e8-43cb-9d20-e8eef1043345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3022789994 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_wipe_secret.3022789994
Directory /workspace/30.hmac_wipe_secret/latest

Test location /workspace/coverage/default/31.hmac_alert_test.162850079
Short name T148
Test name
Test status
Simulation time 12882895 ps
CPU time 0.58 seconds
Started Jul 01 10:41:21 AM PDT 24
Finished Jul 01 10:41:24 AM PDT 24
Peak memory 195756 kb
Host smart-3e8dc6b4-624d-490b-bd15-91c08b5d0094
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162850079 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_alert_test.162850079
Directory /workspace/31.hmac_alert_test/latest

Test location /workspace/coverage/default/31.hmac_back_pressure.2849654510
Short name T21
Test name
Test status
Simulation time 34865634218 ps
CPU time 99.79 seconds
Started Jul 01 10:41:16 AM PDT 24
Finished Jul 01 10:43:00 AM PDT 24
Peak memory 200592 kb
Host smart-d6c1ef16-6ed1-4b28-9769-0aeb0af4b5ca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2849654510 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_back_pressure.2849654510
Directory /workspace/31.hmac_back_pressure/latest

Test location /workspace/coverage/default/31.hmac_burst_wr.3610457930
Short name T397
Test name
Test status
Simulation time 3430708909 ps
CPU time 61.07 seconds
Started Jul 01 10:41:11 AM PDT 24
Finished Jul 01 10:42:13 AM PDT 24
Peak memory 200296 kb
Host smart-1acbdc12-2f2a-4fbd-bd92-53377623cdce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610457930 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_burst_wr.3610457930
Directory /workspace/31.hmac_burst_wr/latest

Test location /workspace/coverage/default/31.hmac_datapath_stress.3469132118
Short name T174
Test name
Test status
Simulation time 3582171744 ps
CPU time 657.46 seconds
Started Jul 01 10:41:21 AM PDT 24
Finished Jul 01 10:52:22 AM PDT 24
Peak memory 728460 kb
Host smart-eab9c506-e547-49cf-bce8-aca3e7c62985
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3469132118 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_datapath_stress.3469132118
Directory /workspace/31.hmac_datapath_stress/latest

Test location /workspace/coverage/default/31.hmac_error.714803628
Short name T219
Test name
Test status
Simulation time 4520301035 ps
CPU time 13.56 seconds
Started Jul 01 10:41:18 AM PDT 24
Finished Jul 01 10:41:35 AM PDT 24
Peak memory 200260 kb
Host smart-8fef6fb3-ef30-4b5d-98e4-f415b4589fa0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714803628 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_error.714803628
Directory /workspace/31.hmac_error/latest

Test location /workspace/coverage/default/31.hmac_long_msg.3934032128
Short name T52
Test name
Test status
Simulation time 28968370122 ps
CPU time 97.55 seconds
Started Jul 01 10:41:14 AM PDT 24
Finished Jul 01 10:42:53 AM PDT 24
Peak memory 200300 kb
Host smart-d519f796-f45a-4b09-a5e9-ae6fd05adac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934032128 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_long_msg.3934032128
Directory /workspace/31.hmac_long_msg/latest

Test location /workspace/coverage/default/31.hmac_smoke.1434160062
Short name T333
Test name
Test status
Simulation time 302252202 ps
CPU time 12.62 seconds
Started Jul 01 10:41:18 AM PDT 24
Finished Jul 01 10:41:34 AM PDT 24
Peak memory 200200 kb
Host smart-27a5141c-e57b-4769-90df-8c14eb92f44f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434160062 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_smoke.1434160062
Directory /workspace/31.hmac_smoke/latest

Test location /workspace/coverage/default/31.hmac_stress_all.3656113603
Short name T168
Test name
Test status
Simulation time 32909606823 ps
CPU time 139.37 seconds
Started Jul 01 10:41:14 AM PDT 24
Finished Jul 01 10:43:35 AM PDT 24
Peak memory 200300 kb
Host smart-e634f32c-640e-4a95-9361-efeb0ff67d65
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656113603 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.hmac_stress_all.3656113603
Directory /workspace/31.hmac_stress_all/latest

Test location /workspace/coverage/default/31.hmac_wipe_secret.2777811978
Short name T2
Test name
Test status
Simulation time 6939672881 ps
CPU time 90.6 seconds
Started Jul 01 10:41:17 AM PDT 24
Finished Jul 01 10:42:51 AM PDT 24
Peak memory 200344 kb
Host smart-21e1bac6-d7f5-4943-a618-9e163bdf6327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777811978 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_wipe_secret.2777811978
Directory /workspace/31.hmac_wipe_secret/latest

Test location /workspace/coverage/default/32.hmac_alert_test.1521818888
Short name T218
Test name
Test status
Simulation time 190390803 ps
CPU time 0.59 seconds
Started Jul 01 10:41:11 AM PDT 24
Finished Jul 01 10:41:12 AM PDT 24
Peak memory 195792 kb
Host smart-0e87946e-1960-4436-bd4f-38d22049082b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521818888 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_alert_test.1521818888
Directory /workspace/32.hmac_alert_test/latest

Test location /workspace/coverage/default/32.hmac_back_pressure.2539114104
Short name T30
Test name
Test status
Simulation time 1628218068 ps
CPU time 96.65 seconds
Started Jul 01 10:41:25 AM PDT 24
Finished Jul 01 10:43:03 AM PDT 24
Peak memory 200172 kb
Host smart-765fa315-2f1c-40c9-bd8c-4a1c0865aef3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2539114104 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_back_pressure.2539114104
Directory /workspace/32.hmac_back_pressure/latest

Test location /workspace/coverage/default/32.hmac_burst_wr.1032473885
Short name T320
Test name
Test status
Simulation time 3003832191 ps
CPU time 38.08 seconds
Started Jul 01 10:41:19 AM PDT 24
Finished Jul 01 10:42:01 AM PDT 24
Peak memory 200280 kb
Host smart-6b0021e4-d7d7-4b6e-9cf1-de0050452044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1032473885 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_burst_wr.1032473885
Directory /workspace/32.hmac_burst_wr/latest

Test location /workspace/coverage/default/32.hmac_datapath_stress.1681283900
Short name T457
Test name
Test status
Simulation time 40893531700 ps
CPU time 648.05 seconds
Started Jul 01 10:41:16 AM PDT 24
Finished Jul 01 10:52:06 AM PDT 24
Peak memory 749472 kb
Host smart-4383c414-cac5-4763-b17f-729c72bb0b32
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1681283900 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_datapath_stress.1681283900
Directory /workspace/32.hmac_datapath_stress/latest

Test location /workspace/coverage/default/32.hmac_error.3662520311
Short name T522
Test name
Test status
Simulation time 180993977 ps
CPU time 0.98 seconds
Started Jul 01 10:41:18 AM PDT 24
Finished Jul 01 10:41:23 AM PDT 24
Peak memory 199856 kb
Host smart-d833b900-03c7-4a9b-a10d-b4f6ba89e979
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662520311 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_error.3662520311
Directory /workspace/32.hmac_error/latest

Test location /workspace/coverage/default/32.hmac_long_msg.2432824324
Short name T239
Test name
Test status
Simulation time 7318237920 ps
CPU time 138.87 seconds
Started Jul 01 10:41:14 AM PDT 24
Finished Jul 01 10:43:35 AM PDT 24
Peak memory 215984 kb
Host smart-66f93d0d-027d-4a67-80b2-4efe771b2d64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432824324 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_long_msg.2432824324
Directory /workspace/32.hmac_long_msg/latest

Test location /workspace/coverage/default/32.hmac_smoke.2936032796
Short name T359
Test name
Test status
Simulation time 1988542298 ps
CPU time 8.17 seconds
Started Jul 01 10:41:16 AM PDT 24
Finished Jul 01 10:41:27 AM PDT 24
Peak memory 200180 kb
Host smart-a43691a4-4750-4adc-85ef-f186854a699f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936032796 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_smoke.2936032796
Directory /workspace/32.hmac_smoke/latest

Test location /workspace/coverage/default/32.hmac_stress_all.1380299735
Short name T357
Test name
Test status
Simulation time 24479859256 ps
CPU time 4227.61 seconds
Started Jul 01 10:41:23 AM PDT 24
Finished Jul 01 11:51:53 AM PDT 24
Peak memory 868476 kb
Host smart-f2898974-c2e1-40a5-86ef-3f37717bbcae
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380299735 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.hmac_stress_all.1380299735
Directory /workspace/32.hmac_stress_all/latest

Test location /workspace/coverage/default/32.hmac_wipe_secret.3074487577
Short name T235
Test name
Test status
Simulation time 10739985395 ps
CPU time 78.88 seconds
Started Jul 01 10:41:17 AM PDT 24
Finished Jul 01 10:42:39 AM PDT 24
Peak memory 200332 kb
Host smart-0e7ffd0f-ef4e-4161-a7c0-7feeefc3e6f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3074487577 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_wipe_secret.3074487577
Directory /workspace/32.hmac_wipe_secret/latest

Test location /workspace/coverage/default/33.hmac_alert_test.1463064541
Short name T181
Test name
Test status
Simulation time 51225181 ps
CPU time 0.59 seconds
Started Jul 01 10:41:18 AM PDT 24
Finished Jul 01 10:41:22 AM PDT 24
Peak memory 196104 kb
Host smart-bf0dd0bf-ebb4-40b5-86b6-7fa31cecc295
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463064541 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_alert_test.1463064541
Directory /workspace/33.hmac_alert_test/latest

Test location /workspace/coverage/default/33.hmac_back_pressure.3058417264
Short name T19
Test name
Test status
Simulation time 585247942 ps
CPU time 33.64 seconds
Started Jul 01 10:41:16 AM PDT 24
Finished Jul 01 10:41:53 AM PDT 24
Peak memory 200180 kb
Host smart-052fa57e-946c-4773-aba2-ba8f0eeee0fc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3058417264 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_back_pressure.3058417264
Directory /workspace/33.hmac_back_pressure/latest

Test location /workspace/coverage/default/33.hmac_burst_wr.1418269597
Short name T414
Test name
Test status
Simulation time 1173337221 ps
CPU time 65.83 seconds
Started Jul 01 10:41:19 AM PDT 24
Finished Jul 01 10:42:28 AM PDT 24
Peak memory 200160 kb
Host smart-39a7740e-3234-455e-95cf-84f6a01448dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418269597 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_burst_wr.1418269597
Directory /workspace/33.hmac_burst_wr/latest

Test location /workspace/coverage/default/33.hmac_datapath_stress.3897994891
Short name T413
Test name
Test status
Simulation time 490568777 ps
CPU time 66.28 seconds
Started Jul 01 10:41:17 AM PDT 24
Finished Jul 01 10:42:27 AM PDT 24
Peak memory 325456 kb
Host smart-0214eea2-1259-413c-b2dd-7beaded11e51
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3897994891 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_datapath_stress.3897994891
Directory /workspace/33.hmac_datapath_stress/latest

Test location /workspace/coverage/default/33.hmac_error.3998852248
Short name T387
Test name
Test status
Simulation time 1075298285 ps
CPU time 29.25 seconds
Started Jul 01 10:42:18 AM PDT 24
Finished Jul 01 10:42:49 AM PDT 24
Peak memory 199252 kb
Host smart-1d46ff15-98b8-4278-a5a3-effc2b600d6d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998852248 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_error.3998852248
Directory /workspace/33.hmac_error/latest

Test location /workspace/coverage/default/33.hmac_long_msg.527959416
Short name T360
Test name
Test status
Simulation time 1219684508 ps
CPU time 68.63 seconds
Started Jul 01 10:41:17 AM PDT 24
Finished Jul 01 10:42:29 AM PDT 24
Peak memory 200160 kb
Host smart-96b5687e-ec0d-4d8a-aab0-95ca4e9e8df4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=527959416 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_long_msg.527959416
Directory /workspace/33.hmac_long_msg/latest

Test location /workspace/coverage/default/33.hmac_smoke.4067815681
Short name T214
Test name
Test status
Simulation time 355360795 ps
CPU time 4.41 seconds
Started Jul 01 10:41:14 AM PDT 24
Finished Jul 01 10:41:20 AM PDT 24
Peak memory 200224 kb
Host smart-28e1d583-9522-4248-9bed-f676cc92836e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067815681 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_smoke.4067815681
Directory /workspace/33.hmac_smoke/latest

Test location /workspace/coverage/default/33.hmac_wipe_secret.873681775
Short name T250
Test name
Test status
Simulation time 3968964010 ps
CPU time 76.24 seconds
Started Jul 01 10:41:18 AM PDT 24
Finished Jul 01 10:42:38 AM PDT 24
Peak memory 200256 kb
Host smart-1db4107b-5b93-40ee-aab9-0b1b5509f29c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873681775 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_wipe_secret.873681775
Directory /workspace/33.hmac_wipe_secret/latest

Test location /workspace/coverage/default/34.hmac_alert_test.2825260645
Short name T17
Test name
Test status
Simulation time 38518518 ps
CPU time 0.59 seconds
Started Jul 01 10:41:18 AM PDT 24
Finished Jul 01 10:41:22 AM PDT 24
Peak memory 194980 kb
Host smart-da3993a3-0f13-4a36-accb-7ef70b95627f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825260645 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_alert_test.2825260645
Directory /workspace/34.hmac_alert_test/latest

Test location /workspace/coverage/default/34.hmac_back_pressure.814957116
Short name T85
Test name
Test status
Simulation time 2220444944 ps
CPU time 57.75 seconds
Started Jul 01 10:41:11 AM PDT 24
Finished Jul 01 10:42:09 AM PDT 24
Peak memory 200180 kb
Host smart-635593f0-857d-4f18-8aa0-337373201323
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=814957116 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_back_pressure.814957116
Directory /workspace/34.hmac_back_pressure/latest

Test location /workspace/coverage/default/34.hmac_burst_wr.2049485109
Short name T302
Test name
Test status
Simulation time 5167155554 ps
CPU time 35.88 seconds
Started Jul 01 10:41:29 AM PDT 24
Finished Jul 01 10:42:07 AM PDT 24
Peak memory 200232 kb
Host smart-409c5baf-e3a4-4c01-ab17-fc9126a2a93a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049485109 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_burst_wr.2049485109
Directory /workspace/34.hmac_burst_wr/latest

Test location /workspace/coverage/default/34.hmac_datapath_stress.3248558045
Short name T80
Test name
Test status
Simulation time 5579715906 ps
CPU time 1171.89 seconds
Started Jul 01 10:41:20 AM PDT 24
Finished Jul 01 11:00:56 AM PDT 24
Peak memory 751608 kb
Host smart-0879a31b-eecb-430d-8ee9-0d0452e0dc9c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3248558045 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_datapath_stress.3248558045
Directory /workspace/34.hmac_datapath_stress/latest

Test location /workspace/coverage/default/34.hmac_error.3292984031
Short name T323
Test name
Test status
Simulation time 11297734002 ps
CPU time 133.83 seconds
Started Jul 01 10:41:19 AM PDT 24
Finished Jul 01 10:43:37 AM PDT 24
Peak memory 200308 kb
Host smart-eaa909d4-1199-40e6-9a34-a214d8d71c5d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292984031 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_error.3292984031
Directory /workspace/34.hmac_error/latest

Test location /workspace/coverage/default/34.hmac_long_msg.1989688813
Short name T197
Test name
Test status
Simulation time 2450174227 ps
CPU time 32.69 seconds
Started Jul 01 10:41:15 AM PDT 24
Finished Jul 01 10:41:50 AM PDT 24
Peak memory 200248 kb
Host smart-3fad6587-aeb2-4387-8d12-0a206a6a2eec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989688813 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_long_msg.1989688813
Directory /workspace/34.hmac_long_msg/latest

Test location /workspace/coverage/default/34.hmac_smoke.482463721
Short name T157
Test name
Test status
Simulation time 66972485 ps
CPU time 3.17 seconds
Started Jul 01 10:41:07 AM PDT 24
Finished Jul 01 10:41:12 AM PDT 24
Peak memory 200144 kb
Host smart-00a5ea2e-4777-4fff-9309-4d055cfe6684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=482463721 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_smoke.482463721
Directory /workspace/34.hmac_smoke/latest

Test location /workspace/coverage/default/34.hmac_stress_all.792514303
Short name T51
Test name
Test status
Simulation time 2869421422 ps
CPU time 150.38 seconds
Started Jul 01 10:41:58 AM PDT 24
Finished Jul 01 10:44:30 AM PDT 24
Peak memory 200300 kb
Host smart-0bdf2710-24d1-43d1-a7a5-99e83d1eea0c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792514303 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 34.hmac_stress_all.792514303
Directory /workspace/34.hmac_stress_all/latest

Test location /workspace/coverage/default/34.hmac_wipe_secret.289947480
Short name T468
Test name
Test status
Simulation time 15606216265 ps
CPU time 48.73 seconds
Started Jul 01 10:41:19 AM PDT 24
Finished Jul 01 10:42:11 AM PDT 24
Peak memory 200372 kb
Host smart-e519403e-0237-41d3-b973-49ed389c2ceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289947480 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_wipe_secret.289947480
Directory /workspace/34.hmac_wipe_secret/latest

Test location /workspace/coverage/default/35.hmac_alert_test.269857155
Short name T443
Test name
Test status
Simulation time 40004438 ps
CPU time 0.58 seconds
Started Jul 01 10:41:41 AM PDT 24
Finished Jul 01 10:41:43 AM PDT 24
Peak memory 195704 kb
Host smart-9f2a5789-40fc-47e0-8da1-61d826238951
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269857155 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_alert_test.269857155
Directory /workspace/35.hmac_alert_test/latest

Test location /workspace/coverage/default/35.hmac_back_pressure.1448144231
Short name T183
Test name
Test status
Simulation time 459969831 ps
CPU time 21.89 seconds
Started Jul 01 10:41:22 AM PDT 24
Finished Jul 01 10:41:47 AM PDT 24
Peak memory 200376 kb
Host smart-50a69c7d-9496-44e4-8aad-d08eb8fe1284
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1448144231 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_back_pressure.1448144231
Directory /workspace/35.hmac_back_pressure/latest

Test location /workspace/coverage/default/35.hmac_burst_wr.1482815637
Short name T230
Test name
Test status
Simulation time 1784523080 ps
CPU time 24.51 seconds
Started Jul 01 10:41:24 AM PDT 24
Finished Jul 01 10:41:50 AM PDT 24
Peak memory 200192 kb
Host smart-7d27a943-eea2-4900-a72c-cfe7e3b76a98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482815637 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_burst_wr.1482815637
Directory /workspace/35.hmac_burst_wr/latest

Test location /workspace/coverage/default/35.hmac_datapath_stress.2851366814
Short name T155
Test name
Test status
Simulation time 1173303717 ps
CPU time 77.98 seconds
Started Jul 01 10:41:30 AM PDT 24
Finished Jul 01 10:42:50 AM PDT 24
Peak memory 330300 kb
Host smart-2fc6806d-6430-47ed-8902-9c11ee826d22
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2851366814 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_datapath_stress.2851366814
Directory /workspace/35.hmac_datapath_stress/latest

Test location /workspace/coverage/default/35.hmac_error.290720109
Short name T344
Test name
Test status
Simulation time 50356193027 ps
CPU time 227.68 seconds
Started Jul 01 10:41:15 AM PDT 24
Finished Jul 01 10:45:05 AM PDT 24
Peak memory 200208 kb
Host smart-f64075f1-d9b9-4941-ae4f-38079051ca78
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290720109 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_error.290720109
Directory /workspace/35.hmac_error/latest

Test location /workspace/coverage/default/35.hmac_long_msg.2925137510
Short name T409
Test name
Test status
Simulation time 10687786114 ps
CPU time 45.81 seconds
Started Jul 01 10:41:30 AM PDT 24
Finished Jul 01 10:42:18 AM PDT 24
Peak memory 200384 kb
Host smart-6944e667-9d8b-4fd1-9359-95856b39b2a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925137510 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_long_msg.2925137510
Directory /workspace/35.hmac_long_msg/latest

Test location /workspace/coverage/default/35.hmac_smoke.2749316140
Short name T517
Test name
Test status
Simulation time 726295263 ps
CPU time 12.11 seconds
Started Jul 01 10:42:00 AM PDT 24
Finished Jul 01 10:42:13 AM PDT 24
Peak memory 200360 kb
Host smart-d3898093-775b-4827-81a1-09f5b84555ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749316140 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_smoke.2749316140
Directory /workspace/35.hmac_smoke/latest

Test location /workspace/coverage/default/35.hmac_stress_all.1298019155
Short name T95
Test name
Test status
Simulation time 9759527544 ps
CPU time 551.63 seconds
Started Jul 01 10:41:25 AM PDT 24
Finished Jul 01 10:50:38 AM PDT 24
Peak memory 250852 kb
Host smart-fba71f5c-99cf-4579-92e9-3671f7074015
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298019155 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.hmac_stress_all.1298019155
Directory /workspace/35.hmac_stress_all/latest

Test location /workspace/coverage/default/35.hmac_wipe_secret.2392407620
Short name T512
Test name
Test status
Simulation time 6798326847 ps
CPU time 93.9 seconds
Started Jul 01 10:41:17 AM PDT 24
Finished Jul 01 10:42:55 AM PDT 24
Peak memory 200320 kb
Host smart-9c7d77b2-4fd4-43b1-a8c1-77701d3e23f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392407620 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_wipe_secret.2392407620
Directory /workspace/35.hmac_wipe_secret/latest

Test location /workspace/coverage/default/36.hmac_alert_test.4138981293
Short name T182
Test name
Test status
Simulation time 14446106 ps
CPU time 0.58 seconds
Started Jul 01 10:41:27 AM PDT 24
Finished Jul 01 10:41:29 AM PDT 24
Peak memory 195096 kb
Host smart-dbc18783-c467-4554-83f8-cac00674090b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138981293 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_alert_test.4138981293
Directory /workspace/36.hmac_alert_test/latest

Test location /workspace/coverage/default/36.hmac_back_pressure.1049575934
Short name T455
Test name
Test status
Simulation time 3493227318 ps
CPU time 48.16 seconds
Started Jul 01 10:41:17 AM PDT 24
Finished Jul 01 10:42:09 AM PDT 24
Peak memory 200236 kb
Host smart-67ba0256-3535-49a0-8db3-463a7ca08f72
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1049575934 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_back_pressure.1049575934
Directory /workspace/36.hmac_back_pressure/latest

Test location /workspace/coverage/default/36.hmac_burst_wr.167954293
Short name T440
Test name
Test status
Simulation time 3507347173 ps
CPU time 19.76 seconds
Started Jul 01 10:41:17 AM PDT 24
Finished Jul 01 10:41:41 AM PDT 24
Peak memory 200240 kb
Host smart-894e3d91-b314-4ce4-aada-4053c049855d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167954293 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_burst_wr.167954293
Directory /workspace/36.hmac_burst_wr/latest

Test location /workspace/coverage/default/36.hmac_datapath_stress.1847060657
Short name T31
Test name
Test status
Simulation time 1965824548 ps
CPU time 379.78 seconds
Started Jul 01 10:41:56 AM PDT 24
Finished Jul 01 10:48:18 AM PDT 24
Peak memory 684364 kb
Host smart-95d3ec79-a3f5-4933-90ac-d91a7ac9e8e3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1847060657 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_datapath_stress.1847060657
Directory /workspace/36.hmac_datapath_stress/latest

Test location /workspace/coverage/default/36.hmac_error.163560914
Short name T423
Test name
Test status
Simulation time 2210160644 ps
CPU time 119.97 seconds
Started Jul 01 10:41:16 AM PDT 24
Finished Jul 01 10:43:20 AM PDT 24
Peak memory 200216 kb
Host smart-cbf5093b-f7ae-40df-a985-dd6ef62ec2ad
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163560914 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_error.163560914
Directory /workspace/36.hmac_error/latest

Test location /workspace/coverage/default/36.hmac_long_msg.1290403282
Short name T477
Test name
Test status
Simulation time 1013121526 ps
CPU time 57.39 seconds
Started Jul 01 10:41:16 AM PDT 24
Finished Jul 01 10:42:17 AM PDT 24
Peak memory 200164 kb
Host smart-96e07e52-2f54-4eaf-8b9d-0c37895cd374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290403282 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_long_msg.1290403282
Directory /workspace/36.hmac_long_msg/latest

Test location /workspace/coverage/default/36.hmac_smoke.3454845782
Short name T265
Test name
Test status
Simulation time 3097320520 ps
CPU time 10.24 seconds
Started Jul 01 10:41:51 AM PDT 24
Finished Jul 01 10:42:04 AM PDT 24
Peak memory 200220 kb
Host smart-88928c7c-f6b3-4cc5-a5c4-550569e5b28c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454845782 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_smoke.3454845782
Directory /workspace/36.hmac_smoke/latest

Test location /workspace/coverage/default/36.hmac_stress_all.2341852464
Short name T312
Test name
Test status
Simulation time 29047243354 ps
CPU time 388.93 seconds
Started Jul 01 10:41:40 AM PDT 24
Finished Jul 01 10:48:10 AM PDT 24
Peak memory 216580 kb
Host smart-1f804419-417f-4b35-ad71-01930e8773da
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341852464 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.hmac_stress_all.2341852464
Directory /workspace/36.hmac_stress_all/latest

Test location /workspace/coverage/default/36.hmac_wipe_secret.3374939379
Short name T404
Test name
Test status
Simulation time 4285153971 ps
CPU time 55.44 seconds
Started Jul 01 10:41:21 AM PDT 24
Finished Jul 01 10:42:19 AM PDT 24
Peak memory 200172 kb
Host smart-e112345c-c6ec-449e-8d51-5e2ed9fd9d7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3374939379 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_wipe_secret.3374939379
Directory /workspace/36.hmac_wipe_secret/latest

Test location /workspace/coverage/default/37.hmac_alert_test.38984902
Short name T416
Test name
Test status
Simulation time 15908117 ps
CPU time 0.63 seconds
Started Jul 01 10:41:17 AM PDT 24
Finished Jul 01 10:41:21 AM PDT 24
Peak memory 196072 kb
Host smart-58498622-113a-42a8-925b-516329372216
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38984902 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_alert_test.38984902
Directory /workspace/37.hmac_alert_test/latest

Test location /workspace/coverage/default/37.hmac_back_pressure.684727772
Short name T288
Test name
Test status
Simulation time 612721043 ps
CPU time 34.85 seconds
Started Jul 01 10:41:52 AM PDT 24
Finished Jul 01 10:42:29 AM PDT 24
Peak memory 200184 kb
Host smart-06919ae8-7879-4201-ab34-ec6553877a6b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=684727772 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_back_pressure.684727772
Directory /workspace/37.hmac_back_pressure/latest

Test location /workspace/coverage/default/37.hmac_burst_wr.4060674555
Short name T420
Test name
Test status
Simulation time 17286311045 ps
CPU time 55.36 seconds
Started Jul 01 10:41:40 AM PDT 24
Finished Jul 01 10:42:36 AM PDT 24
Peak memory 200388 kb
Host smart-b8fad8ea-1095-420d-91f6-ddf0fd627439
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060674555 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_burst_wr.4060674555
Directory /workspace/37.hmac_burst_wr/latest

Test location /workspace/coverage/default/37.hmac_datapath_stress.480625893
Short name T7
Test name
Test status
Simulation time 6044279146 ps
CPU time 439.81 seconds
Started Jul 01 10:41:18 AM PDT 24
Finished Jul 01 10:48:41 AM PDT 24
Peak memory 667776 kb
Host smart-73675f99-bd1a-440f-b6c9-6009e4057259
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=480625893 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_datapath_stress.480625893
Directory /workspace/37.hmac_datapath_stress/latest

Test location /workspace/coverage/default/37.hmac_error.1030161042
Short name T480
Test name
Test status
Simulation time 3146240762 ps
CPU time 91.05 seconds
Started Jul 01 10:41:16 AM PDT 24
Finished Jul 01 10:42:50 AM PDT 24
Peak memory 200244 kb
Host smart-977fcc50-a2bc-4299-92de-a0eb8b80de14
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030161042 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_error.1030161042
Directory /workspace/37.hmac_error/latest

Test location /workspace/coverage/default/37.hmac_long_msg.3253383957
Short name T264
Test name
Test status
Simulation time 396435577 ps
CPU time 22.52 seconds
Started Jul 01 10:41:13 AM PDT 24
Finished Jul 01 10:41:37 AM PDT 24
Peak memory 200196 kb
Host smart-947ae97d-d46a-454f-8920-049485d1a9e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253383957 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_long_msg.3253383957
Directory /workspace/37.hmac_long_msg/latest

Test location /workspace/coverage/default/37.hmac_smoke.1940067391
Short name T90
Test name
Test status
Simulation time 2808909223 ps
CPU time 11.95 seconds
Started Jul 01 10:41:14 AM PDT 24
Finished Jul 01 10:41:28 AM PDT 24
Peak memory 200264 kb
Host smart-0bf664d4-a607-4eb1-aa61-242714958297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940067391 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_smoke.1940067391
Directory /workspace/37.hmac_smoke/latest

Test location /workspace/coverage/default/37.hmac_stress_all.70952131
Short name T236
Test name
Test status
Simulation time 15823359035 ps
CPU time 889.78 seconds
Started Jul 01 10:41:56 AM PDT 24
Finished Jul 01 10:56:48 AM PDT 24
Peak memory 434040 kb
Host smart-b8b87483-6bac-4db8-ace2-8f94186f47f8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70952131 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 37.hmac_stress_all.70952131
Directory /workspace/37.hmac_stress_all/latest

Test location /workspace/coverage/default/37.hmac_wipe_secret.2035760285
Short name T458
Test name
Test status
Simulation time 5210964163 ps
CPU time 47.54 seconds
Started Jul 01 10:41:18 AM PDT 24
Finished Jul 01 10:42:09 AM PDT 24
Peak memory 200340 kb
Host smart-0be8d1f1-72fd-4275-aee5-888896ccf684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035760285 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_wipe_secret.2035760285
Directory /workspace/37.hmac_wipe_secret/latest

Test location /workspace/coverage/default/38.hmac_alert_test.3040996497
Short name T300
Test name
Test status
Simulation time 12986419 ps
CPU time 0.61 seconds
Started Jul 01 10:41:17 AM PDT 24
Finished Jul 01 10:41:22 AM PDT 24
Peak memory 196140 kb
Host smart-2238aed0-3094-4396-8e7c-bed54160f713
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040996497 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_alert_test.3040996497
Directory /workspace/38.hmac_alert_test/latest

Test location /workspace/coverage/default/38.hmac_back_pressure.2345173931
Short name T27
Test name
Test status
Simulation time 13134002929 ps
CPU time 93.98 seconds
Started Jul 01 10:41:22 AM PDT 24
Finished Jul 01 10:42:59 AM PDT 24
Peak memory 200292 kb
Host smart-fd4f677f-bb60-4356-bc7d-5f90075f5db7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2345173931 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_back_pressure.2345173931
Directory /workspace/38.hmac_back_pressure/latest

Test location /workspace/coverage/default/38.hmac_burst_wr.4014974173
Short name T205
Test name
Test status
Simulation time 171488262 ps
CPU time 4.88 seconds
Started Jul 01 10:41:26 AM PDT 24
Finished Jul 01 10:41:33 AM PDT 24
Peak memory 200212 kb
Host smart-6d9e3398-26f7-4f93-8c26-301a17ffc919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014974173 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_burst_wr.4014974173
Directory /workspace/38.hmac_burst_wr/latest

Test location /workspace/coverage/default/38.hmac_datapath_stress.3481306740
Short name T424
Test name
Test status
Simulation time 11068022222 ps
CPU time 379.14 seconds
Started Jul 01 10:41:16 AM PDT 24
Finished Jul 01 10:47:39 AM PDT 24
Peak memory 447036 kb
Host smart-d9ce9a8c-ad0f-42fa-b835-d8f88f7f8cf4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3481306740 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_datapath_stress.3481306740
Directory /workspace/38.hmac_datapath_stress/latest

Test location /workspace/coverage/default/38.hmac_error.3640715564
Short name T156
Test name
Test status
Simulation time 18243946556 ps
CPU time 118.66 seconds
Started Jul 01 10:41:46 AM PDT 24
Finished Jul 01 10:43:45 AM PDT 24
Peak memory 200348 kb
Host smart-9500ca24-b705-43b6-8d8d-ca4eb66a095f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640715564 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_error.3640715564
Directory /workspace/38.hmac_error/latest

Test location /workspace/coverage/default/38.hmac_long_msg.278304839
Short name T234
Test name
Test status
Simulation time 70538839199 ps
CPU time 158.88 seconds
Started Jul 01 10:41:24 AM PDT 24
Finished Jul 01 10:44:05 AM PDT 24
Peak memory 200312 kb
Host smart-2c23e0c6-d7b8-4173-b81e-46278e8e7939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278304839 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_long_msg.278304839
Directory /workspace/38.hmac_long_msg/latest

Test location /workspace/coverage/default/38.hmac_smoke.906123940
Short name T179
Test name
Test status
Simulation time 1361515111 ps
CPU time 8.13 seconds
Started Jul 01 10:41:17 AM PDT 24
Finished Jul 01 10:41:28 AM PDT 24
Peak memory 200252 kb
Host smart-dbed7a0d-d51d-41df-9062-d941fbc94916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906123940 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_smoke.906123940
Directory /workspace/38.hmac_smoke/latest

Test location /workspace/coverage/default/38.hmac_stress_all.3042745623
Short name T25
Test name
Test status
Simulation time 96089083467 ps
CPU time 3786.67 seconds
Started Jul 01 10:41:19 AM PDT 24
Finished Jul 01 11:44:30 AM PDT 24
Peak memory 824888 kb
Host smart-d8211b65-12cd-442f-9ef3-33609a1bb809
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042745623 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.hmac_stress_all.3042745623
Directory /workspace/38.hmac_stress_all/latest

Test location /workspace/coverage/default/38.hmac_wipe_secret.3508763509
Short name T491
Test name
Test status
Simulation time 2032069534 ps
CPU time 88.68 seconds
Started Jul 01 10:41:20 AM PDT 24
Finished Jul 01 10:42:52 AM PDT 24
Peak memory 200036 kb
Host smart-ed5cf70e-07d6-45c3-8323-cbfcb89b8f22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508763509 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_wipe_secret.3508763509
Directory /workspace/38.hmac_wipe_secret/latest

Test location /workspace/coverage/default/39.hmac_alert_test.2393952134
Short name T396
Test name
Test status
Simulation time 58839456 ps
CPU time 0.62 seconds
Started Jul 01 10:41:19 AM PDT 24
Finished Jul 01 10:41:23 AM PDT 24
Peak memory 196132 kb
Host smart-39e7e63d-b0cc-4bd1-92d9-6e6ee32557cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393952134 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_alert_test.2393952134
Directory /workspace/39.hmac_alert_test/latest

Test location /workspace/coverage/default/39.hmac_back_pressure.2126716019
Short name T14
Test name
Test status
Simulation time 1472193909 ps
CPU time 81.21 seconds
Started Jul 01 10:41:19 AM PDT 24
Finished Jul 01 10:42:44 AM PDT 24
Peak memory 200172 kb
Host smart-f1ad386d-5ca6-4e67-8171-088f120f9d4f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2126716019 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_back_pressure.2126716019
Directory /workspace/39.hmac_back_pressure/latest

Test location /workspace/coverage/default/39.hmac_burst_wr.2875909993
Short name T261
Test name
Test status
Simulation time 509332332 ps
CPU time 27.74 seconds
Started Jul 01 10:41:28 AM PDT 24
Finished Jul 01 10:41:58 AM PDT 24
Peak memory 200252 kb
Host smart-69e53838-4aa7-408a-8c13-5201cdfdfc3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875909993 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_burst_wr.2875909993
Directory /workspace/39.hmac_burst_wr/latest

Test location /workspace/coverage/default/39.hmac_datapath_stress.2686777178
Short name T489
Test name
Test status
Simulation time 19450636010 ps
CPU time 1012.92 seconds
Started Jul 01 10:41:20 AM PDT 24
Finished Jul 01 10:58:16 AM PDT 24
Peak memory 691884 kb
Host smart-fa35873e-499a-4984-a193-0ed2bf313409
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2686777178 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_datapath_stress.2686777178
Directory /workspace/39.hmac_datapath_stress/latest

Test location /workspace/coverage/default/39.hmac_error.1837529323
Short name T54
Test name
Test status
Simulation time 64858766203 ps
CPU time 176.64 seconds
Started Jul 01 10:41:56 AM PDT 24
Finished Jul 01 10:44:55 AM PDT 24
Peak memory 200256 kb
Host smart-d9fb0b38-297d-4d99-85ad-4d71224e7a02
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837529323 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_error.1837529323
Directory /workspace/39.hmac_error/latest

Test location /workspace/coverage/default/39.hmac_long_msg.3577258469
Short name T260
Test name
Test status
Simulation time 45762466268 ps
CPU time 162.95 seconds
Started Jul 01 10:41:37 AM PDT 24
Finished Jul 01 10:44:21 AM PDT 24
Peak memory 200344 kb
Host smart-19f51f54-da4d-45fb-ae70-d1d6b0c17ecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577258469 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_long_msg.3577258469
Directory /workspace/39.hmac_long_msg/latest

Test location /workspace/coverage/default/39.hmac_smoke.2423686989
Short name T226
Test name
Test status
Simulation time 820562012 ps
CPU time 3.73 seconds
Started Jul 01 10:41:54 AM PDT 24
Finished Jul 01 10:42:00 AM PDT 24
Peak memory 200248 kb
Host smart-8c45fdad-9805-4fbf-95c6-feb13ebed33b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423686989 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_smoke.2423686989
Directory /workspace/39.hmac_smoke/latest

Test location /workspace/coverage/default/39.hmac_stress_all.443849404
Short name T64
Test name
Test status
Simulation time 38790944103 ps
CPU time 941.11 seconds
Started Jul 01 10:41:46 AM PDT 24
Finished Jul 01 10:57:28 AM PDT 24
Peak memory 677436 kb
Host smart-8d0ea694-409c-414b-a741-d807d1c3c754
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443849404 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 39.hmac_stress_all.443849404
Directory /workspace/39.hmac_stress_all/latest

Test location /workspace/coverage/default/39.hmac_wipe_secret.1314512957
Short name T383
Test name
Test status
Simulation time 8094115460 ps
CPU time 112.9 seconds
Started Jul 01 10:41:42 AM PDT 24
Finished Jul 01 10:43:36 AM PDT 24
Peak memory 200336 kb
Host smart-4297818b-f674-4781-9428-b15b344fd6ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314512957 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_wipe_secret.1314512957
Directory /workspace/39.hmac_wipe_secret/latest

Test location /workspace/coverage/default/4.hmac_alert_test.2448069783
Short name T529
Test name
Test status
Simulation time 13406242 ps
CPU time 0.56 seconds
Started Jul 01 10:40:42 AM PDT 24
Finished Jul 01 10:40:43 AM PDT 24
Peak memory 195016 kb
Host smart-9c7b92c5-a762-4fe7-baeb-fc2e07e73483
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448069783 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_alert_test.2448069783
Directory /workspace/4.hmac_alert_test/latest

Test location /workspace/coverage/default/4.hmac_back_pressure.3393435786
Short name T419
Test name
Test status
Simulation time 75466379 ps
CPU time 4.14 seconds
Started Jul 01 10:41:59 AM PDT 24
Finished Jul 01 10:42:05 AM PDT 24
Peak memory 199760 kb
Host smart-b9564b37-d1c6-4d2c-ada2-eb2869c5aa0f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3393435786 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_back_pressure.3393435786
Directory /workspace/4.hmac_back_pressure/latest

Test location /workspace/coverage/default/4.hmac_burst_wr.2584461066
Short name T160
Test name
Test status
Simulation time 3055399281 ps
CPU time 45.94 seconds
Started Jul 01 10:40:51 AM PDT 24
Finished Jul 01 10:41:38 AM PDT 24
Peak memory 200284 kb
Host smart-8b5755e2-eb5c-4a25-85e5-e74e485915bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584461066 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_burst_wr.2584461066
Directory /workspace/4.hmac_burst_wr/latest

Test location /workspace/coverage/default/4.hmac_datapath_stress.2446757803
Short name T364
Test name
Test status
Simulation time 10436280799 ps
CPU time 788.99 seconds
Started Jul 01 10:42:00 AM PDT 24
Finished Jul 01 10:55:11 AM PDT 24
Peak memory 746992 kb
Host smart-29bc68a0-6253-4098-9f09-e24f5b9f2530
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2446757803 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_datapath_stress.2446757803
Directory /workspace/4.hmac_datapath_stress/latest

Test location /workspace/coverage/default/4.hmac_error.2054371865
Short name T532
Test name
Test status
Simulation time 3210795869 ps
CPU time 180.8 seconds
Started Jul 01 10:40:51 AM PDT 24
Finished Jul 01 10:43:53 AM PDT 24
Peak memory 200256 kb
Host smart-cd710067-bfb1-4cf1-b98d-76f391b23da9
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054371865 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_error.2054371865
Directory /workspace/4.hmac_error/latest

Test location /workspace/coverage/default/4.hmac_long_msg.4203598850
Short name T279
Test name
Test status
Simulation time 7970019847 ps
CPU time 72.82 seconds
Started Jul 01 10:40:46 AM PDT 24
Finished Jul 01 10:42:01 AM PDT 24
Peak memory 200340 kb
Host smart-c636a76b-4c58-44af-93df-cdd3c9323040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4203598850 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_long_msg.4203598850
Directory /workspace/4.hmac_long_msg/latest

Test location /workspace/coverage/default/4.hmac_sec_cm.209777655
Short name T43
Test name
Test status
Simulation time 43723873 ps
CPU time 0.82 seconds
Started Jul 01 10:40:41 AM PDT 24
Finished Jul 01 10:40:43 AM PDT 24
Peak memory 218512 kb
Host smart-b2dbbb15-6b6a-44f0-af68-c04e734155b0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209777655 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_sec_cm.209777655
Directory /workspace/4.hmac_sec_cm/latest

Test location /workspace/coverage/default/4.hmac_smoke.2584552487
Short name T83
Test name
Test status
Simulation time 589842686 ps
CPU time 9.29 seconds
Started Jul 01 10:40:47 AM PDT 24
Finished Jul 01 10:40:57 AM PDT 24
Peak memory 200140 kb
Host smart-911468d2-fa9a-4ada-b7ce-5b622793e4fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584552487 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_smoke.2584552487
Directory /workspace/4.hmac_smoke/latest

Test location /workspace/coverage/default/4.hmac_stress_all.1994036992
Short name T94
Test name
Test status
Simulation time 15608551251 ps
CPU time 1263.03 seconds
Started Jul 01 10:40:45 AM PDT 24
Finished Jul 01 11:01:49 AM PDT 24
Peak memory 729152 kb
Host smart-888f97bf-8247-431b-88f0-46041f1dfc09
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994036992 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all.1994036992
Directory /workspace/4.hmac_stress_all/latest

Test location /workspace/coverage/default/4.hmac_stress_all_with_rand_reset.3794275197
Short name T61
Test name
Test status
Simulation time 1285473802588 ps
CPU time 5281.9 seconds
Started Jul 01 10:40:48 AM PDT 24
Finished Jul 01 12:08:51 PM PDT 24
Peak memory 832152 kb
Host smart-3f31e199-81b4-45fb-8e17-b77c2619806f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3794275197 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all_with_rand_reset.3794275197
Directory /workspace/4.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.hmac_test_hmac256_vectors.3457560387
Short name T216
Test name
Test status
Simulation time 7311929588 ps
CPU time 83.51 seconds
Started Jul 01 10:40:37 AM PDT 24
Finished Jul 01 10:42:01 AM PDT 24
Peak memory 200316 kb
Host smart-888b920f-5565-4119-bcaf-c3163ac25dbb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3457560387 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac256_vectors.3457560387
Directory /workspace/4.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_hmac384_vectors.2453496972
Short name T67
Test name
Test status
Simulation time 2238800244 ps
CPU time 84.6 seconds
Started Jul 01 10:41:05 AM PDT 24
Finished Jul 01 10:42:31 AM PDT 24
Peak memory 200296 kb
Host smart-bac581ce-7879-468c-84a3-c9cea9ebc4f2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2453496972 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac384_vectors.2453496972
Directory /workspace/4.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_hmac512_vectors.1634723286
Short name T192
Test name
Test status
Simulation time 6813844617 ps
CPU time 77.67 seconds
Started Jul 01 10:40:39 AM PDT 24
Finished Jul 01 10:41:57 AM PDT 24
Peak memory 200368 kb
Host smart-56668bc0-e64a-40d0-a200-e448205dc8b1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1634723286 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac512_vectors.1634723286
Directory /workspace/4.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha256_vectors.2968976009
Short name T473
Test name
Test status
Simulation time 21817554566 ps
CPU time 623.93 seconds
Started Jul 01 10:40:41 AM PDT 24
Finished Jul 01 10:51:06 AM PDT 24
Peak memory 200244 kb
Host smart-17d4931d-c48e-48eb-a036-87910dfb9058
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2968976009 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha256_vectors.2968976009
Directory /workspace/4.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha384_vectors.2485067015
Short name T211
Test name
Test status
Simulation time 160469628681 ps
CPU time 2154.7 seconds
Started Jul 01 10:40:46 AM PDT 24
Finished Jul 01 11:16:42 AM PDT 24
Peak memory 215756 kb
Host smart-f249c237-bf9e-46a4-9a34-a2ea41a0816b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2485067015 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha384_vectors.2485067015
Directory /workspace/4.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha512_vectors.2637936536
Short name T266
Test name
Test status
Simulation time 278248561871 ps
CPU time 2209 seconds
Started Jul 01 10:41:55 AM PDT 24
Finished Jul 01 11:18:47 AM PDT 24
Peak memory 215480 kb
Host smart-295db347-9955-426f-9722-1e1ce3a8423f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_200_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2637936536 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha512_vectors.2637936536
Directory /workspace/4.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/4.hmac_wipe_secret.97112814
Short name T202
Test name
Test status
Simulation time 12707774255 ps
CPU time 112.44 seconds
Started Jul 01 10:40:47 AM PDT 24
Finished Jul 01 10:42:40 AM PDT 24
Peak memory 200340 kb
Host smart-15a8fce7-6245-46c8-90a9-b14f8b24ea18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97112814 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_wipe_secret.97112814
Directory /workspace/4.hmac_wipe_secret/latest

Test location /workspace/coverage/default/40.hmac_alert_test.2414247622
Short name T353
Test name
Test status
Simulation time 46847865 ps
CPU time 0.62 seconds
Started Jul 01 10:41:22 AM PDT 24
Finished Jul 01 10:41:25 AM PDT 24
Peak memory 196140 kb
Host smart-a02394f6-41d7-44cf-90d1-7aa39e956461
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414247622 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_alert_test.2414247622
Directory /workspace/40.hmac_alert_test/latest

Test location /workspace/coverage/default/40.hmac_back_pressure.3731644984
Short name T306
Test name
Test status
Simulation time 1738278777 ps
CPU time 100.04 seconds
Started Jul 01 10:41:43 AM PDT 24
Finished Jul 01 10:43:23 AM PDT 24
Peak memory 200192 kb
Host smart-959c796b-c6bb-49d5-938a-a0874dd77803
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3731644984 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_back_pressure.3731644984
Directory /workspace/40.hmac_back_pressure/latest

Test location /workspace/coverage/default/40.hmac_burst_wr.3587078958
Short name T391
Test name
Test status
Simulation time 6137901324 ps
CPU time 24.47 seconds
Started Jul 01 10:41:31 AM PDT 24
Finished Jul 01 10:41:57 AM PDT 24
Peak memory 200388 kb
Host smart-6e82ce39-d569-4bd8-9daf-bd9112d3b460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587078958 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_burst_wr.3587078958
Directory /workspace/40.hmac_burst_wr/latest

Test location /workspace/coverage/default/40.hmac_datapath_stress.1787886860
Short name T352
Test name
Test status
Simulation time 4173644729 ps
CPU time 253.31 seconds
Started Jul 01 10:41:34 AM PDT 24
Finished Jul 01 10:45:48 AM PDT 24
Peak memory 575488 kb
Host smart-b2c2a179-08fc-40de-a415-e29378ca839d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1787886860 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_datapath_stress.1787886860
Directory /workspace/40.hmac_datapath_stress/latest

Test location /workspace/coverage/default/40.hmac_error.3281567670
Short name T47
Test name
Test status
Simulation time 2783341777 ps
CPU time 10.76 seconds
Started Jul 01 10:41:28 AM PDT 24
Finished Jul 01 10:41:40 AM PDT 24
Peak memory 200120 kb
Host smart-4dc8b97b-760a-40ca-9f47-f1920a0bc381
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281567670 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_error.3281567670
Directory /workspace/40.hmac_error/latest

Test location /workspace/coverage/default/40.hmac_long_msg.2357093438
Short name T191
Test name
Test status
Simulation time 1269691316 ps
CPU time 16.5 seconds
Started Jul 01 10:41:17 AM PDT 24
Finished Jul 01 10:41:38 AM PDT 24
Peak memory 200176 kb
Host smart-a49f772e-053e-483e-b00a-8b2ceca81afd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357093438 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_long_msg.2357093438
Directory /workspace/40.hmac_long_msg/latest

Test location /workspace/coverage/default/40.hmac_smoke.127896319
Short name T167
Test name
Test status
Simulation time 541961984 ps
CPU time 5.15 seconds
Started Jul 01 10:41:24 AM PDT 24
Finished Jul 01 10:41:31 AM PDT 24
Peak memory 200016 kb
Host smart-11d96771-d2b6-4e26-bfed-62c66cbea671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127896319 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_smoke.127896319
Directory /workspace/40.hmac_smoke/latest

Test location /workspace/coverage/default/40.hmac_stress_all.1392637300
Short name T76
Test name
Test status
Simulation time 122772594184 ps
CPU time 674.34 seconds
Started Jul 01 10:41:22 AM PDT 24
Finished Jul 01 10:52:39 AM PDT 24
Peak memory 485380 kb
Host smart-6fa8b1a2-c01e-4557-abd4-0886f5cb0de9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392637300 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.hmac_stress_all.1392637300
Directory /workspace/40.hmac_stress_all/latest

Test location /workspace/coverage/default/40.hmac_wipe_secret.2436163118
Short name T334
Test name
Test status
Simulation time 107163055891 ps
CPU time 76.86 seconds
Started Jul 01 10:41:36 AM PDT 24
Finished Jul 01 10:42:53 AM PDT 24
Peak memory 200224 kb
Host smart-cbf51aee-b3f3-47b1-9115-d547bb3da4bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436163118 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_wipe_secret.2436163118
Directory /workspace/40.hmac_wipe_secret/latest

Test location /workspace/coverage/default/41.hmac_alert_test.2216126066
Short name T89
Test name
Test status
Simulation time 22480139 ps
CPU time 0.61 seconds
Started Jul 01 10:41:24 AM PDT 24
Finished Jul 01 10:41:26 AM PDT 24
Peak memory 195884 kb
Host smart-54808219-81e6-45f6-a57e-a085909ef7c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216126066 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_alert_test.2216126066
Directory /workspace/41.hmac_alert_test/latest

Test location /workspace/coverage/default/41.hmac_back_pressure.166360914
Short name T403
Test name
Test status
Simulation time 284258190 ps
CPU time 7.82 seconds
Started Jul 01 10:41:22 AM PDT 24
Finished Jul 01 10:41:32 AM PDT 24
Peak memory 200176 kb
Host smart-483640e6-2237-4835-b728-5a6c9d28fe76
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=166360914 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_back_pressure.166360914
Directory /workspace/41.hmac_back_pressure/latest

Test location /workspace/coverage/default/41.hmac_burst_wr.3217979442
Short name T381
Test name
Test status
Simulation time 6616670527 ps
CPU time 60.02 seconds
Started Jul 01 10:41:26 AM PDT 24
Finished Jul 01 10:42:28 AM PDT 24
Peak memory 200344 kb
Host smart-6178969c-6c6b-483e-8447-e26b72eb2bc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217979442 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_burst_wr.3217979442
Directory /workspace/41.hmac_burst_wr/latest

Test location /workspace/coverage/default/41.hmac_datapath_stress.59856014
Short name T405
Test name
Test status
Simulation time 6424776771 ps
CPU time 274.89 seconds
Started Jul 01 10:41:22 AM PDT 24
Finished Jul 01 10:45:59 AM PDT 24
Peak memory 485468 kb
Host smart-02333216-a00c-4278-b2b5-79c7df66ac1e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=59856014 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_datapath_stress.59856014
Directory /workspace/41.hmac_datapath_stress/latest

Test location /workspace/coverage/default/41.hmac_error.2987167839
Short name T490
Test name
Test status
Simulation time 1091090176 ps
CPU time 59.6 seconds
Started Jul 01 10:41:30 AM PDT 24
Finished Jul 01 10:42:32 AM PDT 24
Peak memory 200184 kb
Host smart-cec21e5d-ae86-4eee-a763-4ed9da5afc22
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987167839 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_error.2987167839
Directory /workspace/41.hmac_error/latest

Test location /workspace/coverage/default/41.hmac_long_msg.2004347185
Short name T514
Test name
Test status
Simulation time 7747298262 ps
CPU time 142.93 seconds
Started Jul 01 10:41:28 AM PDT 24
Finished Jul 01 10:43:52 AM PDT 24
Peak memory 200364 kb
Host smart-8c65eecf-f6f4-42a1-acc0-27076bf01df3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004347185 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_long_msg.2004347185
Directory /workspace/41.hmac_long_msg/latest

Test location /workspace/coverage/default/41.hmac_smoke.4195899595
Short name T297
Test name
Test status
Simulation time 486377171 ps
CPU time 2.35 seconds
Started Jul 01 10:41:24 AM PDT 24
Finished Jul 01 10:41:28 AM PDT 24
Peak memory 200152 kb
Host smart-76bc8e77-a082-44f7-a82d-a474d62075e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4195899595 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_smoke.4195899595
Directory /workspace/41.hmac_smoke/latest

Test location /workspace/coverage/default/41.hmac_stress_all.1799064019
Short name T86
Test name
Test status
Simulation time 49991624402 ps
CPU time 325.92 seconds
Started Jul 01 10:41:28 AM PDT 24
Finished Jul 01 10:46:56 AM PDT 24
Peak memory 200144 kb
Host smart-1cad227e-7ff2-415f-b27d-4f558cc00425
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799064019 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.hmac_stress_all.1799064019
Directory /workspace/41.hmac_stress_all/latest

Test location /workspace/coverage/default/41.hmac_wipe_secret.3562289747
Short name T434
Test name
Test status
Simulation time 1324109222 ps
CPU time 22.18 seconds
Started Jul 01 10:41:24 AM PDT 24
Finished Jul 01 10:41:48 AM PDT 24
Peak memory 200220 kb
Host smart-1df9d749-de9e-4383-8c10-390a381b502b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562289747 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_wipe_secret.3562289747
Directory /workspace/41.hmac_wipe_secret/latest

Test location /workspace/coverage/default/42.hmac_alert_test.3426912063
Short name T286
Test name
Test status
Simulation time 19029786 ps
CPU time 0.63 seconds
Started Jul 01 10:41:31 AM PDT 24
Finished Jul 01 10:41:33 AM PDT 24
Peak memory 196140 kb
Host smart-2aab86ea-ebc8-4e46-8a7a-32c441b9f005
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426912063 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_alert_test.3426912063
Directory /workspace/42.hmac_alert_test/latest

Test location /workspace/coverage/default/42.hmac_back_pressure.1581641604
Short name T427
Test name
Test status
Simulation time 1172397543 ps
CPU time 32.03 seconds
Started Jul 01 10:41:26 AM PDT 24
Finished Jul 01 10:42:00 AM PDT 24
Peak memory 200088 kb
Host smart-64812e91-b7bf-4fb6-9667-0730a0bf5c22
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1581641604 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_back_pressure.1581641604
Directory /workspace/42.hmac_back_pressure/latest

Test location /workspace/coverage/default/42.hmac_burst_wr.2378738041
Short name T313
Test name
Test status
Simulation time 19810821 ps
CPU time 0.69 seconds
Started Jul 01 10:41:23 AM PDT 24
Finished Jul 01 10:41:26 AM PDT 24
Peak memory 196728 kb
Host smart-a0898c92-84e3-402b-af68-e4db48fb9681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378738041 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_burst_wr.2378738041
Directory /workspace/42.hmac_burst_wr/latest

Test location /workspace/coverage/default/42.hmac_datapath_stress.3368179480
Short name T280
Test name
Test status
Simulation time 14691049353 ps
CPU time 545.06 seconds
Started Jul 01 10:41:46 AM PDT 24
Finished Jul 01 10:50:52 AM PDT 24
Peak memory 643172 kb
Host smart-5fa487ae-7501-4997-b19b-9118bbaa3900
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3368179480 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_datapath_stress.3368179480
Directory /workspace/42.hmac_datapath_stress/latest

Test location /workspace/coverage/default/42.hmac_error.788329156
Short name T212
Test name
Test status
Simulation time 1095214270 ps
CPU time 35.24 seconds
Started Jul 01 10:41:20 AM PDT 24
Finished Jul 01 10:41:58 AM PDT 24
Peak memory 200048 kb
Host smart-a30eb5af-269d-4cbf-a664-2162d71f319e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788329156 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_error.788329156
Directory /workspace/42.hmac_error/latest

Test location /workspace/coverage/default/42.hmac_long_msg.4033817103
Short name T496
Test name
Test status
Simulation time 790319548 ps
CPU time 3.09 seconds
Started Jul 01 10:41:29 AM PDT 24
Finished Jul 01 10:41:34 AM PDT 24
Peak memory 200248 kb
Host smart-33eeaa7b-b988-45ca-b975-19d4be45a4cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033817103 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_long_msg.4033817103
Directory /workspace/42.hmac_long_msg/latest

Test location /workspace/coverage/default/42.hmac_smoke.3833425726
Short name T184
Test name
Test status
Simulation time 762919316 ps
CPU time 6.56 seconds
Started Jul 01 10:41:44 AM PDT 24
Finished Jul 01 10:41:51 AM PDT 24
Peak memory 200132 kb
Host smart-0d6c9559-1c58-4b07-932c-7f9e233a04af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833425726 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_smoke.3833425726
Directory /workspace/42.hmac_smoke/latest

Test location /workspace/coverage/default/42.hmac_stress_all.592628917
Short name T516
Test name
Test status
Simulation time 38874966453 ps
CPU time 165.33 seconds
Started Jul 01 10:41:36 AM PDT 24
Finished Jul 01 10:44:21 AM PDT 24
Peak memory 200324 kb
Host smart-1997dd70-30e4-4549-ab03-9f052534462d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592628917 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 42.hmac_stress_all.592628917
Directory /workspace/42.hmac_stress_all/latest

Test location /workspace/coverage/default/42.hmac_wipe_secret.2344391182
Short name T232
Test name
Test status
Simulation time 26524403741 ps
CPU time 90.32 seconds
Started Jul 01 10:41:23 AM PDT 24
Finished Jul 01 10:42:55 AM PDT 24
Peak memory 200304 kb
Host smart-896f4344-144f-40a2-a6a0-5d6ba04d23c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344391182 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_wipe_secret.2344391182
Directory /workspace/42.hmac_wipe_secret/latest

Test location /workspace/coverage/default/43.hmac_alert_test.3079680748
Short name T488
Test name
Test status
Simulation time 19741074 ps
CPU time 0.58 seconds
Started Jul 01 10:41:28 AM PDT 24
Finished Jul 01 10:41:31 AM PDT 24
Peak memory 196092 kb
Host smart-dec4a043-300e-4da5-bebf-d004d3b80919
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079680748 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_alert_test.3079680748
Directory /workspace/43.hmac_alert_test/latest

Test location /workspace/coverage/default/43.hmac_back_pressure.1493393586
Short name T304
Test name
Test status
Simulation time 1005016141 ps
CPU time 24.45 seconds
Started Jul 01 10:41:38 AM PDT 24
Finished Jul 01 10:42:03 AM PDT 24
Peak memory 200132 kb
Host smart-58adee6a-cd71-4f7b-adff-085e4b4dd08f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1493393586 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_back_pressure.1493393586
Directory /workspace/43.hmac_back_pressure/latest

Test location /workspace/coverage/default/43.hmac_burst_wr.237098975
Short name T474
Test name
Test status
Simulation time 12423502683 ps
CPU time 34.91 seconds
Started Jul 01 10:41:18 AM PDT 24
Finished Jul 01 10:41:57 AM PDT 24
Peak memory 199892 kb
Host smart-70c77ae0-eabe-47a3-b0ce-7c8a79779f7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237098975 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_burst_wr.237098975
Directory /workspace/43.hmac_burst_wr/latest

Test location /workspace/coverage/default/43.hmac_datapath_stress.189242616
Short name T281
Test name
Test status
Simulation time 23512464780 ps
CPU time 1040.04 seconds
Started Jul 01 10:41:38 AM PDT 24
Finished Jul 01 10:58:59 AM PDT 24
Peak memory 707396 kb
Host smart-ac4277e3-3445-425b-a877-2870ef66bf8f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=189242616 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_datapath_stress.189242616
Directory /workspace/43.hmac_datapath_stress/latest

Test location /workspace/coverage/default/43.hmac_error.1546498729
Short name T378
Test name
Test status
Simulation time 2179543958 ps
CPU time 122.37 seconds
Started Jul 01 10:41:36 AM PDT 24
Finished Jul 01 10:43:39 AM PDT 24
Peak memory 200624 kb
Host smart-14b560c0-b3e3-4a8a-9ecf-e620f349ff4d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546498729 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_error.1546498729
Directory /workspace/43.hmac_error/latest

Test location /workspace/coverage/default/43.hmac_long_msg.190086230
Short name T26
Test name
Test status
Simulation time 15218239838 ps
CPU time 114.87 seconds
Started Jul 01 10:41:45 AM PDT 24
Finished Jul 01 10:43:40 AM PDT 24
Peak memory 216548 kb
Host smart-1ed0a7d8-81a2-41fe-97dd-dae1cfdb688f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190086230 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_long_msg.190086230
Directory /workspace/43.hmac_long_msg/latest

Test location /workspace/coverage/default/43.hmac_smoke.1602752789
Short name T465
Test name
Test status
Simulation time 602489242 ps
CPU time 5.22 seconds
Started Jul 01 10:41:26 AM PDT 24
Finished Jul 01 10:41:32 AM PDT 24
Peak memory 200108 kb
Host smart-a097c6c4-a85b-4949-809b-c679f9dfd679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602752789 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_smoke.1602752789
Directory /workspace/43.hmac_smoke/latest

Test location /workspace/coverage/default/43.hmac_stress_all.4294324483
Short name T475
Test name
Test status
Simulation time 139582812204 ps
CPU time 3285.7 seconds
Started Jul 01 10:41:27 AM PDT 24
Finished Jul 01 11:36:15 AM PDT 24
Peak memory 778140 kb
Host smart-8f908efe-9d5c-4102-8cee-b874470bbbde
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294324483 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.hmac_stress_all.4294324483
Directory /workspace/43.hmac_stress_all/latest

Test location /workspace/coverage/default/43.hmac_wipe_secret.2916067020
Short name T97
Test name
Test status
Simulation time 5312215234 ps
CPU time 122.81 seconds
Started Jul 01 10:41:43 AM PDT 24
Finished Jul 01 10:43:46 AM PDT 24
Peak memory 200328 kb
Host smart-a3d9195a-fa77-40d5-a784-7489f79317cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916067020 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_wipe_secret.2916067020
Directory /workspace/43.hmac_wipe_secret/latest

Test location /workspace/coverage/default/44.hmac_alert_test.1562763909
Short name T374
Test name
Test status
Simulation time 35096342 ps
CPU time 0.61 seconds
Started Jul 01 10:41:23 AM PDT 24
Finished Jul 01 10:41:26 AM PDT 24
Peak memory 196444 kb
Host smart-1452cee9-a299-4370-83a8-32a30b892210
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562763909 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_alert_test.1562763909
Directory /workspace/44.hmac_alert_test/latest

Test location /workspace/coverage/default/44.hmac_back_pressure.544794962
Short name T15
Test name
Test status
Simulation time 2549878383 ps
CPU time 86.75 seconds
Started Jul 01 10:41:24 AM PDT 24
Finished Jul 01 10:42:53 AM PDT 24
Peak memory 200268 kb
Host smart-06d8e99e-4961-401e-9cdf-624b8c770e6e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=544794962 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_back_pressure.544794962
Directory /workspace/44.hmac_back_pressure/latest

Test location /workspace/coverage/default/44.hmac_burst_wr.1688650231
Short name T63
Test name
Test status
Simulation time 532896931 ps
CPU time 18.8 seconds
Started Jul 01 10:41:21 AM PDT 24
Finished Jul 01 10:41:43 AM PDT 24
Peak memory 200168 kb
Host smart-b1555507-d28c-40ec-8b64-f3632ead07ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688650231 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_burst_wr.1688650231
Directory /workspace/44.hmac_burst_wr/latest

Test location /workspace/coverage/default/44.hmac_datapath_stress.133897459
Short name T141
Test name
Test status
Simulation time 5422883724 ps
CPU time 228.54 seconds
Started Jul 01 10:41:26 AM PDT 24
Finished Jul 01 10:45:17 AM PDT 24
Peak memory 466500 kb
Host smart-5696f4a4-a201-4352-8681-6174e781ec1a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=133897459 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_datapath_stress.133897459
Directory /workspace/44.hmac_datapath_stress/latest

Test location /workspace/coverage/default/44.hmac_error.1400217800
Short name T240
Test name
Test status
Simulation time 6019755946 ps
CPU time 57.16 seconds
Started Jul 01 10:41:41 AM PDT 24
Finished Jul 01 10:42:39 AM PDT 24
Peak memory 200360 kb
Host smart-d02417a8-f5b3-4353-9ae5-d79f82e91680
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400217800 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_error.1400217800
Directory /workspace/44.hmac_error/latest

Test location /workspace/coverage/default/44.hmac_long_msg.1573764635
Short name T278
Test name
Test status
Simulation time 4587860430 ps
CPU time 66.08 seconds
Started Jul 01 10:41:24 AM PDT 24
Finished Jul 01 10:42:32 AM PDT 24
Peak memory 200316 kb
Host smart-21e2fe10-8cb4-4897-922e-0df20e7ff23f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573764635 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_long_msg.1573764635
Directory /workspace/44.hmac_long_msg/latest

Test location /workspace/coverage/default/44.hmac_smoke.4166016126
Short name T159
Test name
Test status
Simulation time 131560819 ps
CPU time 4.8 seconds
Started Jul 01 10:41:27 AM PDT 24
Finished Jul 01 10:41:34 AM PDT 24
Peak memory 200180 kb
Host smart-be1209eb-c705-4229-8773-6462595be44a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166016126 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_smoke.4166016126
Directory /workspace/44.hmac_smoke/latest

Test location /workspace/coverage/default/44.hmac_wipe_secret.559713840
Short name T175
Test name
Test status
Simulation time 7636431771 ps
CPU time 130.17 seconds
Started Jul 01 10:41:22 AM PDT 24
Finished Jul 01 10:43:35 AM PDT 24
Peak memory 200308 kb
Host smart-22b5b408-f7ac-4aa8-8fdb-61dc94ad1458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559713840 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_wipe_secret.559713840
Directory /workspace/44.hmac_wipe_secret/latest

Test location /workspace/coverage/default/45.hmac_alert_test.1687776618
Short name T146
Test name
Test status
Simulation time 45986839 ps
CPU time 0.59 seconds
Started Jul 01 10:41:29 AM PDT 24
Finished Jul 01 10:41:31 AM PDT 24
Peak memory 195772 kb
Host smart-13a4c34d-9220-413c-b2d3-db41e0ff365a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687776618 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_alert_test.1687776618
Directory /workspace/45.hmac_alert_test/latest

Test location /workspace/coverage/default/45.hmac_back_pressure.2672828921
Short name T171
Test name
Test status
Simulation time 4081510863 ps
CPU time 55.85 seconds
Started Jul 01 10:41:24 AM PDT 24
Finished Jul 01 10:42:22 AM PDT 24
Peak memory 208364 kb
Host smart-84bfba7e-fedc-4a01-938b-2c05b54b2eeb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2672828921 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_back_pressure.2672828921
Directory /workspace/45.hmac_back_pressure/latest

Test location /workspace/coverage/default/45.hmac_burst_wr.2840123433
Short name T69
Test name
Test status
Simulation time 8095425652 ps
CPU time 23.83 seconds
Started Jul 01 10:41:45 AM PDT 24
Finished Jul 01 10:42:09 AM PDT 24
Peak memory 200156 kb
Host smart-1cf11fae-12af-4694-9ab7-c1959ee86171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840123433 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_burst_wr.2840123433
Directory /workspace/45.hmac_burst_wr/latest

Test location /workspace/coverage/default/45.hmac_datapath_stress.2897071711
Short name T400
Test name
Test status
Simulation time 8712571556 ps
CPU time 1948.87 seconds
Started Jul 01 10:41:28 AM PDT 24
Finished Jul 01 11:13:59 AM PDT 24
Peak memory 758656 kb
Host smart-24571416-a3bf-4a85-9b0b-006b8f288f39
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2897071711 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_datapath_stress.2897071711
Directory /workspace/45.hmac_datapath_stress/latest

Test location /workspace/coverage/default/45.hmac_error.2965021170
Short name T92
Test name
Test status
Simulation time 563332157 ps
CPU time 10.11 seconds
Started Jul 01 10:41:57 AM PDT 24
Finished Jul 01 10:42:09 AM PDT 24
Peak memory 200036 kb
Host smart-bd7e2dfc-049c-4fb3-9e44-1c047c9f2a43
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965021170 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_error.2965021170
Directory /workspace/45.hmac_error/latest

Test location /workspace/coverage/default/45.hmac_long_msg.2095287985
Short name T421
Test name
Test status
Simulation time 2561661808 ps
CPU time 138.26 seconds
Started Jul 01 10:41:37 AM PDT 24
Finished Jul 01 10:43:56 AM PDT 24
Peak memory 200096 kb
Host smart-e1c97eb9-6839-4284-bcfc-0148213e7ff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095287985 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_long_msg.2095287985
Directory /workspace/45.hmac_long_msg/latest

Test location /workspace/coverage/default/45.hmac_smoke.1217179604
Short name T519
Test name
Test status
Simulation time 1326806895 ps
CPU time 11.66 seconds
Started Jul 01 10:41:43 AM PDT 24
Finished Jul 01 10:41:55 AM PDT 24
Peak memory 200220 kb
Host smart-2b0bb09b-b3d8-4f26-9904-98070c324e7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217179604 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_smoke.1217179604
Directory /workspace/45.hmac_smoke/latest

Test location /workspace/coverage/default/45.hmac_stress_all.621418282
Short name T411
Test name
Test status
Simulation time 37241101117 ps
CPU time 688.03 seconds
Started Jul 01 10:41:43 AM PDT 24
Finished Jul 01 10:53:12 AM PDT 24
Peak memory 406916 kb
Host smart-45ccd2ec-d145-4114-8045-d81a192112b8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621418282 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 45.hmac_stress_all.621418282
Directory /workspace/45.hmac_stress_all/latest

Test location /workspace/coverage/default/45.hmac_wipe_secret.719780314
Short name T484
Test name
Test status
Simulation time 33863894744 ps
CPU time 84.51 seconds
Started Jul 01 10:41:29 AM PDT 24
Finished Jul 01 10:42:56 AM PDT 24
Peak memory 200300 kb
Host smart-4acf8274-b55f-4dc6-b7ce-98782bbfdf1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719780314 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_wipe_secret.719780314
Directory /workspace/45.hmac_wipe_secret/latest

Test location /workspace/coverage/default/46.hmac_alert_test.3072868881
Short name T506
Test name
Test status
Simulation time 12460297 ps
CPU time 0.57 seconds
Started Jul 01 10:41:29 AM PDT 24
Finished Jul 01 10:41:31 AM PDT 24
Peak memory 195932 kb
Host smart-f3d6e0f0-e61a-41b6-bdec-c932efe5a43d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072868881 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_alert_test.3072868881
Directory /workspace/46.hmac_alert_test/latest

Test location /workspace/coverage/default/46.hmac_back_pressure.3768025964
Short name T340
Test name
Test status
Simulation time 605293834 ps
CPU time 30.71 seconds
Started Jul 01 10:41:26 AM PDT 24
Finished Jul 01 10:41:58 AM PDT 24
Peak memory 200176 kb
Host smart-e5ec2187-2a3e-4e43-bdcb-9807c6f86270
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3768025964 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_back_pressure.3768025964
Directory /workspace/46.hmac_back_pressure/latest

Test location /workspace/coverage/default/46.hmac_burst_wr.2361288409
Short name T38
Test name
Test status
Simulation time 783341596 ps
CPU time 43 seconds
Started Jul 01 10:41:33 AM PDT 24
Finished Jul 01 10:42:17 AM PDT 24
Peak memory 200088 kb
Host smart-146d202d-5e95-42b3-bd59-b4aa278031db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361288409 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_burst_wr.2361288409
Directory /workspace/46.hmac_burst_wr/latest

Test location /workspace/coverage/default/46.hmac_datapath_stress.2506255658
Short name T495
Test name
Test status
Simulation time 8283897594 ps
CPU time 780.83 seconds
Started Jul 01 10:41:46 AM PDT 24
Finished Jul 01 10:54:47 AM PDT 24
Peak memory 697316 kb
Host smart-c782f433-ceb5-49bd-ab92-a0c3e9dc18a7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2506255658 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_datapath_stress.2506255658
Directory /workspace/46.hmac_datapath_stress/latest

Test location /workspace/coverage/default/46.hmac_error.3680853085
Short name T238
Test name
Test status
Simulation time 12648022816 ps
CPU time 173.28 seconds
Started Jul 01 10:41:22 AM PDT 24
Finished Jul 01 10:44:18 AM PDT 24
Peak memory 200284 kb
Host smart-050b5b5c-d03f-4d64-a35d-a6ac143e9a7a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680853085 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_error.3680853085
Directory /workspace/46.hmac_error/latest

Test location /workspace/coverage/default/46.hmac_long_msg.2623684803
Short name T330
Test name
Test status
Simulation time 7781153129 ps
CPU time 141.29 seconds
Started Jul 01 10:41:27 AM PDT 24
Finished Jul 01 10:43:50 AM PDT 24
Peak memory 200368 kb
Host smart-5ecb640c-16b2-4038-81d9-2cd0408bd82c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623684803 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_long_msg.2623684803
Directory /workspace/46.hmac_long_msg/latest

Test location /workspace/coverage/default/46.hmac_smoke.1817869541
Short name T231
Test name
Test status
Simulation time 119534655 ps
CPU time 2.05 seconds
Started Jul 01 10:41:27 AM PDT 24
Finished Jul 01 10:41:31 AM PDT 24
Peak memory 200244 kb
Host smart-63f28709-fba2-4177-83ed-f88bf74d14b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817869541 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_smoke.1817869541
Directory /workspace/46.hmac_smoke/latest

Test location /workspace/coverage/default/46.hmac_wipe_secret.2119588759
Short name T1
Test name
Test status
Simulation time 2652313126 ps
CPU time 129.4 seconds
Started Jul 01 10:41:33 AM PDT 24
Finished Jul 01 10:43:44 AM PDT 24
Peak memory 200032 kb
Host smart-4bd1e2b2-4bde-43fb-b153-0651c3f5b19f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119588759 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_wipe_secret.2119588759
Directory /workspace/46.hmac_wipe_secret/latest

Test location /workspace/coverage/default/47.hmac_alert_test.3125395547
Short name T329
Test name
Test status
Simulation time 14848312 ps
CPU time 0.56 seconds
Started Jul 01 10:41:29 AM PDT 24
Finished Jul 01 10:41:32 AM PDT 24
Peak memory 195852 kb
Host smart-e56cd84b-e4ab-45f8-87a0-4394cd68c7d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125395547 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_alert_test.3125395547
Directory /workspace/47.hmac_alert_test/latest

Test location /workspace/coverage/default/47.hmac_back_pressure.2068049994
Short name T528
Test name
Test status
Simulation time 605915980 ps
CPU time 34.18 seconds
Started Jul 01 10:41:28 AM PDT 24
Finished Jul 01 10:42:04 AM PDT 24
Peak memory 200228 kb
Host smart-726bd190-fddd-46de-a9da-4da1f30c3a35
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2068049994 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_back_pressure.2068049994
Directory /workspace/47.hmac_back_pressure/latest

Test location /workspace/coverage/default/47.hmac_burst_wr.1052906079
Short name T207
Test name
Test status
Simulation time 3627599130 ps
CPU time 46.2 seconds
Started Jul 01 10:41:31 AM PDT 24
Finished Jul 01 10:42:19 AM PDT 24
Peak memory 200324 kb
Host smart-4ca6b92c-e332-4f14-b65b-f465f23bb843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052906079 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_burst_wr.1052906079
Directory /workspace/47.hmac_burst_wr/latest

Test location /workspace/coverage/default/47.hmac_datapath_stress.3693286116
Short name T422
Test name
Test status
Simulation time 3005300905 ps
CPU time 480.25 seconds
Started Jul 01 10:41:41 AM PDT 24
Finished Jul 01 10:49:42 AM PDT 24
Peak memory 695008 kb
Host smart-f0b61bdf-73b6-4073-84b4-69804ba2d057
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3693286116 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_datapath_stress.3693286116
Directory /workspace/47.hmac_datapath_stress/latest

Test location /workspace/coverage/default/47.hmac_error.511910302
Short name T53
Test name
Test status
Simulation time 52644103 ps
CPU time 0.8 seconds
Started Jul 01 10:41:55 AM PDT 24
Finished Jul 01 10:41:58 AM PDT 24
Peak memory 196996 kb
Host smart-98d2b187-af5b-49de-9e02-56c867687f65
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511910302 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_error.511910302
Directory /workspace/47.hmac_error/latest

Test location /workspace/coverage/default/47.hmac_long_msg.2220617793
Short name T65
Test name
Test status
Simulation time 15718336027 ps
CPU time 50.82 seconds
Started Jul 01 10:41:31 AM PDT 24
Finished Jul 01 10:42:23 AM PDT 24
Peak memory 200372 kb
Host smart-0a6d7d62-2731-40b0-9627-d565202ced2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2220617793 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_long_msg.2220617793
Directory /workspace/47.hmac_long_msg/latest

Test location /workspace/coverage/default/47.hmac_smoke.2805203514
Short name T243
Test name
Test status
Simulation time 235726959 ps
CPU time 3.11 seconds
Started Jul 01 10:42:06 AM PDT 24
Finished Jul 01 10:42:12 AM PDT 24
Peak memory 200336 kb
Host smart-7cfe95b2-e3f9-4bfd-8579-2bbc90116d0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805203514 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_smoke.2805203514
Directory /workspace/47.hmac_smoke/latest

Test location /workspace/coverage/default/47.hmac_stress_all.2205272111
Short name T75
Test name
Test status
Simulation time 62540002 ps
CPU time 0.66 seconds
Started Jul 01 10:41:33 AM PDT 24
Finished Jul 01 10:41:34 AM PDT 24
Peak memory 195808 kb
Host smart-8598b67d-1e8a-4265-82af-209995dbc30c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205272111 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.hmac_stress_all.2205272111
Directory /workspace/47.hmac_stress_all/latest

Test location /workspace/coverage/default/47.hmac_wipe_secret.1315308533
Short name T198
Test name
Test status
Simulation time 8491080417 ps
CPU time 61.21 seconds
Started Jul 01 10:41:27 AM PDT 24
Finished Jul 01 10:42:30 AM PDT 24
Peak memory 200300 kb
Host smart-22b3bbd7-60b2-46fd-9309-2ae39d581e9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315308533 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_wipe_secret.1315308533
Directory /workspace/47.hmac_wipe_secret/latest

Test location /workspace/coverage/default/48.hmac_alert_test.1387499849
Short name T503
Test name
Test status
Simulation time 12598143 ps
CPU time 0.6 seconds
Started Jul 01 10:41:43 AM PDT 24
Finished Jul 01 10:41:44 AM PDT 24
Peak memory 195108 kb
Host smart-e6be74ab-5550-4d0f-af58-d0f9af1c2e4e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387499849 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_alert_test.1387499849
Directory /workspace/48.hmac_alert_test/latest

Test location /workspace/coverage/default/48.hmac_back_pressure.2899408470
Short name T321
Test name
Test status
Simulation time 708014244 ps
CPU time 29.95 seconds
Started Jul 01 10:41:27 AM PDT 24
Finished Jul 01 10:41:59 AM PDT 24
Peak memory 200180 kb
Host smart-0308f48f-19bc-401c-80c6-92cae47f5155
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2899408470 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_back_pressure.2899408470
Directory /workspace/48.hmac_back_pressure/latest

Test location /workspace/coverage/default/48.hmac_burst_wr.3214852611
Short name T12
Test name
Test status
Simulation time 3585113897 ps
CPU time 11.52 seconds
Started Jul 01 10:41:28 AM PDT 24
Finished Jul 01 10:41:42 AM PDT 24
Peak memory 200320 kb
Host smart-5470aa77-8586-4334-b587-bc7288909f4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214852611 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_burst_wr.3214852611
Directory /workspace/48.hmac_burst_wr/latest

Test location /workspace/coverage/default/48.hmac_datapath_stress.813324708
Short name T462
Test name
Test status
Simulation time 18366094124 ps
CPU time 827.42 seconds
Started Jul 01 10:41:28 AM PDT 24
Finished Jul 01 10:55:17 AM PDT 24
Peak memory 725380 kb
Host smart-2efcb030-fb26-4cc7-9d4c-bd2daff4a587
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=813324708 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_datapath_stress.813324708
Directory /workspace/48.hmac_datapath_stress/latest

Test location /workspace/coverage/default/48.hmac_error.3028770282
Short name T345
Test name
Test status
Simulation time 14539451548 ps
CPU time 134.19 seconds
Started Jul 01 10:41:37 AM PDT 24
Finished Jul 01 10:43:51 AM PDT 24
Peak memory 200316 kb
Host smart-54970f7c-a7f7-49da-a084-66431b6fb4cc
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028770282 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_error.3028770282
Directory /workspace/48.hmac_error/latest

Test location /workspace/coverage/default/48.hmac_long_msg.1318786379
Short name T453
Test name
Test status
Simulation time 968271370 ps
CPU time 56.9 seconds
Started Jul 01 10:41:44 AM PDT 24
Finished Jul 01 10:42:41 AM PDT 24
Peak memory 200220 kb
Host smart-c71ade07-f958-4179-be3f-8b7cf56af52d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1318786379 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_long_msg.1318786379
Directory /workspace/48.hmac_long_msg/latest

Test location /workspace/coverage/default/48.hmac_smoke.4065652305
Short name T18
Test name
Test status
Simulation time 157481953 ps
CPU time 2.66 seconds
Started Jul 01 10:41:41 AM PDT 24
Finished Jul 01 10:41:44 AM PDT 24
Peak memory 200196 kb
Host smart-cdc15739-9100-4442-be45-fd12eaff1236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065652305 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_smoke.4065652305
Directory /workspace/48.hmac_smoke/latest

Test location /workspace/coverage/default/48.hmac_stress_all.1082810964
Short name T498
Test name
Test status
Simulation time 17199165101 ps
CPU time 716.76 seconds
Started Jul 01 10:41:27 AM PDT 24
Finished Jul 01 10:53:26 AM PDT 24
Peak memory 655376 kb
Host smart-039a1861-85dc-4b3e-89ac-7ccb483e458a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082810964 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.hmac_stress_all.1082810964
Directory /workspace/48.hmac_stress_all/latest

Test location /workspace/coverage/default/48.hmac_wipe_secret.1548198750
Short name T448
Test name
Test status
Simulation time 9835404968 ps
CPU time 129.72 seconds
Started Jul 01 10:41:26 AM PDT 24
Finished Jul 01 10:43:38 AM PDT 24
Peak memory 200300 kb
Host smart-9a70aa55-afc1-4e97-a108-153845d21148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1548198750 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_wipe_secret.1548198750
Directory /workspace/48.hmac_wipe_secret/latest

Test location /workspace/coverage/default/49.hmac_alert_test.2258127415
Short name T338
Test name
Test status
Simulation time 36632346 ps
CPU time 0.58 seconds
Started Jul 01 10:41:56 AM PDT 24
Finished Jul 01 10:41:59 AM PDT 24
Peak memory 195204 kb
Host smart-c2dafdf5-4816-45aa-a742-2d7449067438
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258127415 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_alert_test.2258127415
Directory /workspace/49.hmac_alert_test/latest

Test location /workspace/coverage/default/49.hmac_back_pressure.4291690661
Short name T147
Test name
Test status
Simulation time 658753918 ps
CPU time 8.81 seconds
Started Jul 01 10:41:44 AM PDT 24
Finished Jul 01 10:41:54 AM PDT 24
Peak memory 200196 kb
Host smart-9897ccf6-769c-42d7-9026-d1adc25acbf9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4291690661 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_back_pressure.4291690661
Directory /workspace/49.hmac_back_pressure/latest

Test location /workspace/coverage/default/49.hmac_burst_wr.517701187
Short name T450
Test name
Test status
Simulation time 244181365 ps
CPU time 4.56 seconds
Started Jul 01 10:41:25 AM PDT 24
Finished Jul 01 10:41:31 AM PDT 24
Peak memory 200292 kb
Host smart-959299dd-d4c9-4ebe-a939-011438687c9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517701187 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_burst_wr.517701187
Directory /workspace/49.hmac_burst_wr/latest

Test location /workspace/coverage/default/49.hmac_datapath_stress.77020870
Short name T258
Test name
Test status
Simulation time 816156639 ps
CPU time 86.29 seconds
Started Jul 01 10:41:44 AM PDT 24
Finished Jul 01 10:43:11 AM PDT 24
Peak memory 355308 kb
Host smart-5539d921-1f90-4bdb-90b6-1da4fdbb68ae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=77020870 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_datapath_stress.77020870
Directory /workspace/49.hmac_datapath_stress/latest

Test location /workspace/coverage/default/49.hmac_error.1872449313
Short name T388
Test name
Test status
Simulation time 6899590813 ps
CPU time 44.82 seconds
Started Jul 01 10:41:41 AM PDT 24
Finished Jul 01 10:42:26 AM PDT 24
Peak memory 200348 kb
Host smart-40a47453-16d1-4998-8e26-54a061b4a9f0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872449313 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_error.1872449313
Directory /workspace/49.hmac_error/latest

Test location /workspace/coverage/default/49.hmac_long_msg.355197078
Short name T143
Test name
Test status
Simulation time 63165300115 ps
CPU time 121.5 seconds
Started Jul 01 10:41:33 AM PDT 24
Finished Jul 01 10:43:35 AM PDT 24
Peak memory 200400 kb
Host smart-e95f9f0d-f468-4210-a233-5889b9516224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355197078 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_long_msg.355197078
Directory /workspace/49.hmac_long_msg/latest

Test location /workspace/coverage/default/49.hmac_smoke.1058938156
Short name T410
Test name
Test status
Simulation time 77987003 ps
CPU time 3.47 seconds
Started Jul 01 10:41:29 AM PDT 24
Finished Jul 01 10:41:35 AM PDT 24
Peak memory 200172 kb
Host smart-d279304c-bcc4-405c-8962-5c1b0eca5f72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058938156 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_smoke.1058938156
Directory /workspace/49.hmac_smoke/latest

Test location /workspace/coverage/default/49.hmac_stress_all.2755572385
Short name T428
Test name
Test status
Simulation time 214130492058 ps
CPU time 1030.55 seconds
Started Jul 01 10:41:45 AM PDT 24
Finished Jul 01 10:58:56 AM PDT 24
Peak memory 354844 kb
Host smart-2e5c380e-a520-4af1-adb5-4da95755435a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755572385 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.hmac_stress_all.2755572385
Directory /workspace/49.hmac_stress_all/latest

Test location /workspace/coverage/default/49.hmac_wipe_secret.668745850
Short name T494
Test name
Test status
Simulation time 66569694010 ps
CPU time 123.55 seconds
Started Jul 01 10:41:33 AM PDT 24
Finished Jul 01 10:43:37 AM PDT 24
Peak memory 200344 kb
Host smart-c912cf8a-a710-446f-8c34-b02b42aa56a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=668745850 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_wipe_secret.668745850
Directory /workspace/49.hmac_wipe_secret/latest

Test location /workspace/coverage/default/5.hmac_alert_test.2118323816
Short name T252
Test name
Test status
Simulation time 42325629 ps
CPU time 0.67 seconds
Started Jul 01 10:40:45 AM PDT 24
Finished Jul 01 10:40:47 AM PDT 24
Peak memory 197112 kb
Host smart-2776ad76-e672-4e19-a585-6ca2cd1f7004
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118323816 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_alert_test.2118323816
Directory /workspace/5.hmac_alert_test/latest

Test location /workspace/coverage/default/5.hmac_back_pressure.1064233041
Short name T511
Test name
Test status
Simulation time 583737438 ps
CPU time 31.8 seconds
Started Jul 01 10:42:07 AM PDT 24
Finished Jul 01 10:42:41 AM PDT 24
Peak memory 200032 kb
Host smart-1d44ba0c-8179-49af-8c74-65fe01dad835
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1064233041 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_back_pressure.1064233041
Directory /workspace/5.hmac_back_pressure/latest

Test location /workspace/coverage/default/5.hmac_burst_wr.2091273794
Short name T394
Test name
Test status
Simulation time 2605469923 ps
CPU time 33.05 seconds
Started Jul 01 10:42:05 AM PDT 24
Finished Jul 01 10:42:40 AM PDT 24
Peak memory 200108 kb
Host smart-ffc74fd0-c898-42cb-a615-82d0b7688e54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091273794 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_burst_wr.2091273794
Directory /workspace/5.hmac_burst_wr/latest

Test location /workspace/coverage/default/5.hmac_datapath_stress.2146058018
Short name T445
Test name
Test status
Simulation time 30195579 ps
CPU time 0.71 seconds
Started Jul 01 10:40:46 AM PDT 24
Finished Jul 01 10:40:50 AM PDT 24
Peak memory 198248 kb
Host smart-ff14b277-10c8-430f-9eb4-612fc916901b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2146058018 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_datapath_stress.2146058018
Directory /workspace/5.hmac_datapath_stress/latest

Test location /workspace/coverage/default/5.hmac_error.1662492445
Short name T176
Test name
Test status
Simulation time 702316909 ps
CPU time 37.22 seconds
Started Jul 01 10:40:49 AM PDT 24
Finished Jul 01 10:41:27 AM PDT 24
Peak memory 200056 kb
Host smart-3117263b-eb55-4b91-b27e-83b2a745a8e1
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662492445 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_error.1662492445
Directory /workspace/5.hmac_error/latest

Test location /workspace/coverage/default/5.hmac_long_msg.3535753141
Short name T308
Test name
Test status
Simulation time 1618619608 ps
CPU time 21.21 seconds
Started Jul 01 10:42:05 AM PDT 24
Finished Jul 01 10:42:28 AM PDT 24
Peak memory 199924 kb
Host smart-61c755fb-fbf3-4ea9-b8f6-3bb75246f00e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535753141 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_long_msg.3535753141
Directory /workspace/5.hmac_long_msg/latest

Test location /workspace/coverage/default/5.hmac_stress_all.2561294793
Short name T68
Test name
Test status
Simulation time 420632100089 ps
CPU time 1085.87 seconds
Started Jul 01 10:40:50 AM PDT 24
Finished Jul 01 10:58:57 AM PDT 24
Peak memory 654240 kb
Host smart-ba2f2e79-8026-4fa3-90a1-2457061d6c5b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561294793 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all.2561294793
Directory /workspace/5.hmac_stress_all/latest

Test location /workspace/coverage/default/5.hmac_stress_all_with_rand_reset.1412764922
Short name T62
Test name
Test status
Simulation time 81242571300 ps
CPU time 2290.87 seconds
Started Jul 01 10:41:08 AM PDT 24
Finished Jul 01 11:19:19 AM PDT 24
Peak memory 739772 kb
Host smart-f5bcaa1a-e1fe-4a42-9b5d-ae60437c8bad
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1412764922 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all_with_rand_reset.1412764922
Directory /workspace/5.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.hmac_wipe_secret.3293318883
Short name T379
Test name
Test status
Simulation time 1368125734 ps
CPU time 24.49 seconds
Started Jul 01 10:42:11 AM PDT 24
Finished Jul 01 10:42:39 AM PDT 24
Peak memory 200012 kb
Host smart-6c22dce6-f45a-4349-b3b2-c81bad49ff68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293318883 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_wipe_secret.3293318883
Directory /workspace/5.hmac_wipe_secret/latest

Test location /workspace/coverage/default/6.hmac_alert_test.2652602228
Short name T204
Test name
Test status
Simulation time 14093781 ps
CPU time 0.58 seconds
Started Jul 01 10:40:49 AM PDT 24
Finished Jul 01 10:40:50 AM PDT 24
Peak memory 196088 kb
Host smart-f1e3ba5b-06e3-483b-8980-baceeaf9626a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652602228 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_alert_test.2652602228
Directory /workspace/6.hmac_alert_test/latest

Test location /workspace/coverage/default/6.hmac_back_pressure.4151614105
Short name T471
Test name
Test status
Simulation time 358921695 ps
CPU time 19.11 seconds
Started Jul 01 10:40:50 AM PDT 24
Finished Jul 01 10:41:10 AM PDT 24
Peak memory 200120 kb
Host smart-a59662c7-a143-4f02-909b-a7414ca8c020
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4151614105 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_back_pressure.4151614105
Directory /workspace/6.hmac_back_pressure/latest

Test location /workspace/coverage/default/6.hmac_burst_wr.485761502
Short name T505
Test name
Test status
Simulation time 503349250 ps
CPU time 28.03 seconds
Started Jul 01 10:40:51 AM PDT 24
Finished Jul 01 10:41:20 AM PDT 24
Peak memory 200208 kb
Host smart-1eede294-772e-4ea9-9f62-55d43bc5d083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485761502 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_burst_wr.485761502
Directory /workspace/6.hmac_burst_wr/latest

Test location /workspace/coverage/default/6.hmac_datapath_stress.1370846802
Short name T188
Test name
Test status
Simulation time 7392671412 ps
CPU time 307.32 seconds
Started Jul 01 10:42:09 AM PDT 24
Finished Jul 01 10:47:19 AM PDT 24
Peak memory 665480 kb
Host smart-a71b7b95-da73-4c29-aa26-b509c6f34e0e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1370846802 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_datapath_stress.1370846802
Directory /workspace/6.hmac_datapath_stress/latest

Test location /workspace/coverage/default/6.hmac_error.3584147085
Short name T142
Test name
Test status
Simulation time 225779714990 ps
CPU time 138.65 seconds
Started Jul 01 10:42:06 AM PDT 24
Finished Jul 01 10:44:27 AM PDT 24
Peak memory 200184 kb
Host smart-66ff27c5-a234-490c-a6ac-7403ab8010f8
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584147085 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_error.3584147085
Directory /workspace/6.hmac_error/latest

Test location /workspace/coverage/default/6.hmac_long_msg.809834732
Short name T298
Test name
Test status
Simulation time 9657267261 ps
CPU time 179.97 seconds
Started Jul 01 10:40:47 AM PDT 24
Finished Jul 01 10:43:49 AM PDT 24
Peak memory 200352 kb
Host smart-b3ff617f-3043-479f-9ef1-aa6e1d350e2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809834732 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_long_msg.809834732
Directory /workspace/6.hmac_long_msg/latest

Test location /workspace/coverage/default/6.hmac_smoke.4278308853
Short name T220
Test name
Test status
Simulation time 1783268396 ps
CPU time 8.12 seconds
Started Jul 01 10:40:47 AM PDT 24
Finished Jul 01 10:40:57 AM PDT 24
Peak memory 200192 kb
Host smart-2778f811-37a0-4fb1-abba-04dbedbcbdfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278308853 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_smoke.4278308853
Directory /workspace/6.hmac_smoke/latest

Test location /workspace/coverage/default/6.hmac_stress_all.3268499487
Short name T237
Test name
Test status
Simulation time 78116885676 ps
CPU time 3471.84 seconds
Started Jul 01 10:40:35 AM PDT 24
Finished Jul 01 11:38:28 AM PDT 24
Peak memory 783116 kb
Host smart-aca8de9b-4638-408a-a8af-34020d633863
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268499487 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all.3268499487
Directory /workspace/6.hmac_stress_all/latest

Test location /workspace/coverage/default/6.hmac_stress_all_with_rand_reset.3643561137
Short name T23
Test name
Test status
Simulation time 183388249364 ps
CPU time 5112.44 seconds
Started Jul 01 10:40:41 AM PDT 24
Finished Jul 01 12:05:55 PM PDT 24
Peak memory 849284 kb
Host smart-77bc4aca-dc0c-4bad-a43d-4add66e446ea
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3643561137 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all_with_rand_reset.3643561137
Directory /workspace/6.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.hmac_wipe_secret.1972443341
Short name T467
Test name
Test status
Simulation time 30366461943 ps
CPU time 118.32 seconds
Started Jul 01 10:42:00 AM PDT 24
Finished Jul 01 10:43:59 AM PDT 24
Peak memory 200228 kb
Host smart-72b1c951-1091-4c4f-a10c-24a6e150c8c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972443341 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_wipe_secret.1972443341
Directory /workspace/6.hmac_wipe_secret/latest

Test location /workspace/coverage/default/7.hmac_alert_test.2314389999
Short name T225
Test name
Test status
Simulation time 34217985 ps
CPU time 0.59 seconds
Started Jul 01 10:40:42 AM PDT 24
Finished Jul 01 10:40:43 AM PDT 24
Peak memory 195104 kb
Host smart-09f1aa07-f90f-4ace-b776-aee5967fe5f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314389999 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_alert_test.2314389999
Directory /workspace/7.hmac_alert_test/latest

Test location /workspace/coverage/default/7.hmac_back_pressure.558381617
Short name T415
Test name
Test status
Simulation time 1109615722 ps
CPU time 60.58 seconds
Started Jul 01 10:40:56 AM PDT 24
Finished Jul 01 10:41:57 AM PDT 24
Peak memory 200060 kb
Host smart-e33b440c-269f-4473-bc0f-4932470a8f91
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=558381617 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_back_pressure.558381617
Directory /workspace/7.hmac_back_pressure/latest

Test location /workspace/coverage/default/7.hmac_burst_wr.3357057863
Short name T326
Test name
Test status
Simulation time 5224587700 ps
CPU time 67.09 seconds
Started Jul 01 10:40:56 AM PDT 24
Finished Jul 01 10:42:04 AM PDT 24
Peak memory 200528 kb
Host smart-47757624-6f29-451e-9176-52f0de03f068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357057863 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_burst_wr.3357057863
Directory /workspace/7.hmac_burst_wr/latest

Test location /workspace/coverage/default/7.hmac_datapath_stress.3221992361
Short name T436
Test name
Test status
Simulation time 327428396 ps
CPU time 16.81 seconds
Started Jul 01 10:42:05 AM PDT 24
Finished Jul 01 10:42:24 AM PDT 24
Peak memory 237852 kb
Host smart-b34d9537-4d1b-47b0-a6cd-cc8abcc5cafd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3221992361 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_datapath_stress.3221992361
Directory /workspace/7.hmac_datapath_stress/latest

Test location /workspace/coverage/default/7.hmac_error.1628944985
Short name T241
Test name
Test status
Simulation time 20484711128 ps
CPU time 84.28 seconds
Started Jul 01 10:41:16 AM PDT 24
Finished Jul 01 10:42:44 AM PDT 24
Peak memory 200296 kb
Host smart-46004510-cc7e-46e0-9780-cf3f8ff2284f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628944985 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_error.1628944985
Directory /workspace/7.hmac_error/latest

Test location /workspace/coverage/default/7.hmac_long_msg.4118591426
Short name T432
Test name
Test status
Simulation time 7798947723 ps
CPU time 138.41 seconds
Started Jul 01 10:42:03 AM PDT 24
Finished Jul 01 10:44:23 AM PDT 24
Peak memory 216396 kb
Host smart-876608fd-9940-40bd-ba66-6a13edb4b0f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118591426 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_long_msg.4118591426
Directory /workspace/7.hmac_long_msg/latest

Test location /workspace/coverage/default/7.hmac_smoke.3442126733
Short name T358
Test name
Test status
Simulation time 476435104 ps
CPU time 5.84 seconds
Started Jul 01 10:40:44 AM PDT 24
Finished Jul 01 10:40:51 AM PDT 24
Peak memory 200176 kb
Host smart-d64a16b8-5f96-493e-887b-6fbd544db3f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442126733 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_smoke.3442126733
Directory /workspace/7.hmac_smoke/latest

Test location /workspace/coverage/default/7.hmac_stress_all.2019452130
Short name T28
Test name
Test status
Simulation time 44530819520 ps
CPU time 717.5 seconds
Started Jul 01 10:40:49 AM PDT 24
Finished Jul 01 10:52:47 AM PDT 24
Peak memory 200284 kb
Host smart-79baf6db-3a2b-41bf-bd7c-5d011133efb6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019452130 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all.2019452130
Directory /workspace/7.hmac_stress_all/latest

Test location /workspace/coverage/default/7.hmac_stress_all_with_rand_reset.149480491
Short name T11
Test name
Test status
Simulation time 309198477260 ps
CPU time 6594.49 seconds
Started Jul 01 10:40:42 AM PDT 24
Finished Jul 01 12:30:39 PM PDT 24
Peak memory 864320 kb
Host smart-75da3004-67a4-440e-ac70-fab91bd64a52
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=149480491 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all_with_rand_reset.149480491
Directory /workspace/7.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.hmac_wipe_secret.2860138638
Short name T346
Test name
Test status
Simulation time 13620020882 ps
CPU time 41.15 seconds
Started Jul 01 10:40:49 AM PDT 24
Finished Jul 01 10:41:37 AM PDT 24
Peak memory 200268 kb
Host smart-bfa945bb-2d54-4b49-b3fc-aca43228792e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860138638 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_wipe_secret.2860138638
Directory /workspace/7.hmac_wipe_secret/latest

Test location /workspace/coverage/default/8.hmac_alert_test.3013316861
Short name T398
Test name
Test status
Simulation time 83831707 ps
CPU time 0.58 seconds
Started Jul 01 10:40:50 AM PDT 24
Finished Jul 01 10:40:52 AM PDT 24
Peak memory 196128 kb
Host smart-63958648-6b03-4787-9277-152267b0c232
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013316861 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_alert_test.3013316861
Directory /workspace/8.hmac_alert_test/latest

Test location /workspace/coverage/default/8.hmac_back_pressure.3597102616
Short name T369
Test name
Test status
Simulation time 960976559 ps
CPU time 53.05 seconds
Started Jul 01 10:42:03 AM PDT 24
Finished Jul 01 10:42:56 AM PDT 24
Peak memory 200076 kb
Host smart-73eba798-fa0c-4d02-bea2-93d94bf841b3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3597102616 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_back_pressure.3597102616
Directory /workspace/8.hmac_back_pressure/latest

Test location /workspace/coverage/default/8.hmac_burst_wr.3143710318
Short name T307
Test name
Test status
Simulation time 2893394824 ps
CPU time 27.13 seconds
Started Jul 01 10:40:44 AM PDT 24
Finished Jul 01 10:41:12 AM PDT 24
Peak memory 200240 kb
Host smart-7457b51e-3d02-47c2-b930-bab26dd0dcf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143710318 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_burst_wr.3143710318
Directory /workspace/8.hmac_burst_wr/latest

Test location /workspace/coverage/default/8.hmac_datapath_stress.2841781072
Short name T362
Test name
Test status
Simulation time 1274964893 ps
CPU time 189.58 seconds
Started Jul 01 10:42:07 AM PDT 24
Finished Jul 01 10:45:19 AM PDT 24
Peak memory 457000 kb
Host smart-86a6de85-3903-4776-88a6-8c7d804f1f52
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2841781072 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_datapath_stress.2841781072
Directory /workspace/8.hmac_datapath_stress/latest

Test location /workspace/coverage/default/8.hmac_error.4119237123
Short name T476
Test name
Test status
Simulation time 28430106799 ps
CPU time 123.02 seconds
Started Jul 01 10:40:38 AM PDT 24
Finished Jul 01 10:42:41 AM PDT 24
Peak memory 200296 kb
Host smart-d9683937-3490-43f9-ac41-ffcbac769443
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119237123 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_error.4119237123
Directory /workspace/8.hmac_error/latest

Test location /workspace/coverage/default/8.hmac_long_msg.510758666
Short name T328
Test name
Test status
Simulation time 123132888441 ps
CPU time 174.43 seconds
Started Jul 01 10:42:06 AM PDT 24
Finished Jul 01 10:45:02 AM PDT 24
Peak memory 200196 kb
Host smart-51e043fe-95e3-436f-802e-21b10cbfe203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510758666 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_long_msg.510758666
Directory /workspace/8.hmac_long_msg/latest

Test location /workspace/coverage/default/8.hmac_smoke.218166155
Short name T290
Test name
Test status
Simulation time 372020833 ps
CPU time 8.47 seconds
Started Jul 01 10:41:40 AM PDT 24
Finished Jul 01 10:41:50 AM PDT 24
Peak memory 199192 kb
Host smart-25eb3e6b-93e9-453a-ba51-9fc1ce1d286c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218166155 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_smoke.218166155
Directory /workspace/8.hmac_smoke/latest

Test location /workspace/coverage/default/8.hmac_stress_all.239114304
Short name T99
Test name
Test status
Simulation time 16661121665 ps
CPU time 98.45 seconds
Started Jul 01 10:42:07 AM PDT 24
Finished Jul 01 10:43:48 AM PDT 24
Peak memory 200152 kb
Host smart-33e4ce92-f34e-4c58-b6f1-dd53d5a81aa8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239114304 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all.239114304
Directory /workspace/8.hmac_stress_all/latest

Test location /workspace/coverage/default/8.hmac_wipe_secret.3243705164
Short name T469
Test name
Test status
Simulation time 42143772455 ps
CPU time 134.7 seconds
Started Jul 01 10:41:02 AM PDT 24
Finished Jul 01 10:43:17 AM PDT 24
Peak memory 200312 kb
Host smart-b894d480-648e-40cd-b6e7-b80167330bd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243705164 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_wipe_secret.3243705164
Directory /workspace/8.hmac_wipe_secret/latest

Test location /workspace/coverage/default/9.hmac_alert_test.3001007252
Short name T460
Test name
Test status
Simulation time 21060883 ps
CPU time 0.61 seconds
Started Jul 01 10:41:10 AM PDT 24
Finished Jul 01 10:41:11 AM PDT 24
Peak memory 196796 kb
Host smart-886cbafe-3810-4837-a8cf-96ebb0110d98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001007252 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_alert_test.3001007252
Directory /workspace/9.hmac_alert_test/latest

Test location /workspace/coverage/default/9.hmac_back_pressure.1425811087
Short name T521
Test name
Test status
Simulation time 486151210 ps
CPU time 13.37 seconds
Started Jul 01 10:40:45 AM PDT 24
Finished Jul 01 10:40:59 AM PDT 24
Peak memory 200116 kb
Host smart-0295e16f-3d3d-45d4-8298-2aa326e83356
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1425811087 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_back_pressure.1425811087
Directory /workspace/9.hmac_back_pressure/latest

Test location /workspace/coverage/default/9.hmac_burst_wr.3965188209
Short name T412
Test name
Test status
Simulation time 977476213 ps
CPU time 15.79 seconds
Started Jul 01 10:40:45 AM PDT 24
Finished Jul 01 10:41:02 AM PDT 24
Peak memory 200328 kb
Host smart-5adffa4d-2b34-41f6-92ae-401022da08a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965188209 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_burst_wr.3965188209
Directory /workspace/9.hmac_burst_wr/latest

Test location /workspace/coverage/default/9.hmac_datapath_stress.3971680347
Short name T504
Test name
Test status
Simulation time 4621942799 ps
CPU time 462.74 seconds
Started Jul 01 10:40:57 AM PDT 24
Finished Jul 01 10:48:41 AM PDT 24
Peak memory 675892 kb
Host smart-9d74c261-0f75-4c22-bf6f-03e75f69faa0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3971680347 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_datapath_stress.3971680347
Directory /workspace/9.hmac_datapath_stress/latest

Test location /workspace/coverage/default/9.hmac_error.1172923252
Short name T354
Test name
Test status
Simulation time 14076912146 ps
CPU time 237.01 seconds
Started Jul 01 10:40:50 AM PDT 24
Finished Jul 01 10:44:47 AM PDT 24
Peak memory 200304 kb
Host smart-c7a92adc-b99c-4c38-b4a7-d91351a07a7e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172923252 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_error.1172923252
Directory /workspace/9.hmac_error/latest

Test location /workspace/coverage/default/9.hmac_long_msg.1328386071
Short name T518
Test name
Test status
Simulation time 2620503910 ps
CPU time 131.81 seconds
Started Jul 01 10:40:40 AM PDT 24
Finished Jul 01 10:42:53 AM PDT 24
Peak memory 200228 kb
Host smart-8a79a20d-48cd-416b-a18d-e1c3b4ce7732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328386071 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_long_msg.1328386071
Directory /workspace/9.hmac_long_msg/latest

Test location /workspace/coverage/default/9.hmac_smoke.611466316
Short name T492
Test name
Test status
Simulation time 4424386398 ps
CPU time 11.66 seconds
Started Jul 01 10:40:41 AM PDT 24
Finished Jul 01 10:40:53 AM PDT 24
Peak memory 200344 kb
Host smart-05b11365-d105-4aa4-81fb-c54c9be19ea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611466316 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_smoke.611466316
Directory /workspace/9.hmac_smoke/latest

Test location /workspace/coverage/default/9.hmac_stress_all.1623033148
Short name T342
Test name
Test status
Simulation time 19589873663 ps
CPU time 797.51 seconds
Started Jul 01 10:41:13 AM PDT 24
Finished Jul 01 10:54:33 AM PDT 24
Peak memory 622468 kb
Host smart-d7c58641-8bbc-4fff-b20d-8d690d707206
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623033148 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all.1623033148
Directory /workspace/9.hmac_stress_all/latest

Test location /workspace/coverage/default/9.hmac_wipe_secret.1983468180
Short name T487
Test name
Test status
Simulation time 5311325044 ps
CPU time 59.79 seconds
Started Jul 01 10:40:56 AM PDT 24
Finished Jul 01 10:41:57 AM PDT 24
Peak memory 200276 kb
Host smart-e4e3fbd0-3832-45a4-8cff-86f11cbf6696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983468180 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_wipe_secret.1983468180
Directory /workspace/9.hmac_wipe_secret/latest
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