Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	17947053	1			T1	1798		T2	1		T3	2193
all_values[1]	17947053	1			T1	1798		T2	1		T3	2193
all_values[2]	17947053	1			T1	1798		T2	1		T3	2193

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

191414

1

T7

1818

T8

12

T11

772

auto[1]

53649745

1

T1

5394

T2

3

T3

6579

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

45958874

1

T1

4744

T2

3

T3

5966

auto[1]

7882285

1

T1

650

T3

613

T5

135

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	57707	1			T11	462		T21	171		T71	3
all_values[0]	auto[0]	auto[1]	324	1			T11	4		T21	4		T22	4
all_values[0]	auto[1]	auto[0]	17868042	1			T1	1794		T2	1		T3	2163
all_values[0]	auto[1]	auto[1]	20980	1			T1	4		T3	30		T5	135
all_values[1]	auto[0]	auto[0]	70193	1			T7	1818		T11	302		T15	87
all_values[1]	auto[0]	auto[1]	196	1			T21	1		T41	5		T12	5
all_values[1]	auto[1]	auto[0]	17876356	1			T1	1798		T2	1		T3	2193
all_values[1]	auto[1]	auto[1]	308	1			T8	2		T11	1		T21	3
all_values[2]	auto[0]	auto[0]	30616	1			T8	1		T11	2		T15	87
all_values[2]	auto[0]	auto[1]	32378	1			T8	11		T11	2		T21	3
all_values[2]	auto[1]	auto[0]	10055960	1			T1	1152		T2	1		T3	1610
all_values[2]	auto[1]	auto[1]	7828099	1			T1	646		T3	583		T4	26574