Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::msg_len_cg

Group : hmac_env_pkg::hmac_env_cov::msg_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
52.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	8	10	55.56
Crosses	32	16	16	50.00

Variables for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
hmac_en	2	0	2	100.00	100	1	1	2
msg_len_lower_cp	15	7	8	53.33	100	1	1	0
msg_len_upper_cp	1	1	0	0.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
msg_len_lower_cross	30	14	16	53.33	100	1	1	0
msg_len_upper_cross	2	2	0	0.00	100	1	1	0

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

141110

1

T1

4

T3

30

T6

44

auto[1]

154300

1

T1

4

T3

36

T5

144

---

Summary for Variable msg_len_lower_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	7	8	53.33

User Defined Bins for msg_len_lower_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
len_2049	0	1	1
len_2047	0	1	1
len_1025	0	1	1
len_1023	0	1	1
len_513	0	1	1
len_511	0	1	1
len_1	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_2050_plus	114277	1			T1	4		T3	1		T4	13
len_1026_2046	8069	1			T3	11		T6	1		T7	1
len_514_1022	5796	1			T3	7		T8	9		T11	177
len_2_510	5897	1			T3	6		T4	18		T7	15
len_2048	381	1			T3	2		T8	2		T11	3
len_1024	1866	1			T3	1		T5	72		T8	4
len_512	559	1			T3	4		T7	1		T8	2
len_0	10862	1			T3	1		T8	9		T11	79

---

Summary for Variable msg_len_upper_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	1	0	0.00

User Defined Bins for msg_len_upper_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
len_upper	0	1	1

---

Summary for Cross msg_len_lower_cross

Samples crossed: hmac_en msg_len_lower_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	14	16	53.33	14

Automatically Generated Cross Bins for msg_len_lower_cross

Element holes

hmac_en	msg_len_lower_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[len_2049]	--	--	2
*	[len_2047 , len_1025]	--	--	4
*	[len_1023 , len_513]	--	--	4
*	[len_511 , len_1]	--	--	4

Covered bins

hmac_en	msg_len_lower_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	len_2050_plus	57603	1			T1	2		T3	1		T6	21
auto[0]	len_1026_2046	3109	1			T3	1		T6	1		T8	32
auto[0]	len_514_1022	2666	1			T3	4		T8	4		T11	77
auto[0]	len_2_510	2271	1			T3	6		T8	2		T11	20
auto[0]	len_2048	208	1			T3	1		T8	1		T11	3
auto[0]	len_1024	300	1			T8	3		T11	5		T15	2
auto[0]	len_512	247	1			T3	2		T8	1		T11	4
auto[0]	len_0	4153	1			T11	6		T15	2		T23	3
auto[1]	len_2050_plus	56674	1			T1	2		T4	13		T6	11
auto[1]	len_1026_2046	4960	1			T3	10		T7	1		T8	99
auto[1]	len_514_1022	3130	1			T3	3		T8	5		T11	100
auto[1]	len_2_510	3626	1			T4	18		T7	15		T8	4
auto[1]	len_2048	173	1			T3	1		T8	1		T23	1
auto[1]	len_1024	1566	1			T3	1		T5	72		T8	1
auto[1]	len_512	312	1			T3	2		T7	1		T8	1
auto[1]	len_0	6709	1			T3	1		T8	9		T11	73

---

Summary for Cross msg_len_upper_cross

Samples crossed: hmac_en msg_len_upper_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	2	2	0	0.00	2

Automatically Generated Cross Bins for msg_len_upper_cross

Uncovered bins

hmac_en	msg_len_upper_cp	COUNT	AT LEAST	NUMBER	STATUS
*	*	--	--	2