Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::status_cg

Group : hmac_env_pkg::hmac_env_cov::status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	192	0	192	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	2
key_swap	2	0	2	100.00	100	1	1	2
sta_fifo_depth	8	0	8	100.00	100	1	1	0
sta_fifo_empty	2	0	2	100.00	100	1	1	2
sta_fifo_full	2	0	2	100.00	100	1	1	2

Crosses for Group hmac_env_pkg::hmac_env_cov::status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
fifo_empty_cross	32	0	32	100.00	100	1	1	0
fifo_full_cross	32	0	32	100.00	100	1	1	0
fifo_depth_cross	128	0	128	100.00	100	1	1	0

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4605799

1

T1

4

T3

434

T5

3127

auto[1]

2798583

1

T3

599

T4

13871

T6

24

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2856855

1

T3

450

T4

11390

T6

14

auto[1]

4547527

1

T1

4

T3

583

T5

3127

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3388031

1

T1

1

T3

419

T6

21

auto[1]

4016351

1

T1

3

T3

614

T5

3127

---

Summary for Variable key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for key_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4538605

1

T1

3

T3

541

T5

3127

auto[1]

2865777

1

T1

1

T3

492

T4

14177

---

Summary for Variable sta_fifo_depth

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for sta_fifo_depth

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	6564310	1			T1	2		T3	996		T5	2946
fifo_depth[1]	128452	1			T3	16		T5	130		T4	510
fifo_depth[2]	104695	1			T3	11		T5	40		T4	529
fifo_depth[3]	85083	1			T3	7		T5	8		T4	532
fifo_depth[4]	76822	1			T3	2		T5	3		T4	503
fifo_depth[5]	60955	1			T1	1		T3	1		T4	417
fifo_depth[6]	49196	1			T4	316		T7	234		T8	78
fifo_depth[7]	33279	1			T1	1		T4	210		T7	172

---

Summary for Variable sta_fifo_empty

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_empty

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

840072

1

T1

2

T3

37

T5

181

auto[1]

6564310

1

T1

2

T3

996

T5

2946

---

Summary for Variable sta_fifo_full

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_full

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7390692

1

T1

4

T3

1033

T5

3127

auto[1]

13690

1

T8

917

T21

602

T22

1013

---

Summary for Cross fifo_empty_cross

Samples crossed: sta_fifo_empty hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for fifo_empty_cross

Bins

sta_fifo_empty

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

41628

1

T8

5

T11

25

T21

2393

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

42689

1

T8

453

T11

112

T15

34

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

45383

1

T6

2

T11

43

T15

9

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

44701

1

T6

2

T8

1212

T11

40

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

192438

1

T6

1

T8

1399

T11

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

43520

1

T1

1

T6

1

T8

165

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

33651

1

T3

1

T6

1

T8

892

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

33489

1

T6

2

T8

737

T11

85

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

45072

1

T3

8

T4

128

T11

48

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

46074

1

T3

4

T4

173

T6

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

35222

1

T7

799

T8

50

T11

182

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

45551

1

T3

1

T4

210

T6

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

54516

1

T1

1

T5

181

T4

634

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

47766

1

T3

2

T4

956

T6

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

46901

1

T3

10

T4

945

T7

14

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

41471

1

T3

11

T4

165

T7

261

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

178482

1

T3

104

T8

31

T11

2573

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

175000

1

T8

514

T11

4678

T15

880

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

173758

1

T3

25

T6

3

T11

1546

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

178525

1

T6

1

T8

120

T11

1177

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

1675911

1

T3

98

T6

4

T8

476

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

172716

1

T3

61

T8

159

T11

987

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

169968

1

T3

81

T8

10

T11

2154

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

186172

1

T3

49

T6

4

T8

9

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

451218

1

T3

78

T4

634

T7

1350

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

507592

1

T3

70

T4

5636

T7

8567

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

427371

1

T3

27

T4

3967

T6

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

418589

1

T3

133

T4

642

T6

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

494025

1

T1

2

T5

2946

T4

4020

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

437152

1

T3

9

T4

3216

T6

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

473061

1

T3

109

T4

4763

T6

3

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

444770

1

T3

152

T4

3179

T6

1

---

Summary for Cross fifo_full_cross

Samples crossed: sta_fifo_full hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for fifo_full_cross

Bins

sta_fifo_full

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

218575

1

T3

104

T8

36

T11

2598

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

215441

1

T8

966

T11

4790

T15

914

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

217852

1

T3

25

T6

5

T11

1589

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

222114

1

T6

3

T8

1077

T11

1217

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

1867665

1

T3

98

T6

5

T8

1871

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

215239

1

T1

1

T3

61

T6

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

202756

1

T3

82

T6

1

T8

830

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

218643

1

T3

49

T6

6

T8

430

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

495591

1

T3

86

T4

762

T7

1350

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

553525

1

T3

74

T4

5809

T6

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

462352

1

T3

27

T4

3967

T6

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

463801

1

T3

134

T4

852

T6

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

548072

1

T1

3

T5

3127

T4

4654

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

483798

1

T3

11

T4

4172

T6

4

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

519342

1

T3

119

T4

5708

T6

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

485926

1

T3

163

T4

3344

T6

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

1535

1

T21

118

T22

83

T118

24

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

2248

1

T8

1

T21

71

T22

21

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

1289

1

T22

79

T41

5

T17

3

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

1112

1

T8

255

T21

10

T22

106

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

684

1

T8

4

T21

1

T41

320

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

997

1

T8

33

T21

261

T41

3

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

863

1

T8

72

T21

4

T103

12

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

1018

1

T8

316

T21

59

T22

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

699

1

T17

92

T103

5

T83

107

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

141

1

T8

2

T118

106

T17

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

241

1

T22

11

T17

1

T119

63

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

339

1

T8

78

T41

9

T10

13

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

469

1

T17

24

T75

8

T103

359

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

1120

1

T22

712

T17

18

T75

8

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

620

1

T8

156

T21

78

T41

9

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

315

1

T103

1

T119

2

T120

3

---

Summary for Cross fifo_depth_cross

Samples crossed: sta_fifo_depth hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for fifo_depth_cross

Bins

sta_fifo_depth

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fifo_depth[0]

auto[0]

auto[0]

auto[0]

auto[0]

178482

1

T3

104

T8

31

T11

2573

fifo_depth[0]

auto[0]

auto[0]

auto[0]

auto[1]

175000

1

T8

514

T11

4678

T15

880

fifo_depth[0]

auto[0]

auto[0]

auto[1]

auto[0]

173758

1

T3

25

T6

3

T11

1546

fifo_depth[0]

auto[0]

auto[0]

auto[1]

auto[1]

178525

1

T6

1

T8

120

T11

1177

fifo_depth[0]

auto[0]

auto[1]

auto[0]

auto[0]

1675911

1

T3

98

T6

4

T8

476

fifo_depth[0]

auto[0]

auto[1]

auto[0]

auto[1]

172716

1

T3

61

T8

159

T11

987

fifo_depth[0]

auto[0]

auto[1]

auto[1]

auto[0]

169968

1

T3

81

T8

10

T11

2154

fifo_depth[0]

auto[0]

auto[1]

auto[1]

auto[1]

186172

1

T3

49

T6

4

T8

9

fifo_depth[0]

auto[1]

auto[0]

auto[0]

auto[0]

451218

1

T3

78

T4

634

T7

1350

fifo_depth[0]

auto[1]

auto[0]

auto[0]

auto[1]

507592

1

T3

70

T4

5636

T7

8567

fifo_depth[0]

auto[1]

auto[0]

auto[1]

auto[0]

427371

1

T3

27

T4

3967

T6

2

fifo_depth[0]

auto[1]

auto[0]

auto[1]

auto[1]

418589

1

T3

133

T4

642

T6

2

fifo_depth[0]

auto[1]

auto[1]

auto[0]

auto[0]

494025

1

T1

2

T5

2946

T4

4020

fifo_depth[0]

auto[1]

auto[1]

auto[0]

auto[1]

437152

1

T3

9

T4

3216

T6

2

fifo_depth[0]

auto[1]

auto[1]

auto[1]

auto[0]

473061

1

T3

109

T4

4763

T6

3

fifo_depth[0]

auto[1]

auto[1]

auto[1]

auto[1]

444770

1

T3

152

T4

3179

T6

1

fifo_depth[1]

auto[0]

auto[0]

auto[0]

auto[0]

3655

1

T8

1

T11

16

T21

112

fifo_depth[1]

auto[0]

auto[0]

auto[0]

auto[1]

4133

1

T8

2

T11

82

T15

25

fifo_depth[1]

auto[0]

auto[0]

auto[1]

auto[0]

3981

1

T11

20

T15

5

T21

12

fifo_depth[1]

auto[0]

auto[0]

auto[1]

auto[1]

3984

1

T8

28

T11

13

T15

15

fifo_depth[1]

auto[0]

auto[1]

auto[0]

auto[0]

48548

1

T8

17

T11

2

T15

24

fifo_depth[1]

auto[0]

auto[1]

auto[0]

auto[1]

3530

1

T8

8

T11

23

T21

92

fifo_depth[1]

auto[0]

auto[1]

auto[1]

auto[0]

3473

1

T3

1

T8

1

T11

30

fifo_depth[1]

auto[0]

auto[1]

auto[1]

auto[1]

3734

1

T11

68

T15

11

T21

111

fifo_depth[1]

auto[1]

auto[0]

auto[0]

auto[0]

6973

1

T3

5

T4

22

T11

38

fifo_depth[1]

auto[1]

auto[0]

auto[0]

auto[1]

6669

1

T4

26

T7

119

T11

68

fifo_depth[1]

auto[1]

auto[0]

auto[1]

auto[0]

5265

1

T7

108

T11

125

T15

23

fifo_depth[1]

auto[1]

auto[0]

auto[1]

auto[1]

6523

1

T3

1

T4

31

T11

70

fifo_depth[1]

auto[1]

auto[1]

auto[0]

auto[0]

8717

1

T5

130

T4

116

T11

57

fifo_depth[1]

auto[1]

auto[1]

auto[0]

auto[1]

6696

1

T4

139

T7

119

T11

5

fifo_depth[1]

auto[1]

auto[1]

auto[1]

auto[0]

6662

1

T3

4

T4

144

T7

2

fifo_depth[1]

auto[1]

auto[1]

auto[1]

auto[1]

5909

1

T3

5

T4

32

T7

57

fifo_depth[2]

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1

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18

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8

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1

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1

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12

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1

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14

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6

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1

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2

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4

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1

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8

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1

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112

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1

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130

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47

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4

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1

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23

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1

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134

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1

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3

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160

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3

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1

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33

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51

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1

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8

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1

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1

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3

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1

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1

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19

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2

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1

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32

T7

98

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1

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108

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1

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4

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1

T4

27

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6

T21

32

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1

T5

8

T4

109

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6

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1

T4

149

T7

108

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2

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1

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1

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166

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1

T3

3

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30

T7

48

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1

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1

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159

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31

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1

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1

T21

68

fifo_depth[4]

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1

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5

T15

1

T21

86

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1

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30

T11

4

T21

146

fifo_depth[4]

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1

T8

31

T15

1

T21

23

fifo_depth[4]

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1

T8

7

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6

T21

68

fifo_depth[4]

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1

T8

6

T11

6

T21

102

fifo_depth[4]

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1

T8

1

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1

T21

113

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1

T3

1

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21

T23

2

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1

T4

18

T7

84

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10

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1

T7

115

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5

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2

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1

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1

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25

fifo_depth[4]

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1

T5

3

T4

119

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2

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1

T4

136

T7

103

T21

162

fifo_depth[4]

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1

T3

1

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156

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4

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1

T4

28

T7

35

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1

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1

T21

110

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3

T22

74

fifo_depth[5]

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1

T8

2

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3

T21

57

fifo_depth[5]

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1

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3

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8

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4

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1

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32

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2

T21

118

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1

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16

T21

21

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9

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1

T8

8

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4

T21

45

fifo_depth[5]

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1

T11

1

T21

74

T121

21

fifo_depth[5]

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1

T11

1

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100

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13

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1

T4

13

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1

T21

193

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1

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20

T7

91

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12

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1

T7

112

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3

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50

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1

T4

28

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1

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89

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1

T4

130

T7

94

T21

155

fifo_depth[5]

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1

T3

1

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121

T7

1

fifo_depth[5]

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1

T4

16

T7

35

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1

T21

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40

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13

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79

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1

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2

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1

T8

33

T21

94

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13

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1

T8

29

T21

37

T42

1

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1

T8

6

T21

33

T47

1

fifo_depth[6]

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1

T11

3

T21

58

T121

13

fifo_depth[6]

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1

T11

1

T21

89

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4

fifo_depth[6]

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1

T4

16

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1

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136

fifo_depth[6]

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1

T4

19

T7

56

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7

fifo_depth[6]

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1

T7

93

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1

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50

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1

T4

26

T11

1

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10

fifo_depth[6]

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1

T4

43

T11

2

T21

231

fifo_depth[6]

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1

T4

114

T7

65

T21

129

fifo_depth[6]

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1

T4

90

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1

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1

fifo_depth[6]

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1

T4

8

T7

19

T23

2

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76

T22

65

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8

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1

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T21

62

T121

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1

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19

T121

4

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1

T8

31

T21

53

T121

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1

T8

19

T21

34

T48

986

fifo_depth[7]

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1

T1

1

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5

T21

13

fifo_depth[7]

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1

T8

2

T21

36

T121

10

fifo_depth[7]

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1

T11

1

T21

46

T121

1

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2218

1

T4

10

T23

1

T21

110

fifo_depth[7]

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1

T4

9

T7

32

T8

13

fifo_depth[7]

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1

T7

71

T23

2

T21

32

fifo_depth[7]

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1

T4

19

T11

2

T21

7

fifo_depth[7]

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1

T4

24

T11

1

T21

177

fifo_depth[7]

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2552

1

T4

81

T7

60

T21

72

fifo_depth[7]

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auto[0]

2346

1

T4

59

T7

1

T8

1

fifo_depth[7]

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auto[1]

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2184

1

T4

8

T7

8

T23

1