Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	17947053	1			T1	1798		T2	1		T3	2193
all_pins[1]	17947053	1			T1	1798		T2	1		T3	2193
all_pins[2]	17947053	1			T1	1798		T2	1		T3	2193

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	45990829	1			T1	4743		T2	3		T3	5965
values[0x1]	7850330	1			T1	651		T3	614		T5	135
transitions[0x0=>0x1]	7850166	1			T1	651		T3	614		T5	135
transitions[0x1=>0x0]	7850178	1			T1	651		T3	614		T5	135

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	17925158	1			T1	1793		T2	1		T3	2162
all_pins[0]	values[0x1]	21895	1			T1	5		T3	31		T5	135
all_pins[0]	transitions[0x0=>0x1]	21812	1			T1	5		T3	31		T5	135
all_pins[0]	transitions[0x1=>0x0]	7828028	1			T1	646		T3	583		T4	26574
all_pins[1]	values[0x0]	17946717	1			T1	1798		T2	1		T3	2193
all_pins[1]	values[0x1]	336	1			T8	3		T11	1		T21	3
all_pins[1]	transitions[0x0=>0x1]	296	1			T8	3		T21	3		T22	3
all_pins[1]	transitions[0x1=>0x0]	21855	1			T1	5		T3	31		T5	135
all_pins[2]	values[0x0]	10118954	1			T1	1152		T2	1		T3	1610
all_pins[2]	values[0x1]	7828099	1			T1	646		T3	583		T4	26574
all_pins[2]	transitions[0x0=>0x1]	7828058	1			T1	646		T3	583		T4	26574
all_pins[2]	transitions[0x1=>0x0]	295	1			T8	3		T11	1		T21	2