Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 0 18 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 0 18 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 897 1 T11 10 T21 4 T41 17
all_values[1] 897 1 T11 10 T21 4 T41 17
all_values[2] 897 1 T11 10 T21 4 T41 17


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1385 1 T11 10 T21 7 T41 28
auto[1] 1306 1 T11 20 T21 5 T41 23


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 911 1 T11 17 T21 1 T41 13
auto[1] 1780 1 T11 13 T21 11 T41 38


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1519 1 T11 23 T21 6 T41 24
auto[1] 1172 1 T11 7 T21 6 T41 27


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 0 18 100.00
Automatically Generated Cross Bins 18 0 18 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 190 1 T11 3 T41 1 T77 6
all_values[0] auto[0] auto[0] auto[1] 71 1 T21 2 T41 1 T12 1
all_values[0] auto[0] auto[1] auto[0] 148 1 T41 3 T12 5 T17 1
all_values[0] auto[0] auto[1] auto[1] 105 1 T11 3 T41 1 T12 2
all_values[0] auto[1] auto[0] auto[1] 203 1 T11 1 T21 1 T41 8
all_values[0] auto[1] auto[1] auto[1] 180 1 T11 3 T21 1 T41 3
all_values[1] auto[0] auto[0] auto[0] 144 1 T11 1 T21 1 T12 1
all_values[1] auto[0] auto[0] auto[1] 114 1 T21 1 T12 1 T17 1
all_values[1] auto[0] auto[1] auto[0] 137 1 T11 7 T41 4 T12 2
all_values[1] auto[0] auto[1] auto[1] 116 1 T11 1 T41 4 T12 3
all_values[1] auto[1] auto[0] auto[1] 199 1 T41 5 T12 5 T77 4
all_values[1] auto[1] auto[1] auto[1] 187 1 T11 1 T21 2 T41 4
all_values[2] auto[0] auto[0] auto[0] 153 1 T11 3 T41 5 T12 3
all_values[2] auto[0] auto[0] auto[1] 113 1 T11 1 T21 1 T41 3
all_values[2] auto[0] auto[1] auto[0] 139 1 T11 3 T12 8 T17 1
all_values[2] auto[0] auto[1] auto[1] 89 1 T11 1 T21 1 T41 2
all_values[2] auto[1] auto[0] auto[1] 198 1 T11 1 T21 1 T41 5
all_values[2] auto[1] auto[1] auto[1] 205 1 T11 1 T21 1 T41 2


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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