Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::cfg_cg

Group : hmac_env_pkg::hmac_env_cov::cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	90	0	90	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_size	5	0	5	100.00	100	1	1	0
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	0
key_length	7	0	7	100.00	100	1	1	0
key_swap	2	0	2	100.00	100	1	1	2
sha_en	2	0	2	100.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cfg_cross	16	0	16	100.00	100	1	1	0
hmac_dis_x_sha_en	4	0	4	100.00	100	1	1	0
key_x_digest_mismatch	35	0	35	100.00	100	1	1	0
key_length_x_digest_size	35	0	35	100.00	100	1	1	0

Summary for Variable digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for digest_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sha2_invalid	4483	1			T3	4		T4	8		T6	6
sha2_none	4513	1			T1	1		T3	9		T4	6
sha2_512	8041	1			T3	11		T4	6		T6	4
sha2_384	7895	1			T1	3		T3	7		T4	12
sha2_256	6539	1			T3	8		T5	135		T4	8

---

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19505

1

T1

5

T3

16

T5

135

auto[1]

12362

1

T3

25

T4

19

T6

24

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

12049

1

T3

17

T4

17

T6

14

auto[1]

19818

1

T1

5

T3

24

T5

135

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

16450

1

T1

3

T3

25

T5

135

disabled

15417

1

T1

2

T3

16

T6

22

---

Summary for Variable key_length

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for key_length

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	5057	1			T3	10		T4	4		T6	6
key_none	7980	1			T3	5		T4	5		T6	3
key_1024	4606	1			T1	1		T3	4		T4	8
key_512	3968	1			T1	3		T3	7		T5	45
key_384	3551	1			T1	1		T3	4		T5	90
key_256	3458	1			T3	6		T4	5		T6	5
key_128	3149	1			T3	5		T4	7		T6	3

---

Summary for Variable key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for key_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19740

1

T1

3

T3

20

T5

135

auto[1]

12127

1

T1

2

T3

21

T4

18

---

Summary for Variable sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

31687

1

T1

5

T3

41

T5

135

disabled

180

1

T21

4

T40

2

T41

2

---

Summary for Cross cfg_cross

Samples crossed: hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cfg_cross

Bins

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

auto[0]

auto[0]

auto[0]

1661

1

T3

2

T4

3

T7

3

enabled

auto[0]

auto[0]

auto[1]

1700

1

T3

5

T4

7

T6

1

enabled

auto[0]

auto[1]

auto[0]

1622

1

T3

2

T4

5

T6

2

enabled

auto[0]

auto[1]

auto[1]

1730

1

T3

4

T4

2

T6

3

enabled

auto[1]

auto[0]

auto[0]

4382

1

T1

3

T5

135

T4

7

enabled

auto[1]

auto[0]

auto[1]

1668

1

T3

2

T4

4

T6

4

enabled

auto[1]

auto[1]

auto[0]

1946

1

T3

5

T4

7

T6

3

enabled

auto[1]

auto[1]

auto[1]

1741

1

T3

5

T4

5

T6

1

disabled

auto[0]

auto[0]

auto[0]

1351

1

T3

3

T8

1

T11

15

disabled

auto[0]

auto[0]

auto[1]

1337

1

T8

2

T11

18

T15

3

disabled

auto[0]

auto[1]

auto[0]

1309

1

T3

1

T6

5

T11

16

disabled

auto[0]

auto[1]

auto[1]

1339

1

T6

3

T8

4

T11

12

disabled

auto[1]

auto[0]

auto[0]

6139

1

T3

2

T6

6

T8

5

disabled

auto[1]

auto[0]

auto[1]

1267

1

T1

2

T3

2

T6

1

disabled

auto[1]

auto[1]

auto[0]

1330

1

T3

5

T6

1

T8

2

disabled

auto[1]

auto[1]

auto[1]

1345

1

T3

3

T6

6

T8

2

---

Summary for Cross hmac_dis_x_sha_en

Samples crossed: hmac_en sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	3	0	3	100.00
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for hmac_dis_x_sha_en

Bins

hmac_en

sha_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

enabled

16379

1

T1

3

T3

25

T5

135

enabled

disabled

71

1

T21

2

T12

4

T37

1

disabled

disabled

109

1

T21

2

T40

2

T41

2

User Defined Cross Bins for hmac_dis_x_sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

15308

1

T1

2

T3

16

T6

22

---

Summary for Cross key_x_digest_mismatch

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	35	0	35	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for key_x_digest_mismatch

Bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	sha2_invalid	1144	1			T3	1		T4	1		T7	2
key_invalid	sha2_none	951	1			T3	3		T6	3		T7	1
key_invalid	sha2_512	947	1			T3	2		T6	1		T8	1
key_invalid	sha2_384	995	1			T3	1		T4	3		T6	1
key_invalid	sha2_256	917	1			T3	3		T6	1		T8	2
key_none	sha2_invalid	612	1			T4	4		T6	1		T8	1
key_none	sha2_none	590	1			T3	2		T8	1		T11	5
key_none	sha2_512	2560	1			T3	2		T6	1		T7	2
key_none	sha2_384	2574	1			T7	2		T8	3		T11	10
key_none	sha2_256	1604	1			T4	1		T6	1		T7	4
key_1024	sha2_invalid	540	1			T4	1		T7	1		T11	6
key_1024	sha2_none	602	1			T1	1		T3	2		T4	2
key_1024	sha2_512	1788	1			T4	1		T7	3		T8	1
key_1024	sha2_384	1022	1			T3	2		T4	3		T6	1
key_512	sha2_invalid	527	1			T3	2		T6	1		T8	3
key_512	sha2_none	563	1			T4	1		T6	1		T7	1
key_512	sha2_512	677	1			T3	1		T4	2		T6	1
key_512	sha2_384	1274	1			T1	2		T3	1		T4	2
key_512	sha2_256	880	1			T3	3		T5	45		T4	2
key_384	sha2_invalid	549	1			T3	1		T4	1		T6	3
key_384	sha2_none	573	1			T3	1		T6	1		T7	2
key_384	sha2_512	677	1			T3	1		T11	8		T15	2
key_384	sha2_384	631	1			T1	1		T4	2		T6	2
key_384	sha2_256	1068	1			T3	1		T5	90		T4	1
key_256	sha2_invalid	568	1			T4	1		T7	1		T8	2
key_256	sha2_none	601	1			T3	1		T4	1		T7	3
key_256	sha2_512	702	1			T3	3		T4	1		T6	1
key_256	sha2_384	704	1			T3	1		T4	1		T11	12
key_256	sha2_256	829	1			T4	1		T6	4		T7	1
key_128	sha2_invalid	518	1			T6	1		T7	2		T11	4
key_128	sha2_none	616	1			T4	2		T7	2		T8	2
key_128	sha2_512	665	1			T3	2		T4	2		T7	1
key_128	sha2_384	681	1			T3	2		T4	1		T6	2
key_128	sha2_256	623	1			T3	1		T4	2		T8	2

User Defined Cross Bins for key_x_digest_mismatch

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

603

1

T4

1

T7

2

T8

2

---

Summary for Cross key_length_x_digest_size

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	35	0	35	100.00

Automatically Generated Cross Bins for key_length_x_digest_size

Bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	sha2_invalid	1144	1			T3	1		T4	1		T7	2
key_invalid	sha2_none	951	1			T3	3		T6	3		T7	1
key_invalid	sha2_512	947	1			T3	2		T6	1		T8	1
key_invalid	sha2_384	995	1			T3	1		T4	3		T6	1
key_invalid	sha2_256	917	1			T3	3		T6	1		T8	2
key_none	sha2_invalid	612	1			T4	4		T6	1		T8	1
key_none	sha2_none	590	1			T3	2		T8	1		T11	5
key_none	sha2_512	2560	1			T3	2		T6	1		T7	2
key_none	sha2_384	2574	1			T7	2		T8	3		T11	10
key_none	sha2_256	1604	1			T4	1		T6	1		T7	4
key_1024	sha2_invalid	540	1			T4	1		T7	1		T11	6
key_1024	sha2_none	602	1			T1	1		T3	2		T4	2
key_1024	sha2_512	1788	1			T4	1		T7	3		T8	1
key_1024	sha2_384	1022	1			T3	2		T4	3		T6	1
key_1024	sha2_256	603	1			T4	1		T7	2		T8	2
key_512	sha2_invalid	527	1			T3	2		T6	1		T8	3
key_512	sha2_none	563	1			T4	1		T6	1		T7	1
key_512	sha2_512	677	1			T3	1		T4	2		T6	1
key_512	sha2_384	1274	1			T1	2		T3	1		T4	2
key_512	sha2_256	880	1			T3	3		T5	45		T4	2
key_384	sha2_invalid	549	1			T3	1		T4	1		T6	3
key_384	sha2_none	573	1			T3	1		T6	1		T7	2
key_384	sha2_512	677	1			T3	1		T11	8		T15	2
key_384	sha2_384	631	1			T1	1		T4	2		T6	2
key_384	sha2_256	1068	1			T3	1		T5	90		T4	1
key_256	sha2_invalid	568	1			T4	1		T7	1		T8	2
key_256	sha2_none	601	1			T3	1		T4	1		T7	3
key_256	sha2_512	702	1			T3	3		T4	1		T6	1
key_256	sha2_384	704	1			T3	1		T4	1		T11	12
key_256	sha2_256	829	1			T4	1		T6	4		T7	1
key_128	sha2_invalid	518	1			T6	1		T7	2		T11	4
key_128	sha2_none	616	1			T4	2		T7	2		T8	2
key_128	sha2_512	665	1			T3	2		T4	2		T7	1
key_128	sha2_384	681	1			T3	2		T4	1		T6	2
key_128	sha2_256	623	1			T3	1		T4	2		T8	2