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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
94.34 95.95 94.24 100.00 82.05 92.33 99.49 96.35


Total test records in report: 658
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T84 /workspace/coverage/cover_reg_top/7.hmac_csr_rw.1665140701 Jul 01 04:29:50 PM PDT 24 Jul 01 04:30:02 PM PDT 24 18074790 ps
T65 /workspace/coverage/cover_reg_top/1.hmac_csr_rw.2355226621 Jul 01 04:29:50 PM PDT 24 Jul 01 04:30:03 PM PDT 24 55459760 ps
T66 /workspace/coverage/cover_reg_top/8.hmac_csr_rw.3159382888 Jul 01 04:30:19 PM PDT 24 Jul 01 04:30:35 PM PDT 24 33175171 ps
T97 /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.3668509826 Jul 01 04:30:18 PM PDT 24 Jul 01 04:30:36 PM PDT 24 124267930 ps
T98 /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.1839724111 Jul 01 04:30:02 PM PDT 24 Jul 01 04:30:16 PM PDT 24 44245114 ps
T535 /workspace/coverage/cover_reg_top/0.hmac_tl_errors.2775014830 Jul 01 04:29:48 PM PDT 24 Jul 01 04:30:02 PM PDT 24 306113650 ps
T536 /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.1330825666 Jul 01 04:30:02 PM PDT 24 Jul 01 04:30:16 PM PDT 24 21910506 ps
T67 /workspace/coverage/cover_reg_top/0.hmac_csr_rw.156700935 Jul 01 04:30:00 PM PDT 24 Jul 01 04:30:13 PM PDT 24 36326639 ps
T537 /workspace/coverage/cover_reg_top/14.hmac_tl_errors.1709318694 Jul 01 04:30:15 PM PDT 24 Jul 01 04:30:35 PM PDT 24 60268938 ps
T538 /workspace/coverage/cover_reg_top/9.hmac_intr_test.2836324510 Jul 01 04:29:50 PM PDT 24 Jul 01 04:30:02 PM PDT 24 93795071 ps
T68 /workspace/coverage/cover_reg_top/3.hmac_intr_test.1607890736 Jul 01 04:29:59 PM PDT 24 Jul 01 04:30:12 PM PDT 24 66196837 ps
T99 /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.3996636058 Jul 01 04:29:59 PM PDT 24 Jul 01 04:30:13 PM PDT 24 125627240 ps
T539 /workspace/coverage/cover_reg_top/3.hmac_tl_errors.3338620273 Jul 01 04:30:22 PM PDT 24 Jul 01 04:30:40 PM PDT 24 290488597 ps
T69 /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.1705642754 Jul 01 04:30:13 PM PDT 24 Jul 01 04:30:32 PM PDT 24 305701383 ps
T540 /workspace/coverage/cover_reg_top/25.hmac_intr_test.4157716301 Jul 01 04:30:04 PM PDT 24 Jul 01 04:30:18 PM PDT 24 36776226 ps
T541 /workspace/coverage/cover_reg_top/21.hmac_intr_test.245596840 Jul 01 04:30:11 PM PDT 24 Jul 01 04:30:28 PM PDT 24 17566945 ps
T542 /workspace/coverage/cover_reg_top/28.hmac_intr_test.2652937770 Jul 01 04:30:07 PM PDT 24 Jul 01 04:30:24 PM PDT 24 57657023 ps
T543 /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.1995625805 Jul 01 04:30:15 PM PDT 24 Jul 01 04:30:35 PM PDT 24 96683376 ps
T544 /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.1856533039 Jul 01 04:29:59 PM PDT 24 Jul 01 04:44:13 PM PDT 24 80536073648 ps
T105 /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.865576066 Jul 01 04:30:06 PM PDT 24 Jul 01 04:30:25 PM PDT 24 277808271 ps
T100 /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.1078506028 Jul 01 04:30:04 PM PDT 24 Jul 01 04:30:21 PM PDT 24 44994781 ps
T101 /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.3336195558 Jul 01 04:30:07 PM PDT 24 Jul 01 04:30:24 PM PDT 24 105713266 ps
T85 /workspace/coverage/cover_reg_top/6.hmac_csr_rw.3766602407 Jul 01 04:29:50 PM PDT 24 Jul 01 04:30:03 PM PDT 24 30026086 ps
T545 /workspace/coverage/cover_reg_top/18.hmac_tl_errors.2808558094 Jul 01 04:30:14 PM PDT 24 Jul 01 04:30:34 PM PDT 24 139568625 ps
T546 /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.3998623620 Jul 01 04:30:09 PM PDT 24 Jul 01 04:30:26 PM PDT 24 39517251 ps
T102 /workspace/coverage/cover_reg_top/14.hmac_csr_rw.1663013071 Jul 01 04:30:14 PM PDT 24 Jul 01 04:30:32 PM PDT 24 58374472 ps
T107 /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.633529961 Jul 01 04:30:05 PM PDT 24 Jul 01 04:30:22 PM PDT 24 152652761 ps
T547 /workspace/coverage/cover_reg_top/11.hmac_tl_errors.2600451190 Jul 01 04:30:04 PM PDT 24 Jul 01 04:30:20 PM PDT 24 51933430 ps
T548 /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.1688197690 Jul 01 04:30:09 PM PDT 24 Jul 01 04:30:26 PM PDT 24 160611870 ps
T549 /workspace/coverage/cover_reg_top/10.hmac_tl_errors.336429924 Jul 01 04:29:45 PM PDT 24 Jul 01 04:29:59 PM PDT 24 41795402 ps
T550 /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.2486185379 Jul 01 04:29:55 PM PDT 24 Jul 01 04:30:08 PM PDT 24 415282844 ps
T551 /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.1596356537 Jul 01 04:30:05 PM PDT 24 Jul 01 04:30:22 PM PDT 24 477736645 ps
T552 /workspace/coverage/cover_reg_top/48.hmac_intr_test.2868122707 Jul 01 04:30:18 PM PDT 24 Jul 01 04:30:35 PM PDT 24 13073286 ps
T553 /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.720166092 Jul 01 04:29:56 PM PDT 24 Jul 01 04:30:12 PM PDT 24 359655974 ps
T554 /workspace/coverage/cover_reg_top/15.hmac_csr_rw.2809931227 Jul 01 04:29:52 PM PDT 24 Jul 01 04:30:05 PM PDT 24 25225520 ps
T555 /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.3466435681 Jul 01 04:30:15 PM PDT 24 Jul 01 04:30:34 PM PDT 24 46330750 ps
T556 /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.3437761096 Jul 01 04:30:00 PM PDT 24 Jul 01 04:30:14 PM PDT 24 235005514 ps
T557 /workspace/coverage/cover_reg_top/10.hmac_csr_rw.105072424 Jul 01 04:30:01 PM PDT 24 Jul 01 04:30:14 PM PDT 24 24618021 ps
T86 /workspace/coverage/cover_reg_top/17.hmac_csr_rw.2575631193 Jul 01 04:30:05 PM PDT 24 Jul 01 04:30:20 PM PDT 24 15432228 ps
T558 /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.2952971170 Jul 01 04:29:59 PM PDT 24 Jul 01 04:30:12 PM PDT 24 137438046 ps
T87 /workspace/coverage/cover_reg_top/19.hmac_csr_rw.3416267249 Jul 01 04:30:08 PM PDT 24 Jul 01 04:30:25 PM PDT 24 40913545 ps
T559 /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.2153438299 Jul 01 04:29:58 PM PDT 24 Jul 01 04:30:25 PM PDT 24 1104196915 ps
T560 /workspace/coverage/cover_reg_top/12.hmac_intr_test.1153767985 Jul 01 04:29:58 PM PDT 24 Jul 01 04:30:10 PM PDT 24 62874555 ps
T561 /workspace/coverage/cover_reg_top/6.hmac_intr_test.3694702383 Jul 01 04:30:05 PM PDT 24 Jul 01 04:30:20 PM PDT 24 23363934 ps
T562 /workspace/coverage/cover_reg_top/45.hmac_intr_test.406756489 Jul 01 04:30:15 PM PDT 24 Jul 01 04:30:34 PM PDT 24 72884429 ps
T563 /workspace/coverage/cover_reg_top/22.hmac_intr_test.1272894145 Jul 01 04:30:07 PM PDT 24 Jul 01 04:30:24 PM PDT 24 28149060 ps
T564 /workspace/coverage/cover_reg_top/8.hmac_intr_test.2530184683 Jul 01 04:29:50 PM PDT 24 Jul 01 04:30:02 PM PDT 24 91097840 ps
T113 /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.3837670599 Jul 01 04:30:14 PM PDT 24 Jul 01 04:30:35 PM PDT 24 747780479 ps
T565 /workspace/coverage/cover_reg_top/41.hmac_intr_test.4287903968 Jul 01 04:30:24 PM PDT 24 Jul 01 04:30:39 PM PDT 24 38708846 ps
T566 /workspace/coverage/cover_reg_top/49.hmac_intr_test.3677018797 Jul 01 04:30:29 PM PDT 24 Jul 01 04:30:42 PM PDT 24 13370784 ps
T567 /workspace/coverage/cover_reg_top/40.hmac_intr_test.1651825011 Jul 01 04:30:05 PM PDT 24 Jul 01 04:30:20 PM PDT 24 15690784 ps
T568 /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.982516432 Jul 01 04:29:47 PM PDT 24 Jul 01 04:30:00 PM PDT 24 28448062 ps
T569 /workspace/coverage/cover_reg_top/11.hmac_intr_test.2239768720 Jul 01 04:30:02 PM PDT 24 Jul 01 04:30:15 PM PDT 24 32198887 ps
T570 /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.417371796 Jul 01 04:30:05 PM PDT 24 Jul 01 04:30:22 PM PDT 24 96174502 ps
T88 /workspace/coverage/cover_reg_top/12.hmac_csr_rw.37079372 Jul 01 04:29:59 PM PDT 24 Jul 01 04:30:12 PM PDT 24 267002928 ps
T571 /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.2259814617 Jul 01 04:31:01 PM PDT 24 Jul 01 04:31:15 PM PDT 24 1444889243 ps
T572 /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.1401885203 Jul 01 04:29:57 PM PDT 24 Jul 01 04:30:10 PM PDT 24 78624539 ps
T573 /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.3100626205 Jul 01 04:30:02 PM PDT 24 Jul 01 04:30:16 PM PDT 24 97763088 ps
T109 /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.2286746539 Jul 01 04:30:04 PM PDT 24 Jul 01 04:30:19 PM PDT 24 381328149 ps
T108 /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.2196015527 Jul 01 04:30:05 PM PDT 24 Jul 01 04:30:23 PM PDT 24 133183152 ps
T574 /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.2505148913 Jul 01 04:30:07 PM PDT 24 Jul 01 04:30:25 PM PDT 24 70609535 ps
T575 /workspace/coverage/cover_reg_top/9.hmac_csr_rw.3017748908 Jul 01 04:29:57 PM PDT 24 Jul 01 04:30:08 PM PDT 24 22184221 ps
T576 /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.4026036719 Jul 01 04:29:58 PM PDT 24 Jul 01 04:30:10 PM PDT 24 19437542 ps
T89 /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.3688635423 Jul 01 04:29:59 PM PDT 24 Jul 01 04:30:19 PM PDT 24 476787485 ps
T577 /workspace/coverage/cover_reg_top/35.hmac_intr_test.1947199062 Jul 01 04:30:22 PM PDT 24 Jul 01 04:30:37 PM PDT 24 39134249 ps
T106 /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.1690226949 Jul 01 04:30:15 PM PDT 24 Jul 01 04:30:35 PM PDT 24 80144042 ps
T578 /workspace/coverage/cover_reg_top/4.hmac_intr_test.3206663297 Jul 01 04:30:12 PM PDT 24 Jul 01 04:30:29 PM PDT 24 57836768 ps
T579 /workspace/coverage/cover_reg_top/38.hmac_intr_test.1424326919 Jul 01 04:30:08 PM PDT 24 Jul 01 04:30:25 PM PDT 24 57574134 ps
T580 /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.2498502886 Jul 01 04:30:12 PM PDT 24 Jul 01 04:30:30 PM PDT 24 331360344 ps
T581 /workspace/coverage/cover_reg_top/15.hmac_intr_test.3837413840 Jul 01 04:29:58 PM PDT 24 Jul 01 04:30:10 PM PDT 24 34647355 ps
T582 /workspace/coverage/cover_reg_top/13.hmac_tl_errors.4113822398 Jul 01 04:30:01 PM PDT 24 Jul 01 04:30:15 PM PDT 24 1127830580 ps
T583 /workspace/coverage/cover_reg_top/5.hmac_tl_errors.1783189028 Jul 01 04:29:58 PM PDT 24 Jul 01 04:30:11 PM PDT 24 197662568 ps
T584 /workspace/coverage/cover_reg_top/31.hmac_intr_test.1356608265 Jul 01 04:30:03 PM PDT 24 Jul 01 04:30:16 PM PDT 24 18321522 ps
T585 /workspace/coverage/cover_reg_top/6.hmac_tl_errors.2138812394 Jul 01 04:29:50 PM PDT 24 Jul 01 04:30:03 PM PDT 24 299906359 ps
T586 /workspace/coverage/cover_reg_top/10.hmac_intr_test.1343977330 Jul 01 04:29:50 PM PDT 24 Jul 01 04:30:02 PM PDT 24 77109772 ps
T90 /workspace/coverage/cover_reg_top/16.hmac_csr_rw.2469948492 Jul 01 04:29:51 PM PDT 24 Jul 01 04:30:03 PM PDT 24 49793382 ps
T587 /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.1817164485 Jul 01 04:30:06 PM PDT 24 Jul 01 04:30:25 PM PDT 24 91816720 ps
T110 /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.1034183664 Jul 01 04:30:04 PM PDT 24 Jul 01 04:30:19 PM PDT 24 81356747 ps
T588 /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.3276470623 Jul 01 04:29:53 PM PDT 24 Jul 01 04:30:07 PM PDT 24 82955073 ps
T589 /workspace/coverage/cover_reg_top/8.hmac_tl_errors.2166615920 Jul 01 04:30:12 PM PDT 24 Jul 01 04:30:33 PM PDT 24 147021217 ps
T91 /workspace/coverage/cover_reg_top/5.hmac_csr_rw.1110970004 Jul 01 04:29:49 PM PDT 24 Jul 01 04:30:01 PM PDT 24 16496862 ps
T590 /workspace/coverage/cover_reg_top/32.hmac_intr_test.2730442230 Jul 01 04:30:03 PM PDT 24 Jul 01 04:30:16 PM PDT 24 18021891 ps
T591 /workspace/coverage/cover_reg_top/46.hmac_intr_test.447820678 Jul 01 04:30:22 PM PDT 24 Jul 01 04:30:37 PM PDT 24 21780759 ps
T592 /workspace/coverage/cover_reg_top/24.hmac_intr_test.1091983949 Jul 01 04:30:17 PM PDT 24 Jul 01 04:30:35 PM PDT 24 53887779 ps
T593 /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.2994167076 Jul 01 04:30:08 PM PDT 24 Jul 01 04:30:27 PM PDT 24 314484459 ps
T594 /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.2118277026 Jul 01 04:30:14 PM PDT 24 Jul 01 04:30:33 PM PDT 24 83300818 ps
T595 /workspace/coverage/cover_reg_top/19.hmac_intr_test.238564119 Jul 01 04:30:06 PM PDT 24 Jul 01 04:30:22 PM PDT 24 13923823 ps
T596 /workspace/coverage/cover_reg_top/16.hmac_tl_errors.1753041651 Jul 01 04:30:06 PM PDT 24 Jul 01 04:30:25 PM PDT 24 442734100 ps
T597 /workspace/coverage/cover_reg_top/5.hmac_intr_test.2906155748 Jul 01 04:30:06 PM PDT 24 Jul 01 04:30:21 PM PDT 24 17294250 ps
T598 /workspace/coverage/cover_reg_top/7.hmac_tl_errors.3813475696 Jul 01 04:29:58 PM PDT 24 Jul 01 04:30:12 PM PDT 24 176045518 ps
T599 /workspace/coverage/cover_reg_top/11.hmac_csr_rw.4174462209 Jul 01 04:30:01 PM PDT 24 Jul 01 04:30:14 PM PDT 24 15207723 ps
T600 /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.171120081 Jul 01 04:30:05 PM PDT 24 Jul 01 04:30:22 PM PDT 24 747560773 ps
T601 /workspace/coverage/cover_reg_top/16.hmac_intr_test.3185452155 Jul 01 04:30:08 PM PDT 24 Jul 01 04:30:25 PM PDT 24 18059361 ps
T602 /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.2087040377 Jul 01 04:29:50 PM PDT 24 Jul 01 04:30:03 PM PDT 24 87448640 ps
T114 /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.2476257717 Jul 01 04:30:00 PM PDT 24 Jul 01 04:30:15 PM PDT 24 164980439 ps
T92 /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.2509251793 Jul 01 04:30:11 PM PDT 24 Jul 01 04:30:28 PM PDT 24 35780069 ps
T603 /workspace/coverage/cover_reg_top/29.hmac_intr_test.2030101653 Jul 01 04:30:10 PM PDT 24 Jul 01 04:30:28 PM PDT 24 42778326 ps
T604 /workspace/coverage/cover_reg_top/15.hmac_tl_errors.3581706475 Jul 01 04:30:05 PM PDT 24 Jul 01 04:30:22 PM PDT 24 390316317 ps
T605 /workspace/coverage/cover_reg_top/26.hmac_intr_test.2361056975 Jul 01 04:30:06 PM PDT 24 Jul 01 04:30:21 PM PDT 24 18386073 ps
T112 /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.2181381334 Jul 01 04:29:58 PM PDT 24 Jul 01 04:30:14 PM PDT 24 247490158 ps
T606 /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.961106812 Jul 01 04:29:55 PM PDT 24 Jul 01 04:30:08 PM PDT 24 395410440 ps
T607 /workspace/coverage/cover_reg_top/4.hmac_tl_errors.847033673 Jul 01 04:30:08 PM PDT 24 Jul 01 04:30:28 PM PDT 24 140147655 ps
T608 /workspace/coverage/cover_reg_top/1.hmac_intr_test.2278394441 Jul 01 04:30:15 PM PDT 24 Jul 01 04:30:33 PM PDT 24 46031475 ps
T115 /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.1930996018 Jul 01 04:30:14 PM PDT 24 Jul 01 04:30:35 PM PDT 24 458389963 ps
T609 /workspace/coverage/cover_reg_top/39.hmac_intr_test.1367600655 Jul 01 04:30:23 PM PDT 24 Jul 01 04:30:38 PM PDT 24 33194638 ps
T610 /workspace/coverage/cover_reg_top/33.hmac_intr_test.910517908 Jul 01 04:30:21 PM PDT 24 Jul 01 04:30:37 PM PDT 24 41646723 ps
T611 /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.3299107583 Jul 01 04:29:49 PM PDT 24 Jul 01 04:30:06 PM PDT 24 420809452 ps
T612 /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.2196761449 Jul 01 04:30:04 PM PDT 24 Jul 01 04:30:18 PM PDT 24 81153181 ps
T613 /workspace/coverage/cover_reg_top/34.hmac_intr_test.2818096363 Jul 01 04:30:05 PM PDT 24 Jul 01 04:30:21 PM PDT 24 80405144 ps
T614 /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.209454460 Jul 01 04:29:51 PM PDT 24 Jul 01 04:30:03 PM PDT 24 41727779 ps
T615 /workspace/coverage/cover_reg_top/30.hmac_intr_test.1100122336 Jul 01 04:30:06 PM PDT 24 Jul 01 04:30:22 PM PDT 24 17985545 ps
T93 /workspace/coverage/cover_reg_top/4.hmac_csr_rw.2701146662 Jul 01 04:29:49 PM PDT 24 Jul 01 04:30:02 PM PDT 24 56364429 ps
T616 /workspace/coverage/cover_reg_top/7.hmac_intr_test.1926250390 Jul 01 04:29:57 PM PDT 24 Jul 01 04:30:08 PM PDT 24 12940519 ps
T617 /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.2014882201 Jul 01 04:30:19 PM PDT 24 Jul 01 04:30:51 PM PDT 24 6051242568 ps
T618 /workspace/coverage/cover_reg_top/2.hmac_tl_errors.35466110 Jul 01 04:30:07 PM PDT 24 Jul 01 04:30:26 PM PDT 24 162907294 ps
T619 /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.1020083598 Jul 01 04:29:48 PM PDT 24 Jul 01 04:30:01 PM PDT 24 38090974 ps
T620 /workspace/coverage/cover_reg_top/44.hmac_intr_test.216527468 Jul 01 04:30:16 PM PDT 24 Jul 01 04:30:34 PM PDT 24 20498780 ps
T621 /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.3258799529 Jul 01 04:29:52 PM PDT 24 Jul 01 04:30:07 PM PDT 24 313258906 ps
T111 /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.9612011 Jul 01 04:30:02 PM PDT 24 Jul 01 04:30:19 PM PDT 24 479597792 ps
T94 /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.1067686263 Jul 01 04:29:53 PM PDT 24 Jul 01 04:30:13 PM PDT 24 560951580 ps
T622 /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.2365500892 Jul 01 04:30:03 PM PDT 24 Jul 01 04:30:17 PM PDT 24 234576353 ps
T623 /workspace/coverage/cover_reg_top/17.hmac_intr_test.191570135 Jul 01 04:30:05 PM PDT 24 Jul 01 04:30:20 PM PDT 24 14089212 ps
T95 /workspace/coverage/cover_reg_top/2.hmac_csr_rw.28106040 Jul 01 04:29:49 PM PDT 24 Jul 01 04:30:01 PM PDT 24 17299966 ps
T624 /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.3727949874 Jul 01 04:30:05 PM PDT 24 Jul 01 04:30:37 PM PDT 24 1647748557 ps
T625 /workspace/coverage/cover_reg_top/14.hmac_intr_test.2758992537 Jul 01 04:30:00 PM PDT 24 Jul 01 04:30:13 PM PDT 24 119671936 ps
T626 /workspace/coverage/cover_reg_top/9.hmac_tl_errors.774991984 Jul 01 04:30:05 PM PDT 24 Jul 01 04:30:22 PM PDT 24 227669384 ps
T627 /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.963988544 Jul 01 04:30:05 PM PDT 24 Jul 01 04:30:21 PM PDT 24 63472415 ps
T628 /workspace/coverage/cover_reg_top/2.hmac_intr_test.2169016150 Jul 01 04:30:02 PM PDT 24 Jul 01 04:30:15 PM PDT 24 12837507 ps
T629 /workspace/coverage/cover_reg_top/19.hmac_tl_errors.3281196931 Jul 01 04:30:08 PM PDT 24 Jul 01 04:30:28 PM PDT 24 962786615 ps
T630 /workspace/coverage/cover_reg_top/0.hmac_intr_test.3559935826 Jul 01 04:30:09 PM PDT 24 Jul 01 04:30:26 PM PDT 24 20029332 ps
T631 /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.1171527827 Jul 01 04:30:14 PM PDT 24 Jul 01 04:30:34 PM PDT 24 39942547 ps
T632 /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.2388913185 Jul 01 04:30:02 PM PDT 24 Jul 01 04:30:16 PM PDT 24 69617855 ps
T633 /workspace/coverage/cover_reg_top/1.hmac_tl_errors.2888775445 Jul 01 04:30:05 PM PDT 24 Jul 01 04:30:21 PM PDT 24 151216492 ps
T634 /workspace/coverage/cover_reg_top/36.hmac_intr_test.3410968283 Jul 01 04:30:08 PM PDT 24 Jul 01 04:30:25 PM PDT 24 41386387 ps
T635 /workspace/coverage/cover_reg_top/42.hmac_intr_test.147566400 Jul 01 04:30:15 PM PDT 24 Jul 01 04:30:33 PM PDT 24 46571373 ps
T636 /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.1661367006 Jul 01 04:30:06 PM PDT 24 Jul 01 04:30:23 PM PDT 24 34353344 ps
T637 /workspace/coverage/cover_reg_top/27.hmac_intr_test.1716520114 Jul 01 04:30:06 PM PDT 24 Jul 01 04:30:21 PM PDT 24 16854973 ps
T638 /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.2863844660 Jul 01 04:29:49 PM PDT 24 Jul 01 04:30:03 PM PDT 24 719551020 ps
T639 /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.4141950434 Jul 01 04:30:14 PM PDT 24 Jul 01 04:30:32 PM PDT 24 134774259 ps
T640 /workspace/coverage/cover_reg_top/23.hmac_intr_test.722408954 Jul 01 04:30:14 PM PDT 24 Jul 01 04:30:32 PM PDT 24 29836126 ps
T641 /workspace/coverage/cover_reg_top/43.hmac_intr_test.2557624852 Jul 01 04:30:16 PM PDT 24 Jul 01 04:30:34 PM PDT 24 19151235 ps
T642 /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.1164850290 Jul 01 04:29:44 PM PDT 24 Jul 01 04:29:59 PM PDT 24 164958127 ps
T643 /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.2447552784 Jul 01 04:29:52 PM PDT 24 Jul 01 04:30:12 PM PDT 24 453545839 ps
T644 /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.1578986267 Jul 01 04:30:16 PM PDT 24 Jul 01 04:30:34 PM PDT 24 42620613 ps
T645 /workspace/coverage/cover_reg_top/20.hmac_intr_test.2144345830 Jul 01 04:30:10 PM PDT 24 Jul 01 04:30:26 PM PDT 24 13947472 ps
T646 /workspace/coverage/cover_reg_top/17.hmac_tl_errors.2364703651 Jul 01 04:30:09 PM PDT 24 Jul 01 04:30:27 PM PDT 24 71627191 ps
T647 /workspace/coverage/cover_reg_top/37.hmac_intr_test.3951560860 Jul 01 04:30:11 PM PDT 24 Jul 01 04:30:28 PM PDT 24 16283930 ps
T648 /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.398970358 Jul 01 04:31:19 PM PDT 24 Jul 01 04:31:33 PM PDT 24 86169808 ps
T649 /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.902591663 Jul 01 04:29:45 PM PDT 24 Jul 01 04:29:58 PM PDT 24 54637335 ps
T650 /workspace/coverage/cover_reg_top/13.hmac_intr_test.2152973563 Jul 01 04:31:18 PM PDT 24 Jul 01 04:31:30 PM PDT 24 12302852 ps
T651 /workspace/coverage/cover_reg_top/18.hmac_intr_test.222280260 Jul 01 04:30:05 PM PDT 24 Jul 01 04:30:20 PM PDT 24 15085201 ps
T652 /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.925044001 Jul 01 04:30:00 PM PDT 24 Jul 01 04:30:22 PM PDT 24 1331481391 ps
T653 /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.2550665036 Jul 01 04:29:52 PM PDT 24 Jul 01 04:30:07 PM PDT 24 432185235 ps
T654 /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.125479562 Jul 01 04:29:59 PM PDT 24 Jul 01 04:30:13 PM PDT 24 378425253 ps
T655 /workspace/coverage/cover_reg_top/13.hmac_csr_rw.3860105251 Jul 01 04:30:10 PM PDT 24 Jul 01 04:30:27 PM PDT 24 33680727 ps
T656 /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.3397757435 Jul 01 04:30:03 PM PDT 24 Jul 01 04:50:03 PM PDT 24 705797719055 ps
T657 /workspace/coverage/cover_reg_top/3.hmac_csr_rw.1102099777 Jul 01 04:29:58 PM PDT 24 Jul 01 04:30:10 PM PDT 24 52605172 ps
T658 /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.1824393740 Jul 01 04:30:05 PM PDT 24 Jul 01 04:46:58 PM PDT 24 90834999511 ps

Test location /workspace/coverage/default/15.hmac_long_msg.1763125959
Short name T15
Test name
Test status
Simulation time 181580122008 ps
CPU time 133.31 seconds
Started Jul 01 04:42:47 PM PDT 24
Finished Jul 01 04:45:15 PM PDT 24
Peak memory 200608 kb
Host smart-02e2909f-05bf-4dba-8799-0c8f4aaed5b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763125959 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_long_msg.1763125959
Directory /workspace/15.hmac_long_msg/latest

Test location /workspace/coverage/default/2.hmac_stress_all_with_rand_reset.470334883
Short name T12
Test name
Test status
Simulation time 2141393142720 ps
CPU time 3161.24 seconds
Started Jul 01 04:42:34 PM PDT 24
Finished Jul 01 05:35:34 PM PDT 24
Peak memory 745692 kb
Host smart-b5d3c119-fc42-4410-87bb-8d5488b66a96
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=470334883 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all_with_rand_reset.470334883
Directory /workspace/2.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.hmac_stress_all.503991593
Short name T21
Test name
Test status
Simulation time 351861210301 ps
CPU time 3057.61 seconds
Started Jul 01 04:42:55 PM PDT 24
Finished Jul 01 05:34:04 PM PDT 24
Peak memory 821176 kb
Host smart-af7658ba-6d7a-453e-b1e8-ba6161e6ca24
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503991593 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 13.hmac_stress_all.503991593
Directory /workspace/13.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.865576066
Short name T105
Test name
Test status
Simulation time 277808271 ps
CPU time 4.28 seconds
Started Jul 01 04:30:06 PM PDT 24
Finished Jul 01 04:30:25 PM PDT 24
Peak memory 199764 kb
Host smart-2e0da666-f114-4a70-8ca7-478275cca75d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865576066 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_intg_err.865576066
Directory /workspace/16.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.hmac_stress_all.3440448464
Short name T17
Test name
Test status
Simulation time 47744677888 ps
CPU time 3192.5 seconds
Started Jul 01 04:42:26 PM PDT 24
Finished Jul 01 05:35:55 PM PDT 24
Peak memory 813236 kb
Host smart-48008aa5-3511-42e7-b4a8-e6ebebdc127f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440448464 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all.3440448464
Directory /workspace/0.hmac_stress_all/latest

Test location /workspace/coverage/default/1.hmac_sec_cm.1108430706
Short name T50
Test name
Test status
Simulation time 122682697 ps
CPU time 0.88 seconds
Started Jul 01 04:42:33 PM PDT 24
Finished Jul 01 04:42:52 PM PDT 24
Peak memory 218704 kb
Host smart-2c8b81b6-b1a7-4ee4-86ec-c9deb14dfe8d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108430706 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_sec_cm.1108430706
Directory /workspace/1.hmac_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_rw.156700935
Short name T67
Test name
Test status
Simulation time 36326639 ps
CPU time 1.03 seconds
Started Jul 01 04:30:00 PM PDT 24
Finished Jul 01 04:30:13 PM PDT 24
Peak memory 199448 kb
Host smart-8c7a3ff1-3413-493b-92d7-1d224b955eb1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156700935 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_rw.156700935
Directory /workspace/0.hmac_csr_rw/latest

Test location /workspace/coverage/default/7.hmac_stress_all.2182525378
Short name T10
Test name
Test status
Simulation time 33579119911 ps
CPU time 517 seconds
Started Jul 01 04:42:41 PM PDT 24
Finished Jul 01 04:51:34 PM PDT 24
Peak memory 471532 kb
Host smart-93a617f7-6ba6-49f0-a9a0-bb93fbc82f13
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182525378 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all.2182525378
Directory /workspace/7.hmac_stress_all/latest

Test location /workspace/coverage/default/12.hmac_alert_test.4193614495
Short name T140
Test name
Test status
Simulation time 44457313 ps
CPU time 0.57 seconds
Started Jul 01 04:42:49 PM PDT 24
Finished Jul 01 04:43:04 PM PDT 24
Peak memory 195208 kb
Host smart-0897163a-80d4-4ad7-a7ab-5078d18f6ada
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193614495 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_alert_test.4193614495
Directory /workspace/12.hmac_alert_test/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.1930996018
Short name T115
Test name
Test status
Simulation time 458389963 ps
CPU time 3.85 seconds
Started Jul 01 04:30:14 PM PDT 24
Finished Jul 01 04:30:35 PM PDT 24
Peak memory 199404 kb
Host smart-b6552de3-a222-45e3-abcc-727ed0774a4d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930996018 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_intg_err.1930996018
Directory /workspace/2.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/25.hmac_stress_all.1175299209
Short name T41
Test name
Test status
Simulation time 62803254505 ps
CPU time 2220.87 seconds
Started Jul 01 04:43:10 PM PDT 24
Finished Jul 01 05:20:17 PM PDT 24
Peak memory 756164 kb
Host smart-8b7fe658-8139-4c9f-9e86-6b0f39a3c3ad
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175299209 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.hmac_stress_all.1175299209
Directory /workspace/25.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.2181381334
Short name T112
Test name
Test status
Simulation time 247490158 ps
CPU time 4.08 seconds
Started Jul 01 04:29:58 PM PDT 24
Finished Jul 01 04:30:14 PM PDT 24
Peak memory 199404 kb
Host smart-3e23abc0-d0ab-42b3-95ac-05ae2a0f3489
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181381334 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_intg_err.2181381334
Directory /workspace/12.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.9612011
Short name T111
Test name
Test status
Simulation time 479597792 ps
CPU time 4.25 seconds
Started Jul 01 04:30:02 PM PDT 24
Finished Jul 01 04:30:19 PM PDT 24
Peak memory 199392 kb
Host smart-f296c26c-f443-4073-ba2d-b0aaf4bcdfc1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9612011 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_intg_err.9612011
Directory /workspace/5.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.3659843729
Short name T56
Test name
Test status
Simulation time 95527129 ps
CPU time 2.99 seconds
Started Jul 01 04:30:10 PM PDT 24
Finished Jul 01 04:30:29 PM PDT 24
Peak memory 199608 kb
Host smart-927a5d36-deae-4e33-9e33-1d644d4e644c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659843729 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_intg_err.3659843729
Directory /workspace/6.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/10.hmac_burst_wr.1010122159
Short name T466
Test name
Test status
Simulation time 3358931009 ps
CPU time 47.56 seconds
Started Jul 01 04:42:45 PM PDT 24
Finished Jul 01 04:43:47 PM PDT 24
Peak memory 216680 kb
Host smart-76833a70-7cd2-4df5-a76a-d9ecd97b2680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010122159 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_burst_wr.1010122159
Directory /workspace/10.hmac_burst_wr/latest

Test location /workspace/coverage/default/1.hmac_stress_all_with_rand_reset.3398510603
Short name T20
Test name
Test status
Simulation time 74061188268 ps
CPU time 247.82 seconds
Started Jul 01 04:42:28 PM PDT 24
Finished Jul 01 04:46:52 PM PDT 24
Peak memory 216816 kb
Host smart-ae6f26c3-3b64-4dc8-bccc-bbf969bcce82
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3398510603 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all_with_rand_reset.3398510603
Directory /workspace/1.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.3258799529
Short name T621
Test name
Test status
Simulation time 313258906 ps
CPU time 3.19 seconds
Started Jul 01 04:29:52 PM PDT 24
Finished Jul 01 04:30:07 PM PDT 24
Peak memory 199388 kb
Host smart-1538c08f-86de-4d4d-8dc9-924bcad22398
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258799529 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_aliasing.3258799529
Directory /workspace/0.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.3727949874
Short name T624
Test name
Test status
Simulation time 1647748557 ps
CPU time 17.09 seconds
Started Jul 01 04:30:05 PM PDT 24
Finished Jul 01 04:30:37 PM PDT 24
Peak memory 198648 kb
Host smart-6ef65518-3653-4657-bce6-997ffbaa84b8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727949874 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_bit_bash.3727949874
Directory /workspace/0.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.4026036719
Short name T576
Test name
Test status
Simulation time 19437542 ps
CPU time 0.84 seconds
Started Jul 01 04:29:58 PM PDT 24
Finished Jul 01 04:30:10 PM PDT 24
Peak memory 199304 kb
Host smart-2dab0629-03bf-4a8c-b8dc-2a407a052e8c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026036719 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_hw_reset.4026036719
Directory /workspace/0.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.2087040377
Short name T602
Test name
Test status
Simulation time 87448640 ps
CPU time 1.32 seconds
Started Jul 01 04:29:50 PM PDT 24
Finished Jul 01 04:30:03 PM PDT 24
Peak memory 199428 kb
Host smart-328d4f77-a08d-4bd3-bf73-26ded8b3ae29
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087040377 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.hmac_csr_mem_rw_with_rand_reset.2087040377
Directory /workspace/0.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_intr_test.3559935826
Short name T630
Test name
Test status
Simulation time 20029332 ps
CPU time 0.61 seconds
Started Jul 01 04:30:09 PM PDT 24
Finished Jul 01 04:30:26 PM PDT 24
Peak memory 194744 kb
Host smart-7e65179c-c9ec-4bea-b843-097ed058cb48
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559935826 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_intr_test.3559935826
Directory /workspace/0.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.3996636058
Short name T99
Test name
Test status
Simulation time 125627240 ps
CPU time 1.57 seconds
Started Jul 01 04:29:59 PM PDT 24
Finished Jul 01 04:30:13 PM PDT 24
Peak memory 199552 kb
Host smart-5110b3c0-32c2-407f-813c-ac29b3ec17d9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996636058 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_same_csr
_outstanding.3996636058
Directory /workspace/0.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_errors.2775014830
Short name T535
Test name
Test status
Simulation time 306113650 ps
CPU time 1.93 seconds
Started Jul 01 04:29:48 PM PDT 24
Finished Jul 01 04:30:02 PM PDT 24
Peak memory 199448 kb
Host smart-0a43a38b-481c-44aa-a6b5-560b3a092621
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775014830 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_errors.2775014830
Directory /workspace/0.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.1164850290
Short name T642
Test name
Test status
Simulation time 164958127 ps
CPU time 3.05 seconds
Started Jul 01 04:29:44 PM PDT 24
Finished Jul 01 04:29:59 PM PDT 24
Peak memory 199424 kb
Host smart-1b34f0f9-3292-48b4-9b86-15f4a9db6278
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164850290 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_intg_err.1164850290
Directory /workspace/0.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.1067686263
Short name T94
Test name
Test status
Simulation time 560951580 ps
CPU time 8.8 seconds
Started Jul 01 04:29:53 PM PDT 24
Finished Jul 01 04:30:13 PM PDT 24
Peak memory 199396 kb
Host smart-64861d17-73d0-48ea-8922-2b7a9d49027a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067686263 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_aliasing.1067686263
Directory /workspace/1.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.720166092
Short name T553
Test name
Test status
Simulation time 359655974 ps
CPU time 5.56 seconds
Started Jul 01 04:29:56 PM PDT 24
Finished Jul 01 04:30:12 PM PDT 24
Peak memory 198536 kb
Host smart-3ce8e23d-5a9d-4a73-8af5-a9354266ccc0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720166092 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_bit_bash.720166092
Directory /workspace/1.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.209454460
Short name T614
Test name
Test status
Simulation time 41727779 ps
CPU time 0.97 seconds
Started Jul 01 04:29:51 PM PDT 24
Finished Jul 01 04:30:03 PM PDT 24
Peak memory 199064 kb
Host smart-af1ac22b-313d-40d0-b0ac-3c8b207ceb37
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209454460 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_hw_reset.209454460
Directory /workspace/1.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.1705642754
Short name T69
Test name
Test status
Simulation time 305701383 ps
CPU time 1.86 seconds
Started Jul 01 04:30:13 PM PDT 24
Finished Jul 01 04:30:32 PM PDT 24
Peak memory 199580 kb
Host smart-3e6af25c-9605-4b2d-8261-d734de592e55
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705642754 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.hmac_csr_mem_rw_with_rand_reset.1705642754
Directory /workspace/1.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_rw.2355226621
Short name T65
Test name
Test status
Simulation time 55459760 ps
CPU time 0.83 seconds
Started Jul 01 04:29:50 PM PDT 24
Finished Jul 01 04:30:03 PM PDT 24
Peak memory 198836 kb
Host smart-564e0349-c705-4aab-bef5-669cbb631474
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355226621 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_rw.2355226621
Directory /workspace/1.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_intr_test.2278394441
Short name T608
Test name
Test status
Simulation time 46031475 ps
CPU time 0.61 seconds
Started Jul 01 04:30:15 PM PDT 24
Finished Jul 01 04:30:33 PM PDT 24
Peak memory 194400 kb
Host smart-007dc06f-adc3-448b-aa7c-cecc82cf2bb5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278394441 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_intr_test.2278394441
Directory /workspace/1.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.2550665036
Short name T653
Test name
Test status
Simulation time 432185235 ps
CPU time 2.1 seconds
Started Jul 01 04:29:52 PM PDT 24
Finished Jul 01 04:30:07 PM PDT 24
Peak memory 199384 kb
Host smart-59344017-7c62-4f66-b3e6-b4cbddd980e2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550665036 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_same_csr
_outstanding.2550665036
Directory /workspace/1.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_errors.2888775445
Short name T633
Test name
Test status
Simulation time 151216492 ps
CPU time 1.9 seconds
Started Jul 01 04:30:05 PM PDT 24
Finished Jul 01 04:30:21 PM PDT 24
Peak memory 199468 kb
Host smart-3ddb5bd2-95d0-445f-b295-c52703ec2899
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888775445 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_errors.2888775445
Directory /workspace/1.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.3837670599
Short name T113
Test name
Test status
Simulation time 747780479 ps
CPU time 3.23 seconds
Started Jul 01 04:30:14 PM PDT 24
Finished Jul 01 04:30:35 PM PDT 24
Peak memory 199472 kb
Host smart-aff56c78-3502-498c-9b86-2b809b4d1c36
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837670599 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_intg_err.3837670599
Directory /workspace/1.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.1995625805
Short name T543
Test name
Test status
Simulation time 96683376 ps
CPU time 2.73 seconds
Started Jul 01 04:30:15 PM PDT 24
Finished Jul 01 04:30:35 PM PDT 24
Peak memory 214972 kb
Host smart-3720f7fa-3fd3-4ace-9571-da92da087575
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995625805 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.hmac_csr_mem_rw_with_rand_reset.1995625805
Directory /workspace/10.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_rw.105072424
Short name T557
Test name
Test status
Simulation time 24618021 ps
CPU time 0.79 seconds
Started Jul 01 04:30:01 PM PDT 24
Finished Jul 01 04:30:14 PM PDT 24
Peak memory 199092 kb
Host smart-834776f0-a22f-4ae1-8666-2fbb238d36ca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105072424 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_rw.105072424
Directory /workspace/10.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_intr_test.1343977330
Short name T586
Test name
Test status
Simulation time 77109772 ps
CPU time 0.6 seconds
Started Jul 01 04:29:50 PM PDT 24
Finished Jul 01 04:30:02 PM PDT 24
Peak memory 194392 kb
Host smart-ad62bc8e-fd4d-40cf-86a7-e58a96f203a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343977330 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_intr_test.1343977330
Directory /workspace/10.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.1839724111
Short name T98
Test name
Test status
Simulation time 44245114 ps
CPU time 1.18 seconds
Started Jul 01 04:30:02 PM PDT 24
Finished Jul 01 04:30:16 PM PDT 24
Peak memory 199448 kb
Host smart-a6c7efc5-743a-4425-b05b-fd83b3e86ed7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839724111 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_same_cs
r_outstanding.1839724111
Directory /workspace/10.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_errors.336429924
Short name T549
Test name
Test status
Simulation time 41795402 ps
CPU time 1.95 seconds
Started Jul 01 04:29:45 PM PDT 24
Finished Jul 01 04:29:59 PM PDT 24
Peak memory 199528 kb
Host smart-2a748b0e-18ec-4654-8f47-e80449c36e0f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336429924 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_errors.336429924
Directory /workspace/10.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.2196015527
Short name T108
Test name
Test status
Simulation time 133183152 ps
CPU time 3.99 seconds
Started Jul 01 04:30:05 PM PDT 24
Finished Jul 01 04:30:23 PM PDT 24
Peak memory 199396 kb
Host smart-5eb3df6c-06eb-44bc-bf6e-3de2b88e39d4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196015527 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_intg_err.2196015527
Directory /workspace/10.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.1596356537
Short name T551
Test name
Test status
Simulation time 477736645 ps
CPU time 2.18 seconds
Started Jul 01 04:30:05 PM PDT 24
Finished Jul 01 04:30:22 PM PDT 24
Peak memory 199532 kb
Host smart-309e9104-4790-490f-9d01-1f0ceb141084
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596356537 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.hmac_csr_mem_rw_with_rand_reset.1596356537
Directory /workspace/11.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_rw.4174462209
Short name T599
Test name
Test status
Simulation time 15207723 ps
CPU time 0.68 seconds
Started Jul 01 04:30:01 PM PDT 24
Finished Jul 01 04:30:14 PM PDT 24
Peak memory 197860 kb
Host smart-31d06d55-fe87-41c1-9f3e-441d310f23c7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174462209 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_rw.4174462209
Directory /workspace/11.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_intr_test.2239768720
Short name T569
Test name
Test status
Simulation time 32198887 ps
CPU time 0.58 seconds
Started Jul 01 04:30:02 PM PDT 24
Finished Jul 01 04:30:15 PM PDT 24
Peak memory 194424 kb
Host smart-b197d7cf-1ef8-4ccb-9079-09101e2f184e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239768720 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_intr_test.2239768720
Directory /workspace/11.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.3668509826
Short name T97
Test name
Test status
Simulation time 124267930 ps
CPU time 1.68 seconds
Started Jul 01 04:30:18 PM PDT 24
Finished Jul 01 04:30:36 PM PDT 24
Peak memory 199452 kb
Host smart-fa290896-59c9-43a5-b848-3d486df11bcf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668509826 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_same_cs
r_outstanding.3668509826
Directory /workspace/11.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_errors.2600451190
Short name T547
Test name
Test status
Simulation time 51933430 ps
CPU time 2.61 seconds
Started Jul 01 04:30:04 PM PDT 24
Finished Jul 01 04:30:20 PM PDT 24
Peak memory 199384 kb
Host smart-e8177bd2-8e14-43b3-9766-ce5257ee60d0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600451190 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_errors.2600451190
Directory /workspace/11.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.2286746539
Short name T109
Test name
Test status
Simulation time 381328149 ps
CPU time 2.01 seconds
Started Jul 01 04:30:04 PM PDT 24
Finished Jul 01 04:30:19 PM PDT 24
Peak memory 199500 kb
Host smart-035b6a3c-d2a0-409f-8641-9122641af615
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286746539 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_intg_err.2286746539
Directory /workspace/11.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.3998623620
Short name T546
Test name
Test status
Simulation time 39517251 ps
CPU time 1.23 seconds
Started Jul 01 04:30:09 PM PDT 24
Finished Jul 01 04:30:26 PM PDT 24
Peak memory 199324 kb
Host smart-181da024-ec23-4975-88fe-1e367ba8ad0f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998623620 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.hmac_csr_mem_rw_with_rand_reset.3998623620
Directory /workspace/12.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_rw.37079372
Short name T88
Test name
Test status
Simulation time 267002928 ps
CPU time 0.9 seconds
Started Jul 01 04:29:59 PM PDT 24
Finished Jul 01 04:30:12 PM PDT 24
Peak memory 199276 kb
Host smart-d047dd3a-d607-4269-8afd-1b5a3b3f9459
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37079372 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_rw.37079372
Directory /workspace/12.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_intr_test.1153767985
Short name T560
Test name
Test status
Simulation time 62874555 ps
CPU time 0.61 seconds
Started Jul 01 04:29:58 PM PDT 24
Finished Jul 01 04:30:10 PM PDT 24
Peak memory 194376 kb
Host smart-e7e0c586-63c3-4769-9ef9-d358fd2774cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153767985 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_intr_test.1153767985
Directory /workspace/12.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.3466435681
Short name T555
Test name
Test status
Simulation time 46330750 ps
CPU time 2.05 seconds
Started Jul 01 04:30:15 PM PDT 24
Finished Jul 01 04:30:34 PM PDT 24
Peak memory 198860 kb
Host smart-b7c802e2-781e-491c-8a25-0198d10f87c3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466435681 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_same_cs
r_outstanding.3466435681
Directory /workspace/12.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_errors.172298124
Short name T72
Test name
Test status
Simulation time 114953608 ps
CPU time 2.52 seconds
Started Jul 01 04:30:04 PM PDT 24
Finished Jul 01 04:30:20 PM PDT 24
Peak memory 199404 kb
Host smart-f8ece0b0-b22f-4020-99f4-ca9b2a78ecf9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172298124 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_errors.172298124
Directory /workspace/12.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.3397757435
Short name T656
Test name
Test status
Simulation time 705797719055 ps
CPU time 1187.15 seconds
Started Jul 01 04:30:03 PM PDT 24
Finished Jul 01 04:50:03 PM PDT 24
Peak memory 215988 kb
Host smart-324efbb2-35aa-49d2-8841-25e4524dae98
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397757435 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.hmac_csr_mem_rw_with_rand_reset.3397757435
Directory /workspace/13.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_rw.3860105251
Short name T655
Test name
Test status
Simulation time 33680727 ps
CPU time 0.91 seconds
Started Jul 01 04:30:10 PM PDT 24
Finished Jul 01 04:30:27 PM PDT 24
Peak memory 199372 kb
Host smart-94d53ddf-56ea-4516-9446-cac347ddc6f1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860105251 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_rw.3860105251
Directory /workspace/13.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_intr_test.2152973563
Short name T650
Test name
Test status
Simulation time 12302852 ps
CPU time 0.61 seconds
Started Jul 01 04:31:18 PM PDT 24
Finished Jul 01 04:31:30 PM PDT 24
Peak memory 194304 kb
Host smart-f10781c7-e779-4518-a655-b5eb8fb810c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152973563 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_intr_test.2152973563
Directory /workspace/13.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.2259814617
Short name T571
Test name
Test status
Simulation time 1444889243 ps
CPU time 2.29 seconds
Started Jul 01 04:31:01 PM PDT 24
Finished Jul 01 04:31:15 PM PDT 24
Peak memory 198636 kb
Host smart-9ce9a89e-a66d-44f9-ad2b-56224d2e3823
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259814617 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_same_cs
r_outstanding.2259814617
Directory /workspace/13.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_errors.4113822398
Short name T582
Test name
Test status
Simulation time 1127830580 ps
CPU time 1.62 seconds
Started Jul 01 04:30:01 PM PDT 24
Finished Jul 01 04:30:15 PM PDT 24
Peak memory 199392 kb
Host smart-b6a42ace-ce2f-4881-bfec-3679f3007211
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113822398 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_errors.4113822398
Directory /workspace/13.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.4284951820
Short name T55
Test name
Test status
Simulation time 352061974 ps
CPU time 2.84 seconds
Started Jul 01 04:30:13 PM PDT 24
Finished Jul 01 04:30:33 PM PDT 24
Peak memory 199408 kb
Host smart-d5eee135-a25f-462e-9981-8f4269717a20
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284951820 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_intg_err.4284951820
Directory /workspace/13.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.2388913185
Short name T632
Test name
Test status
Simulation time 69617855 ps
CPU time 1.53 seconds
Started Jul 01 04:30:02 PM PDT 24
Finished Jul 01 04:30:16 PM PDT 24
Peak memory 199460 kb
Host smart-74cffdbc-ead6-45a2-a7f8-5604591f9082
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388913185 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.hmac_csr_mem_rw_with_rand_reset.2388913185
Directory /workspace/14.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_rw.1663013071
Short name T102
Test name
Test status
Simulation time 58374472 ps
CPU time 0.89 seconds
Started Jul 01 04:30:14 PM PDT 24
Finished Jul 01 04:30:32 PM PDT 24
Peak memory 198584 kb
Host smart-83ef488d-2b51-4b44-9e76-6b3aa4dd2edd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663013071 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_rw.1663013071
Directory /workspace/14.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_intr_test.2758992537
Short name T625
Test name
Test status
Simulation time 119671936 ps
CPU time 0.61 seconds
Started Jul 01 04:30:00 PM PDT 24
Finished Jul 01 04:30:13 PM PDT 24
Peak memory 194400 kb
Host smart-17d85dac-05d1-4ca6-b3c9-789bf37e21dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758992537 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_intr_test.2758992537
Directory /workspace/14.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.4141950434
Short name T639
Test name
Test status
Simulation time 134774259 ps
CPU time 1.27 seconds
Started Jul 01 04:30:14 PM PDT 24
Finished Jul 01 04:30:32 PM PDT 24
Peak memory 198792 kb
Host smart-85ba2524-9244-4995-a313-4edd551f91ec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141950434 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_same_cs
r_outstanding.4141950434
Directory /workspace/14.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_errors.1709318694
Short name T537
Test name
Test status
Simulation time 60268938 ps
CPU time 3.35 seconds
Started Jul 01 04:30:15 PM PDT 24
Finished Jul 01 04:30:35 PM PDT 24
Peak memory 199408 kb
Host smart-70116844-d4a6-4ec7-b409-fa6baa783eb0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709318694 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_errors.1709318694
Directory /workspace/14.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.398970358
Short name T648
Test name
Test status
Simulation time 86169808 ps
CPU time 2.66 seconds
Started Jul 01 04:31:19 PM PDT 24
Finished Jul 01 04:31:33 PM PDT 24
Peak memory 199320 kb
Host smart-37bde287-5870-43c0-ba89-97dff76335ce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398970358 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_intg_err.398970358
Directory /workspace/14.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.2505148913
Short name T574
Test name
Test status
Simulation time 70609535 ps
CPU time 1.66 seconds
Started Jul 01 04:30:07 PM PDT 24
Finished Jul 01 04:30:25 PM PDT 24
Peak memory 199516 kb
Host smart-1640a5c7-4611-4f4c-93c7-ec3139a3a975
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505148913 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.hmac_csr_mem_rw_with_rand_reset.2505148913
Directory /workspace/15.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_rw.2809931227
Short name T554
Test name
Test status
Simulation time 25225520 ps
CPU time 0.69 seconds
Started Jul 01 04:29:52 PM PDT 24
Finished Jul 01 04:30:05 PM PDT 24
Peak memory 197256 kb
Host smart-4472377f-259c-4f0d-8b48-3e25b74a2acd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809931227 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_rw.2809931227
Directory /workspace/15.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_intr_test.3837413840
Short name T581
Test name
Test status
Simulation time 34647355 ps
CPU time 0.59 seconds
Started Jul 01 04:29:58 PM PDT 24
Finished Jul 01 04:30:10 PM PDT 24
Peak memory 194412 kb
Host smart-05cb5e1f-922b-4dec-9303-10bc88b026e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837413840 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_intr_test.3837413840
Directory /workspace/15.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.2365500892
Short name T622
Test name
Test status
Simulation time 234576353 ps
CPU time 1.62 seconds
Started Jul 01 04:30:03 PM PDT 24
Finished Jul 01 04:30:17 PM PDT 24
Peak memory 199540 kb
Host smart-ede148e4-41d2-431c-802b-25be3de54762
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365500892 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_same_cs
r_outstanding.2365500892
Directory /workspace/15.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_errors.3581706475
Short name T604
Test name
Test status
Simulation time 390316317 ps
CPU time 2.13 seconds
Started Jul 01 04:30:05 PM PDT 24
Finished Jul 01 04:30:22 PM PDT 24
Peak memory 199160 kb
Host smart-889dc466-0268-4cd0-8a6a-77271561bf53
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581706475 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_errors.3581706475
Directory /workspace/15.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.2476257717
Short name T114
Test name
Test status
Simulation time 164980439 ps
CPU time 3.1 seconds
Started Jul 01 04:30:00 PM PDT 24
Finished Jul 01 04:30:15 PM PDT 24
Peak memory 199384 kb
Host smart-05d9e5f8-4c6f-4ccd-a54e-4cd50aba4b2a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476257717 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_intg_err.2476257717
Directory /workspace/15.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.2994167076
Short name T593
Test name
Test status
Simulation time 314484459 ps
CPU time 2.13 seconds
Started Jul 01 04:30:08 PM PDT 24
Finished Jul 01 04:30:27 PM PDT 24
Peak memory 199536 kb
Host smart-2d514f0e-5023-45a3-9152-9e661eaea693
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994167076 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.hmac_csr_mem_rw_with_rand_reset.2994167076
Directory /workspace/16.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_rw.2469948492
Short name T90
Test name
Test status
Simulation time 49793382 ps
CPU time 0.8 seconds
Started Jul 01 04:29:51 PM PDT 24
Finished Jul 01 04:30:03 PM PDT 24
Peak memory 199332 kb
Host smart-36d806f1-c28c-40c8-9815-4adcf6b95d97
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469948492 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_rw.2469948492
Directory /workspace/16.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_intr_test.3185452155
Short name T601
Test name
Test status
Simulation time 18059361 ps
CPU time 0.62 seconds
Started Jul 01 04:30:08 PM PDT 24
Finished Jul 01 04:30:25 PM PDT 24
Peak memory 194652 kb
Host smart-007eeb1d-f027-4441-b605-275fddec4423
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185452155 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_intr_test.3185452155
Directory /workspace/16.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.1078506028
Short name T100
Test name
Test status
Simulation time 44994781 ps
CPU time 2.07 seconds
Started Jul 01 04:30:04 PM PDT 24
Finished Jul 01 04:30:21 PM PDT 24
Peak memory 199560 kb
Host smart-cfe0d0c9-0e3d-45fc-b499-5e9f86dc140d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078506028 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_same_cs
r_outstanding.1078506028
Directory /workspace/16.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_errors.1753041651
Short name T596
Test name
Test status
Simulation time 442734100 ps
CPU time 3.62 seconds
Started Jul 01 04:30:06 PM PDT 24
Finished Jul 01 04:30:25 PM PDT 24
Peak memory 199404 kb
Host smart-e6cbb1d0-dfd2-4da7-8511-a1fd3764cb5f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753041651 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_errors.1753041651
Directory /workspace/16.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.1688197690
Short name T548
Test name
Test status
Simulation time 160611870 ps
CPU time 1.19 seconds
Started Jul 01 04:30:09 PM PDT 24
Finished Jul 01 04:30:26 PM PDT 24
Peak memory 199440 kb
Host smart-2b9c2c8d-8d06-47c5-8067-61a51c267eb0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688197690 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.hmac_csr_mem_rw_with_rand_reset.1688197690
Directory /workspace/17.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_rw.2575631193
Short name T86
Test name
Test status
Simulation time 15432228 ps
CPU time 0.79 seconds
Started Jul 01 04:30:05 PM PDT 24
Finished Jul 01 04:30:20 PM PDT 24
Peak memory 198780 kb
Host smart-3312e6a8-b4e9-4e91-9ea8-100a2b39ed17
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575631193 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_rw.2575631193
Directory /workspace/17.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_intr_test.191570135
Short name T623
Test name
Test status
Simulation time 14089212 ps
CPU time 0.66 seconds
Started Jul 01 04:30:05 PM PDT 24
Finished Jul 01 04:30:20 PM PDT 24
Peak memory 194424 kb
Host smart-45da5fe3-99d0-4270-a40f-7679251ac531
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191570135 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_intr_test.191570135
Directory /workspace/17.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.2498502886
Short name T580
Test name
Test status
Simulation time 331360344 ps
CPU time 1.59 seconds
Started Jul 01 04:30:12 PM PDT 24
Finished Jul 01 04:30:30 PM PDT 24
Peak memory 199388 kb
Host smart-6f7c62c3-0503-4151-acc7-f32938d9446f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498502886 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_same_cs
r_outstanding.2498502886
Directory /workspace/17.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_errors.2364703651
Short name T646
Test name
Test status
Simulation time 71627191 ps
CPU time 1.18 seconds
Started Jul 01 04:30:09 PM PDT 24
Finished Jul 01 04:30:27 PM PDT 24
Peak memory 199396 kb
Host smart-c8470b3f-b080-4a2b-b648-cc487c323ea1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364703651 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_errors.2364703651
Directory /workspace/17.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.2118277026
Short name T594
Test name
Test status
Simulation time 83300818 ps
CPU time 1.89 seconds
Started Jul 01 04:30:14 PM PDT 24
Finished Jul 01 04:30:33 PM PDT 24
Peak memory 199428 kb
Host smart-e1344211-0023-4fea-8eee-399ae893c25a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118277026 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_intg_err.2118277026
Directory /workspace/17.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.1330825666
Short name T536
Test name
Test status
Simulation time 21910506 ps
CPU time 1.12 seconds
Started Jul 01 04:30:02 PM PDT 24
Finished Jul 01 04:30:16 PM PDT 24
Peak memory 199388 kb
Host smart-150c946e-6988-4f25-bff9-eb7b7d3f43c1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330825666 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.hmac_csr_mem_rw_with_rand_reset.1330825666
Directory /workspace/18.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_rw.1882322366
Short name T533
Test name
Test status
Simulation time 85925247 ps
CPU time 0.73 seconds
Started Jul 01 04:30:06 PM PDT 24
Finished Jul 01 04:30:21 PM PDT 24
Peak memory 197628 kb
Host smart-89d37a14-917a-4613-b465-66de6a8f0c59
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882322366 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_rw.1882322366
Directory /workspace/18.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_intr_test.222280260
Short name T651
Test name
Test status
Simulation time 15085201 ps
CPU time 0.62 seconds
Started Jul 01 04:30:05 PM PDT 24
Finished Jul 01 04:30:20 PM PDT 24
Peak memory 194404 kb
Host smart-d408f178-56b4-4d53-882e-279a53b0b62d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222280260 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_intr_test.222280260
Directory /workspace/18.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.934380243
Short name T96
Test name
Test status
Simulation time 24378080 ps
CPU time 1.07 seconds
Started Jul 01 04:30:13 PM PDT 24
Finished Jul 01 04:30:32 PM PDT 24
Peak memory 199320 kb
Host smart-e16b53ab-544b-4d54-8ba1-b9873ddc0c9f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934380243 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_same_csr
_outstanding.934380243
Directory /workspace/18.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_errors.2808558094
Short name T545
Test name
Test status
Simulation time 139568625 ps
CPU time 2.92 seconds
Started Jul 01 04:30:14 PM PDT 24
Finished Jul 01 04:30:34 PM PDT 24
Peak memory 199468 kb
Host smart-996caa0d-5294-44af-ba65-0ca53551c308
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808558094 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_errors.2808558094
Directory /workspace/18.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.1690226949
Short name T106
Test name
Test status
Simulation time 80144042 ps
CPU time 1.85 seconds
Started Jul 01 04:30:15 PM PDT 24
Finished Jul 01 04:30:35 PM PDT 24
Peak memory 199484 kb
Host smart-54d3ea16-110e-492f-a4ea-7394092b32bc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690226949 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_intg_err.1690226949
Directory /workspace/18.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.1171527827
Short name T631
Test name
Test status
Simulation time 39942547 ps
CPU time 2.54 seconds
Started Jul 01 04:30:14 PM PDT 24
Finished Jul 01 04:30:34 PM PDT 24
Peak memory 207832 kb
Host smart-5f17d8e5-f75a-426d-8312-db53b41be1f8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171527827 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.hmac_csr_mem_rw_with_rand_reset.1171527827
Directory /workspace/19.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_rw.3416267249
Short name T87
Test name
Test status
Simulation time 40913545 ps
CPU time 0.69 seconds
Started Jul 01 04:30:08 PM PDT 24
Finished Jul 01 04:30:25 PM PDT 24
Peak memory 197584 kb
Host smart-ed881f0b-5ddd-4bf8-aa28-36f29ebdc9fa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416267249 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_rw.3416267249
Directory /workspace/19.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_intr_test.238564119
Short name T595
Test name
Test status
Simulation time 13923823 ps
CPU time 0.55 seconds
Started Jul 01 04:30:06 PM PDT 24
Finished Jul 01 04:30:22 PM PDT 24
Peak memory 194368 kb
Host smart-e494568b-18a2-461c-acdf-f454ba5b5bb4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238564119 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_intr_test.238564119
Directory /workspace/19.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.3336195558
Short name T101
Test name
Test status
Simulation time 105713266 ps
CPU time 1.13 seconds
Started Jul 01 04:30:07 PM PDT 24
Finished Jul 01 04:30:24 PM PDT 24
Peak memory 197724 kb
Host smart-c4b2484c-cd00-4015-927a-b33b635003cb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336195558 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_same_cs
r_outstanding.3336195558
Directory /workspace/19.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_errors.3281196931
Short name T629
Test name
Test status
Simulation time 962786615 ps
CPU time 3.18 seconds
Started Jul 01 04:30:08 PM PDT 24
Finished Jul 01 04:30:28 PM PDT 24
Peak memory 199480 kb
Host smart-06444de8-23a8-4033-b636-8c0e7be53501
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281196931 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_errors.3281196931
Directory /workspace/19.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.171120081
Short name T600
Test name
Test status
Simulation time 747560773 ps
CPU time 3.23 seconds
Started Jul 01 04:30:05 PM PDT 24
Finished Jul 01 04:30:22 PM PDT 24
Peak memory 199472 kb
Host smart-dd4a83ae-9e62-42d1-90ef-df88823378d6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171120081 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_intg_err.171120081
Directory /workspace/19.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.2447552784
Short name T643
Test name
Test status
Simulation time 453545839 ps
CPU time 8.45 seconds
Started Jul 01 04:29:52 PM PDT 24
Finished Jul 01 04:30:12 PM PDT 24
Peak memory 199376 kb
Host smart-83015396-b63c-4e94-ae98-cac136353b92
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447552784 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_aliasing.2447552784
Directory /workspace/2.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.2153438299
Short name T559
Test name
Test status
Simulation time 1104196915 ps
CPU time 16.23 seconds
Started Jul 01 04:29:58 PM PDT 24
Finished Jul 01 04:30:25 PM PDT 24
Peak memory 199460 kb
Host smart-df64c8df-91d4-4cef-8777-468481c687d2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153438299 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_bit_bash.2153438299
Directory /workspace/2.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.2196761449
Short name T612
Test name
Test status
Simulation time 81153181 ps
CPU time 0.99 seconds
Started Jul 01 04:30:04 PM PDT 24
Finished Jul 01 04:30:18 PM PDT 24
Peak memory 199208 kb
Host smart-c8abae73-468b-464a-8039-da34f947f7d7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196761449 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_hw_reset.2196761449
Directory /workspace/2.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.963988544
Short name T627
Test name
Test status
Simulation time 63472415 ps
CPU time 1.72 seconds
Started Jul 01 04:30:05 PM PDT 24
Finished Jul 01 04:30:21 PM PDT 24
Peak memory 199468 kb
Host smart-72d7e443-0ddf-40f8-bc17-a2869113fc60
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963988544 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.hmac_csr_mem_rw_with_rand_reset.963988544
Directory /workspace/2.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_rw.28106040
Short name T95
Test name
Test status
Simulation time 17299966 ps
CPU time 0.88 seconds
Started Jul 01 04:29:49 PM PDT 24
Finished Jul 01 04:30:01 PM PDT 24
Peak memory 199268 kb
Host smart-0e5e7148-8821-4018-acd5-132f034534b9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28106040 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_rw.28106040
Directory /workspace/2.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_intr_test.2169016150
Short name T628
Test name
Test status
Simulation time 12837507 ps
CPU time 0.59 seconds
Started Jul 01 04:30:02 PM PDT 24
Finished Jul 01 04:30:15 PM PDT 24
Peak memory 194432 kb
Host smart-48611c02-fc3c-4712-a7b9-9016150ae0d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169016150 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_intr_test.2169016150
Directory /workspace/2.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.1020083598
Short name T619
Test name
Test status
Simulation time 38090974 ps
CPU time 1.6 seconds
Started Jul 01 04:29:48 PM PDT 24
Finished Jul 01 04:30:01 PM PDT 24
Peak memory 199336 kb
Host smart-16edef02-31c0-4a2e-b813-ab69f8909fda
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020083598 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_same_csr
_outstanding.1020083598
Directory /workspace/2.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_errors.35466110
Short name T618
Test name
Test status
Simulation time 162907294 ps
CPU time 2.96 seconds
Started Jul 01 04:30:07 PM PDT 24
Finished Jul 01 04:30:26 PM PDT 24
Peak memory 199456 kb
Host smart-069466f9-e850-4b35-be81-e87f979378fc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35466110 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_errors.35466110
Directory /workspace/2.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.hmac_intr_test.2144345830
Short name T645
Test name
Test status
Simulation time 13947472 ps
CPU time 0.59 seconds
Started Jul 01 04:30:10 PM PDT 24
Finished Jul 01 04:30:26 PM PDT 24
Peak memory 194388 kb
Host smart-f8c289dc-8596-4e0e-971c-87e8d74eebd0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144345830 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.hmac_intr_test.2144345830
Directory /workspace/20.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.hmac_intr_test.245596840
Short name T541
Test name
Test status
Simulation time 17566945 ps
CPU time 0.57 seconds
Started Jul 01 04:30:11 PM PDT 24
Finished Jul 01 04:30:28 PM PDT 24
Peak memory 194352 kb
Host smart-732fcc06-feb1-4b20-950f-3c0f9e8e90eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245596840 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.hmac_intr_test.245596840
Directory /workspace/21.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.hmac_intr_test.1272894145
Short name T563
Test name
Test status
Simulation time 28149060 ps
CPU time 0.63 seconds
Started Jul 01 04:30:07 PM PDT 24
Finished Jul 01 04:30:24 PM PDT 24
Peak memory 194476 kb
Host smart-705d6f85-ad98-4095-9a56-00c145e4e2ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272894145 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.hmac_intr_test.1272894145
Directory /workspace/22.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.hmac_intr_test.722408954
Short name T640
Test name
Test status
Simulation time 29836126 ps
CPU time 0.6 seconds
Started Jul 01 04:30:14 PM PDT 24
Finished Jul 01 04:30:32 PM PDT 24
Peak memory 194284 kb
Host smart-abd6db68-e474-4652-a7ed-d13ca525b529
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722408954 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.hmac_intr_test.722408954
Directory /workspace/23.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.hmac_intr_test.1091983949
Short name T592
Test name
Test status
Simulation time 53887779 ps
CPU time 0.63 seconds
Started Jul 01 04:30:17 PM PDT 24
Finished Jul 01 04:30:35 PM PDT 24
Peak memory 194420 kb
Host smart-480e1f61-4eed-4353-8165-8c3135c5bc2b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091983949 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.hmac_intr_test.1091983949
Directory /workspace/24.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.hmac_intr_test.4157716301
Short name T540
Test name
Test status
Simulation time 36776226 ps
CPU time 0.63 seconds
Started Jul 01 04:30:04 PM PDT 24
Finished Jul 01 04:30:18 PM PDT 24
Peak memory 194504 kb
Host smart-b4566902-7bac-409f-bc53-3d5891ba80cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157716301 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.hmac_intr_test.4157716301
Directory /workspace/25.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.hmac_intr_test.2361056975
Short name T605
Test name
Test status
Simulation time 18386073 ps
CPU time 0.59 seconds
Started Jul 01 04:30:06 PM PDT 24
Finished Jul 01 04:30:21 PM PDT 24
Peak memory 194388 kb
Host smart-74f610cd-5de5-48cb-a270-d9594c1157f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361056975 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.hmac_intr_test.2361056975
Directory /workspace/26.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.hmac_intr_test.1716520114
Short name T637
Test name
Test status
Simulation time 16854973 ps
CPU time 0.62 seconds
Started Jul 01 04:30:06 PM PDT 24
Finished Jul 01 04:30:21 PM PDT 24
Peak memory 194400 kb
Host smart-04059e54-4f86-4259-9da8-bc82e88c9595
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716520114 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.hmac_intr_test.1716520114
Directory /workspace/27.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.hmac_intr_test.2652937770
Short name T542
Test name
Test status
Simulation time 57657023 ps
CPU time 0.56 seconds
Started Jul 01 04:30:07 PM PDT 24
Finished Jul 01 04:30:24 PM PDT 24
Peak memory 194356 kb
Host smart-7f8ee9a3-701a-4e51-b2e5-54894dc1e6aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652937770 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.hmac_intr_test.2652937770
Directory /workspace/28.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.hmac_intr_test.2030101653
Short name T603
Test name
Test status
Simulation time 42778326 ps
CPU time 0.58 seconds
Started Jul 01 04:30:10 PM PDT 24
Finished Jul 01 04:30:28 PM PDT 24
Peak memory 194464 kb
Host smart-13a094f6-68fc-443e-b76f-1d9df5e24ea4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030101653 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.hmac_intr_test.2030101653
Directory /workspace/29.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.3299107583
Short name T611
Test name
Test status
Simulation time 420809452 ps
CPU time 6.09 seconds
Started Jul 01 04:29:49 PM PDT 24
Finished Jul 01 04:30:06 PM PDT 24
Peak memory 199444 kb
Host smart-fbde17e7-1ed5-4c4c-81cd-764d4dad6ab7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299107583 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_aliasing.3299107583
Directory /workspace/3.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.2014882201
Short name T617
Test name
Test status
Simulation time 6051242568 ps
CPU time 16.96 seconds
Started Jul 01 04:30:19 PM PDT 24
Finished Jul 01 04:30:51 PM PDT 24
Peak memory 199272 kb
Host smart-90b5466a-866b-4cf6-bfad-7abaaa006de5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014882201 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_bit_bash.2014882201
Directory /workspace/3.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.1578986267
Short name T644
Test name
Test status
Simulation time 42620613 ps
CPU time 1.07 seconds
Started Jul 01 04:30:16 PM PDT 24
Finished Jul 01 04:30:34 PM PDT 24
Peak memory 199308 kb
Host smart-5fa2c523-52c2-43e2-80b7-b7525a1702ad
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578986267 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_hw_reset.1578986267
Directory /workspace/3.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.1856533039
Short name T544
Test name
Test status
Simulation time 80536073648 ps
CPU time 842.85 seconds
Started Jul 01 04:29:59 PM PDT 24
Finished Jul 01 04:44:13 PM PDT 24
Peak memory 215960 kb
Host smart-337d689b-f572-46d4-a220-0d396ce5d3bd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856533039 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.hmac_csr_mem_rw_with_rand_reset.1856533039
Directory /workspace/3.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_rw.1102099777
Short name T657
Test name
Test status
Simulation time 52605172 ps
CPU time 0.68 seconds
Started Jul 01 04:29:58 PM PDT 24
Finished Jul 01 04:30:10 PM PDT 24
Peak memory 197180 kb
Host smart-e0189df8-131d-42b1-a7cf-dc931255d2b3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102099777 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_rw.1102099777
Directory /workspace/3.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_intr_test.1607890736
Short name T68
Test name
Test status
Simulation time 66196837 ps
CPU time 0.62 seconds
Started Jul 01 04:29:59 PM PDT 24
Finished Jul 01 04:30:12 PM PDT 24
Peak memory 194404 kb
Host smart-97deb055-2485-46c8-8143-98832ca3199b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607890736 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_intr_test.1607890736
Directory /workspace/3.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.1661367006
Short name T636
Test name
Test status
Simulation time 34353344 ps
CPU time 1.63 seconds
Started Jul 01 04:30:06 PM PDT 24
Finished Jul 01 04:30:23 PM PDT 24
Peak memory 199408 kb
Host smart-1530f7ac-e836-42dd-aca9-b20940a5ee97
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661367006 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_same_csr
_outstanding.1661367006
Directory /workspace/3.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_errors.3338620273
Short name T539
Test name
Test status
Simulation time 290488597 ps
CPU time 2.69 seconds
Started Jul 01 04:30:22 PM PDT 24
Finished Jul 01 04:30:40 PM PDT 24
Peak memory 199420 kb
Host smart-4d660e07-244a-457f-83f4-ce9763bc8d4a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338620273 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_errors.3338620273
Directory /workspace/3.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.1034183664
Short name T110
Test name
Test status
Simulation time 81356747 ps
CPU time 1.78 seconds
Started Jul 01 04:30:04 PM PDT 24
Finished Jul 01 04:30:19 PM PDT 24
Peak memory 199448 kb
Host smart-aa207f2b-055f-4cd3-ba7c-82e8ad860f88
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034183664 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_intg_err.1034183664
Directory /workspace/3.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.hmac_intr_test.1100122336
Short name T615
Test name
Test status
Simulation time 17985545 ps
CPU time 0.59 seconds
Started Jul 01 04:30:06 PM PDT 24
Finished Jul 01 04:30:22 PM PDT 24
Peak memory 194460 kb
Host smart-cd3a5a7f-6593-4d96-9737-f64b314d9d49
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100122336 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.hmac_intr_test.1100122336
Directory /workspace/30.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.hmac_intr_test.1356608265
Short name T584
Test name
Test status
Simulation time 18321522 ps
CPU time 0.63 seconds
Started Jul 01 04:30:03 PM PDT 24
Finished Jul 01 04:30:16 PM PDT 24
Peak memory 194516 kb
Host smart-67d98663-abc6-4cdd-b162-9a07800dada7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356608265 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.hmac_intr_test.1356608265
Directory /workspace/31.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.hmac_intr_test.2730442230
Short name T590
Test name
Test status
Simulation time 18021891 ps
CPU time 0.63 seconds
Started Jul 01 04:30:03 PM PDT 24
Finished Jul 01 04:30:16 PM PDT 24
Peak memory 194420 kb
Host smart-8c02f13c-b78a-4f4b-be35-05ccb40357e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730442230 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.hmac_intr_test.2730442230
Directory /workspace/32.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.hmac_intr_test.910517908
Short name T610
Test name
Test status
Simulation time 41646723 ps
CPU time 0.62 seconds
Started Jul 01 04:30:21 PM PDT 24
Finished Jul 01 04:30:37 PM PDT 24
Peak memory 194696 kb
Host smart-fef95793-c7d8-4d7e-a2ac-776d0ad4bb27
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910517908 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.hmac_intr_test.910517908
Directory /workspace/33.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.hmac_intr_test.2818096363
Short name T613
Test name
Test status
Simulation time 80405144 ps
CPU time 0.59 seconds
Started Jul 01 04:30:05 PM PDT 24
Finished Jul 01 04:30:21 PM PDT 24
Peak memory 194564 kb
Host smart-495edd54-0d25-4edf-9b4b-fa55d2a4c3eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818096363 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.hmac_intr_test.2818096363
Directory /workspace/34.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.hmac_intr_test.1947199062
Short name T577
Test name
Test status
Simulation time 39134249 ps
CPU time 0.59 seconds
Started Jul 01 04:30:22 PM PDT 24
Finished Jul 01 04:30:37 PM PDT 24
Peak memory 194396 kb
Host smart-1167bdcf-1194-479b-a98c-a84ccb03fe70
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947199062 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.hmac_intr_test.1947199062
Directory /workspace/35.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.hmac_intr_test.3410968283
Short name T634
Test name
Test status
Simulation time 41386387 ps
CPU time 0.57 seconds
Started Jul 01 04:30:08 PM PDT 24
Finished Jul 01 04:30:25 PM PDT 24
Peak memory 194484 kb
Host smart-715c820b-4e56-4606-8fad-e2aad1c4da17
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410968283 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.hmac_intr_test.3410968283
Directory /workspace/36.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.hmac_intr_test.3951560860
Short name T647
Test name
Test status
Simulation time 16283930 ps
CPU time 0.6 seconds
Started Jul 01 04:30:11 PM PDT 24
Finished Jul 01 04:30:28 PM PDT 24
Peak memory 194420 kb
Host smart-45371b96-36c0-4e61-8ef2-ef3dee1698b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951560860 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.hmac_intr_test.3951560860
Directory /workspace/37.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.hmac_intr_test.1424326919
Short name T579
Test name
Test status
Simulation time 57574134 ps
CPU time 0.6 seconds
Started Jul 01 04:30:08 PM PDT 24
Finished Jul 01 04:30:25 PM PDT 24
Peak memory 194412 kb
Host smart-6512dd23-0862-4969-814e-6118a5e80e98
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424326919 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.hmac_intr_test.1424326919
Directory /workspace/38.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.hmac_intr_test.1367600655
Short name T609
Test name
Test status
Simulation time 33194638 ps
CPU time 0.59 seconds
Started Jul 01 04:30:23 PM PDT 24
Finished Jul 01 04:30:38 PM PDT 24
Peak memory 194396 kb
Host smart-b7a99b6f-63d9-4ed8-a902-e16c9036182b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367600655 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.hmac_intr_test.1367600655
Directory /workspace/39.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.3688635423
Short name T89
Test name
Test status
Simulation time 476787485 ps
CPU time 9.06 seconds
Started Jul 01 04:29:59 PM PDT 24
Finished Jul 01 04:30:19 PM PDT 24
Peak memory 199392 kb
Host smart-29b769ff-9ced-47f0-bbcb-8df3ae82266a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688635423 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_aliasing.3688635423
Directory /workspace/4.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.925044001
Short name T652
Test name
Test status
Simulation time 1331481391 ps
CPU time 11 seconds
Started Jul 01 04:30:00 PM PDT 24
Finished Jul 01 04:30:22 PM PDT 24
Peak memory 199344 kb
Host smart-355e7e71-ed94-4175-9298-e9d8c9f68c46
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925044001 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_bit_bash.925044001
Directory /workspace/4.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.2509251793
Short name T92
Test name
Test status
Simulation time 35780069 ps
CPU time 0.74 seconds
Started Jul 01 04:30:11 PM PDT 24
Finished Jul 01 04:30:28 PM PDT 24
Peak memory 197928 kb
Host smart-e571d06b-715e-4a1d-896b-002769ffc911
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509251793 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_hw_reset.2509251793
Directory /workspace/4.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.1824393740
Short name T658
Test name
Test status
Simulation time 90834999511 ps
CPU time 998.25 seconds
Started Jul 01 04:30:05 PM PDT 24
Finished Jul 01 04:46:58 PM PDT 24
Peak memory 216040 kb
Host smart-7c72b0f8-51a6-4765-9fdf-9bf77002b370
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824393740 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.hmac_csr_mem_rw_with_rand_reset.1824393740
Directory /workspace/4.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_rw.2701146662
Short name T93
Test name
Test status
Simulation time 56364429 ps
CPU time 0.91 seconds
Started Jul 01 04:29:49 PM PDT 24
Finished Jul 01 04:30:02 PM PDT 24
Peak memory 199288 kb
Host smart-f5db98bf-c6f7-45c1-adde-2ab7bb70f47f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701146662 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_rw.2701146662
Directory /workspace/4.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_intr_test.3206663297
Short name T578
Test name
Test status
Simulation time 57836768 ps
CPU time 0.61 seconds
Started Jul 01 04:30:12 PM PDT 24
Finished Jul 01 04:30:29 PM PDT 24
Peak memory 194508 kb
Host smart-4fd62f4e-514f-496d-b7f9-4ea68da8b7b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206663297 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_intr_test.3206663297
Directory /workspace/4.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.2863844660
Short name T638
Test name
Test status
Simulation time 719551020 ps
CPU time 2.46 seconds
Started Jul 01 04:29:49 PM PDT 24
Finished Jul 01 04:30:03 PM PDT 24
Peak memory 199384 kb
Host smart-9709c94b-4434-4dde-a354-fc0762af912b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863844660 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_same_csr
_outstanding.2863844660
Directory /workspace/4.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_errors.847033673
Short name T607
Test name
Test status
Simulation time 140147655 ps
CPU time 3.3 seconds
Started Jul 01 04:30:08 PM PDT 24
Finished Jul 01 04:30:28 PM PDT 24
Peak memory 199588 kb
Host smart-d7479687-d2bb-43ef-9417-22b43fb73b2f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847033673 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_errors.847033673
Directory /workspace/4.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.417371796
Short name T570
Test name
Test status
Simulation time 96174502 ps
CPU time 1.84 seconds
Started Jul 01 04:30:05 PM PDT 24
Finished Jul 01 04:30:22 PM PDT 24
Peak memory 199408 kb
Host smart-cdb5f17b-c763-4a8f-9e2b-8eb7656a4d9f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417371796 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_intg_err.417371796
Directory /workspace/4.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.hmac_intr_test.1651825011
Short name T567
Test name
Test status
Simulation time 15690784 ps
CPU time 0.59 seconds
Started Jul 01 04:30:05 PM PDT 24
Finished Jul 01 04:30:20 PM PDT 24
Peak memory 194088 kb
Host smart-792d1e8b-5206-49e9-b436-0003f96ee028
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651825011 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.hmac_intr_test.1651825011
Directory /workspace/40.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.hmac_intr_test.4287903968
Short name T565
Test name
Test status
Simulation time 38708846 ps
CPU time 0.57 seconds
Started Jul 01 04:30:24 PM PDT 24
Finished Jul 01 04:30:39 PM PDT 24
Peak memory 194324 kb
Host smart-76960ac2-021e-4e95-8cdb-22bb71620ba0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287903968 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.hmac_intr_test.4287903968
Directory /workspace/41.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.hmac_intr_test.147566400
Short name T635
Test name
Test status
Simulation time 46571373 ps
CPU time 0.68 seconds
Started Jul 01 04:30:15 PM PDT 24
Finished Jul 01 04:30:33 PM PDT 24
Peak memory 194476 kb
Host smart-ba50b91b-73da-4e03-bfc2-e193634041f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147566400 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.hmac_intr_test.147566400
Directory /workspace/42.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.hmac_intr_test.2557624852
Short name T641
Test name
Test status
Simulation time 19151235 ps
CPU time 0.62 seconds
Started Jul 01 04:30:16 PM PDT 24
Finished Jul 01 04:30:34 PM PDT 24
Peak memory 194452 kb
Host smart-0b6dc803-9a03-42b7-8f6b-bec3cac0cb34
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557624852 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.hmac_intr_test.2557624852
Directory /workspace/43.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.hmac_intr_test.216527468
Short name T620
Test name
Test status
Simulation time 20498780 ps
CPU time 0.6 seconds
Started Jul 01 04:30:16 PM PDT 24
Finished Jul 01 04:30:34 PM PDT 24
Peak memory 194480 kb
Host smart-e5834d7a-a332-446a-a088-ad714e6473fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216527468 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.hmac_intr_test.216527468
Directory /workspace/44.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.hmac_intr_test.406756489
Short name T562
Test name
Test status
Simulation time 72884429 ps
CPU time 0.59 seconds
Started Jul 01 04:30:15 PM PDT 24
Finished Jul 01 04:30:34 PM PDT 24
Peak memory 194412 kb
Host smart-efc01e07-8289-498b-808e-12056b0ad571
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406756489 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.hmac_intr_test.406756489
Directory /workspace/45.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.hmac_intr_test.447820678
Short name T591
Test name
Test status
Simulation time 21780759 ps
CPU time 0.58 seconds
Started Jul 01 04:30:22 PM PDT 24
Finished Jul 01 04:30:37 PM PDT 24
Peak memory 194424 kb
Host smart-bedc066c-943a-4e7f-a866-12d75e922b57
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447820678 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.hmac_intr_test.447820678
Directory /workspace/46.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.hmac_intr_test.2445602294
Short name T534
Test name
Test status
Simulation time 18878526 ps
CPU time 0.65 seconds
Started Jul 01 04:30:16 PM PDT 24
Finished Jul 01 04:30:34 PM PDT 24
Peak memory 194628 kb
Host smart-f5fa80e6-d223-4f97-ade7-616241e17849
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445602294 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.hmac_intr_test.2445602294
Directory /workspace/47.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.hmac_intr_test.2868122707
Short name T552
Test name
Test status
Simulation time 13073286 ps
CPU time 0.61 seconds
Started Jul 01 04:30:18 PM PDT 24
Finished Jul 01 04:30:35 PM PDT 24
Peak memory 194508 kb
Host smart-630da730-21fc-4c65-b337-6120e89e4869
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868122707 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.hmac_intr_test.2868122707
Directory /workspace/48.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.hmac_intr_test.3677018797
Short name T566
Test name
Test status
Simulation time 13370784 ps
CPU time 0.6 seconds
Started Jul 01 04:30:29 PM PDT 24
Finished Jul 01 04:30:42 PM PDT 24
Peak memory 194412 kb
Host smart-ecd28e21-693b-43d6-a1df-92e3a1ea5cda
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677018797 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.hmac_intr_test.3677018797
Directory /workspace/49.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.982516432
Short name T568
Test name
Test status
Simulation time 28448062 ps
CPU time 1.85 seconds
Started Jul 01 04:29:47 PM PDT 24
Finished Jul 01 04:30:00 PM PDT 24
Peak memory 199656 kb
Host smart-ff6eba78-95d1-4566-9f28-f561a6a6bce4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982516432 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.hmac_csr_mem_rw_with_rand_reset.982516432
Directory /workspace/5.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_rw.1110970004
Short name T91
Test name
Test status
Simulation time 16496862 ps
CPU time 0.78 seconds
Started Jul 01 04:29:49 PM PDT 24
Finished Jul 01 04:30:01 PM PDT 24
Peak memory 198436 kb
Host smart-cdc55a24-d37b-4a54-a511-de4d846e4389
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110970004 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_rw.1110970004
Directory /workspace/5.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_intr_test.2906155748
Short name T597
Test name
Test status
Simulation time 17294250 ps
CPU time 0.6 seconds
Started Jul 01 04:30:06 PM PDT 24
Finished Jul 01 04:30:21 PM PDT 24
Peak memory 194400 kb
Host smart-a6ad2b50-6b22-4aa1-be1d-aaa9d7ce74a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906155748 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_intr_test.2906155748
Directory /workspace/5.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.2486185379
Short name T550
Test name
Test status
Simulation time 415282844 ps
CPU time 2.4 seconds
Started Jul 01 04:29:55 PM PDT 24
Finished Jul 01 04:30:08 PM PDT 24
Peak memory 199608 kb
Host smart-4941654d-8b2f-41e7-9353-8efe2e6316c5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486185379 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_same_csr
_outstanding.2486185379
Directory /workspace/5.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_errors.1783189028
Short name T583
Test name
Test status
Simulation time 197662568 ps
CPU time 1.69 seconds
Started Jul 01 04:29:58 PM PDT 24
Finished Jul 01 04:30:11 PM PDT 24
Peak memory 199392 kb
Host smart-b0d03994-afc5-407a-a0bb-f7d6f1a713fa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783189028 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_errors.1783189028
Directory /workspace/5.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.961106812
Short name T606
Test name
Test status
Simulation time 395410440 ps
CPU time 2.16 seconds
Started Jul 01 04:29:55 PM PDT 24
Finished Jul 01 04:30:08 PM PDT 24
Peak memory 199524 kb
Host smart-780af7ad-91aa-42fb-a340-a1bb554cbc0e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961106812 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.hmac_csr_mem_rw_with_rand_reset.961106812
Directory /workspace/6.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_rw.3766602407
Short name T85
Test name
Test status
Simulation time 30026086 ps
CPU time 0.84 seconds
Started Jul 01 04:29:50 PM PDT 24
Finished Jul 01 04:30:03 PM PDT 24
Peak memory 199132 kb
Host smart-b96ec29e-ae7e-4a4f-b46a-67c4e73dd3f2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766602407 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_rw.3766602407
Directory /workspace/6.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_intr_test.3694702383
Short name T561
Test name
Test status
Simulation time 23363934 ps
CPU time 0.6 seconds
Started Jul 01 04:30:05 PM PDT 24
Finished Jul 01 04:30:20 PM PDT 24
Peak memory 194396 kb
Host smart-8565ce8e-f12d-4d8a-8163-4b5819c9997d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694702383 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_intr_test.3694702383
Directory /workspace/6.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.2952971170
Short name T558
Test name
Test status
Simulation time 137438046 ps
CPU time 1.63 seconds
Started Jul 01 04:29:59 PM PDT 24
Finished Jul 01 04:30:12 PM PDT 24
Peak memory 199532 kb
Host smart-06afd168-c621-4602-bdde-7ee7fa0a166e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952971170 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_same_csr
_outstanding.2952971170
Directory /workspace/6.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_errors.2138812394
Short name T585
Test name
Test status
Simulation time 299906359 ps
CPU time 1.6 seconds
Started Jul 01 04:29:50 PM PDT 24
Finished Jul 01 04:30:03 PM PDT 24
Peak memory 199628 kb
Host smart-4671a71e-0fb7-4e98-b578-28cb90c8adf0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138812394 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_errors.2138812394
Directory /workspace/6.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.1817164485
Short name T587
Test name
Test status
Simulation time 91816720 ps
CPU time 2.99 seconds
Started Jul 01 04:30:06 PM PDT 24
Finished Jul 01 04:30:25 PM PDT 24
Peak memory 207728 kb
Host smart-4c0e8413-e4a5-4c84-8251-0f00b22c9303
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817164485 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.hmac_csr_mem_rw_with_rand_reset.1817164485
Directory /workspace/7.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_rw.1665140701
Short name T84
Test name
Test status
Simulation time 18074790 ps
CPU time 0.72 seconds
Started Jul 01 04:29:50 PM PDT 24
Finished Jul 01 04:30:02 PM PDT 24
Peak memory 198056 kb
Host smart-7eef95c8-98f3-43ab-9390-f92da2fdc72a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665140701 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_rw.1665140701
Directory /workspace/7.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_intr_test.1926250390
Short name T616
Test name
Test status
Simulation time 12940519 ps
CPU time 0.59 seconds
Started Jul 01 04:29:57 PM PDT 24
Finished Jul 01 04:30:08 PM PDT 24
Peak memory 194496 kb
Host smart-b463f276-a4ef-4a24-895b-6fd4c9013d8e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926250390 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_intr_test.1926250390
Directory /workspace/7.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.3437761096
Short name T556
Test name
Test status
Simulation time 235005514 ps
CPU time 1.94 seconds
Started Jul 01 04:30:00 PM PDT 24
Finished Jul 01 04:30:14 PM PDT 24
Peak memory 199384 kb
Host smart-7d9834c2-7605-41bb-9dee-6edbe732987e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437761096 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_same_csr
_outstanding.3437761096
Directory /workspace/7.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_errors.3813475696
Short name T598
Test name
Test status
Simulation time 176045518 ps
CPU time 2.64 seconds
Started Jul 01 04:29:58 PM PDT 24
Finished Jul 01 04:30:12 PM PDT 24
Peak memory 199460 kb
Host smart-44d6bc8b-95ee-414a-842b-911bd4d47537
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813475696 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_errors.3813475696
Directory /workspace/7.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.902591663
Short name T649
Test name
Test status
Simulation time 54637335 ps
CPU time 1.81 seconds
Started Jul 01 04:29:45 PM PDT 24
Finished Jul 01 04:29:58 PM PDT 24
Peak memory 199620 kb
Host smart-e1c01a9a-8062-4697-87c4-9b8093331b51
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902591663 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_intg_err.902591663
Directory /workspace/7.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.3276470623
Short name T588
Test name
Test status
Simulation time 82955073 ps
CPU time 2.56 seconds
Started Jul 01 04:29:53 PM PDT 24
Finished Jul 01 04:30:07 PM PDT 24
Peak memory 199508 kb
Host smart-c360fd8c-fcc2-4835-98dd-62dba6c45bb1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276470623 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.hmac_csr_mem_rw_with_rand_reset.3276470623
Directory /workspace/8.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_rw.3159382888
Short name T66
Test name
Test status
Simulation time 33175171 ps
CPU time 1.03 seconds
Started Jul 01 04:30:19 PM PDT 24
Finished Jul 01 04:30:35 PM PDT 24
Peak memory 199288 kb
Host smart-3a5ddc90-e6ac-474b-971c-8d9dd791d38c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159382888 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_rw.3159382888
Directory /workspace/8.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_intr_test.2530184683
Short name T564
Test name
Test status
Simulation time 91097840 ps
CPU time 0.6 seconds
Started Jul 01 04:29:50 PM PDT 24
Finished Jul 01 04:30:02 PM PDT 24
Peak memory 194456 kb
Host smart-88eeeb5d-e91c-451f-9475-9ef54be2548b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530184683 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_intr_test.2530184683
Directory /workspace/8.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.3100626205
Short name T573
Test name
Test status
Simulation time 97763088 ps
CPU time 1.14 seconds
Started Jul 01 04:30:02 PM PDT 24
Finished Jul 01 04:30:16 PM PDT 24
Peak memory 199376 kb
Host smart-5d96dd64-2d4a-4614-85e0-ca7e7c29d509
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100626205 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_same_csr
_outstanding.3100626205
Directory /workspace/8.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_errors.2166615920
Short name T589
Test name
Test status
Simulation time 147021217 ps
CPU time 2.84 seconds
Started Jul 01 04:30:12 PM PDT 24
Finished Jul 01 04:30:33 PM PDT 24
Peak memory 199576 kb
Host smart-86488b40-86f5-43dc-911b-e046f7109bfc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166615920 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_errors.2166615920
Directory /workspace/8.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.294226433
Short name T57
Test name
Test status
Simulation time 905186070 ps
CPU time 1.95 seconds
Started Jul 01 04:29:49 PM PDT 24
Finished Jul 01 04:30:03 PM PDT 24
Peak memory 199452 kb
Host smart-ba56181f-3f65-4da4-b4a6-0fb5ba429183
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294226433 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_intg_err.294226433
Directory /workspace/8.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.1401885203
Short name T572
Test name
Test status
Simulation time 78624539 ps
CPU time 2.5 seconds
Started Jul 01 04:29:57 PM PDT 24
Finished Jul 01 04:30:10 PM PDT 24
Peak memory 199580 kb
Host smart-6cd2fce9-837b-45bf-b99f-56fb97640f2a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401885203 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.hmac_csr_mem_rw_with_rand_reset.1401885203
Directory /workspace/9.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_rw.3017748908
Short name T575
Test name
Test status
Simulation time 22184221 ps
CPU time 0.77 seconds
Started Jul 01 04:29:57 PM PDT 24
Finished Jul 01 04:30:08 PM PDT 24
Peak memory 199324 kb
Host smart-514a7048-9e1d-4df9-95e2-b4cb1245caed
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017748908 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_rw.3017748908
Directory /workspace/9.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_intr_test.2836324510
Short name T538
Test name
Test status
Simulation time 93795071 ps
CPU time 0.57 seconds
Started Jul 01 04:29:50 PM PDT 24
Finished Jul 01 04:30:02 PM PDT 24
Peak memory 194408 kb
Host smart-f9fd3e94-1c74-4452-ac2c-93647a7e0827
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836324510 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_intr_test.2836324510
Directory /workspace/9.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.125479562
Short name T654
Test name
Test status
Simulation time 378425253 ps
CPU time 1.69 seconds
Started Jul 01 04:29:59 PM PDT 24
Finished Jul 01 04:30:13 PM PDT 24
Peak memory 199536 kb
Host smart-9fd84a3f-b23b-4999-b33a-4c2f7a8d7319
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125479562 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_same_csr_
outstanding.125479562
Directory /workspace/9.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_errors.774991984
Short name T626
Test name
Test status
Simulation time 227669384 ps
CPU time 2.12 seconds
Started Jul 01 04:30:05 PM PDT 24
Finished Jul 01 04:30:22 PM PDT 24
Peak memory 199360 kb
Host smart-1536469d-bb6e-40f6-b50d-d5eea13e8fc4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774991984 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_errors.774991984
Directory /workspace/9.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.633529961
Short name T107
Test name
Test status
Simulation time 152652761 ps
CPU time 2.84 seconds
Started Jul 01 04:30:05 PM PDT 24
Finished Jul 01 04:30:22 PM PDT 24
Peak memory 199708 kb
Host smart-fef4dee0-1287-42cc-9b3b-bf6615c2bec0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633529961 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_intg_err.633529961
Directory /workspace/9.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.hmac_alert_test.1603341745
Short name T180
Test name
Test status
Simulation time 14175300 ps
CPU time 0.65 seconds
Started Jul 01 04:42:26 PM PDT 24
Finished Jul 01 04:42:42 PM PDT 24
Peak memory 196256 kb
Host smart-afc7fed0-7cfc-47dd-aaa0-d22bbe3ae5a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603341745 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_alert_test.1603341745
Directory /workspace/0.hmac_alert_test/latest

Test location /workspace/coverage/default/0.hmac_back_pressure.3922371532
Short name T427
Test name
Test status
Simulation time 1665187291 ps
CPU time 95.32 seconds
Started Jul 01 04:42:26 PM PDT 24
Finished Jul 01 04:44:17 PM PDT 24
Peak memory 200300 kb
Host smart-724a6eb6-99f5-4188-bfcb-31e723569a3f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3922371532 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_back_pressure.3922371532
Directory /workspace/0.hmac_back_pressure/latest

Test location /workspace/coverage/default/0.hmac_burst_wr.1699039131
Short name T199
Test name
Test status
Simulation time 1310346426 ps
CPU time 34 seconds
Started Jul 01 04:42:25 PM PDT 24
Finished Jul 01 04:43:14 PM PDT 24
Peak memory 200268 kb
Host smart-a2ad63b7-4922-429c-b418-129b0ca9d5f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699039131 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_burst_wr.1699039131
Directory /workspace/0.hmac_burst_wr/latest

Test location /workspace/coverage/default/0.hmac_datapath_stress.44262639
Short name T7
Test name
Test status
Simulation time 4986913092 ps
CPU time 875.55 seconds
Started Jul 01 04:42:24 PM PDT 24
Finished Jul 01 04:57:10 PM PDT 24
Peak memory 743680 kb
Host smart-09be96ba-ea30-4618-b658-cd08f49d2c81
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=44262639 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_datapath_stress.44262639
Directory /workspace/0.hmac_datapath_stress/latest

Test location /workspace/coverage/default/0.hmac_error.2871292925
Short name T425
Test name
Test status
Simulation time 23602010796 ps
CPU time 208.88 seconds
Started Jul 01 04:42:25 PM PDT 24
Finished Jul 01 04:46:09 PM PDT 24
Peak memory 200396 kb
Host smart-0e3c7225-ecfa-417e-867c-552f4840bcc9
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871292925 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_error.2871292925
Directory /workspace/0.hmac_error/latest

Test location /workspace/coverage/default/0.hmac_long_msg.1838761308
Short name T393
Test name
Test status
Simulation time 6737304161 ps
CPU time 97.6 seconds
Started Jul 01 04:42:28 PM PDT 24
Finished Jul 01 04:44:24 PM PDT 24
Peak memory 200440 kb
Host smart-d9e5f9ea-6128-48eb-a253-e348f3168738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838761308 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_long_msg.1838761308
Directory /workspace/0.hmac_long_msg/latest

Test location /workspace/coverage/default/0.hmac_sec_cm.4228150519
Short name T52
Test name
Test status
Simulation time 83785002 ps
CPU time 1 seconds
Started Jul 01 04:42:24 PM PDT 24
Finished Jul 01 04:42:36 PM PDT 24
Peak memory 219748 kb
Host smart-3fc63508-675a-4a2a-ad88-a67e58937797
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228150519 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_sec_cm.4228150519
Directory /workspace/0.hmac_sec_cm/latest

Test location /workspace/coverage/default/0.hmac_smoke.2560816725
Short name T340
Test name
Test status
Simulation time 342196083 ps
CPU time 7.56 seconds
Started Jul 01 04:42:25 PM PDT 24
Finished Jul 01 04:42:45 PM PDT 24
Peak memory 200308 kb
Host smart-4240c653-44ea-4977-bea2-729eeffea5f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560816725 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_smoke.2560816725
Directory /workspace/0.hmac_smoke/latest

Test location /workspace/coverage/default/0.hmac_stress_all_with_rand_reset.1341239960
Short name T14
Test name
Test status
Simulation time 801130613883 ps
CPU time 6558.9 seconds
Started Jul 01 04:42:28 PM PDT 24
Finished Jul 01 06:32:06 PM PDT 24
Peak memory 824872 kb
Host smart-06ca2a9e-9ee9-436c-8b66-e4a5b98670fa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1341239960 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all_with_rand_reset.1341239960
Directory /workspace/0.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.hmac_test_hmac256_vectors.88538541
Short name T426
Test name
Test status
Simulation time 3221932053 ps
CPU time 61.58 seconds
Started Jul 01 04:42:29 PM PDT 24
Finished Jul 01 04:43:49 PM PDT 24
Peak memory 200392 kb
Host smart-78445dcf-6b5d-45df-b0fb-d2e78b83e23e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=88538541 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac256_vectors.88538541
Directory /workspace/0.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_hmac384_vectors.369082056
Short name T296
Test name
Test status
Simulation time 2426440812 ps
CPU time 94.72 seconds
Started Jul 01 04:42:29 PM PDT 24
Finished Jul 01 04:44:22 PM PDT 24
Peak memory 200400 kb
Host smart-3dbb9a0a-fd3d-4379-ad87-fdfe118ff248
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=369082056 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac384_vectors.369082056
Directory /workspace/0.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_hmac512_vectors.2775673884
Short name T449
Test name
Test status
Simulation time 12059036706 ps
CPU time 68.65 seconds
Started Jul 01 04:42:29 PM PDT 24
Finished Jul 01 04:43:56 PM PDT 24
Peak memory 200468 kb
Host smart-6ce4fee0-9491-451b-b5a0-c4bb764a97c7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2775673884 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac512_vectors.2775673884
Directory /workspace/0.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha256_vectors.3650477574
Short name T281
Test name
Test status
Simulation time 10272092129 ps
CPU time 587.12 seconds
Started Jul 01 04:42:25 PM PDT 24
Finished Jul 01 04:52:24 PM PDT 24
Peak memory 200456 kb
Host smart-f6ae8fa1-883f-4767-9fb0-50ad5b718b7e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3650477574 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha256_vectors.3650477574
Directory /workspace/0.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha384_vectors.1472790490
Short name T48
Test name
Test status
Simulation time 160171522985 ps
CPU time 2226.54 seconds
Started Jul 01 04:42:25 PM PDT 24
Finished Jul 01 05:19:47 PM PDT 24
Peak memory 216336 kb
Host smart-9db01ba1-0333-47b9-a4d9-4e4d32dfdc1c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1472790490 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha384_vectors.1472790490
Directory /workspace/0.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha512_vectors.2548842525
Short name T182
Test name
Test status
Simulation time 159720792660 ps
CPU time 2112.49 seconds
Started Jul 01 04:42:27 PM PDT 24
Finished Jul 01 05:17:56 PM PDT 24
Peak memory 215980 kb
Host smart-c9281da1-a831-46dd-b050-04b5c2420131
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_200_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2548842525 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha512_vectors.2548842525
Directory /workspace/0.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/0.hmac_wipe_secret.569718639
Short name T424
Test name
Test status
Simulation time 19338989367 ps
CPU time 124.41 seconds
Started Jul 01 04:42:28 PM PDT 24
Finished Jul 01 04:44:51 PM PDT 24
Peak memory 200468 kb
Host smart-05a5b0f5-2bd0-4c0b-b926-4c62c4be621d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=569718639 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_wipe_secret.569718639
Directory /workspace/0.hmac_wipe_secret/latest

Test location /workspace/coverage/default/1.hmac_alert_test.3330676937
Short name T430
Test name
Test status
Simulation time 17830343 ps
CPU time 0.69 seconds
Started Jul 01 04:42:28 PM PDT 24
Finished Jul 01 04:42:47 PM PDT 24
Peak memory 195212 kb
Host smart-19f38fa9-cac3-431c-96ae-972bd3321eeb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330676937 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_alert_test.3330676937
Directory /workspace/1.hmac_alert_test/latest

Test location /workspace/coverage/default/1.hmac_back_pressure.1019462589
Short name T288
Test name
Test status
Simulation time 3261735816 ps
CPU time 93.26 seconds
Started Jul 01 04:42:27 PM PDT 24
Finished Jul 01 04:44:17 PM PDT 24
Peak memory 200308 kb
Host smart-d9f67adf-ba1a-4bd5-b8ee-41e4dbe123d5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1019462589 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_back_pressure.1019462589
Directory /workspace/1.hmac_back_pressure/latest

Test location /workspace/coverage/default/1.hmac_burst_wr.3806339121
Short name T492
Test name
Test status
Simulation time 6782741981 ps
CPU time 45.82 seconds
Started Jul 01 04:42:26 PM PDT 24
Finished Jul 01 04:43:26 PM PDT 24
Peak memory 200432 kb
Host smart-a70a8266-c5cb-4f6a-9b51-580274e3f269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806339121 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_burst_wr.3806339121
Directory /workspace/1.hmac_burst_wr/latest

Test location /workspace/coverage/default/1.hmac_datapath_stress.4035603666
Short name T311
Test name
Test status
Simulation time 1147193783 ps
CPU time 116.89 seconds
Started Jul 01 04:42:26 PM PDT 24
Finished Jul 01 04:44:39 PM PDT 24
Peak memory 593344 kb
Host smart-f700a53d-50e5-4ea1-9598-272d64b2f9b2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4035603666 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_datapath_stress.4035603666
Directory /workspace/1.hmac_datapath_stress/latest

Test location /workspace/coverage/default/1.hmac_error.1337948501
Short name T226
Test name
Test status
Simulation time 16737056977 ps
CPU time 68.89 seconds
Started Jul 01 04:42:28 PM PDT 24
Finished Jul 01 04:43:55 PM PDT 24
Peak memory 200392 kb
Host smart-ea6130ec-80c5-4190-b423-2fbde5069eb7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337948501 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_error.1337948501
Directory /workspace/1.hmac_error/latest

Test location /workspace/coverage/default/1.hmac_long_msg.172716613
Short name T278
Test name
Test status
Simulation time 7317391695 ps
CPU time 133.79 seconds
Started Jul 01 04:42:29 PM PDT 24
Finished Jul 01 04:45:01 PM PDT 24
Peak memory 200496 kb
Host smart-b4ac6798-a4bc-4df8-b36f-153f588d7639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=172716613 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_long_msg.172716613
Directory /workspace/1.hmac_long_msg/latest

Test location /workspace/coverage/default/1.hmac_smoke.3297880101
Short name T529
Test name
Test status
Simulation time 303625915 ps
CPU time 12.83 seconds
Started Jul 01 04:42:30 PM PDT 24
Finished Jul 01 04:43:01 PM PDT 24
Peak memory 200404 kb
Host smart-693fb7ac-12cb-4972-99f7-515be123e8a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297880101 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_smoke.3297880101
Directory /workspace/1.hmac_smoke/latest

Test location /workspace/coverage/default/1.hmac_stress_all.1701964123
Short name T223
Test name
Test status
Simulation time 1674099258 ps
CPU time 52.62 seconds
Started Jul 01 04:42:25 PM PDT 24
Finished Jul 01 04:43:32 PM PDT 24
Peak memory 200504 kb
Host smart-7392420a-448c-48e1-ab8a-3a70abc16258
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701964123 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all.1701964123
Directory /workspace/1.hmac_stress_all/latest

Test location /workspace/coverage/default/1.hmac_test_hmac256_vectors.3490583132
Short name T489
Test name
Test status
Simulation time 4918639827 ps
CPU time 46.21 seconds
Started Jul 01 04:42:26 PM PDT 24
Finished Jul 01 04:43:28 PM PDT 24
Peak memory 200452 kb
Host smart-c84b3b68-7b9c-488f-84ff-1525218ff2c8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3490583132 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac256_vectors.3490583132
Directory /workspace/1.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_hmac384_vectors.3961064199
Short name T313
Test name
Test status
Simulation time 10875436445 ps
CPU time 91.63 seconds
Started Jul 01 04:42:33 PM PDT 24
Finished Jul 01 04:44:23 PM PDT 24
Peak memory 200416 kb
Host smart-cdf2f52f-8e08-4b68-9d2b-78b18beacc89
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3961064199 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac384_vectors.3961064199
Directory /workspace/1.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_hmac512_vectors.827190888
Short name T217
Test name
Test status
Simulation time 13649425229 ps
CPU time 111.37 seconds
Started Jul 01 04:42:33 PM PDT 24
Finished Jul 01 04:44:43 PM PDT 24
Peak memory 200416 kb
Host smart-339c6af9-3ca0-4ac6-9182-21de78434c54
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=827190888 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac512_vectors.827190888
Directory /workspace/1.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha256_vectors.2685500835
Short name T246
Test name
Test status
Simulation time 54168434469 ps
CPU time 650.66 seconds
Started Jul 01 04:42:26 PM PDT 24
Finished Jul 01 04:53:33 PM PDT 24
Peak memory 200404 kb
Host smart-fd3bd0eb-2ad6-4d2d-8bdb-c9028ab74c1c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2685500835 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha256_vectors.2685500835
Directory /workspace/1.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha384_vectors.1049834750
Short name T218
Test name
Test status
Simulation time 206278335980 ps
CPU time 2181.81 seconds
Started Jul 01 04:42:28 PM PDT 24
Finished Jul 01 05:19:08 PM PDT 24
Peak memory 216672 kb
Host smart-7abb8818-aa76-40e7-b914-ffd9f6ff6313
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1049834750 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha384_vectors.1049834750
Directory /workspace/1.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha512_vectors.2624026531
Short name T183
Test name
Test status
Simulation time 140811789653 ps
CPU time 2499.23 seconds
Started Jul 01 04:42:33 PM PDT 24
Finished Jul 01 05:24:31 PM PDT 24
Peak memory 216148 kb
Host smart-969a9271-8049-4a6c-b930-0fc5b107b164
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_200_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2624026531 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha512_vectors.2624026531
Directory /workspace/1.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/1.hmac_wipe_secret.3976097317
Short name T80
Test name
Test status
Simulation time 3876143387 ps
CPU time 83.57 seconds
Started Jul 01 04:42:33 PM PDT 24
Finished Jul 01 04:44:15 PM PDT 24
Peak memory 200412 kb
Host smart-5a8cc434-c0be-4130-aad2-265b03392ed6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976097317 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_wipe_secret.3976097317
Directory /workspace/1.hmac_wipe_secret/latest

Test location /workspace/coverage/default/10.hmac_alert_test.3213394168
Short name T447
Test name
Test status
Simulation time 42373655 ps
CPU time 0.62 seconds
Started Jul 01 04:42:40 PM PDT 24
Finished Jul 01 04:42:57 PM PDT 24
Peak memory 196228 kb
Host smart-7e8098af-66af-4d5b-a065-eda4dabe2819
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213394168 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_alert_test.3213394168
Directory /workspace/10.hmac_alert_test/latest

Test location /workspace/coverage/default/10.hmac_back_pressure.4131340706
Short name T344
Test name
Test status
Simulation time 4418102136 ps
CPU time 45.19 seconds
Started Jul 01 04:42:43 PM PDT 24
Finished Jul 01 04:43:43 PM PDT 24
Peak memory 200468 kb
Host smart-2f0d6c3d-9722-48dd-bc8f-8a83024f34f4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4131340706 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_back_pressure.4131340706
Directory /workspace/10.hmac_back_pressure/latest

Test location /workspace/coverage/default/10.hmac_datapath_stress.2178723744
Short name T156
Test name
Test status
Simulation time 14557960720 ps
CPU time 725.4 seconds
Started Jul 01 04:42:43 PM PDT 24
Finished Jul 01 04:55:03 PM PDT 24
Peak memory 669712 kb
Host smart-26be60c7-4443-4c67-abe1-4de4b61ae705
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2178723744 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_datapath_stress.2178723744
Directory /workspace/10.hmac_datapath_stress/latest

Test location /workspace/coverage/default/10.hmac_error.20204543
Short name T493
Test name
Test status
Simulation time 4005060347 ps
CPU time 54.7 seconds
Started Jul 01 04:42:47 PM PDT 24
Finished Jul 01 04:43:55 PM PDT 24
Peak memory 200392 kb
Host smart-b387f2ac-fc48-49e0-8aa9-ca7b8a7568d9
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20204543 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_error.20204543
Directory /workspace/10.hmac_error/latest

Test location /workspace/coverage/default/10.hmac_long_msg.323493261
Short name T165
Test name
Test status
Simulation time 1606407269 ps
CPU time 81.92 seconds
Started Jul 01 04:42:44 PM PDT 24
Finished Jul 01 04:44:20 PM PDT 24
Peak memory 200372 kb
Host smart-d8a5e450-edf0-44d9-8044-c1af54393d27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323493261 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_long_msg.323493261
Directory /workspace/10.hmac_long_msg/latest

Test location /workspace/coverage/default/10.hmac_smoke.540267355
Short name T525
Test name
Test status
Simulation time 4625366501 ps
CPU time 13.79 seconds
Started Jul 01 04:42:43 PM PDT 24
Finished Jul 01 04:43:12 PM PDT 24
Peak memory 200520 kb
Host smart-05c5df1e-20e0-4740-abc8-63c12097232a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540267355 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_smoke.540267355
Directory /workspace/10.hmac_smoke/latest

Test location /workspace/coverage/default/10.hmac_stress_all.3420176925
Short name T78
Test name
Test status
Simulation time 1841708910 ps
CPU time 19.88 seconds
Started Jul 01 04:42:40 PM PDT 24
Finished Jul 01 04:43:16 PM PDT 24
Peak memory 200224 kb
Host smart-c3bb3ba7-25d9-41e1-909f-97f2a15cea86
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420176925 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.hmac_stress_all.3420176925
Directory /workspace/10.hmac_stress_all/latest

Test location /workspace/coverage/default/10.hmac_wipe_secret.3186423959
Short name T153
Test name
Test status
Simulation time 503044113 ps
CPU time 3.07 seconds
Started Jul 01 04:42:47 PM PDT 24
Finished Jul 01 04:43:04 PM PDT 24
Peak memory 200116 kb
Host smart-e78cdc56-c9ff-47e4-9d95-697450db86ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186423959 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_wipe_secret.3186423959
Directory /workspace/10.hmac_wipe_secret/latest

Test location /workspace/coverage/default/11.hmac_alert_test.563009431
Short name T483
Test name
Test status
Simulation time 10311409 ps
CPU time 0.55 seconds
Started Jul 01 04:42:47 PM PDT 24
Finished Jul 01 04:43:01 PM PDT 24
Peak memory 195136 kb
Host smart-11226e33-db07-49f3-81fa-457c2d71906b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563009431 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_alert_test.563009431
Directory /workspace/11.hmac_alert_test/latest

Test location /workspace/coverage/default/11.hmac_back_pressure.1912320340
Short name T124
Test name
Test status
Simulation time 278152588 ps
CPU time 15.53 seconds
Started Jul 01 04:42:44 PM PDT 24
Finished Jul 01 04:43:14 PM PDT 24
Peak memory 200288 kb
Host smart-b881e235-33ff-4e3a-8bc9-e4035b7d11d1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1912320340 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_back_pressure.1912320340
Directory /workspace/11.hmac_back_pressure/latest

Test location /workspace/coverage/default/11.hmac_burst_wr.1796024588
Short name T117
Test name
Test status
Simulation time 2443737110 ps
CPU time 43.58 seconds
Started Jul 01 04:42:43 PM PDT 24
Finished Jul 01 04:43:42 PM PDT 24
Peak memory 200416 kb
Host smart-0de5751a-1549-47a6-a0fe-03e96873dffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796024588 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_burst_wr.1796024588
Directory /workspace/11.hmac_burst_wr/latest

Test location /workspace/coverage/default/11.hmac_datapath_stress.1077261761
Short name T215
Test name
Test status
Simulation time 2860795865 ps
CPU time 239.08 seconds
Started Jul 01 04:42:50 PM PDT 24
Finished Jul 01 04:47:04 PM PDT 24
Peak memory 611844 kb
Host smart-5285ccea-0fda-4522-a077-032829fea48f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1077261761 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_datapath_stress.1077261761
Directory /workspace/11.hmac_datapath_stress/latest

Test location /workspace/coverage/default/11.hmac_error.3387929749
Short name T282
Test name
Test status
Simulation time 1368998751 ps
CPU time 73.76 seconds
Started Jul 01 04:42:49 PM PDT 24
Finished Jul 01 04:44:17 PM PDT 24
Peak memory 200288 kb
Host smart-c67eaf2a-7f78-4d71-82f9-f71a2a154686
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387929749 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_error.3387929749
Directory /workspace/11.hmac_error/latest

Test location /workspace/coverage/default/11.hmac_long_msg.1844384243
Short name T516
Test name
Test status
Simulation time 50420126007 ps
CPU time 162.13 seconds
Started Jul 01 04:42:45 PM PDT 24
Finished Jul 01 04:45:42 PM PDT 24
Peak memory 200432 kb
Host smart-02453122-a0aa-482b-96a8-59d5ef9f9db2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844384243 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_long_msg.1844384243
Directory /workspace/11.hmac_long_msg/latest

Test location /workspace/coverage/default/11.hmac_smoke.2798368048
Short name T138
Test name
Test status
Simulation time 289921372 ps
CPU time 13.59 seconds
Started Jul 01 04:42:48 PM PDT 24
Finished Jul 01 04:43:16 PM PDT 24
Peak memory 200344 kb
Host smart-1cad2fdf-cfa9-48ad-bac1-23917307f4b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2798368048 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_smoke.2798368048
Directory /workspace/11.hmac_smoke/latest

Test location /workspace/coverage/default/11.hmac_stress_all.4122514313
Short name T185
Test name
Test status
Simulation time 23912999363 ps
CPU time 68.66 seconds
Started Jul 01 04:42:42 PM PDT 24
Finished Jul 01 04:44:06 PM PDT 24
Peak memory 208636 kb
Host smart-e30c9528-b27c-41de-bfda-18bafd0dd9e3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122514313 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.hmac_stress_all.4122514313
Directory /workspace/11.hmac_stress_all/latest

Test location /workspace/coverage/default/11.hmac_wipe_secret.2759771501
Short name T161
Test name
Test status
Simulation time 1236058725 ps
CPU time 63.86 seconds
Started Jul 01 04:42:49 PM PDT 24
Finished Jul 01 04:44:08 PM PDT 24
Peak memory 200308 kb
Host smart-bb55c379-8eeb-46a1-9838-45fce60d94d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759771501 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_wipe_secret.2759771501
Directory /workspace/11.hmac_wipe_secret/latest

Test location /workspace/coverage/default/12.hmac_back_pressure.4152281804
Short name T6
Test name
Test status
Simulation time 4779689453 ps
CPU time 79.91 seconds
Started Jul 01 04:42:48 PM PDT 24
Finished Jul 01 04:44:23 PM PDT 24
Peak memory 200500 kb
Host smart-65f57bde-143c-4870-98a5-d8f0f8d2b9cf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4152281804 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_back_pressure.4152281804
Directory /workspace/12.hmac_back_pressure/latest

Test location /workspace/coverage/default/12.hmac_burst_wr.3575989762
Short name T225
Test name
Test status
Simulation time 2649470857 ps
CPU time 11.96 seconds
Started Jul 01 04:42:49 PM PDT 24
Finished Jul 01 04:43:16 PM PDT 24
Peak memory 200344 kb
Host smart-6b64b7ae-d086-4153-9d09-44e3549b47b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575989762 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_burst_wr.3575989762
Directory /workspace/12.hmac_burst_wr/latest

Test location /workspace/coverage/default/12.hmac_datapath_stress.1503969257
Short name T332
Test name
Test status
Simulation time 3158935283 ps
CPU time 577.15 seconds
Started Jul 01 04:42:47 PM PDT 24
Finished Jul 01 04:52:38 PM PDT 24
Peak memory 696876 kb
Host smart-b0da45b9-62ef-4569-b9e8-a3851305d6a3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1503969257 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_datapath_stress.1503969257
Directory /workspace/12.hmac_datapath_stress/latest

Test location /workspace/coverage/default/12.hmac_error.1016880935
Short name T379
Test name
Test status
Simulation time 4952416157 ps
CPU time 44.51 seconds
Started Jul 01 04:42:48 PM PDT 24
Finished Jul 01 04:43:46 PM PDT 24
Peak memory 200412 kb
Host smart-f00e3aab-d2ff-495e-98ac-87a7dc915a28
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016880935 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_error.1016880935
Directory /workspace/12.hmac_error/latest

Test location /workspace/coverage/default/12.hmac_long_msg.361575657
Short name T343
Test name
Test status
Simulation time 8515833589 ps
CPU time 150.96 seconds
Started Jul 01 04:42:50 PM PDT 24
Finished Jul 01 04:45:35 PM PDT 24
Peak memory 216712 kb
Host smart-0a14a4b3-c59b-47ba-ab72-575849ac2c6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361575657 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_long_msg.361575657
Directory /workspace/12.hmac_long_msg/latest

Test location /workspace/coverage/default/12.hmac_smoke.2930838012
Short name T294
Test name
Test status
Simulation time 1163587695 ps
CPU time 13.1 seconds
Started Jul 01 04:42:47 PM PDT 24
Finished Jul 01 04:43:14 PM PDT 24
Peak memory 200296 kb
Host smart-a106adc5-761c-4894-af54-8b6c4531e9de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930838012 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_smoke.2930838012
Directory /workspace/12.hmac_smoke/latest

Test location /workspace/coverage/default/12.hmac_stress_all.141185220
Short name T64
Test name
Test status
Simulation time 58487744851 ps
CPU time 696.67 seconds
Started Jul 01 04:42:49 PM PDT 24
Finished Jul 01 04:54:40 PM PDT 24
Peak memory 208536 kb
Host smart-1db38ee6-c292-462c-86b6-e38d20823f7b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141185220 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 12.hmac_stress_all.141185220
Directory /workspace/12.hmac_stress_all/latest

Test location /workspace/coverage/default/12.hmac_wipe_secret.2332231579
Short name T318
Test name
Test status
Simulation time 9500943742 ps
CPU time 122.25 seconds
Started Jul 01 04:42:48 PM PDT 24
Finished Jul 01 04:45:04 PM PDT 24
Peak memory 200628 kb
Host smart-46341325-a366-4aa9-b132-cff6d6ae345e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332231579 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_wipe_secret.2332231579
Directory /workspace/12.hmac_wipe_secret/latest

Test location /workspace/coverage/default/13.hmac_alert_test.2604880688
Short name T232
Test name
Test status
Simulation time 41454537 ps
CPU time 0.62 seconds
Started Jul 01 04:42:48 PM PDT 24
Finished Jul 01 04:43:03 PM PDT 24
Peak memory 197096 kb
Host smart-af512040-5b0e-44ff-9f58-a6c0d1cd68dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604880688 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_alert_test.2604880688
Directory /workspace/13.hmac_alert_test/latest

Test location /workspace/coverage/default/13.hmac_back_pressure.292951128
Short name T488
Test name
Test status
Simulation time 1275742287 ps
CPU time 34.37 seconds
Started Jul 01 04:42:47 PM PDT 24
Finished Jul 01 04:43:36 PM PDT 24
Peak memory 200356 kb
Host smart-4b63cba9-b669-44b2-a88d-880d9e03049a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=292951128 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_back_pressure.292951128
Directory /workspace/13.hmac_back_pressure/latest

Test location /workspace/coverage/default/13.hmac_burst_wr.1184900709
Short name T519
Test name
Test status
Simulation time 437026188 ps
CPU time 7.03 seconds
Started Jul 01 04:42:51 PM PDT 24
Finished Jul 01 04:43:12 PM PDT 24
Peak memory 200288 kb
Host smart-91b4ba66-684f-4cac-8f20-9edea81ced62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184900709 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_burst_wr.1184900709
Directory /workspace/13.hmac_burst_wr/latest

Test location /workspace/coverage/default/13.hmac_datapath_stress.1615404866
Short name T71
Test name
Test status
Simulation time 4095914910 ps
CPU time 644.21 seconds
Started Jul 01 04:42:49 PM PDT 24
Finished Jul 01 04:53:49 PM PDT 24
Peak memory 683780 kb
Host smart-935352ee-cfd6-4f3a-96e9-a7ed2bbc1fae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1615404866 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_datapath_stress.1615404866
Directory /workspace/13.hmac_datapath_stress/latest

Test location /workspace/coverage/default/13.hmac_error.3068513589
Short name T351
Test name
Test status
Simulation time 27717659577 ps
CPU time 93.01 seconds
Started Jul 01 04:42:48 PM PDT 24
Finished Jul 01 04:44:35 PM PDT 24
Peak memory 200328 kb
Host smart-3538ea95-0901-432e-b9f4-483112ba8ecc
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068513589 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_error.3068513589
Directory /workspace/13.hmac_error/latest

Test location /workspace/coverage/default/13.hmac_long_msg.1475010314
Short name T261
Test name
Test status
Simulation time 30500832244 ps
CPU time 96.49 seconds
Started Jul 01 04:42:50 PM PDT 24
Finished Jul 01 04:44:41 PM PDT 24
Peak memory 200432 kb
Host smart-645aafa2-ea68-4c29-90f2-64236a041a14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475010314 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_long_msg.1475010314
Directory /workspace/13.hmac_long_msg/latest

Test location /workspace/coverage/default/13.hmac_smoke.1203490914
Short name T460
Test name
Test status
Simulation time 462489285 ps
CPU time 10.94 seconds
Started Jul 01 04:42:47 PM PDT 24
Finished Jul 01 04:43:12 PM PDT 24
Peak memory 200320 kb
Host smart-d5170aa3-ea00-47b9-a105-a7d13cdc6f07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203490914 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_smoke.1203490914
Directory /workspace/13.hmac_smoke/latest

Test location /workspace/coverage/default/13.hmac_wipe_secret.3506919615
Short name T129
Test name
Test status
Simulation time 16799368873 ps
CPU time 54.91 seconds
Started Jul 01 04:42:48 PM PDT 24
Finished Jul 01 04:43:58 PM PDT 24
Peak memory 200408 kb
Host smart-d7ae9789-5f79-427b-bef0-54465a87bd2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506919615 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_wipe_secret.3506919615
Directory /workspace/13.hmac_wipe_secret/latest

Test location /workspace/coverage/default/14.hmac_alert_test.3291624861
Short name T511
Test name
Test status
Simulation time 23224644 ps
CPU time 0.62 seconds
Started Jul 01 04:42:48 PM PDT 24
Finished Jul 01 04:43:03 PM PDT 24
Peak memory 196944 kb
Host smart-597c6f97-f9ee-4139-8512-5cf24c347dbf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291624861 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_alert_test.3291624861
Directory /workspace/14.hmac_alert_test/latest

Test location /workspace/coverage/default/14.hmac_back_pressure.2660136214
Short name T320
Test name
Test status
Simulation time 8827628153 ps
CPU time 32.66 seconds
Started Jul 01 04:42:48 PM PDT 24
Finished Jul 01 04:43:36 PM PDT 24
Peak memory 208668 kb
Host smart-7c6603bd-1406-4bfc-ba32-27babb8b9931
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2660136214 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_back_pressure.2660136214
Directory /workspace/14.hmac_back_pressure/latest

Test location /workspace/coverage/default/14.hmac_burst_wr.4232201961
Short name T274
Test name
Test status
Simulation time 5553773476 ps
CPU time 34.51 seconds
Started Jul 01 04:42:50 PM PDT 24
Finished Jul 01 04:43:39 PM PDT 24
Peak memory 200460 kb
Host smart-074423e4-3e3d-4a21-8b27-94aef5b9c954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232201961 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_burst_wr.4232201961
Directory /workspace/14.hmac_burst_wr/latest

Test location /workspace/coverage/default/14.hmac_datapath_stress.810505967
Short name T252
Test name
Test status
Simulation time 4649219783 ps
CPU time 207.54 seconds
Started Jul 01 04:42:47 PM PDT 24
Finished Jul 01 04:46:29 PM PDT 24
Peak memory 642748 kb
Host smart-d652ce0d-77ab-4bb4-ac13-3faab8b6440f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=810505967 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_datapath_stress.810505967
Directory /workspace/14.hmac_datapath_stress/latest

Test location /workspace/coverage/default/14.hmac_error.3422347123
Short name T186
Test name
Test status
Simulation time 4864996311 ps
CPU time 15.53 seconds
Started Jul 01 04:42:50 PM PDT 24
Finished Jul 01 04:43:20 PM PDT 24
Peak memory 200412 kb
Host smart-00b8e92e-d92e-4af4-b86d-ebb28735a1c9
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422347123 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_error.3422347123
Directory /workspace/14.hmac_error/latest

Test location /workspace/coverage/default/14.hmac_long_msg.1439451497
Short name T132
Test name
Test status
Simulation time 11999250217 ps
CPU time 165.71 seconds
Started Jul 01 04:42:53 PM PDT 24
Finished Jul 01 04:45:51 PM PDT 24
Peak memory 200476 kb
Host smart-608745d6-185d-4423-a281-35b0363c3c4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1439451497 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_long_msg.1439451497
Directory /workspace/14.hmac_long_msg/latest

Test location /workspace/coverage/default/14.hmac_smoke.1600973174
Short name T499
Test name
Test status
Simulation time 435784358 ps
CPU time 8.02 seconds
Started Jul 01 04:42:49 PM PDT 24
Finished Jul 01 04:43:11 PM PDT 24
Peak memory 200268 kb
Host smart-ed291cae-0e47-4ef4-b212-7bd5b343e6fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600973174 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_smoke.1600973174
Directory /workspace/14.hmac_smoke/latest

Test location /workspace/coverage/default/14.hmac_stress_all.3648811994
Short name T404
Test name
Test status
Simulation time 33835742516 ps
CPU time 538.83 seconds
Started Jul 01 04:42:52 PM PDT 24
Finished Jul 01 04:52:04 PM PDT 24
Peak memory 420008 kb
Host smart-a136a8cc-d219-4e95-8567-ccb40886a225
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648811994 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.hmac_stress_all.3648811994
Directory /workspace/14.hmac_stress_all/latest

Test location /workspace/coverage/default/14.hmac_wipe_secret.3825541697
Short name T326
Test name
Test status
Simulation time 10622528199 ps
CPU time 10.17 seconds
Started Jul 01 04:42:48 PM PDT 24
Finished Jul 01 04:43:12 PM PDT 24
Peak memory 200364 kb
Host smart-77df6a08-c96f-4ebf-a308-33e9b0186eec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825541697 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_wipe_secret.3825541697
Directory /workspace/14.hmac_wipe_secret/latest

Test location /workspace/coverage/default/15.hmac_alert_test.1096819712
Short name T532
Test name
Test status
Simulation time 15546502 ps
CPU time 0.61 seconds
Started Jul 01 04:42:49 PM PDT 24
Finished Jul 01 04:43:04 PM PDT 24
Peak memory 196252 kb
Host smart-58dd97b1-cc75-4004-895f-cf5738a07030
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096819712 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_alert_test.1096819712
Directory /workspace/15.hmac_alert_test/latest

Test location /workspace/coverage/default/15.hmac_back_pressure.112643405
Short name T234
Test name
Test status
Simulation time 2007825797 ps
CPU time 35.04 seconds
Started Jul 01 04:42:48 PM PDT 24
Finished Jul 01 04:43:37 PM PDT 24
Peak memory 200280 kb
Host smart-141c6e8f-f390-4310-9023-f7d43215462e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=112643405 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_back_pressure.112643405
Directory /workspace/15.hmac_back_pressure/latest

Test location /workspace/coverage/default/15.hmac_burst_wr.3602948165
Short name T324
Test name
Test status
Simulation time 3632981308 ps
CPU time 27.63 seconds
Started Jul 01 04:42:50 PM PDT 24
Finished Jul 01 04:43:33 PM PDT 24
Peak memory 200376 kb
Host smart-1496c620-52a6-4966-a60d-6e835dfe4308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602948165 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_burst_wr.3602948165
Directory /workspace/15.hmac_burst_wr/latest

Test location /workspace/coverage/default/15.hmac_datapath_stress.23294297
Short name T249
Test name
Test status
Simulation time 308564623 ps
CPU time 44.72 seconds
Started Jul 01 04:42:55 PM PDT 24
Finished Jul 01 04:43:51 PM PDT 24
Peak memory 320168 kb
Host smart-aae90a6e-863c-4d34-a6c3-95334b48471b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=23294297 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_datapath_stress.23294297
Directory /workspace/15.hmac_datapath_stress/latest

Test location /workspace/coverage/default/15.hmac_error.3454531947
Short name T465
Test name
Test status
Simulation time 3783420123 ps
CPU time 74.29 seconds
Started Jul 01 04:42:49 PM PDT 24
Finished Jul 01 04:44:17 PM PDT 24
Peak memory 200356 kb
Host smart-103ffb98-32f9-47e7-ab0f-3ab8a79db90d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454531947 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_error.3454531947
Directory /workspace/15.hmac_error/latest

Test location /workspace/coverage/default/15.hmac_smoke.1190702278
Short name T164
Test name
Test status
Simulation time 607221078 ps
CPU time 3.14 seconds
Started Jul 01 04:42:49 PM PDT 24
Finished Jul 01 04:43:06 PM PDT 24
Peak memory 200500 kb
Host smart-f59fc526-4c70-427d-8c6e-0bf4de727e56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190702278 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_smoke.1190702278
Directory /workspace/15.hmac_smoke/latest

Test location /workspace/coverage/default/15.hmac_stress_all.2595730672
Short name T120
Test name
Test status
Simulation time 12611093593 ps
CPU time 936.57 seconds
Started Jul 01 04:42:50 PM PDT 24
Finished Jul 01 04:58:41 PM PDT 24
Peak memory 696004 kb
Host smart-0e929d9c-4d9d-4570-a481-26fc969d04c0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595730672 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.hmac_stress_all.2595730672
Directory /workspace/15.hmac_stress_all/latest

Test location /workspace/coverage/default/15.hmac_wipe_secret.862651800
Short name T470
Test name
Test status
Simulation time 9609829331 ps
CPU time 130.76 seconds
Started Jul 01 04:42:50 PM PDT 24
Finished Jul 01 04:45:15 PM PDT 24
Peak memory 200428 kb
Host smart-0563b040-e61b-472f-a5cd-afe5e29ed88b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862651800 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_wipe_secret.862651800
Directory /workspace/15.hmac_wipe_secret/latest

Test location /workspace/coverage/default/16.hmac_alert_test.587991403
Short name T309
Test name
Test status
Simulation time 18144805 ps
CPU time 0.61 seconds
Started Jul 01 04:42:56 PM PDT 24
Finished Jul 01 04:43:07 PM PDT 24
Peak memory 196224 kb
Host smart-c2cdf67a-d205-4aa2-b70c-053727243585
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587991403 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_alert_test.587991403
Directory /workspace/16.hmac_alert_test/latest

Test location /workspace/coverage/default/16.hmac_back_pressure.1032152681
Short name T471
Test name
Test status
Simulation time 5816579344 ps
CPU time 41.71 seconds
Started Jul 01 04:42:49 PM PDT 24
Finished Jul 01 04:43:45 PM PDT 24
Peak memory 200412 kb
Host smart-777d781d-a6b9-4df7-a1c3-daeedb79daa6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1032152681 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_back_pressure.1032152681
Directory /workspace/16.hmac_back_pressure/latest

Test location /workspace/coverage/default/16.hmac_burst_wr.1859274768
Short name T118
Test name
Test status
Simulation time 419713463 ps
CPU time 11.79 seconds
Started Jul 01 04:42:49 PM PDT 24
Finished Jul 01 04:43:15 PM PDT 24
Peak memory 200420 kb
Host smart-3778bf0b-f38d-49b5-b3f7-f9b8e53bd97d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1859274768 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_burst_wr.1859274768
Directory /workspace/16.hmac_burst_wr/latest

Test location /workspace/coverage/default/16.hmac_datapath_stress.3859630216
Short name T195
Test name
Test status
Simulation time 7770390264 ps
CPU time 1763.68 seconds
Started Jul 01 04:42:50 PM PDT 24
Finished Jul 01 05:12:28 PM PDT 24
Peak memory 781436 kb
Host smart-2006dbd6-2190-4578-ba0c-298e2c5c9f0e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3859630216 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_datapath_stress.3859630216
Directory /workspace/16.hmac_datapath_stress/latest

Test location /workspace/coverage/default/16.hmac_error.426656554
Short name T40
Test name
Test status
Simulation time 3497669348 ps
CPU time 98.81 seconds
Started Jul 01 04:43:06 PM PDT 24
Finished Jul 01 04:44:52 PM PDT 24
Peak memory 200348 kb
Host smart-a77cee1c-3fea-4f20-9ac4-5e46334fd6d0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426656554 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_error.426656554
Directory /workspace/16.hmac_error/latest

Test location /workspace/coverage/default/16.hmac_long_msg.2642199724
Short name T126
Test name
Test status
Simulation time 2272827432 ps
CPU time 15.52 seconds
Started Jul 01 04:42:48 PM PDT 24
Finished Jul 01 04:43:17 PM PDT 24
Peak memory 200424 kb
Host smart-bde0bf38-e16c-4aa2-b296-0916dfb543e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2642199724 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_long_msg.2642199724
Directory /workspace/16.hmac_long_msg/latest

Test location /workspace/coverage/default/16.hmac_smoke.4084016211
Short name T60
Test name
Test status
Simulation time 283780202 ps
CPU time 12.51 seconds
Started Jul 01 04:42:48 PM PDT 24
Finished Jul 01 04:43:14 PM PDT 24
Peak memory 200340 kb
Host smart-39f53b71-3987-4de0-aa5a-c8fe656be4db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084016211 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_smoke.4084016211
Directory /workspace/16.hmac_smoke/latest

Test location /workspace/coverage/default/16.hmac_stress_all.523178391
Short name T190
Test name
Test status
Simulation time 231075594025 ps
CPU time 1183.27 seconds
Started Jul 01 04:42:58 PM PDT 24
Finished Jul 01 05:02:51 PM PDT 24
Peak memory 644536 kb
Host smart-0bc1da5c-170f-4884-8cca-25f9c1c89d1e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523178391 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 16.hmac_stress_all.523178391
Directory /workspace/16.hmac_stress_all/latest

Test location /workspace/coverage/default/16.hmac_wipe_secret.1385414871
Short name T374
Test name
Test status
Simulation time 6371658110 ps
CPU time 114.49 seconds
Started Jul 01 04:42:58 PM PDT 24
Finished Jul 01 04:45:02 PM PDT 24
Peak memory 200432 kb
Host smart-3c10ad2f-028f-4bbb-88df-a7e93810a4f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385414871 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_wipe_secret.1385414871
Directory /workspace/16.hmac_wipe_secret/latest

Test location /workspace/coverage/default/17.hmac_alert_test.2281540962
Short name T173
Test name
Test status
Simulation time 22899529 ps
CPU time 0.61 seconds
Started Jul 01 04:42:58 PM PDT 24
Finished Jul 01 04:43:09 PM PDT 24
Peak memory 196224 kb
Host smart-4c29bc2d-741a-4118-88f9-ec24033a3ed1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281540962 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_alert_test.2281540962
Directory /workspace/17.hmac_alert_test/latest

Test location /workspace/coverage/default/17.hmac_back_pressure.2463964876
Short name T458
Test name
Test status
Simulation time 1339461316 ps
CPU time 40.88 seconds
Started Jul 01 04:42:56 PM PDT 24
Finished Jul 01 04:43:48 PM PDT 24
Peak memory 200280 kb
Host smart-a6c74cfe-238a-4e61-ba41-6a39bc2bbaaf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2463964876 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_back_pressure.2463964876
Directory /workspace/17.hmac_back_pressure/latest

Test location /workspace/coverage/default/17.hmac_burst_wr.2467586839
Short name T388
Test name
Test status
Simulation time 18287366443 ps
CPU time 70.61 seconds
Started Jul 01 04:42:59 PM PDT 24
Finished Jul 01 04:44:19 PM PDT 24
Peak memory 216824 kb
Host smart-d308c58f-75d6-4cd4-bdcb-5f67187a95e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467586839 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_burst_wr.2467586839
Directory /workspace/17.hmac_burst_wr/latest

Test location /workspace/coverage/default/17.hmac_datapath_stress.1860626937
Short name T473
Test name
Test status
Simulation time 13296495969 ps
CPU time 616.76 seconds
Started Jul 01 04:42:57 PM PDT 24
Finished Jul 01 04:53:24 PM PDT 24
Peak memory 715844 kb
Host smart-2299e2dd-38f7-4bea-95eb-803a32edb003
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1860626937 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_datapath_stress.1860626937
Directory /workspace/17.hmac_datapath_stress/latest

Test location /workspace/coverage/default/17.hmac_error.1315458809
Short name T505
Test name
Test status
Simulation time 7729542764 ps
CPU time 34.2 seconds
Started Jul 01 04:43:02 PM PDT 24
Finished Jul 01 04:43:44 PM PDT 24
Peak memory 200288 kb
Host smart-8e6e0511-2d50-4c26-b8af-34059042384b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315458809 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_error.1315458809
Directory /workspace/17.hmac_error/latest

Test location /workspace/coverage/default/17.hmac_long_msg.1006068617
Short name T279
Test name
Test status
Simulation time 22131820915 ps
CPU time 99.5 seconds
Started Jul 01 04:42:57 PM PDT 24
Finished Jul 01 04:44:47 PM PDT 24
Peak memory 200484 kb
Host smart-c4fbfa94-0674-4e0d-bfe1-cc8122887ff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006068617 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_long_msg.1006068617
Directory /workspace/17.hmac_long_msg/latest

Test location /workspace/coverage/default/17.hmac_smoke.3387925940
Short name T334
Test name
Test status
Simulation time 3037611771 ps
CPU time 3.45 seconds
Started Jul 01 04:43:04 PM PDT 24
Finished Jul 01 04:43:15 PM PDT 24
Peak memory 200416 kb
Host smart-b7131824-b748-4dc7-acb7-8eb274957009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387925940 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_smoke.3387925940
Directory /workspace/17.hmac_smoke/latest

Test location /workspace/coverage/default/17.hmac_stress_all.3994988248
Short name T496
Test name
Test status
Simulation time 10227448185 ps
CPU time 780.83 seconds
Started Jul 01 04:42:58 PM PDT 24
Finished Jul 01 04:56:09 PM PDT 24
Peak memory 612072 kb
Host smart-3b984e9a-0b01-47de-a4ed-c16fae155525
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994988248 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.hmac_stress_all.3994988248
Directory /workspace/17.hmac_stress_all/latest

Test location /workspace/coverage/default/17.hmac_wipe_secret.4157823373
Short name T336
Test name
Test status
Simulation time 3556119538 ps
CPU time 47.98 seconds
Started Jul 01 04:42:57 PM PDT 24
Finished Jul 01 04:43:55 PM PDT 24
Peak memory 200404 kb
Host smart-2bd676ba-fa75-43f1-9d2f-4c4f734d6b39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4157823373 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_wipe_secret.4157823373
Directory /workspace/17.hmac_wipe_secret/latest

Test location /workspace/coverage/default/18.hmac_alert_test.1728128898
Short name T159
Test name
Test status
Simulation time 59794073 ps
CPU time 0.61 seconds
Started Jul 01 04:42:56 PM PDT 24
Finished Jul 01 04:43:07 PM PDT 24
Peak memory 196228 kb
Host smart-76b72ecd-af77-4125-b820-c5a7577d93cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728128898 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_alert_test.1728128898
Directory /workspace/18.hmac_alert_test/latest

Test location /workspace/coverage/default/18.hmac_back_pressure.1970756230
Short name T264
Test name
Test status
Simulation time 1445132842 ps
CPU time 82.91 seconds
Started Jul 01 04:43:01 PM PDT 24
Finished Jul 01 04:44:32 PM PDT 24
Peak memory 200292 kb
Host smart-9cd93e02-e482-4c66-927e-268b82b21a5b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1970756230 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_back_pressure.1970756230
Directory /workspace/18.hmac_back_pressure/latest

Test location /workspace/coverage/default/18.hmac_burst_wr.1130853783
Short name T445
Test name
Test status
Simulation time 2730817904 ps
CPU time 49.42 seconds
Started Jul 01 04:42:58 PM PDT 24
Finished Jul 01 04:43:58 PM PDT 24
Peak memory 200404 kb
Host smart-495bf009-6c07-4fa6-a5d5-9a2aa0087aa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130853783 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_burst_wr.1130853783
Directory /workspace/18.hmac_burst_wr/latest

Test location /workspace/coverage/default/18.hmac_datapath_stress.1924748378
Short name T515
Test name
Test status
Simulation time 24672461962 ps
CPU time 704.87 seconds
Started Jul 01 04:43:00 PM PDT 24
Finished Jul 01 04:54:54 PM PDT 24
Peak memory 701004 kb
Host smart-22a62500-10c5-4e88-8410-26fa1078ee7c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1924748378 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_datapath_stress.1924748378
Directory /workspace/18.hmac_datapath_stress/latest

Test location /workspace/coverage/default/18.hmac_error.3332290052
Short name T491
Test name
Test status
Simulation time 50008979841 ps
CPU time 70.22 seconds
Started Jul 01 04:42:58 PM PDT 24
Finished Jul 01 04:44:18 PM PDT 24
Peak memory 200508 kb
Host smart-93e8c5c3-eea0-46d1-8ff0-a2553e28e744
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332290052 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_error.3332290052
Directory /workspace/18.hmac_error/latest

Test location /workspace/coverage/default/18.hmac_long_msg.3577064861
Short name T287
Test name
Test status
Simulation time 16890762818 ps
CPU time 118.01 seconds
Started Jul 01 04:42:58 PM PDT 24
Finished Jul 01 04:45:06 PM PDT 24
Peak memory 208620 kb
Host smart-db22940b-564a-498b-8ed5-e526f12ad272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577064861 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_long_msg.3577064861
Directory /workspace/18.hmac_long_msg/latest

Test location /workspace/coverage/default/18.hmac_smoke.2270984647
Short name T531
Test name
Test status
Simulation time 534908913 ps
CPU time 6.83 seconds
Started Jul 01 04:42:58 PM PDT 24
Finished Jul 01 04:43:15 PM PDT 24
Peak memory 200312 kb
Host smart-514dd328-48d5-4493-bd8c-f8fc525a871e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270984647 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_smoke.2270984647
Directory /workspace/18.hmac_smoke/latest

Test location /workspace/coverage/default/18.hmac_stress_all.265794485
Short name T310
Test name
Test status
Simulation time 1287082494 ps
CPU time 6.18 seconds
Started Jul 01 04:42:58 PM PDT 24
Finished Jul 01 04:43:15 PM PDT 24
Peak memory 200364 kb
Host smart-0b08e85a-b459-4598-8af7-701e50b2cd3b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265794485 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 18.hmac_stress_all.265794485
Directory /workspace/18.hmac_stress_all/latest

Test location /workspace/coverage/default/18.hmac_wipe_secret.2598399666
Short name T371
Test name
Test status
Simulation time 1865113222 ps
CPU time 27.46 seconds
Started Jul 01 04:42:57 PM PDT 24
Finished Jul 01 04:43:35 PM PDT 24
Peak memory 200548 kb
Host smart-dacd34d6-53dc-4d1c-9dd7-0e104f3630b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598399666 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_wipe_secret.2598399666
Directory /workspace/18.hmac_wipe_secret/latest

Test location /workspace/coverage/default/19.hmac_alert_test.3878236117
Short name T512
Test name
Test status
Simulation time 54706556 ps
CPU time 0.67 seconds
Started Jul 01 04:42:58 PM PDT 24
Finished Jul 01 04:43:09 PM PDT 24
Peak memory 196932 kb
Host smart-caa43bcf-f733-4f0a-93d9-9266dcaf309a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878236117 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_alert_test.3878236117
Directory /workspace/19.hmac_alert_test/latest

Test location /workspace/coverage/default/19.hmac_back_pressure.2037135448
Short name T403
Test name
Test status
Simulation time 574197840 ps
CPU time 33.04 seconds
Started Jul 01 04:42:57 PM PDT 24
Finished Jul 01 04:43:40 PM PDT 24
Peak memory 200280 kb
Host smart-377a017d-1fdf-4188-8814-f8eaac6d5657
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2037135448 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_back_pressure.2037135448
Directory /workspace/19.hmac_back_pressure/latest

Test location /workspace/coverage/default/19.hmac_burst_wr.1341757510
Short name T526
Test name
Test status
Simulation time 14672546363 ps
CPU time 32.73 seconds
Started Jul 01 04:43:05 PM PDT 24
Finished Jul 01 04:43:45 PM PDT 24
Peak memory 200428 kb
Host smart-7797103f-045c-4073-9bd0-7bae7bbdd97b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341757510 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_burst_wr.1341757510
Directory /workspace/19.hmac_burst_wr/latest

Test location /workspace/coverage/default/19.hmac_datapath_stress.4172550030
Short name T266
Test name
Test status
Simulation time 2475853902 ps
CPU time 215.63 seconds
Started Jul 01 04:42:56 PM PDT 24
Finished Jul 01 04:46:42 PM PDT 24
Peak memory 464900 kb
Host smart-d0b52f4e-d202-43ac-a597-5f452f21ef69
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4172550030 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_datapath_stress.4172550030
Directory /workspace/19.hmac_datapath_stress/latest

Test location /workspace/coverage/default/19.hmac_error.2283896111
Short name T155
Test name
Test status
Simulation time 948817116 ps
CPU time 13.02 seconds
Started Jul 01 04:42:59 PM PDT 24
Finished Jul 01 04:43:22 PM PDT 24
Peak memory 200236 kb
Host smart-a0a6afe9-1db2-4235-8d8d-05fbf18bed6d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283896111 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_error.2283896111
Directory /workspace/19.hmac_error/latest

Test location /workspace/coverage/default/19.hmac_long_msg.1109925383
Short name T443
Test name
Test status
Simulation time 16709799149 ps
CPU time 55.96 seconds
Started Jul 01 04:42:58 PM PDT 24
Finished Jul 01 04:44:04 PM PDT 24
Peak memory 200444 kb
Host smart-f458869d-5908-457f-be2b-0d9ce57ffcf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109925383 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_long_msg.1109925383
Directory /workspace/19.hmac_long_msg/latest

Test location /workspace/coverage/default/19.hmac_smoke.3117672880
Short name T23
Test name
Test status
Simulation time 371340578 ps
CPU time 10.23 seconds
Started Jul 01 04:42:56 PM PDT 24
Finished Jul 01 04:43:17 PM PDT 24
Peak memory 200348 kb
Host smart-4bf0727c-e925-4423-ad83-dfc611214250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3117672880 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_smoke.3117672880
Directory /workspace/19.hmac_smoke/latest

Test location /workspace/coverage/default/19.hmac_stress_all.3226351057
Short name T179
Test name
Test status
Simulation time 125288579471 ps
CPU time 1717.28 seconds
Started Jul 01 04:42:57 PM PDT 24
Finished Jul 01 05:11:44 PM PDT 24
Peak memory 753292 kb
Host smart-9e23b0d8-76d4-413b-b86c-b2f94ed0833c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226351057 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.hmac_stress_all.3226351057
Directory /workspace/19.hmac_stress_all/latest

Test location /workspace/coverage/default/19.hmac_wipe_secret.3948416854
Short name T414
Test name
Test status
Simulation time 2479288141 ps
CPU time 120.97 seconds
Started Jul 01 04:42:59 PM PDT 24
Finished Jul 01 04:45:10 PM PDT 24
Peak memory 200376 kb
Host smart-aaf84315-f5ed-4c3a-9509-8f7ae11de12d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3948416854 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_wipe_secret.3948416854
Directory /workspace/19.hmac_wipe_secret/latest

Test location /workspace/coverage/default/2.hmac_alert_test.1159022139
Short name T44
Test name
Test status
Simulation time 20166917 ps
CPU time 0.62 seconds
Started Jul 01 04:42:41 PM PDT 24
Finished Jul 01 04:42:57 PM PDT 24
Peak memory 195068 kb
Host smart-7bce268e-425c-48dd-a4bf-ea4e9aff6530
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159022139 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_alert_test.1159022139
Directory /workspace/2.hmac_alert_test/latest

Test location /workspace/coverage/default/2.hmac_back_pressure.1891214982
Short name T59
Test name
Test status
Simulation time 251718534 ps
CPU time 13.47 seconds
Started Jul 01 04:42:25 PM PDT 24
Finished Jul 01 04:42:51 PM PDT 24
Peak memory 200252 kb
Host smart-9d925795-9465-4bde-9e34-320183e7d06c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1891214982 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_back_pressure.1891214982
Directory /workspace/2.hmac_back_pressure/latest

Test location /workspace/coverage/default/2.hmac_burst_wr.29185878
Short name T221
Test name
Test status
Simulation time 13764150554 ps
CPU time 64.25 seconds
Started Jul 01 04:42:40 PM PDT 24
Finished Jul 01 04:44:01 PM PDT 24
Peak memory 200352 kb
Host smart-318e4e02-5800-473d-b007-2a10307d47ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29185878 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_burst_wr.29185878
Directory /workspace/2.hmac_burst_wr/latest

Test location /workspace/coverage/default/2.hmac_datapath_stress.2632208082
Short name T335
Test name
Test status
Simulation time 19343929882 ps
CPU time 150.07 seconds
Started Jul 01 04:42:25 PM PDT 24
Finished Jul 01 04:45:10 PM PDT 24
Peak memory 472956 kb
Host smart-4acce015-ec27-426f-9454-45267f7bab53
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2632208082 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_datapath_stress.2632208082
Directory /workspace/2.hmac_datapath_stress/latest

Test location /workspace/coverage/default/2.hmac_error.2870482142
Short name T79
Test name
Test status
Simulation time 36014450675 ps
CPU time 103.52 seconds
Started Jul 01 04:42:36 PM PDT 24
Finished Jul 01 04:44:37 PM PDT 24
Peak memory 200524 kb
Host smart-40cdc21d-f39c-4647-a5d5-185f3ec3436d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870482142 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_error.2870482142
Directory /workspace/2.hmac_error/latest

Test location /workspace/coverage/default/2.hmac_long_msg.3767422081
Short name T364
Test name
Test status
Simulation time 12730564882 ps
CPU time 123.31 seconds
Started Jul 01 04:42:28 PM PDT 24
Finished Jul 01 04:44:48 PM PDT 24
Peak memory 200456 kb
Host smart-0cea0b0e-15ce-4ef6-8bd7-a7d30d30977d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767422081 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_long_msg.3767422081
Directory /workspace/2.hmac_long_msg/latest

Test location /workspace/coverage/default/2.hmac_sec_cm.2714785983
Short name T53
Test name
Test status
Simulation time 72239891 ps
CPU time 0.86 seconds
Started Jul 01 04:42:34 PM PDT 24
Finished Jul 01 04:42:53 PM PDT 24
Peak memory 218728 kb
Host smart-05dbcb2c-dc43-474f-a3fa-41ada78f47ff
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714785983 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_sec_cm.2714785983
Directory /workspace/2.hmac_sec_cm/latest

Test location /workspace/coverage/default/2.hmac_smoke.1550456469
Short name T73
Test name
Test status
Simulation time 585259369 ps
CPU time 8.18 seconds
Started Jul 01 04:42:23 PM PDT 24
Finished Jul 01 04:42:41 PM PDT 24
Peak memory 200264 kb
Host smart-940c8ab3-a32a-4764-b945-b9dd00957e26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550456469 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_smoke.1550456469
Directory /workspace/2.hmac_smoke/latest

Test location /workspace/coverage/default/2.hmac_stress_all.2583301118
Short name T238
Test name
Test status
Simulation time 11546489089 ps
CPU time 1821.18 seconds
Started Jul 01 04:42:35 PM PDT 24
Finished Jul 01 05:13:14 PM PDT 24
Peak memory 779000 kb
Host smart-65f381bd-bef0-4e35-9795-7d3458426177
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583301118 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all.2583301118
Directory /workspace/2.hmac_stress_all/latest

Test location /workspace/coverage/default/2.hmac_test_hmac256_vectors.2693244437
Short name T74
Test name
Test status
Simulation time 1194500917 ps
CPU time 43.46 seconds
Started Jul 01 04:42:38 PM PDT 24
Finished Jul 01 04:43:39 PM PDT 24
Peak memory 200300 kb
Host smart-962431a0-628a-4dcd-8f1a-fe7dd142f2d5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2693244437 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac256_vectors.2693244437
Directory /workspace/2.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_hmac384_vectors.3830998585
Short name T235
Test name
Test status
Simulation time 53458417276 ps
CPU time 69.25 seconds
Started Jul 01 04:42:33 PM PDT 24
Finished Jul 01 04:44:01 PM PDT 24
Peak memory 200376 kb
Host smart-e26413fc-6b11-418a-b412-91820f365c8a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3830998585 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac384_vectors.3830998585
Directory /workspace/2.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_hmac512_vectors.4084598649
Short name T365
Test name
Test status
Simulation time 11103520755 ps
CPU time 128.82 seconds
Started Jul 01 04:42:33 PM PDT 24
Finished Jul 01 04:45:00 PM PDT 24
Peak memory 200548 kb
Host smart-f3fcf352-567d-472c-b72e-8ae0f0f45eca
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4084598649 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac512_vectors.4084598649
Directory /workspace/2.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha256_vectors.3815332860
Short name T152
Test name
Test status
Simulation time 37394395754 ps
CPU time 594.49 seconds
Started Jul 01 04:42:36 PM PDT 24
Finished Jul 01 04:52:48 PM PDT 24
Peak memory 200468 kb
Host smart-9cf2d61e-e069-482a-b4e4-9a9fc9f25315
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3815332860 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha256_vectors.3815332860
Directory /workspace/2.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha384_vectors.3706029259
Short name T417
Test name
Test status
Simulation time 557237905717 ps
CPU time 2682.77 seconds
Started Jul 01 04:42:34 PM PDT 24
Finished Jul 01 05:27:35 PM PDT 24
Peak memory 217020 kb
Host smart-e7f0ea15-719f-4eaa-9465-dfae838e170d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3706029259 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha384_vectors.3706029259
Directory /workspace/2.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha512_vectors.3252465131
Short name T255
Test name
Test status
Simulation time 156505901964 ps
CPU time 2207.14 seconds
Started Jul 01 04:42:41 PM PDT 24
Finished Jul 01 05:19:44 PM PDT 24
Peak memory 215812 kb
Host smart-24cd13a4-1401-464b-b944-78fba37d0870
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_200_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3252465131 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha512_vectors.3252465131
Directory /workspace/2.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/2.hmac_wipe_secret.4242847667
Short name T237
Test name
Test status
Simulation time 89618492 ps
CPU time 5.01 seconds
Started Jul 01 04:42:33 PM PDT 24
Finished Jul 01 04:42:56 PM PDT 24
Peak memory 200300 kb
Host smart-92647765-5376-4184-a266-c6782aff83e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242847667 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_wipe_secret.4242847667
Directory /workspace/2.hmac_wipe_secret/latest

Test location /workspace/coverage/default/20.hmac_alert_test.4086492287
Short name T400
Test name
Test status
Simulation time 28023530 ps
CPU time 0.59 seconds
Started Jul 01 04:42:57 PM PDT 24
Finished Jul 01 04:43:08 PM PDT 24
Peak memory 196204 kb
Host smart-0825b20b-7ae4-4c19-bef0-8fd72c5d9453
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086492287 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_alert_test.4086492287
Directory /workspace/20.hmac_alert_test/latest

Test location /workspace/coverage/default/20.hmac_back_pressure.1520085394
Short name T146
Test name
Test status
Simulation time 1761315797 ps
CPU time 45.23 seconds
Started Jul 01 04:42:57 PM PDT 24
Finished Jul 01 04:43:52 PM PDT 24
Peak memory 200276 kb
Host smart-8c3043f6-c05f-453f-8880-4dd88513eb71
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1520085394 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_back_pressure.1520085394
Directory /workspace/20.hmac_back_pressure/latest

Test location /workspace/coverage/default/20.hmac_burst_wr.1380980026
Short name T395
Test name
Test status
Simulation time 2813527989 ps
CPU time 18.39 seconds
Started Jul 01 04:43:02 PM PDT 24
Finished Jul 01 04:43:28 PM PDT 24
Peak memory 200260 kb
Host smart-3cf36df1-c865-492b-833b-1be2ee284d8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380980026 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_burst_wr.1380980026
Directory /workspace/20.hmac_burst_wr/latest

Test location /workspace/coverage/default/20.hmac_datapath_stress.593984736
Short name T143
Test name
Test status
Simulation time 4216538999 ps
CPU time 636.69 seconds
Started Jul 01 04:42:58 PM PDT 24
Finished Jul 01 04:53:45 PM PDT 24
Peak memory 493508 kb
Host smart-c0cc0574-477e-4c23-9eef-f95882b8770e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=593984736 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_datapath_stress.593984736
Directory /workspace/20.hmac_datapath_stress/latest

Test location /workspace/coverage/default/20.hmac_error.2702311047
Short name T171
Test name
Test status
Simulation time 5207565537 ps
CPU time 89.63 seconds
Started Jul 01 04:42:58 PM PDT 24
Finished Jul 01 04:44:38 PM PDT 24
Peak memory 200388 kb
Host smart-5d07a226-be8c-4cc5-9162-a92be852abfd
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702311047 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_error.2702311047
Directory /workspace/20.hmac_error/latest

Test location /workspace/coverage/default/20.hmac_long_msg.1781426907
Short name T316
Test name
Test status
Simulation time 4912680310 ps
CPU time 140.45 seconds
Started Jul 01 04:42:57 PM PDT 24
Finished Jul 01 04:45:27 PM PDT 24
Peak memory 200392 kb
Host smart-d65054de-5d11-4f73-949c-2d818ff623db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1781426907 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_long_msg.1781426907
Directory /workspace/20.hmac_long_msg/latest

Test location /workspace/coverage/default/20.hmac_smoke.2563475547
Short name T123
Test name
Test status
Simulation time 1373102054 ps
CPU time 16.64 seconds
Started Jul 01 04:42:59 PM PDT 24
Finished Jul 01 04:43:25 PM PDT 24
Peak memory 200312 kb
Host smart-2f36837c-6036-4874-ac3c-1fe84cb7c4d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563475547 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_smoke.2563475547
Directory /workspace/20.hmac_smoke/latest

Test location /workspace/coverage/default/20.hmac_stress_all.3386640454
Short name T103
Test name
Test status
Simulation time 17888715133 ps
CPU time 1562.36 seconds
Started Jul 01 04:43:02 PM PDT 24
Finished Jul 01 05:09:13 PM PDT 24
Peak memory 686008 kb
Host smart-b5516830-550a-4b42-9c14-5e7c59cfbc8f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386640454 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.hmac_stress_all.3386640454
Directory /workspace/20.hmac_stress_all/latest

Test location /workspace/coverage/default/20.hmac_wipe_secret.791593883
Short name T328
Test name
Test status
Simulation time 1688653736 ps
CPU time 20.94 seconds
Started Jul 01 04:43:00 PM PDT 24
Finished Jul 01 04:43:30 PM PDT 24
Peak memory 200364 kb
Host smart-c52e0ffb-7780-401d-9235-7b5cd5d63ace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791593883 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_wipe_secret.791593883
Directory /workspace/20.hmac_wipe_secret/latest

Test location /workspace/coverage/default/21.hmac_alert_test.3681348177
Short name T168
Test name
Test status
Simulation time 24665122 ps
CPU time 0.57 seconds
Started Jul 01 04:43:10 PM PDT 24
Finished Jul 01 04:43:17 PM PDT 24
Peak memory 195188 kb
Host smart-6b73722f-694f-474b-a839-610154760d32
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681348177 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_alert_test.3681348177
Directory /workspace/21.hmac_alert_test/latest

Test location /workspace/coverage/default/21.hmac_back_pressure.1509934786
Short name T394
Test name
Test status
Simulation time 1752844885 ps
CPU time 49.24 seconds
Started Jul 01 04:43:08 PM PDT 24
Finished Jul 01 04:44:03 PM PDT 24
Peak memory 200324 kb
Host smart-a044260f-a7d9-433e-91b2-1c899ba22052
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1509934786 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_back_pressure.1509934786
Directory /workspace/21.hmac_back_pressure/latest

Test location /workspace/coverage/default/21.hmac_burst_wr.876616677
Short name T142
Test name
Test status
Simulation time 105449253 ps
CPU time 1.93 seconds
Started Jul 01 04:43:08 PM PDT 24
Finished Jul 01 04:43:16 PM PDT 24
Peak memory 200196 kb
Host smart-1a06d00f-e38d-4e08-a74b-9b63f57484f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876616677 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_burst_wr.876616677
Directory /workspace/21.hmac_burst_wr/latest

Test location /workspace/coverage/default/21.hmac_datapath_stress.1515665388
Short name T150
Test name
Test status
Simulation time 5474686734 ps
CPU time 1121.62 seconds
Started Jul 01 04:43:08 PM PDT 24
Finished Jul 01 05:01:56 PM PDT 24
Peak memory 770904 kb
Host smart-422419d4-0fcf-43ea-85dc-bee64719125f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1515665388 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_datapath_stress.1515665388
Directory /workspace/21.hmac_datapath_stress/latest

Test location /workspace/coverage/default/21.hmac_error.850587027
Short name T293
Test name
Test status
Simulation time 634266625 ps
CPU time 18.09 seconds
Started Jul 01 04:43:11 PM PDT 24
Finished Jul 01 04:43:36 PM PDT 24
Peak memory 200296 kb
Host smart-a79b7791-d58b-48d9-9f6e-987b7d66519b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850587027 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_error.850587027
Directory /workspace/21.hmac_error/latest

Test location /workspace/coverage/default/21.hmac_long_msg.421366373
Short name T127
Test name
Test status
Simulation time 2548850350 ps
CPU time 70.7 seconds
Started Jul 01 04:42:57 PM PDT 24
Finished Jul 01 04:44:18 PM PDT 24
Peak memory 200404 kb
Host smart-a2a139c8-5cff-4c42-8019-a38c90ab821f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421366373 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_long_msg.421366373
Directory /workspace/21.hmac_long_msg/latest

Test location /workspace/coverage/default/21.hmac_smoke.1159439412
Short name T480
Test name
Test status
Simulation time 1049212905 ps
CPU time 7.1 seconds
Started Jul 01 04:43:01 PM PDT 24
Finished Jul 01 04:43:16 PM PDT 24
Peak memory 200312 kb
Host smart-8878db65-88fa-4bdd-8874-fa756591b07b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159439412 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_smoke.1159439412
Directory /workspace/21.hmac_smoke/latest

Test location /workspace/coverage/default/21.hmac_stress_all.62373068
Short name T433
Test name
Test status
Simulation time 236580654246 ps
CPU time 846.03 seconds
Started Jul 01 04:43:09 PM PDT 24
Finished Jul 01 04:57:21 PM PDT 24
Peak memory 200444 kb
Host smart-d01a96b6-489c-4705-8857-17a531fabdda
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62373068 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 21.hmac_stress_all.62373068
Directory /workspace/21.hmac_stress_all/latest

Test location /workspace/coverage/default/21.hmac_wipe_secret.1275271556
Short name T175
Test name
Test status
Simulation time 1599146588 ps
CPU time 56.75 seconds
Started Jul 01 04:43:09 PM PDT 24
Finished Jul 01 04:44:12 PM PDT 24
Peak memory 200356 kb
Host smart-f54ce665-225b-41b4-a264-52207bea24d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275271556 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_wipe_secret.1275271556
Directory /workspace/21.hmac_wipe_secret/latest

Test location /workspace/coverage/default/22.hmac_alert_test.3992236733
Short name T193
Test name
Test status
Simulation time 19633743 ps
CPU time 0.57 seconds
Started Jul 01 04:43:08 PM PDT 24
Finished Jul 01 04:43:14 PM PDT 24
Peak memory 195200 kb
Host smart-940ebc44-a990-4576-811a-4da107fed8ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992236733 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_alert_test.3992236733
Directory /workspace/22.hmac_alert_test/latest

Test location /workspace/coverage/default/22.hmac_back_pressure.3989808395
Short name T149
Test name
Test status
Simulation time 695497007 ps
CPU time 40.72 seconds
Started Jul 01 04:43:08 PM PDT 24
Finished Jul 01 04:43:55 PM PDT 24
Peak memory 200284 kb
Host smart-25d596f5-122d-49d3-a339-f5b5bc21ddb3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3989808395 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_back_pressure.3989808395
Directory /workspace/22.hmac_back_pressure/latest

Test location /workspace/coverage/default/22.hmac_burst_wr.1307795980
Short name T8
Test name
Test status
Simulation time 807584105 ps
CPU time 43.85 seconds
Started Jul 01 04:43:07 PM PDT 24
Finished Jul 01 04:43:57 PM PDT 24
Peak memory 200316 kb
Host smart-c23222df-09be-4262-937a-1741aca5f7c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307795980 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_burst_wr.1307795980
Directory /workspace/22.hmac_burst_wr/latest

Test location /workspace/coverage/default/22.hmac_datapath_stress.3027429838
Short name T116
Test name
Test status
Simulation time 5645413885 ps
CPU time 530.85 seconds
Started Jul 01 04:43:10 PM PDT 24
Finished Jul 01 04:52:08 PM PDT 24
Peak memory 705828 kb
Host smart-4f406fb8-9b1b-432f-a854-49c4499f7f13
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3027429838 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_datapath_stress.3027429838
Directory /workspace/22.hmac_datapath_stress/latest

Test location /workspace/coverage/default/22.hmac_error.649199485
Short name T363
Test name
Test status
Simulation time 26927176127 ps
CPU time 85.88 seconds
Started Jul 01 04:43:10 PM PDT 24
Finished Jul 01 04:44:43 PM PDT 24
Peak memory 200452 kb
Host smart-c7d73918-7669-4636-8929-d85c8ad7034c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649199485 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_error.649199485
Directory /workspace/22.hmac_error/latest

Test location /workspace/coverage/default/22.hmac_long_msg.1173120392
Short name T341
Test name
Test status
Simulation time 716451699 ps
CPU time 19.28 seconds
Started Jul 01 04:43:09 PM PDT 24
Finished Jul 01 04:43:34 PM PDT 24
Peak memory 200324 kb
Host smart-26238ecf-d9e1-432a-aae0-ac0c0d01bbbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173120392 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_long_msg.1173120392
Directory /workspace/22.hmac_long_msg/latest

Test location /workspace/coverage/default/22.hmac_smoke.906865895
Short name T476
Test name
Test status
Simulation time 673446553 ps
CPU time 11.22 seconds
Started Jul 01 04:43:10 PM PDT 24
Finished Jul 01 04:43:28 PM PDT 24
Peak memory 200352 kb
Host smart-a31ae4c9-c5de-43a9-891c-8d73a81248d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906865895 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_smoke.906865895
Directory /workspace/22.hmac_smoke/latest

Test location /workspace/coverage/default/22.hmac_stress_all.2587059414
Short name T459
Test name
Test status
Simulation time 34106960527 ps
CPU time 357.36 seconds
Started Jul 01 04:43:13 PM PDT 24
Finished Jul 01 04:49:16 PM PDT 24
Peak memory 551980 kb
Host smart-f766ab9e-d6aa-4ca4-9df6-28a256a18a07
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587059414 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.hmac_stress_all.2587059414
Directory /workspace/22.hmac_stress_all/latest

Test location /workspace/coverage/default/22.hmac_wipe_secret.847223037
Short name T506
Test name
Test status
Simulation time 2437482979 ps
CPU time 113.56 seconds
Started Jul 01 04:43:10 PM PDT 24
Finished Jul 01 04:45:10 PM PDT 24
Peak memory 200360 kb
Host smart-728f6c8d-9b38-4ee6-848c-e98af3d781ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847223037 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_wipe_secret.847223037
Directory /workspace/22.hmac_wipe_secret/latest

Test location /workspace/coverage/default/23.hmac_alert_test.3593615619
Short name T464
Test name
Test status
Simulation time 45264432 ps
CPU time 0.57 seconds
Started Jul 01 04:43:09 PM PDT 24
Finished Jul 01 04:43:16 PM PDT 24
Peak memory 196232 kb
Host smart-4640467d-02f6-4e44-984a-81426c85427c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593615619 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_alert_test.3593615619
Directory /workspace/23.hmac_alert_test/latest

Test location /workspace/coverage/default/23.hmac_back_pressure.2746564303
Short name T391
Test name
Test status
Simulation time 580531262 ps
CPU time 15.62 seconds
Started Jul 01 04:43:10 PM PDT 24
Finished Jul 01 04:43:32 PM PDT 24
Peak memory 200332 kb
Host smart-fb02f7f8-9032-4355-888f-a04e827637a0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2746564303 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_back_pressure.2746564303
Directory /workspace/23.hmac_back_pressure/latest

Test location /workspace/coverage/default/23.hmac_burst_wr.3748458525
Short name T162
Test name
Test status
Simulation time 1053481737 ps
CPU time 26.25 seconds
Started Jul 01 04:43:10 PM PDT 24
Finished Jul 01 04:43:42 PM PDT 24
Peak memory 200292 kb
Host smart-a9da9a31-3b8a-4716-b695-c1859214b001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748458525 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_burst_wr.3748458525
Directory /workspace/23.hmac_burst_wr/latest

Test location /workspace/coverage/default/23.hmac_datapath_stress.633737636
Short name T301
Test name
Test status
Simulation time 6005168873 ps
CPU time 496.39 seconds
Started Jul 01 04:43:10 PM PDT 24
Finished Jul 01 04:51:32 PM PDT 24
Peak memory 689616 kb
Host smart-b23f6fa9-96ce-4c61-9824-9fc3bbb5859a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=633737636 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_datapath_stress.633737636
Directory /workspace/23.hmac_datapath_stress/latest

Test location /workspace/coverage/default/23.hmac_error.3598708366
Short name T2
Test name
Test status
Simulation time 20452819 ps
CPU time 0.67 seconds
Started Jul 01 04:43:07 PM PDT 24
Finished Jul 01 04:43:14 PM PDT 24
Peak memory 196636 kb
Host smart-4b6d6023-3fce-4dea-b8de-ce62f7ddd533
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598708366 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_error.3598708366
Directory /workspace/23.hmac_error/latest

Test location /workspace/coverage/default/23.hmac_long_msg.283146316
Short name T372
Test name
Test status
Simulation time 6632906014 ps
CPU time 118.76 seconds
Started Jul 01 04:43:09 PM PDT 24
Finished Jul 01 04:45:14 PM PDT 24
Peak memory 200432 kb
Host smart-9d7e8265-5f91-4928-9fc5-0d759e7013c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283146316 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_long_msg.283146316
Directory /workspace/23.hmac_long_msg/latest

Test location /workspace/coverage/default/23.hmac_smoke.2874039556
Short name T211
Test name
Test status
Simulation time 192027457 ps
CPU time 4.17 seconds
Started Jul 01 04:43:11 PM PDT 24
Finished Jul 01 04:43:22 PM PDT 24
Peak memory 200264 kb
Host smart-e3cbb0d7-c6a2-4bdc-b33a-c509d202a53d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874039556 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_smoke.2874039556
Directory /workspace/23.hmac_smoke/latest

Test location /workspace/coverage/default/23.hmac_stress_all.669625290
Short name T330
Test name
Test status
Simulation time 19794510214 ps
CPU time 362.01 seconds
Started Jul 01 04:43:10 PM PDT 24
Finished Jul 01 04:49:19 PM PDT 24
Peak memory 208720 kb
Host smart-436f06c0-04c3-492b-8ef6-5dfa00b943e2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669625290 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 23.hmac_stress_all.669625290
Directory /workspace/23.hmac_stress_all/latest

Test location /workspace/coverage/default/23.hmac_wipe_secret.1686518616
Short name T514
Test name
Test status
Simulation time 11914902189 ps
CPU time 55.8 seconds
Started Jul 01 04:43:08 PM PDT 24
Finished Jul 01 04:44:10 PM PDT 24
Peak memory 200628 kb
Host smart-707840fd-123b-4102-89f7-a0c8951485f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686518616 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_wipe_secret.1686518616
Directory /workspace/23.hmac_wipe_secret/latest

Test location /workspace/coverage/default/24.hmac_alert_test.3706689715
Short name T469
Test name
Test status
Simulation time 10691604 ps
CPU time 0.56 seconds
Started Jul 01 04:43:10 PM PDT 24
Finished Jul 01 04:43:16 PM PDT 24
Peak memory 195180 kb
Host smart-86c4aca4-6360-4720-a72a-bf6885a835b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706689715 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_alert_test.3706689715
Directory /workspace/24.hmac_alert_test/latest

Test location /workspace/coverage/default/24.hmac_back_pressure.1693168998
Short name T432
Test name
Test status
Simulation time 527150789 ps
CPU time 34 seconds
Started Jul 01 04:43:09 PM PDT 24
Finished Jul 01 04:43:49 PM PDT 24
Peak memory 200248 kb
Host smart-5a3e49e7-1e1c-401a-847f-1b96c2bb4fe7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1693168998 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_back_pressure.1693168998
Directory /workspace/24.hmac_back_pressure/latest

Test location /workspace/coverage/default/24.hmac_burst_wr.191139756
Short name T527
Test name
Test status
Simulation time 683906794 ps
CPU time 38.21 seconds
Started Jul 01 04:43:10 PM PDT 24
Finished Jul 01 04:43:54 PM PDT 24
Peak memory 200244 kb
Host smart-ea34b81e-ff9b-4443-942c-9eaeb01a2e59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191139756 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_burst_wr.191139756
Directory /workspace/24.hmac_burst_wr/latest

Test location /workspace/coverage/default/24.hmac_datapath_stress.2903478834
Short name T292
Test name
Test status
Simulation time 13238150635 ps
CPU time 640.41 seconds
Started Jul 01 04:43:09 PM PDT 24
Finished Jul 01 04:53:56 PM PDT 24
Peak memory 697676 kb
Host smart-93c5e3b9-dfbf-4443-8dd4-31a00b482834
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2903478834 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_datapath_stress.2903478834
Directory /workspace/24.hmac_datapath_stress/latest

Test location /workspace/coverage/default/24.hmac_error.1323475321
Short name T418
Test name
Test status
Simulation time 4362409130 ps
CPU time 162.22 seconds
Started Jul 01 04:43:10 PM PDT 24
Finished Jul 01 04:45:58 PM PDT 24
Peak memory 200368 kb
Host smart-83aa59df-2207-4875-b6a6-1590acbae21e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323475321 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_error.1323475321
Directory /workspace/24.hmac_error/latest

Test location /workspace/coverage/default/24.hmac_long_msg.1033361542
Short name T277
Test name
Test status
Simulation time 18103897017 ps
CPU time 81.41 seconds
Started Jul 01 04:43:08 PM PDT 24
Finished Jul 01 04:44:36 PM PDT 24
Peak memory 200672 kb
Host smart-2dc65436-a631-4307-b6d7-14edddf3c823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033361542 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_long_msg.1033361542
Directory /workspace/24.hmac_long_msg/latest

Test location /workspace/coverage/default/24.hmac_smoke.3227092532
Short name T500
Test name
Test status
Simulation time 2578621146 ps
CPU time 2.57 seconds
Started Jul 01 04:43:11 PM PDT 24
Finished Jul 01 04:43:20 PM PDT 24
Peak memory 200368 kb
Host smart-0d821f3b-9e06-444b-a005-aecbfad25615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227092532 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_smoke.3227092532
Directory /workspace/24.hmac_smoke/latest

Test location /workspace/coverage/default/24.hmac_stress_all.4042727065
Short name T82
Test name
Test status
Simulation time 105980206441 ps
CPU time 343.31 seconds
Started Jul 01 04:43:11 PM PDT 24
Finished Jul 01 04:49:01 PM PDT 24
Peak memory 216812 kb
Host smart-8f1b8087-6524-43bd-9bd8-a1a0fa2166ba
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042727065 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.hmac_stress_all.4042727065
Directory /workspace/24.hmac_stress_all/latest

Test location /workspace/coverage/default/24.hmac_wipe_secret.2964447355
Short name T461
Test name
Test status
Simulation time 4334177048 ps
CPU time 45.17 seconds
Started Jul 01 04:43:08 PM PDT 24
Finished Jul 01 04:44:00 PM PDT 24
Peak memory 200444 kb
Host smart-6037e125-969c-4188-accf-05aa88e0b8c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964447355 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_wipe_secret.2964447355
Directory /workspace/24.hmac_wipe_secret/latest

Test location /workspace/coverage/default/25.hmac_alert_test.3323432585
Short name T305
Test name
Test status
Simulation time 28927989 ps
CPU time 0.58 seconds
Started Jul 01 04:43:13 PM PDT 24
Finished Jul 01 04:43:19 PM PDT 24
Peak memory 195980 kb
Host smart-5a78df9a-f1f8-4630-86d6-648bcc652a62
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323432585 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_alert_test.3323432585
Directory /workspace/25.hmac_alert_test/latest

Test location /workspace/coverage/default/25.hmac_back_pressure.3545101286
Short name T36
Test name
Test status
Simulation time 5698731386 ps
CPU time 83.08 seconds
Started Jul 01 04:43:08 PM PDT 24
Finished Jul 01 04:44:38 PM PDT 24
Peak memory 200456 kb
Host smart-89fb7b4a-31f9-471b-a786-9018fa4fee5d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3545101286 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_back_pressure.3545101286
Directory /workspace/25.hmac_back_pressure/latest

Test location /workspace/coverage/default/25.hmac_burst_wr.345684026
Short name T528
Test name
Test status
Simulation time 966659064 ps
CPU time 53.47 seconds
Started Jul 01 04:43:09 PM PDT 24
Finished Jul 01 04:44:09 PM PDT 24
Peak memory 200296 kb
Host smart-c581a540-f39a-4f33-aac9-cdf955e13527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345684026 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_burst_wr.345684026
Directory /workspace/25.hmac_burst_wr/latest

Test location /workspace/coverage/default/25.hmac_datapath_stress.3113341920
Short name T346
Test name
Test status
Simulation time 3001761462 ps
CPU time 602.42 seconds
Started Jul 01 04:43:11 PM PDT 24
Finished Jul 01 04:53:20 PM PDT 24
Peak memory 638232 kb
Host smart-70460988-d242-46fd-ab4f-2e28e8679d1c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3113341920 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_datapath_stress.3113341920
Directory /workspace/25.hmac_datapath_stress/latest

Test location /workspace/coverage/default/25.hmac_error.3748826248
Short name T479
Test name
Test status
Simulation time 13039039511 ps
CPU time 42.09 seconds
Started Jul 01 04:43:11 PM PDT 24
Finished Jul 01 04:44:00 PM PDT 24
Peak memory 200408 kb
Host smart-473fc97d-2913-4311-931c-7d272332a373
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748826248 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_error.3748826248
Directory /workspace/25.hmac_error/latest

Test location /workspace/coverage/default/25.hmac_long_msg.3623487202
Short name T490
Test name
Test status
Simulation time 1342635794 ps
CPU time 68.34 seconds
Started Jul 01 04:43:11 PM PDT 24
Finished Jul 01 04:44:26 PM PDT 24
Peak memory 200288 kb
Host smart-3409786a-6e53-4fe3-85d3-73dc7a74cd9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3623487202 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_long_msg.3623487202
Directory /workspace/25.hmac_long_msg/latest

Test location /workspace/coverage/default/25.hmac_smoke.827829772
Short name T205
Test name
Test status
Simulation time 990765966 ps
CPU time 3.25 seconds
Started Jul 01 04:43:10 PM PDT 24
Finished Jul 01 04:43:20 PM PDT 24
Peak memory 200348 kb
Host smart-f79df33e-06cd-43c9-ab30-2114230cec70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827829772 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_smoke.827829772
Directory /workspace/25.hmac_smoke/latest

Test location /workspace/coverage/default/25.hmac_wipe_secret.2174205019
Short name T503
Test name
Test status
Simulation time 10919862372 ps
CPU time 97.42 seconds
Started Jul 01 04:43:07 PM PDT 24
Finished Jul 01 04:44:51 PM PDT 24
Peak memory 200448 kb
Host smart-71688b80-d928-4265-b21d-5d6b85b26032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174205019 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_wipe_secret.2174205019
Directory /workspace/25.hmac_wipe_secret/latest

Test location /workspace/coverage/default/26.hmac_alert_test.1329192527
Short name T376
Test name
Test status
Simulation time 13075863 ps
CPU time 0.64 seconds
Started Jul 01 04:43:19 PM PDT 24
Finished Jul 01 04:43:22 PM PDT 24
Peak memory 196896 kb
Host smart-8e14184d-2fc5-4ea4-81c7-b45a223c8a18
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329192527 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_alert_test.1329192527
Directory /workspace/26.hmac_alert_test/latest

Test location /workspace/coverage/default/26.hmac_back_pressure.3010114524
Short name T243
Test name
Test status
Simulation time 4740014391 ps
CPU time 36.18 seconds
Started Jul 01 04:43:13 PM PDT 24
Finished Jul 01 04:43:55 PM PDT 24
Peak memory 200468 kb
Host smart-a16eabb6-2833-4749-85c1-d3f40e1a416e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3010114524 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_back_pressure.3010114524
Directory /workspace/26.hmac_back_pressure/latest

Test location /workspace/coverage/default/26.hmac_burst_wr.4255775229
Short name T518
Test name
Test status
Simulation time 3282772035 ps
CPU time 11.72 seconds
Started Jul 01 04:43:16 PM PDT 24
Finished Jul 01 04:43:32 PM PDT 24
Peak memory 200480 kb
Host smart-80b4bbe2-7a83-44ae-abc1-925bd0f5aea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255775229 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_burst_wr.4255775229
Directory /workspace/26.hmac_burst_wr/latest

Test location /workspace/coverage/default/26.hmac_datapath_stress.1473205950
Short name T257
Test name
Test status
Simulation time 737914692 ps
CPU time 67.21 seconds
Started Jul 01 04:43:13 PM PDT 24
Finished Jul 01 04:44:26 PM PDT 24
Peak memory 393076 kb
Host smart-685409da-8950-4d30-b101-38f4190c6147
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1473205950 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_datapath_stress.1473205950
Directory /workspace/26.hmac_datapath_stress/latest

Test location /workspace/coverage/default/26.hmac_error.3516561579
Short name T494
Test name
Test status
Simulation time 5155469202 ps
CPU time 89.81 seconds
Started Jul 01 04:43:15 PM PDT 24
Finished Jul 01 04:44:50 PM PDT 24
Peak memory 200432 kb
Host smart-0a7704af-f28b-456f-bac6-881a4b1490cf
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516561579 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_error.3516561579
Directory /workspace/26.hmac_error/latest

Test location /workspace/coverage/default/26.hmac_long_msg.1891260110
Short name T409
Test name
Test status
Simulation time 25513385 ps
CPU time 0.81 seconds
Started Jul 01 04:43:11 PM PDT 24
Finished Jul 01 04:43:18 PM PDT 24
Peak memory 198300 kb
Host smart-8998b39e-7c05-4862-ba8a-71d2aa9a031b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891260110 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_long_msg.1891260110
Directory /workspace/26.hmac_long_msg/latest

Test location /workspace/coverage/default/26.hmac_smoke.391214180
Short name T355
Test name
Test status
Simulation time 203768035 ps
CPU time 9.72 seconds
Started Jul 01 04:43:09 PM PDT 24
Finished Jul 01 04:43:25 PM PDT 24
Peak memory 200372 kb
Host smart-ff5f391f-6d25-40d8-b79b-e3224c78fb3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391214180 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_smoke.391214180
Directory /workspace/26.hmac_smoke/latest

Test location /workspace/coverage/default/26.hmac_stress_all.3159499502
Short name T210
Test name
Test status
Simulation time 11820743179 ps
CPU time 147.79 seconds
Started Jul 01 04:43:20 PM PDT 24
Finished Jul 01 04:45:50 PM PDT 24
Peak memory 200396 kb
Host smart-192c22dd-ddd8-4b5d-828e-eb9b17b20886
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159499502 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.hmac_stress_all.3159499502
Directory /workspace/26.hmac_stress_all/latest

Test location /workspace/coverage/default/26.hmac_wipe_secret.888524758
Short name T273
Test name
Test status
Simulation time 1296686391 ps
CPU time 8.79 seconds
Started Jul 01 04:43:14 PM PDT 24
Finished Jul 01 04:43:28 PM PDT 24
Peak memory 200316 kb
Host smart-0f1f0544-f3dd-4d8e-9c80-9344154ebb29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888524758 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_wipe_secret.888524758
Directory /workspace/26.hmac_wipe_secret/latest

Test location /workspace/coverage/default/27.hmac_alert_test.1567071650
Short name T441
Test name
Test status
Simulation time 31843833 ps
CPU time 0.56 seconds
Started Jul 01 04:43:16 PM PDT 24
Finished Jul 01 04:43:21 PM PDT 24
Peak memory 195852 kb
Host smart-89076b94-16f3-4ceb-8a20-8d230af80de7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567071650 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_alert_test.1567071650
Directory /workspace/27.hmac_alert_test/latest

Test location /workspace/coverage/default/27.hmac_back_pressure.2305444278
Short name T18
Test name
Test status
Simulation time 7138850256 ps
CPU time 106.28 seconds
Started Jul 01 04:43:13 PM PDT 24
Finished Jul 01 04:45:05 PM PDT 24
Peak memory 200416 kb
Host smart-90ef2183-c217-4105-ae16-4138e417cb62
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2305444278 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_back_pressure.2305444278
Directory /workspace/27.hmac_back_pressure/latest

Test location /workspace/coverage/default/27.hmac_burst_wr.2836127165
Short name T307
Test name
Test status
Simulation time 13073825993 ps
CPU time 59.76 seconds
Started Jul 01 04:43:14 PM PDT 24
Finished Jul 01 04:44:19 PM PDT 24
Peak memory 200460 kb
Host smart-b826bea6-6d07-49d0-9f0a-51c8cf4fdba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836127165 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_burst_wr.2836127165
Directory /workspace/27.hmac_burst_wr/latest

Test location /workspace/coverage/default/27.hmac_datapath_stress.1839162650
Short name T306
Test name
Test status
Simulation time 6927967299 ps
CPU time 430.01 seconds
Started Jul 01 04:43:15 PM PDT 24
Finished Jul 01 04:50:30 PM PDT 24
Peak memory 502040 kb
Host smart-696d68a7-0f21-41a7-b1e3-44bd0a614c30
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1839162650 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_datapath_stress.1839162650
Directory /workspace/27.hmac_datapath_stress/latest

Test location /workspace/coverage/default/27.hmac_error.2083821020
Short name T203
Test name
Test status
Simulation time 14420450593 ps
CPU time 200.53 seconds
Started Jul 01 04:43:15 PM PDT 24
Finished Jul 01 04:46:40 PM PDT 24
Peak memory 200500 kb
Host smart-24a0dfc3-ef11-41d1-9a03-2d88fe652ab0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083821020 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_error.2083821020
Directory /workspace/27.hmac_error/latest

Test location /workspace/coverage/default/27.hmac_long_msg.3457689296
Short name T498
Test name
Test status
Simulation time 2316684876 ps
CPU time 30.83 seconds
Started Jul 01 04:43:15 PM PDT 24
Finished Jul 01 04:43:51 PM PDT 24
Peak memory 200340 kb
Host smart-43a1643d-8136-450b-8dd2-37181d32579f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457689296 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_long_msg.3457689296
Directory /workspace/27.hmac_long_msg/latest

Test location /workspace/coverage/default/27.hmac_smoke.146569342
Short name T224
Test name
Test status
Simulation time 83301447 ps
CPU time 1.58 seconds
Started Jul 01 04:43:17 PM PDT 24
Finished Jul 01 04:43:22 PM PDT 24
Peak memory 200352 kb
Host smart-312a85ac-0e40-4338-b478-4fc99793c524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146569342 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_smoke.146569342
Directory /workspace/27.hmac_smoke/latest

Test location /workspace/coverage/default/27.hmac_stress_all.3634439835
Short name T214
Test name
Test status
Simulation time 15746212621 ps
CPU time 1617.63 seconds
Started Jul 01 04:43:15 PM PDT 24
Finished Jul 01 05:10:18 PM PDT 24
Peak memory 653108 kb
Host smart-03e9627d-6326-4ade-bc30-29928ae8a63b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634439835 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.hmac_stress_all.3634439835
Directory /workspace/27.hmac_stress_all/latest

Test location /workspace/coverage/default/27.hmac_wipe_secret.2844242338
Short name T317
Test name
Test status
Simulation time 4329808553 ps
CPU time 69.39 seconds
Started Jul 01 04:43:17 PM PDT 24
Finished Jul 01 04:44:30 PM PDT 24
Peak memory 200448 kb
Host smart-63ff46da-72d3-430a-9afb-62a8f5cc465c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844242338 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_wipe_secret.2844242338
Directory /workspace/27.hmac_wipe_secret/latest

Test location /workspace/coverage/default/28.hmac_alert_test.842134551
Short name T468
Test name
Test status
Simulation time 39355806 ps
CPU time 0.58 seconds
Started Jul 01 04:43:23 PM PDT 24
Finished Jul 01 04:43:26 PM PDT 24
Peak memory 196228 kb
Host smart-1b7fac0c-880f-4040-9480-d04143bb3aa1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842134551 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_alert_test.842134551
Directory /workspace/28.hmac_alert_test/latest

Test location /workspace/coverage/default/28.hmac_back_pressure.3196885541
Short name T524
Test name
Test status
Simulation time 2083629381 ps
CPU time 78.76 seconds
Started Jul 01 04:43:14 PM PDT 24
Finished Jul 01 04:44:38 PM PDT 24
Peak memory 200316 kb
Host smart-7c256670-4d65-44c9-b99c-bc128a6e6d5b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3196885541 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_back_pressure.3196885541
Directory /workspace/28.hmac_back_pressure/latest

Test location /workspace/coverage/default/28.hmac_burst_wr.2036565525
Short name T439
Test name
Test status
Simulation time 5029272103 ps
CPU time 36.16 seconds
Started Jul 01 04:43:14 PM PDT 24
Finished Jul 01 04:43:55 PM PDT 24
Peak memory 200416 kb
Host smart-64975ab6-475b-44c2-a2a3-1ea2687ab6dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036565525 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_burst_wr.2036565525
Directory /workspace/28.hmac_burst_wr/latest

Test location /workspace/coverage/default/28.hmac_datapath_stress.2767619704
Short name T304
Test name
Test status
Simulation time 7465087240 ps
CPU time 1546.1 seconds
Started Jul 01 04:43:14 PM PDT 24
Finished Jul 01 05:09:06 PM PDT 24
Peak memory 791672 kb
Host smart-7dd02945-6e13-4980-9e13-986612e368e5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2767619704 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_datapath_stress.2767619704
Directory /workspace/28.hmac_datapath_stress/latest

Test location /workspace/coverage/default/28.hmac_error.3909866088
Short name T308
Test name
Test status
Simulation time 5198359263 ps
CPU time 149.56 seconds
Started Jul 01 04:43:17 PM PDT 24
Finished Jul 01 04:45:50 PM PDT 24
Peak memory 200388 kb
Host smart-5a0d5fae-d40e-47f4-8e06-0c741567370e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909866088 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_error.3909866088
Directory /workspace/28.hmac_error/latest

Test location /workspace/coverage/default/28.hmac_long_msg.2173823463
Short name T259
Test name
Test status
Simulation time 2603203018 ps
CPU time 74.4 seconds
Started Jul 01 04:43:15 PM PDT 24
Finished Jul 01 04:44:34 PM PDT 24
Peak memory 200400 kb
Host smart-8d16ee34-f0a4-4a58-abae-6769a732f383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173823463 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_long_msg.2173823463
Directory /workspace/28.hmac_long_msg/latest

Test location /workspace/coverage/default/28.hmac_smoke.3586827877
Short name T248
Test name
Test status
Simulation time 98387019 ps
CPU time 4.34 seconds
Started Jul 01 04:43:15 PM PDT 24
Finished Jul 01 04:43:24 PM PDT 24
Peak memory 200392 kb
Host smart-94b14732-4861-4cdb-b994-39048fd0e927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586827877 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_smoke.3586827877
Directory /workspace/28.hmac_smoke/latest

Test location /workspace/coverage/default/28.hmac_stress_all.3558738876
Short name T295
Test name
Test status
Simulation time 8350029917 ps
CPU time 1298.5 seconds
Started Jul 01 04:43:22 PM PDT 24
Finished Jul 01 05:05:03 PM PDT 24
Peak memory 760516 kb
Host smart-b4f7f15a-eaae-4b64-91bc-cb4a4410013d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558738876 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.hmac_stress_all.3558738876
Directory /workspace/28.hmac_stress_all/latest

Test location /workspace/coverage/default/28.hmac_wipe_secret.2769933960
Short name T222
Test name
Test status
Simulation time 27678170548 ps
CPU time 57.4 seconds
Started Jul 01 04:43:20 PM PDT 24
Finished Jul 01 04:44:20 PM PDT 24
Peak memory 200404 kb
Host smart-34671d31-941c-4680-8152-8890bb4d1dd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769933960 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_wipe_secret.2769933960
Directory /workspace/28.hmac_wipe_secret/latest

Test location /workspace/coverage/default/29.hmac_alert_test.3466269151
Short name T385
Test name
Test status
Simulation time 20241622 ps
CPU time 0.56 seconds
Started Jul 01 04:43:23 PM PDT 24
Finished Jul 01 04:43:25 PM PDT 24
Peak memory 195872 kb
Host smart-7dd7c545-8fe5-4cc2-a8f1-69f12049cbfd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466269151 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_alert_test.3466269151
Directory /workspace/29.hmac_alert_test/latest

Test location /workspace/coverage/default/29.hmac_back_pressure.368743343
Short name T360
Test name
Test status
Simulation time 9718269505 ps
CPU time 102.34 seconds
Started Jul 01 04:43:21 PM PDT 24
Finished Jul 01 04:45:06 PM PDT 24
Peak memory 216676 kb
Host smart-872a0b7a-0bba-407b-9e48-b040adbe85e2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=368743343 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_back_pressure.368743343
Directory /workspace/29.hmac_back_pressure/latest

Test location /workspace/coverage/default/29.hmac_burst_wr.4173377879
Short name T339
Test name
Test status
Simulation time 4094910962 ps
CPU time 57.1 seconds
Started Jul 01 04:43:24 PM PDT 24
Finished Jul 01 04:44:23 PM PDT 24
Peak memory 200344 kb
Host smart-b9d53ae1-8f91-4779-a225-edd67bc81906
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173377879 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_burst_wr.4173377879
Directory /workspace/29.hmac_burst_wr/latest

Test location /workspace/coverage/default/29.hmac_datapath_stress.913136660
Short name T300
Test name
Test status
Simulation time 6382058374 ps
CPU time 599.98 seconds
Started Jul 01 04:43:21 PM PDT 24
Finished Jul 01 04:53:23 PM PDT 24
Peak memory 686420 kb
Host smart-f4bf7ef6-9d36-4aa7-9851-5085edcf1878
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=913136660 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_datapath_stress.913136660
Directory /workspace/29.hmac_datapath_stress/latest

Test location /workspace/coverage/default/29.hmac_error.667673029
Short name T291
Test name
Test status
Simulation time 44053256308 ps
CPU time 113.95 seconds
Started Jul 01 04:43:21 PM PDT 24
Finished Jul 01 04:45:17 PM PDT 24
Peak memory 200400 kb
Host smart-f412cca6-1b51-43f7-a983-e29c28dd4bd3
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667673029 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_error.667673029
Directory /workspace/29.hmac_error/latest

Test location /workspace/coverage/default/29.hmac_long_msg.2400823885
Short name T342
Test name
Test status
Simulation time 12333785088 ps
CPU time 173.74 seconds
Started Jul 01 04:43:22 PM PDT 24
Finished Jul 01 04:46:18 PM PDT 24
Peak memory 200432 kb
Host smart-cf77e9f7-ba3c-434e-b21f-1c8dcc464f71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400823885 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_long_msg.2400823885
Directory /workspace/29.hmac_long_msg/latest

Test location /workspace/coverage/default/29.hmac_smoke.2903897231
Short name T201
Test name
Test status
Simulation time 1105225741 ps
CPU time 13.07 seconds
Started Jul 01 04:43:24 PM PDT 24
Finished Jul 01 04:43:39 PM PDT 24
Peak memory 200312 kb
Host smart-26af6587-c6f9-4678-b3c3-166bbc999977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903897231 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_smoke.2903897231
Directory /workspace/29.hmac_smoke/latest

Test location /workspace/coverage/default/29.hmac_stress_all.858032223
Short name T263
Test name
Test status
Simulation time 311233054090 ps
CPU time 3111.92 seconds
Started Jul 01 04:43:25 PM PDT 24
Finished Jul 01 05:35:19 PM PDT 24
Peak memory 766392 kb
Host smart-5f575545-a340-4932-a01c-fbdd399500a4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858032223 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 29.hmac_stress_all.858032223
Directory /workspace/29.hmac_stress_all/latest

Test location /workspace/coverage/default/29.hmac_wipe_secret.1835764165
Short name T382
Test name
Test status
Simulation time 22047255855 ps
CPU time 68.98 seconds
Started Jul 01 04:43:22 PM PDT 24
Finished Jul 01 04:44:33 PM PDT 24
Peak memory 200504 kb
Host smart-8bb671cf-5cc0-40ec-aa48-a6918ef38379
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835764165 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_wipe_secret.1835764165
Directory /workspace/29.hmac_wipe_secret/latest

Test location /workspace/coverage/default/3.hmac_alert_test.105360440
Short name T176
Test name
Test status
Simulation time 26029143 ps
CPU time 0.63 seconds
Started Jul 01 04:42:35 PM PDT 24
Finished Jul 01 04:42:53 PM PDT 24
Peak memory 196112 kb
Host smart-a7e3f390-e0a0-46f2-98f0-79a788e4c916
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105360440 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_alert_test.105360440
Directory /workspace/3.hmac_alert_test/latest

Test location /workspace/coverage/default/3.hmac_back_pressure.2460467251
Short name T386
Test name
Test status
Simulation time 2009620788 ps
CPU time 80.98 seconds
Started Jul 01 04:42:33 PM PDT 24
Finished Jul 01 04:44:12 PM PDT 24
Peak memory 200284 kb
Host smart-1e00c735-a596-437c-ab08-59c407a906c0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2460467251 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_back_pressure.2460467251
Directory /workspace/3.hmac_back_pressure/latest

Test location /workspace/coverage/default/3.hmac_burst_wr.3497403751
Short name T192
Test name
Test status
Simulation time 7588958005 ps
CPU time 60.11 seconds
Started Jul 01 04:42:35 PM PDT 24
Finished Jul 01 04:43:53 PM PDT 24
Peak memory 200444 kb
Host smart-bf1246a3-b3b8-4dba-81d5-0ab81e3454c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497403751 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_burst_wr.3497403751
Directory /workspace/3.hmac_burst_wr/latest

Test location /workspace/coverage/default/3.hmac_datapath_stress.1979271400
Short name T504
Test name
Test status
Simulation time 4683793853 ps
CPU time 844.01 seconds
Started Jul 01 04:42:34 PM PDT 24
Finished Jul 01 04:56:56 PM PDT 24
Peak memory 690704 kb
Host smart-9c51f0b6-3780-4897-8889-f54adac94dc6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1979271400 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_datapath_stress.1979271400
Directory /workspace/3.hmac_datapath_stress/latest

Test location /workspace/coverage/default/3.hmac_error.176360264
Short name T327
Test name
Test status
Simulation time 3632415159 ps
CPU time 128.35 seconds
Started Jul 01 04:42:40 PM PDT 24
Finished Jul 01 04:45:05 PM PDT 24
Peak memory 200296 kb
Host smart-32a8e2d8-321f-4666-88e9-7a5a316f96a8
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176360264 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_error.176360264
Directory /workspace/3.hmac_error/latest

Test location /workspace/coverage/default/3.hmac_long_msg.3563713779
Short name T184
Test name
Test status
Simulation time 18582975770 ps
CPU time 148.67 seconds
Started Jul 01 04:42:34 PM PDT 24
Finished Jul 01 04:45:21 PM PDT 24
Peak memory 200452 kb
Host smart-a4987301-d8d0-45b2-b813-09d418056944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563713779 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_long_msg.3563713779
Directory /workspace/3.hmac_long_msg/latest

Test location /workspace/coverage/default/3.hmac_sec_cm.3808367285
Short name T51
Test name
Test status
Simulation time 36486754 ps
CPU time 0.81 seconds
Started Jul 01 04:42:33 PM PDT 24
Finished Jul 01 04:42:52 PM PDT 24
Peak memory 218828 kb
Host smart-a7a297b0-b7bf-4ce9-861c-d1844a53f262
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808367285 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_sec_cm.3808367285
Directory /workspace/3.hmac_sec_cm/latest

Test location /workspace/coverage/default/3.hmac_smoke.4018513999
Short name T34
Test name
Test status
Simulation time 839071948 ps
CPU time 4.37 seconds
Started Jul 01 04:42:34 PM PDT 24
Finished Jul 01 04:42:57 PM PDT 24
Peak memory 200308 kb
Host smart-0aaf252c-764f-4c9b-b3cb-b86df42121b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018513999 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_smoke.4018513999
Directory /workspace/3.hmac_smoke/latest

Test location /workspace/coverage/default/3.hmac_stress_all.3294498612
Short name T77
Test name
Test status
Simulation time 5504093741 ps
CPU time 652.59 seconds
Started Jul 01 04:42:39 PM PDT 24
Finished Jul 01 04:53:48 PM PDT 24
Peak memory 688344 kb
Host smart-cb95c23a-6d8e-4ca4-b1e1-2f8569f5472a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294498612 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all.3294498612
Directory /workspace/3.hmac_stress_all/latest

Test location /workspace/coverage/default/3.hmac_stress_all_with_rand_reset.500179577
Short name T30
Test name
Test status
Simulation time 57797706474 ps
CPU time 5196.95 seconds
Started Jul 01 04:42:32 PM PDT 24
Finished Jul 01 06:09:28 PM PDT 24
Peak memory 857992 kb
Host smart-56d031e5-a56f-4cf3-8533-26f015dc0008
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=500179577 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all_with_rand_reset.500179577
Directory /workspace/3.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.hmac_test_hmac256_vectors.195117103
Short name T495
Test name
Test status
Simulation time 4511784192 ps
CPU time 52.7 seconds
Started Jul 01 04:42:33 PM PDT 24
Finished Jul 01 04:43:44 PM PDT 24
Peak memory 200476 kb
Host smart-c8422608-3e9f-47b2-b641-a39cd8fb2f8e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=195117103 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac256_vectors.195117103
Directory /workspace/3.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_hmac384_vectors.2399145153
Short name T253
Test name
Test status
Simulation time 2239156680 ps
CPU time 84 seconds
Started Jul 01 04:42:34 PM PDT 24
Finished Jul 01 04:44:15 PM PDT 24
Peak memory 200480 kb
Host smart-ba293de7-0d47-4d2c-b6f2-61a2dc250954
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2399145153 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac384_vectors.2399145153
Directory /workspace/3.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_hmac512_vectors.3813131310
Short name T411
Test name
Test status
Simulation time 5792817737 ps
CPU time 87.92 seconds
Started Jul 01 04:42:39 PM PDT 24
Finished Jul 01 04:44:24 PM PDT 24
Peak memory 200244 kb
Host smart-2fb2a159-7bcf-4e7f-87ef-c36f84ecedc8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3813131310 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac512_vectors.3813131310
Directory /workspace/3.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha256_vectors.346683906
Short name T422
Test name
Test status
Simulation time 203377461071 ps
CPU time 632.1 seconds
Started Jul 01 04:42:32 PM PDT 24
Finished Jul 01 04:53:22 PM PDT 24
Peak memory 200436 kb
Host smart-c9682998-22cd-4803-afe5-a28bd68ad4d7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=346683906 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha256_vectors.346683906
Directory /workspace/3.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha384_vectors.3220446099
Short name T42
Test name
Test status
Simulation time 533545974355 ps
CPU time 2340.41 seconds
Started Jul 01 04:42:33 PM PDT 24
Finished Jul 01 05:21:52 PM PDT 24
Peak memory 216860 kb
Host smart-7c2289b6-2b6a-4e03-ac43-f739e33bcd4b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3220446099 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha384_vectors.3220446099
Directory /workspace/3.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha512_vectors.2283270645
Short name T501
Test name
Test status
Simulation time 172148924458 ps
CPU time 2288.37 seconds
Started Jul 01 04:42:38 PM PDT 24
Finished Jul 01 05:21:04 PM PDT 24
Peak memory 215960 kb
Host smart-97fd8cdb-5595-4e26-9350-4974e6e9dc53
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_200_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2283270645 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha512_vectors.2283270645
Directory /workspace/3.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/3.hmac_wipe_secret.1601432363
Short name T508
Test name
Test status
Simulation time 2334366491 ps
CPU time 58.77 seconds
Started Jul 01 04:42:34 PM PDT 24
Finished Jul 01 04:43:50 PM PDT 24
Peak memory 200376 kb
Host smart-13e8f12b-aeaf-4051-8759-238b85ec79ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601432363 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_wipe_secret.1601432363
Directory /workspace/3.hmac_wipe_secret/latest

Test location /workspace/coverage/default/30.hmac_alert_test.1278872967
Short name T151
Test name
Test status
Simulation time 13018084 ps
CPU time 0.58 seconds
Started Jul 01 04:43:20 PM PDT 24
Finished Jul 01 04:43:23 PM PDT 24
Peak memory 195876 kb
Host smart-829bc67e-0054-42d7-b559-f0cd8cce78be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278872967 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_alert_test.1278872967
Directory /workspace/30.hmac_alert_test/latest

Test location /workspace/coverage/default/30.hmac_back_pressure.11802235
Short name T136
Test name
Test status
Simulation time 1187949981 ps
CPU time 64.23 seconds
Started Jul 01 04:43:22 PM PDT 24
Finished Jul 01 04:44:28 PM PDT 24
Peak memory 200272 kb
Host smart-89d24733-7d81-4f54-ae3c-a9b43872bf21
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=11802235 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_back_pressure.11802235
Directory /workspace/30.hmac_back_pressure/latest

Test location /workspace/coverage/default/30.hmac_burst_wr.7598615
Short name T397
Test name
Test status
Simulation time 2169184866 ps
CPU time 12.4 seconds
Started Jul 01 04:43:26 PM PDT 24
Finished Jul 01 04:43:39 PM PDT 24
Peak memory 200368 kb
Host smart-342d0b62-9b80-4249-b44f-784d0e29564e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7598615 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_burst_wr.7598615
Directory /workspace/30.hmac_burst_wr/latest

Test location /workspace/coverage/default/30.hmac_datapath_stress.57962294
Short name T502
Test name
Test status
Simulation time 38214928841 ps
CPU time 1140.63 seconds
Started Jul 01 04:43:19 PM PDT 24
Finished Jul 01 05:02:22 PM PDT 24
Peak memory 731728 kb
Host smart-267f1f35-207b-4f06-8e93-fe42ca261698
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=57962294 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_datapath_stress.57962294
Directory /workspace/30.hmac_datapath_stress/latest

Test location /workspace/coverage/default/30.hmac_error.1503682246
Short name T189
Test name
Test status
Simulation time 12054902342 ps
CPU time 156.73 seconds
Started Jul 01 04:43:25 PM PDT 24
Finished Jul 01 04:46:04 PM PDT 24
Peak memory 200396 kb
Host smart-8b955194-8c2b-4395-b952-5a8ea8a778af
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503682246 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_error.1503682246
Directory /workspace/30.hmac_error/latest

Test location /workspace/coverage/default/30.hmac_long_msg.1043293096
Short name T207
Test name
Test status
Simulation time 7716816227 ps
CPU time 26.5 seconds
Started Jul 01 04:43:21 PM PDT 24
Finished Jul 01 04:43:50 PM PDT 24
Peak memory 200412 kb
Host smart-c865c29d-216e-4b21-9bfd-2b4d686c9a73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043293096 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_long_msg.1043293096
Directory /workspace/30.hmac_long_msg/latest

Test location /workspace/coverage/default/30.hmac_smoke.3480843702
Short name T297
Test name
Test status
Simulation time 542295124 ps
CPU time 11.89 seconds
Started Jul 01 04:43:22 PM PDT 24
Finished Jul 01 04:43:36 PM PDT 24
Peak memory 200228 kb
Host smart-a96c2dd3-70fa-428d-abca-e725438e0589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480843702 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_smoke.3480843702
Directory /workspace/30.hmac_smoke/latest

Test location /workspace/coverage/default/30.hmac_stress_all.4169849363
Short name T254
Test name
Test status
Simulation time 192664417904 ps
CPU time 810.78 seconds
Started Jul 01 04:43:22 PM PDT 24
Finished Jul 01 04:56:55 PM PDT 24
Peak memory 200508 kb
Host smart-6776cfab-bf27-49c1-b4eb-2c0c6a052f50
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169849363 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.hmac_stress_all.4169849363
Directory /workspace/30.hmac_stress_all/latest

Test location /workspace/coverage/default/30.hmac_wipe_secret.3250485066
Short name T267
Test name
Test status
Simulation time 10010879332 ps
CPU time 45.15 seconds
Started Jul 01 04:43:24 PM PDT 24
Finished Jul 01 04:44:11 PM PDT 24
Peak memory 200408 kb
Host smart-afbf032d-67a5-499b-95dd-12b3528feba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250485066 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_wipe_secret.3250485066
Directory /workspace/30.hmac_wipe_secret/latest

Test location /workspace/coverage/default/31.hmac_alert_test.3857911210
Short name T213
Test name
Test status
Simulation time 43078122 ps
CPU time 0.6 seconds
Started Jul 01 04:43:28 PM PDT 24
Finished Jul 01 04:43:30 PM PDT 24
Peak memory 195876 kb
Host smart-09166096-f651-4dee-a699-3ad88e8fc733
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857911210 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_alert_test.3857911210
Directory /workspace/31.hmac_alert_test/latest

Test location /workspace/coverage/default/31.hmac_back_pressure.3601670720
Short name T33
Test name
Test status
Simulation time 11132800119 ps
CPU time 29.9 seconds
Started Jul 01 04:43:30 PM PDT 24
Finished Jul 01 04:44:01 PM PDT 24
Peak memory 200380 kb
Host smart-aa55d179-b8d7-4b93-b17b-5959c6b9c5d7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3601670720 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_back_pressure.3601670720
Directory /workspace/31.hmac_back_pressure/latest

Test location /workspace/coverage/default/31.hmac_burst_wr.1453941285
Short name T119
Test name
Test status
Simulation time 705641017 ps
CPU time 38.65 seconds
Started Jul 01 04:43:28 PM PDT 24
Finished Jul 01 04:44:08 PM PDT 24
Peak memory 200308 kb
Host smart-22c7fb27-36dd-43f7-8466-02c5599ee700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453941285 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_burst_wr.1453941285
Directory /workspace/31.hmac_burst_wr/latest

Test location /workspace/coverage/default/31.hmac_datapath_stress.273031953
Short name T408
Test name
Test status
Simulation time 19676130410 ps
CPU time 928.19 seconds
Started Jul 01 04:43:31 PM PDT 24
Finished Jul 01 04:59:00 PM PDT 24
Peak memory 719196 kb
Host smart-38cf7bd5-72b9-42cd-a7ee-7dbccd1d379e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=273031953 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_datapath_stress.273031953
Directory /workspace/31.hmac_datapath_stress/latest

Test location /workspace/coverage/default/31.hmac_error.3326699864
Short name T37
Test name
Test status
Simulation time 24810472916 ps
CPU time 96.14 seconds
Started Jul 01 04:43:30 PM PDT 24
Finished Jul 01 04:45:07 PM PDT 24
Peak memory 200400 kb
Host smart-4524472a-2dcd-494f-905a-1514df1c3a38
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326699864 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_error.3326699864
Directory /workspace/31.hmac_error/latest

Test location /workspace/coverage/default/31.hmac_long_msg.1516165827
Short name T170
Test name
Test status
Simulation time 8792962605 ps
CPU time 164.79 seconds
Started Jul 01 04:43:28 PM PDT 24
Finished Jul 01 04:46:14 PM PDT 24
Peak memory 200460 kb
Host smart-ce394c1f-1d9f-4138-acae-bae5043e8628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1516165827 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_long_msg.1516165827
Directory /workspace/31.hmac_long_msg/latest

Test location /workspace/coverage/default/31.hmac_smoke.1960114004
Short name T402
Test name
Test status
Simulation time 558001257 ps
CPU time 10.28 seconds
Started Jul 01 04:43:28 PM PDT 24
Finished Jul 01 04:43:39 PM PDT 24
Peak memory 200316 kb
Host smart-69c95033-f318-4c67-b2e1-38e47801db01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960114004 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_smoke.1960114004
Directory /workspace/31.hmac_smoke/latest

Test location /workspace/coverage/default/31.hmac_stress_all.474485870
Short name T269
Test name
Test status
Simulation time 161583011240 ps
CPU time 655.01 seconds
Started Jul 01 04:43:30 PM PDT 24
Finished Jul 01 04:54:26 PM PDT 24
Peak memory 200412 kb
Host smart-d776649f-8836-4cbd-95e6-f4676b36d8c4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474485870 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 31.hmac_stress_all.474485870
Directory /workspace/31.hmac_stress_all/latest

Test location /workspace/coverage/default/31.hmac_wipe_secret.4193421359
Short name T104
Test name
Test status
Simulation time 41415903616 ps
CPU time 124.76 seconds
Started Jul 01 04:43:30 PM PDT 24
Finished Jul 01 04:45:36 PM PDT 24
Peak memory 200344 kb
Host smart-a3a72c3e-cf40-4d75-9ea5-17a9e6e6dd99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193421359 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_wipe_secret.4193421359
Directory /workspace/31.hmac_wipe_secret/latest

Test location /workspace/coverage/default/32.hmac_alert_test.3403099539
Short name T457
Test name
Test status
Simulation time 19278628 ps
CPU time 0.6 seconds
Started Jul 01 04:43:38 PM PDT 24
Finished Jul 01 04:43:40 PM PDT 24
Peak memory 196880 kb
Host smart-129375ed-1263-4df3-8c0c-d6d95e5daef3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403099539 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_alert_test.3403099539
Directory /workspace/32.hmac_alert_test/latest

Test location /workspace/coverage/default/32.hmac_back_pressure.256473896
Short name T487
Test name
Test status
Simulation time 2587150878 ps
CPU time 71.43 seconds
Started Jul 01 04:43:31 PM PDT 24
Finished Jul 01 04:44:44 PM PDT 24
Peak memory 200264 kb
Host smart-920d1518-ef67-49c4-a463-04b9257103f4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=256473896 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_back_pressure.256473896
Directory /workspace/32.hmac_back_pressure/latest

Test location /workspace/coverage/default/32.hmac_burst_wr.1946240761
Short name T312
Test name
Test status
Simulation time 9217229225 ps
CPU time 43.13 seconds
Started Jul 01 04:43:35 PM PDT 24
Finished Jul 01 04:44:20 PM PDT 24
Peak memory 200436 kb
Host smart-a7dda4c7-cc08-4555-b829-f3ae4ae63356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946240761 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_burst_wr.1946240761
Directory /workspace/32.hmac_burst_wr/latest

Test location /workspace/coverage/default/32.hmac_datapath_stress.2372619699
Short name T125
Test name
Test status
Simulation time 4982486528 ps
CPU time 803.94 seconds
Started Jul 01 04:43:34 PM PDT 24
Finished Jul 01 04:57:00 PM PDT 24
Peak memory 625080 kb
Host smart-bf2495c3-0d46-477f-afec-deddc6203f6c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2372619699 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_datapath_stress.2372619699
Directory /workspace/32.hmac_datapath_stress/latest

Test location /workspace/coverage/default/32.hmac_error.2466974354
Short name T436
Test name
Test status
Simulation time 2444329497 ps
CPU time 132.46 seconds
Started Jul 01 04:43:37 PM PDT 24
Finished Jul 01 04:45:51 PM PDT 24
Peak memory 200360 kb
Host smart-954e23a4-d139-4331-8624-5b244b6422da
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466974354 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_error.2466974354
Directory /workspace/32.hmac_error/latest

Test location /workspace/coverage/default/32.hmac_long_msg.3839385040
Short name T229
Test name
Test status
Simulation time 2024353982 ps
CPU time 37 seconds
Started Jul 01 04:43:28 PM PDT 24
Finished Jul 01 04:44:06 PM PDT 24
Peak memory 200312 kb
Host smart-7542bd1e-10d1-401f-8131-a0444aba74bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3839385040 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_long_msg.3839385040
Directory /workspace/32.hmac_long_msg/latest

Test location /workspace/coverage/default/32.hmac_smoke.974569196
Short name T456
Test name
Test status
Simulation time 327165109 ps
CPU time 1.78 seconds
Started Jul 01 04:43:28 PM PDT 24
Finished Jul 01 04:43:31 PM PDT 24
Peak memory 200308 kb
Host smart-07fed85f-4e2d-44d7-adf5-2608dfe709bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974569196 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_smoke.974569196
Directory /workspace/32.hmac_smoke/latest

Test location /workspace/coverage/default/32.hmac_stress_all.2661637693
Short name T455
Test name
Test status
Simulation time 14194607581 ps
CPU time 182.33 seconds
Started Jul 01 04:43:36 PM PDT 24
Finished Jul 01 04:46:40 PM PDT 24
Peak memory 216528 kb
Host smart-8866dd5a-4659-4594-adcc-d56c16b6b1f5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661637693 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.hmac_stress_all.2661637693
Directory /workspace/32.hmac_stress_all/latest

Test location /workspace/coverage/default/32.hmac_wipe_secret.612506140
Short name T429
Test name
Test status
Simulation time 598721568 ps
CPU time 23.58 seconds
Started Jul 01 04:43:34 PM PDT 24
Finished Jul 01 04:43:59 PM PDT 24
Peak memory 200304 kb
Host smart-316bc8f7-cdac-4abf-8a79-592d5884cd7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612506140 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_wipe_secret.612506140
Directory /workspace/32.hmac_wipe_secret/latest

Test location /workspace/coverage/default/33.hmac_alert_test.661960326
Short name T353
Test name
Test status
Simulation time 11864740 ps
CPU time 0.63 seconds
Started Jul 01 04:43:36 PM PDT 24
Finished Jul 01 04:43:38 PM PDT 24
Peak memory 195200 kb
Host smart-ed123e06-26a7-4ac4-9eca-abecbb8423b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661960326 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_alert_test.661960326
Directory /workspace/33.hmac_alert_test/latest

Test location /workspace/coverage/default/33.hmac_back_pressure.365811521
Short name T280
Test name
Test status
Simulation time 2189773676 ps
CPU time 63.77 seconds
Started Jul 01 04:43:35 PM PDT 24
Finished Jul 01 04:44:41 PM PDT 24
Peak memory 200408 kb
Host smart-5b84ce52-99d0-44c9-abd1-4b1b1be7d2ee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=365811521 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_back_pressure.365811521
Directory /workspace/33.hmac_back_pressure/latest

Test location /workspace/coverage/default/33.hmac_burst_wr.1547642916
Short name T145
Test name
Test status
Simulation time 2440670152 ps
CPU time 32.02 seconds
Started Jul 01 04:43:34 PM PDT 24
Finished Jul 01 04:44:08 PM PDT 24
Peak memory 200344 kb
Host smart-2ff72656-ac12-4c61-b3ec-754d216721c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547642916 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_burst_wr.1547642916
Directory /workspace/33.hmac_burst_wr/latest

Test location /workspace/coverage/default/33.hmac_datapath_stress.3553406693
Short name T428
Test name
Test status
Simulation time 10968036653 ps
CPU time 548.52 seconds
Started Jul 01 04:43:36 PM PDT 24
Finished Jul 01 04:52:47 PM PDT 24
Peak memory 698584 kb
Host smart-f968994b-c778-4154-9dfd-13c525aba1e6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3553406693 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_datapath_stress.3553406693
Directory /workspace/33.hmac_datapath_stress/latest

Test location /workspace/coverage/default/33.hmac_error.2671365687
Short name T416
Test name
Test status
Simulation time 4730188692 ps
CPU time 51.29 seconds
Started Jul 01 04:43:35 PM PDT 24
Finished Jul 01 04:44:28 PM PDT 24
Peak memory 200420 kb
Host smart-6f79b473-b8e8-49ea-8234-3479bd6d68f3
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671365687 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_error.2671365687
Directory /workspace/33.hmac_error/latest

Test location /workspace/coverage/default/33.hmac_long_msg.492014310
Short name T390
Test name
Test status
Simulation time 25634941344 ps
CPU time 122.94 seconds
Started Jul 01 04:43:35 PM PDT 24
Finished Jul 01 04:45:40 PM PDT 24
Peak memory 200488 kb
Host smart-90c5782b-f4e9-4ff4-88d3-5523e624eb97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492014310 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_long_msg.492014310
Directory /workspace/33.hmac_long_msg/latest

Test location /workspace/coverage/default/33.hmac_smoke.1873819135
Short name T251
Test name
Test status
Simulation time 860606412 ps
CPU time 13.28 seconds
Started Jul 01 04:43:35 PM PDT 24
Finished Jul 01 04:43:51 PM PDT 24
Peak memory 200356 kb
Host smart-e67feea2-f1e3-4ce8-9a86-55fee1219196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873819135 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_smoke.1873819135
Directory /workspace/33.hmac_smoke/latest

Test location /workspace/coverage/default/33.hmac_stress_all.3084390088
Short name T381
Test name
Test status
Simulation time 143137158968 ps
CPU time 626.53 seconds
Started Jul 01 04:43:36 PM PDT 24
Finished Jul 01 04:54:05 PM PDT 24
Peak memory 200384 kb
Host smart-e8384c7b-3767-4be0-b2e8-7bd8c7946312
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084390088 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.hmac_stress_all.3084390088
Directory /workspace/33.hmac_stress_all/latest

Test location /workspace/coverage/default/33.hmac_wipe_secret.3908987628
Short name T321
Test name
Test status
Simulation time 185302929 ps
CPU time 10.05 seconds
Started Jul 01 04:43:35 PM PDT 24
Finished Jul 01 04:43:48 PM PDT 24
Peak memory 200228 kb
Host smart-e471d2fd-f478-45cf-85c7-846d194d333d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908987628 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_wipe_secret.3908987628
Directory /workspace/33.hmac_wipe_secret/latest

Test location /workspace/coverage/default/34.hmac_alert_test.1644543538
Short name T220
Test name
Test status
Simulation time 22339155 ps
CPU time 0.56 seconds
Started Jul 01 04:43:40 PM PDT 24
Finished Jul 01 04:43:42 PM PDT 24
Peak memory 195812 kb
Host smart-b6bdfe3f-dc61-459e-b3a6-abf5e8713f93
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644543538 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_alert_test.1644543538
Directory /workspace/34.hmac_alert_test/latest

Test location /workspace/coverage/default/34.hmac_back_pressure.1380075135
Short name T265
Test name
Test status
Simulation time 718913190 ps
CPU time 42.54 seconds
Started Jul 01 04:43:40 PM PDT 24
Finished Jul 01 04:44:24 PM PDT 24
Peak memory 200300 kb
Host smart-985e52d8-10f6-488b-a0e6-378c1b28a0f5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1380075135 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_back_pressure.1380075135
Directory /workspace/34.hmac_back_pressure/latest

Test location /workspace/coverage/default/34.hmac_burst_wr.1729627169
Short name T208
Test name
Test status
Simulation time 15873470742 ps
CPU time 55.16 seconds
Started Jul 01 04:43:43 PM PDT 24
Finished Jul 01 04:44:39 PM PDT 24
Peak memory 216924 kb
Host smart-1856730f-796e-4cba-ad27-1f0a0bcc6321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729627169 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_burst_wr.1729627169
Directory /workspace/34.hmac_burst_wr/latest

Test location /workspace/coverage/default/34.hmac_datapath_stress.3626432828
Short name T467
Test name
Test status
Simulation time 16278204399 ps
CPU time 776.52 seconds
Started Jul 01 04:43:41 PM PDT 24
Finished Jul 01 04:56:39 PM PDT 24
Peak memory 716620 kb
Host smart-2bd2842c-b9b1-4524-8ec1-500b4b0f1fd0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3626432828 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_datapath_stress.3626432828
Directory /workspace/34.hmac_datapath_stress/latest

Test location /workspace/coverage/default/34.hmac_error.3509726917
Short name T375
Test name
Test status
Simulation time 37752719200 ps
CPU time 180.51 seconds
Started Jul 01 04:43:41 PM PDT 24
Finished Jul 01 04:46:43 PM PDT 24
Peak memory 200460 kb
Host smart-4e5a6fcf-6e30-49a4-bf23-3e477639d88b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509726917 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_error.3509726917
Directory /workspace/34.hmac_error/latest

Test location /workspace/coverage/default/34.hmac_long_msg.230971486
Short name T507
Test name
Test status
Simulation time 8870710284 ps
CPU time 28.7 seconds
Started Jul 01 04:43:43 PM PDT 24
Finished Jul 01 04:44:13 PM PDT 24
Peak memory 200624 kb
Host smart-6ac4f5d7-ee58-4a36-9148-829bab91b0ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230971486 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_long_msg.230971486
Directory /workspace/34.hmac_long_msg/latest

Test location /workspace/coverage/default/34.hmac_smoke.2976199284
Short name T462
Test name
Test status
Simulation time 1341426622 ps
CPU time 8.59 seconds
Started Jul 01 04:43:34 PM PDT 24
Finished Jul 01 04:43:45 PM PDT 24
Peak memory 200284 kb
Host smart-e750ab29-469b-43cc-8ac7-cfc299d02f93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976199284 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_smoke.2976199284
Directory /workspace/34.hmac_smoke/latest

Test location /workspace/coverage/default/34.hmac_stress_all.3011105875
Short name T196
Test name
Test status
Simulation time 63444683102 ps
CPU time 2386.53 seconds
Started Jul 01 04:43:43 PM PDT 24
Finished Jul 01 05:23:31 PM PDT 24
Peak memory 761500 kb
Host smart-1d945f3e-db7e-4eb0-9920-d4d6ef3fc1c4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011105875 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.hmac_stress_all.3011105875
Directory /workspace/34.hmac_stress_all/latest

Test location /workspace/coverage/default/34.hmac_wipe_secret.163362020
Short name T63
Test name
Test status
Simulation time 1882639207 ps
CPU time 14.15 seconds
Started Jul 01 04:43:43 PM PDT 24
Finished Jul 01 04:43:59 PM PDT 24
Peak memory 200260 kb
Host smart-3ed3e16a-a4f8-41a2-9f85-f75cea0c287f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163362020 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_wipe_secret.163362020
Directory /workspace/34.hmac_wipe_secret/latest

Test location /workspace/coverage/default/35.hmac_alert_test.3088958894
Short name T442
Test name
Test status
Simulation time 13602128 ps
CPU time 0.55 seconds
Started Jul 01 04:43:50 PM PDT 24
Finished Jul 01 04:43:53 PM PDT 24
Peak memory 195820 kb
Host smart-c70e4d42-1bb9-46c8-9fdb-c90e2a7dee74
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088958894 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_alert_test.3088958894
Directory /workspace/35.hmac_alert_test/latest

Test location /workspace/coverage/default/35.hmac_back_pressure.1965864560
Short name T435
Test name
Test status
Simulation time 1372726875 ps
CPU time 77.75 seconds
Started Jul 01 04:43:45 PM PDT 24
Finished Jul 01 04:45:03 PM PDT 24
Peak memory 200264 kb
Host smart-52f40560-74f4-4528-8c69-d4cc8ac73dc2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1965864560 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_back_pressure.1965864560
Directory /workspace/35.hmac_back_pressure/latest

Test location /workspace/coverage/default/35.hmac_burst_wr.3320743574
Short name T438
Test name
Test status
Simulation time 828389614 ps
CPU time 46.12 seconds
Started Jul 01 04:43:40 PM PDT 24
Finished Jul 01 04:44:28 PM PDT 24
Peak memory 200340 kb
Host smart-44c12957-cb34-4827-a329-43e5132ce5fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320743574 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_burst_wr.3320743574
Directory /workspace/35.hmac_burst_wr/latest

Test location /workspace/coverage/default/35.hmac_datapath_stress.945424086
Short name T271
Test name
Test status
Simulation time 5738745196 ps
CPU time 233.09 seconds
Started Jul 01 04:43:43 PM PDT 24
Finished Jul 01 04:47:37 PM PDT 24
Peak memory 620328 kb
Host smart-73e0d60f-a334-45ee-a423-949ba5965579
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=945424086 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_datapath_stress.945424086
Directory /workspace/35.hmac_datapath_stress/latest

Test location /workspace/coverage/default/35.hmac_error.2486547081
Short name T187
Test name
Test status
Simulation time 7285765707 ps
CPU time 104.03 seconds
Started Jul 01 04:43:41 PM PDT 24
Finished Jul 01 04:45:26 PM PDT 24
Peak memory 200452 kb
Host smart-964769c4-2195-42af-8095-b24f5d697ad2
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486547081 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_error.2486547081
Directory /workspace/35.hmac_error/latest

Test location /workspace/coverage/default/35.hmac_long_msg.2289348244
Short name T314
Test name
Test status
Simulation time 728085537 ps
CPU time 10.46 seconds
Started Jul 01 04:43:40 PM PDT 24
Finished Jul 01 04:43:53 PM PDT 24
Peak memory 200320 kb
Host smart-623f9dd7-fe09-4053-afa2-e501fdf504de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2289348244 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_long_msg.2289348244
Directory /workspace/35.hmac_long_msg/latest

Test location /workspace/coverage/default/35.hmac_smoke.2321331234
Short name T384
Test name
Test status
Simulation time 163456250 ps
CPU time 7.31 seconds
Started Jul 01 04:43:42 PM PDT 24
Finished Jul 01 04:43:51 PM PDT 24
Peak memory 200356 kb
Host smart-4cc3a0b6-c829-4e43-bd75-a7afb9784bd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321331234 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_smoke.2321331234
Directory /workspace/35.hmac_smoke/latest

Test location /workspace/coverage/default/35.hmac_stress_all.3495473197
Short name T272
Test name
Test status
Simulation time 16015868968 ps
CPU time 213.96 seconds
Started Jul 01 04:43:46 PM PDT 24
Finished Jul 01 04:47:21 PM PDT 24
Peak memory 208652 kb
Host smart-520d2185-1f93-43ac-9736-04f2ce8264c9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495473197 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.hmac_stress_all.3495473197
Directory /workspace/35.hmac_stress_all/latest

Test location /workspace/coverage/default/35.hmac_wipe_secret.1909731300
Short name T450
Test name
Test status
Simulation time 142636254 ps
CPU time 4.21 seconds
Started Jul 01 04:43:42 PM PDT 24
Finished Jul 01 04:43:47 PM PDT 24
Peak memory 200352 kb
Host smart-71eacdca-b4e1-4e9f-8d96-7bacae7b7cf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909731300 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_wipe_secret.1909731300
Directory /workspace/35.hmac_wipe_secret/latest

Test location /workspace/coverage/default/36.hmac_alert_test.1094725512
Short name T406
Test name
Test status
Simulation time 19624356 ps
CPU time 0.62 seconds
Started Jul 01 04:43:49 PM PDT 24
Finished Jul 01 04:43:52 PM PDT 24
Peak memory 196248 kb
Host smart-a85dd856-9ab0-48f4-87c7-f56066310901
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094725512 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_alert_test.1094725512
Directory /workspace/36.hmac_alert_test/latest

Test location /workspace/coverage/default/36.hmac_back_pressure.2721157977
Short name T367
Test name
Test status
Simulation time 862831658 ps
CPU time 52.93 seconds
Started Jul 01 04:43:48 PM PDT 24
Finished Jul 01 04:44:44 PM PDT 24
Peak memory 200348 kb
Host smart-363d6091-256b-4cf1-a899-f3033691fdd3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2721157977 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_back_pressure.2721157977
Directory /workspace/36.hmac_back_pressure/latest

Test location /workspace/coverage/default/36.hmac_burst_wr.2975041771
Short name T366
Test name
Test status
Simulation time 29201819 ps
CPU time 1.68 seconds
Started Jul 01 04:43:48 PM PDT 24
Finished Jul 01 04:43:51 PM PDT 24
Peak memory 200184 kb
Host smart-9688da3c-8655-48d2-a05d-fdbc7fd46832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975041771 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_burst_wr.2975041771
Directory /workspace/36.hmac_burst_wr/latest

Test location /workspace/coverage/default/36.hmac_datapath_stress.1700204821
Short name T133
Test name
Test status
Simulation time 7131517039 ps
CPU time 271.07 seconds
Started Jul 01 04:43:49 PM PDT 24
Finished Jul 01 04:48:23 PM PDT 24
Peak memory 468012 kb
Host smart-b4f142fe-eef0-4c7c-b650-180db0f4f997
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1700204821 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_datapath_stress.1700204821
Directory /workspace/36.hmac_datapath_stress/latest

Test location /workspace/coverage/default/36.hmac_error.1409206101
Short name T315
Test name
Test status
Simulation time 1135220255 ps
CPU time 61.54 seconds
Started Jul 01 04:43:48 PM PDT 24
Finished Jul 01 04:44:52 PM PDT 24
Peak memory 200220 kb
Host smart-a00f5ce6-5f6a-461c-ac13-b06040737ca5
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409206101 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_error.1409206101
Directory /workspace/36.hmac_error/latest

Test location /workspace/coverage/default/36.hmac_long_msg.707394291
Short name T446
Test name
Test status
Simulation time 31840606123 ps
CPU time 138.73 seconds
Started Jul 01 04:43:48 PM PDT 24
Finished Jul 01 04:46:09 PM PDT 24
Peak memory 200480 kb
Host smart-fd098608-5346-47a2-b72a-6e4eb5a770dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707394291 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_long_msg.707394291
Directory /workspace/36.hmac_long_msg/latest

Test location /workspace/coverage/default/36.hmac_smoke.2171361281
Short name T256
Test name
Test status
Simulation time 864135586 ps
CPU time 14.35 seconds
Started Jul 01 04:43:49 PM PDT 24
Finished Jul 01 04:44:06 PM PDT 24
Peak memory 200324 kb
Host smart-812c5b8e-d984-48e5-89df-4a775409a576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171361281 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_smoke.2171361281
Directory /workspace/36.hmac_smoke/latest

Test location /workspace/coverage/default/36.hmac_stress_all.1080911884
Short name T329
Test name
Test status
Simulation time 64462430962 ps
CPU time 570.92 seconds
Started Jul 01 04:43:49 PM PDT 24
Finished Jul 01 04:53:23 PM PDT 24
Peak memory 345152 kb
Host smart-d29f4791-a23f-4437-9cd0-b25c5d26f366
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080911884 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.hmac_stress_all.1080911884
Directory /workspace/36.hmac_stress_all/latest

Test location /workspace/coverage/default/36.hmac_wipe_secret.1462035973
Short name T147
Test name
Test status
Simulation time 11956665888 ps
CPU time 46.19 seconds
Started Jul 01 04:43:49 PM PDT 24
Finished Jul 01 04:44:38 PM PDT 24
Peak memory 200376 kb
Host smart-f240e35d-00ae-4549-b620-a70ef7c2516d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462035973 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_wipe_secret.1462035973
Directory /workspace/36.hmac_wipe_secret/latest

Test location /workspace/coverage/default/37.hmac_alert_test.3274228417
Short name T352
Test name
Test status
Simulation time 37817069 ps
CPU time 0.56 seconds
Started Jul 01 04:43:50 PM PDT 24
Finished Jul 01 04:43:53 PM PDT 24
Peak memory 195200 kb
Host smart-21d11c74-fa25-4c52-9fc2-df2e2bc62bc2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274228417 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_alert_test.3274228417
Directory /workspace/37.hmac_alert_test/latest

Test location /workspace/coverage/default/37.hmac_back_pressure.3114073334
Short name T239
Test name
Test status
Simulation time 3176844738 ps
CPU time 48.37 seconds
Started Jul 01 04:43:48 PM PDT 24
Finished Jul 01 04:44:38 PM PDT 24
Peak memory 200568 kb
Host smart-e66da5f5-cdc1-4491-a240-57f034ed9a64
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3114073334 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_back_pressure.3114073334
Directory /workspace/37.hmac_back_pressure/latest

Test location /workspace/coverage/default/37.hmac_burst_wr.1687911976
Short name T497
Test name
Test status
Simulation time 7743451914 ps
CPU time 48.71 seconds
Started Jul 01 04:43:51 PM PDT 24
Finished Jul 01 04:44:42 PM PDT 24
Peak memory 200416 kb
Host smart-913978cd-617a-4fef-bfad-5699711c3adc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687911976 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_burst_wr.1687911976
Directory /workspace/37.hmac_burst_wr/latest

Test location /workspace/coverage/default/37.hmac_datapath_stress.2638753293
Short name T286
Test name
Test status
Simulation time 3041960893 ps
CPU time 531.76 seconds
Started Jul 01 04:43:48 PM PDT 24
Finished Jul 01 04:52:41 PM PDT 24
Peak memory 600308 kb
Host smart-45e8c74c-4bbc-4cf0-be81-7cc056437b79
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2638753293 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_datapath_stress.2638753293
Directory /workspace/37.hmac_datapath_stress/latest

Test location /workspace/coverage/default/37.hmac_error.61026235
Short name T298
Test name
Test status
Simulation time 71769261492 ps
CPU time 203.25 seconds
Started Jul 01 04:43:48 PM PDT 24
Finished Jul 01 04:47:14 PM PDT 24
Peak memory 200412 kb
Host smart-7431f7b0-c3ca-4ee4-aba3-9832286c37cb
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61026235 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_error.61026235
Directory /workspace/37.hmac_error/latest

Test location /workspace/coverage/default/37.hmac_long_msg.1804317558
Short name T451
Test name
Test status
Simulation time 6397808770 ps
CPU time 109.15 seconds
Started Jul 01 04:43:47 PM PDT 24
Finished Jul 01 04:45:38 PM PDT 24
Peak memory 200476 kb
Host smart-9825fe5d-d3be-464c-9096-f13fa7ea652d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1804317558 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_long_msg.1804317558
Directory /workspace/37.hmac_long_msg/latest

Test location /workspace/coverage/default/37.hmac_smoke.405328660
Short name T258
Test name
Test status
Simulation time 801333908 ps
CPU time 5.13 seconds
Started Jul 01 04:43:49 PM PDT 24
Finished Jul 01 04:43:57 PM PDT 24
Peak memory 200376 kb
Host smart-f8d8ae7d-61db-4506-a6f3-22b032460234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=405328660 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_smoke.405328660
Directory /workspace/37.hmac_smoke/latest

Test location /workspace/coverage/default/37.hmac_stress_all.586341517
Short name T27
Test name
Test status
Simulation time 14557642741 ps
CPU time 1168.17 seconds
Started Jul 01 04:43:47 PM PDT 24
Finished Jul 01 05:03:16 PM PDT 24
Peak memory 655540 kb
Host smart-d40c9521-6b96-49c5-b1e5-cd41c9c8f76e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586341517 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 37.hmac_stress_all.586341517
Directory /workspace/37.hmac_stress_all/latest

Test location /workspace/coverage/default/37.hmac_wipe_secret.2043104484
Short name T440
Test name
Test status
Simulation time 7129434243 ps
CPU time 91.51 seconds
Started Jul 01 04:43:51 PM PDT 24
Finished Jul 01 04:45:25 PM PDT 24
Peak memory 200472 kb
Host smart-d9128adf-de5b-4712-a26b-01f4f0a43cb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043104484 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_wipe_secret.2043104484
Directory /workspace/37.hmac_wipe_secret/latest

Test location /workspace/coverage/default/38.hmac_alert_test.4088735033
Short name T354
Test name
Test status
Simulation time 16497250 ps
CPU time 0.62 seconds
Started Jul 01 04:43:55 PM PDT 24
Finished Jul 01 04:44:01 PM PDT 24
Peak memory 196844 kb
Host smart-d05bead9-e4f4-4551-bbbd-8edc04baebde
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088735033 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_alert_test.4088735033
Directory /workspace/38.hmac_alert_test/latest

Test location /workspace/coverage/default/38.hmac_back_pressure.116527061
Short name T9
Test name
Test status
Simulation time 960504203 ps
CPU time 53.68 seconds
Started Jul 01 04:43:55 PM PDT 24
Finished Jul 01 04:44:54 PM PDT 24
Peak memory 200288 kb
Host smart-980cb578-c412-4a6a-a4bf-d4cefa99f1e4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=116527061 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_back_pressure.116527061
Directory /workspace/38.hmac_back_pressure/latest

Test location /workspace/coverage/default/38.hmac_burst_wr.2549806564
Short name T31
Test name
Test status
Simulation time 14547530064 ps
CPU time 43.29 seconds
Started Jul 01 04:43:55 PM PDT 24
Finished Jul 01 04:44:44 PM PDT 24
Peak memory 200440 kb
Host smart-7ca85d7f-f751-4790-a43e-5147dea6f3ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2549806564 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_burst_wr.2549806564
Directory /workspace/38.hmac_burst_wr/latest

Test location /workspace/coverage/default/38.hmac_datapath_stress.313231941
Short name T463
Test name
Test status
Simulation time 3933217513 ps
CPU time 160.97 seconds
Started Jul 01 04:43:56 PM PDT 24
Finished Jul 01 04:46:42 PM PDT 24
Peak memory 437280 kb
Host smart-a2ed5f3c-6c62-4d21-b8af-7773eb486bd5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=313231941 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_datapath_stress.313231941
Directory /workspace/38.hmac_datapath_stress/latest

Test location /workspace/coverage/default/38.hmac_error.2342007859
Short name T419
Test name
Test status
Simulation time 5653188003 ps
CPU time 10.21 seconds
Started Jul 01 04:44:00 PM PDT 24
Finished Jul 01 04:44:14 PM PDT 24
Peak memory 200368 kb
Host smart-cb6a7bf0-59ee-4acd-8f60-cdb10af27bd9
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342007859 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_error.2342007859
Directory /workspace/38.hmac_error/latest

Test location /workspace/coverage/default/38.hmac_long_msg.4137649043
Short name T275
Test name
Test status
Simulation time 18380038194 ps
CPU time 39.66 seconds
Started Jul 01 04:43:53 PM PDT 24
Finished Jul 01 04:44:37 PM PDT 24
Peak memory 216840 kb
Host smart-6403b8e6-0574-406e-a956-8daa489ee270
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137649043 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_long_msg.4137649043
Directory /workspace/38.hmac_long_msg/latest

Test location /workspace/coverage/default/38.hmac_smoke.3438465404
Short name T478
Test name
Test status
Simulation time 154989330 ps
CPU time 1.83 seconds
Started Jul 01 04:43:49 PM PDT 24
Finished Jul 01 04:43:53 PM PDT 24
Peak memory 200296 kb
Host smart-a153b7d1-c533-4167-bf9e-a3be6ca30f3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438465404 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_smoke.3438465404
Directory /workspace/38.hmac_smoke/latest

Test location /workspace/coverage/default/38.hmac_stress_all.1601695488
Short name T11
Test name
Test status
Simulation time 76209523420 ps
CPU time 1818.46 seconds
Started Jul 01 04:43:54 PM PDT 24
Finished Jul 01 05:14:17 PM PDT 24
Peak memory 745600 kb
Host smart-742a65b7-ac14-4e10-9069-2930893df4b9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601695488 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.hmac_stress_all.1601695488
Directory /workspace/38.hmac_stress_all/latest

Test location /workspace/coverage/default/38.hmac_wipe_secret.723915396
Short name T453
Test name
Test status
Simulation time 29464911591 ps
CPU time 102.87 seconds
Started Jul 01 04:43:54 PM PDT 24
Finished Jul 01 04:45:42 PM PDT 24
Peak memory 200424 kb
Host smart-9bd6af92-489a-4f83-9a15-49d0bf3f42a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723915396 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_wipe_secret.723915396
Directory /workspace/38.hmac_wipe_secret/latest

Test location /workspace/coverage/default/39.hmac_alert_test.801557344
Short name T283
Test name
Test status
Simulation time 45113409 ps
CPU time 0.57 seconds
Started Jul 01 04:43:54 PM PDT 24
Finished Jul 01 04:43:59 PM PDT 24
Peak memory 195868 kb
Host smart-61eea0f7-362c-47ab-afe2-e4923273bcdf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801557344 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_alert_test.801557344
Directory /workspace/39.hmac_alert_test/latest

Test location /workspace/coverage/default/39.hmac_back_pressure.263223976
Short name T154
Test name
Test status
Simulation time 1890663428 ps
CPU time 30.06 seconds
Started Jul 01 04:43:56 PM PDT 24
Finished Jul 01 04:44:31 PM PDT 24
Peak memory 200372 kb
Host smart-8f83c2fa-e827-423c-ae40-c8b1a6d0091a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=263223976 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_back_pressure.263223976
Directory /workspace/39.hmac_back_pressure/latest

Test location /workspace/coverage/default/39.hmac_burst_wr.1554946113
Short name T405
Test name
Test status
Simulation time 76915626 ps
CPU time 2.19 seconds
Started Jul 01 04:43:57 PM PDT 24
Finished Jul 01 04:44:04 PM PDT 24
Peak memory 200308 kb
Host smart-cd3cb4d3-f973-4ce2-a612-9494d643b8e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554946113 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_burst_wr.1554946113
Directory /workspace/39.hmac_burst_wr/latest

Test location /workspace/coverage/default/39.hmac_datapath_stress.3397272018
Short name T333
Test name
Test status
Simulation time 3706633691 ps
CPU time 644.31 seconds
Started Jul 01 04:43:56 PM PDT 24
Finished Jul 01 04:54:45 PM PDT 24
Peak memory 700540 kb
Host smart-e4e4f2b6-1d43-4333-b8b7-e6afa1134773
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3397272018 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_datapath_stress.3397272018
Directory /workspace/39.hmac_datapath_stress/latest

Test location /workspace/coverage/default/39.hmac_error.579579036
Short name T481
Test name
Test status
Simulation time 589603254 ps
CPU time 16.21 seconds
Started Jul 01 04:43:58 PM PDT 24
Finished Jul 01 04:44:19 PM PDT 24
Peak memory 200492 kb
Host smart-6035ae73-4fde-4470-b1c4-cb3bcabfba0a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579579036 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_error.579579036
Directory /workspace/39.hmac_error/latest

Test location /workspace/coverage/default/39.hmac_long_msg.1602367269
Short name T475
Test name
Test status
Simulation time 11073883730 ps
CPU time 149.91 seconds
Started Jul 01 04:43:55 PM PDT 24
Finished Jul 01 04:46:30 PM PDT 24
Peak memory 200612 kb
Host smart-bd777bca-63de-4faa-a07c-f15b9a5a0e1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602367269 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_long_msg.1602367269
Directory /workspace/39.hmac_long_msg/latest

Test location /workspace/coverage/default/39.hmac_smoke.4288546608
Short name T3
Test name
Test status
Simulation time 3367521344 ps
CPU time 15.63 seconds
Started Jul 01 04:43:55 PM PDT 24
Finished Jul 01 04:44:15 PM PDT 24
Peak memory 200428 kb
Host smart-e0c2917f-bea7-4f79-8ba0-53a61bbd5412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288546608 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_smoke.4288546608
Directory /workspace/39.hmac_smoke/latest

Test location /workspace/coverage/default/39.hmac_stress_all.1979402754
Short name T28
Test name
Test status
Simulation time 122496834608 ps
CPU time 2317.88 seconds
Started Jul 01 04:43:56 PM PDT 24
Finished Jul 01 05:22:38 PM PDT 24
Peak memory 761036 kb
Host smart-e110e7ac-cc7d-435c-9fd7-c910661f7408
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979402754 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.hmac_stress_all.1979402754
Directory /workspace/39.hmac_stress_all/latest

Test location /workspace/coverage/default/39.hmac_wipe_secret.1760767342
Short name T368
Test name
Test status
Simulation time 9712611888 ps
CPU time 82.6 seconds
Started Jul 01 04:43:55 PM PDT 24
Finished Jul 01 04:45:23 PM PDT 24
Peak memory 200400 kb
Host smart-e5a71386-50f3-4560-a66c-ceab88d8262f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760767342 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_wipe_secret.1760767342
Directory /workspace/39.hmac_wipe_secret/latest

Test location /workspace/coverage/default/4.hmac_alert_test.4025338369
Short name T520
Test name
Test status
Simulation time 13004517 ps
CPU time 0.57 seconds
Started Jul 01 04:42:40 PM PDT 24
Finished Jul 01 04:42:57 PM PDT 24
Peak memory 196876 kb
Host smart-2bd5bcb6-ae27-469f-ad28-2b984a4935a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025338369 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_alert_test.4025338369
Directory /workspace/4.hmac_alert_test/latest

Test location /workspace/coverage/default/4.hmac_back_pressure.4150799892
Short name T383
Test name
Test status
Simulation time 703356114 ps
CPU time 42.31 seconds
Started Jul 01 04:42:37 PM PDT 24
Finished Jul 01 04:43:37 PM PDT 24
Peak memory 200292 kb
Host smart-c836ff9b-8d4a-4a33-a381-ff2d4dc8b975
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4150799892 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_back_pressure.4150799892
Directory /workspace/4.hmac_back_pressure/latest

Test location /workspace/coverage/default/4.hmac_burst_wr.2238713756
Short name T47
Test name
Test status
Simulation time 6182625044 ps
CPU time 43.23 seconds
Started Jul 01 04:42:33 PM PDT 24
Finished Jul 01 04:43:35 PM PDT 24
Peak memory 200476 kb
Host smart-64b652ca-74f0-48cf-bfe5-d44d036e8d4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238713756 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_burst_wr.2238713756
Directory /workspace/4.hmac_burst_wr/latest

Test location /workspace/coverage/default/4.hmac_datapath_stress.2804233491
Short name T216
Test name
Test status
Simulation time 445192035 ps
CPU time 61.45 seconds
Started Jul 01 04:42:38 PM PDT 24
Finished Jul 01 04:43:57 PM PDT 24
Peak memory 340216 kb
Host smart-df784e4c-6d26-41af-bdc8-738c6de0ad6f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2804233491 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_datapath_stress.2804233491
Directory /workspace/4.hmac_datapath_stress/latest

Test location /workspace/coverage/default/4.hmac_error.2620854130
Short name T362
Test name
Test status
Simulation time 9161259639 ps
CPU time 132.04 seconds
Started Jul 01 04:42:35 PM PDT 24
Finished Jul 01 04:45:05 PM PDT 24
Peak memory 200380 kb
Host smart-34c10e98-a298-41b9-94ec-48a2848e558a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620854130 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_error.2620854130
Directory /workspace/4.hmac_error/latest

Test location /workspace/coverage/default/4.hmac_long_msg.90132101
Short name T62
Test name
Test status
Simulation time 3145109966 ps
CPU time 55.43 seconds
Started Jul 01 04:42:39 PM PDT 24
Finished Jul 01 04:43:51 PM PDT 24
Peak memory 200428 kb
Host smart-47599c7b-60cd-4e53-a6a3-bae40656a4f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90132101 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_long_msg.90132101
Directory /workspace/4.hmac_long_msg/latest

Test location /workspace/coverage/default/4.hmac_sec_cm.1429732490
Short name T49
Test name
Test status
Simulation time 299359842 ps
CPU time 0.93 seconds
Started Jul 01 04:42:36 PM PDT 24
Finished Jul 01 04:42:54 PM PDT 24
Peak memory 218768 kb
Host smart-a1705ba7-16d9-4cf6-b412-d7e2223b4a37
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429732490 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_sec_cm.1429732490
Directory /workspace/4.hmac_sec_cm/latest

Test location /workspace/coverage/default/4.hmac_smoke.2193038757
Short name T38
Test name
Test status
Simulation time 310058313 ps
CPU time 14.75 seconds
Started Jul 01 04:42:32 PM PDT 24
Finished Jul 01 04:43:05 PM PDT 24
Peak memory 200332 kb
Host smart-31115ec7-2e79-48b1-9c03-e297b95a225c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193038757 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_smoke.2193038757
Directory /workspace/4.hmac_smoke/latest

Test location /workspace/coverage/default/4.hmac_stress_all.1571697586
Short name T83
Test name
Test status
Simulation time 439544454899 ps
CPU time 2632.03 seconds
Started Jul 01 04:42:40 PM PDT 24
Finished Jul 01 05:26:48 PM PDT 24
Peak memory 760560 kb
Host smart-a0edad84-9654-492d-bb13-c3f9393c0cba
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571697586 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all.1571697586
Directory /workspace/4.hmac_stress_all/latest

Test location /workspace/coverage/default/4.hmac_stress_all_with_rand_reset.4157730150
Short name T19
Test name
Test status
Simulation time 419389116065 ps
CPU time 1562.02 seconds
Started Jul 01 04:42:35 PM PDT 24
Finished Jul 01 05:08:55 PM PDT 24
Peak memory 716116 kb
Host smart-ba4456b6-c445-42c8-bb9c-868fcf82c1be
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4157730150 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all_with_rand_reset.4157730150
Directory /workspace/4.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.hmac_test_hmac256_vectors.3442921033
Short name T5
Test name
Test status
Simulation time 21774531377 ps
CPU time 42.08 seconds
Started Jul 01 04:42:36 PM PDT 24
Finished Jul 01 04:43:35 PM PDT 24
Peak memory 200476 kb
Host smart-87af1ac5-c487-4982-91dc-bc10cbae5522
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3442921033 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac256_vectors.3442921033
Directory /workspace/4.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_hmac384_vectors.1337392548
Short name T325
Test name
Test status
Simulation time 1750778946 ps
CPU time 54.41 seconds
Started Jul 01 04:42:34 PM PDT 24
Finished Jul 01 04:43:46 PM PDT 24
Peak memory 200296 kb
Host smart-a47b69da-ca26-45f7-a25b-3d1daf67118b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1337392548 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac384_vectors.1337392548
Directory /workspace/4.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_hmac512_vectors.2283330510
Short name T177
Test name
Test status
Simulation time 21712387889 ps
CPU time 120.29 seconds
Started Jul 01 04:42:39 PM PDT 24
Finished Jul 01 04:44:56 PM PDT 24
Peak memory 200220 kb
Host smart-e5f766f2-9e42-4fb3-a972-f1983e1a984f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2283330510 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac512_vectors.2283330510
Directory /workspace/4.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha256_vectors.3902371813
Short name T421
Test name
Test status
Simulation time 50694292278 ps
CPU time 653.39 seconds
Started Jul 01 04:42:40 PM PDT 24
Finished Jul 01 04:53:50 PM PDT 24
Peak memory 200372 kb
Host smart-543f24aa-fcd1-422d-9459-aaf5e32b35db
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3902371813 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha256_vectors.3902371813
Directory /workspace/4.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha384_vectors.33193571
Short name T530
Test name
Test status
Simulation time 143079890427 ps
CPU time 2432.97 seconds
Started Jul 01 04:42:32 PM PDT 24
Finished Jul 01 05:23:23 PM PDT 24
Peak memory 216132 kb
Host smart-fb689e5a-cc32-4054-a8d2-b51ecff03d4c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=33193571 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha384_vectors.33193571
Directory /workspace/4.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha512_vectors.2018873359
Short name T134
Test name
Test status
Simulation time 42191453752 ps
CPU time 2303.71 seconds
Started Jul 01 04:42:34 PM PDT 24
Finished Jul 01 05:21:16 PM PDT 24
Peak memory 215812 kb
Host smart-433acf11-e5ee-4ea4-8e84-27d29ef2c4dc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_200_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2018873359 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha512_vectors.2018873359
Directory /workspace/4.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/4.hmac_wipe_secret.1393217227
Short name T228
Test name
Test status
Simulation time 1218880586 ps
CPU time 22.15 seconds
Started Jul 01 04:42:39 PM PDT 24
Finished Jul 01 04:43:18 PM PDT 24
Peak memory 200304 kb
Host smart-0c89e4c9-f56b-4af5-a6ae-5ce41789f927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393217227 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_wipe_secret.1393217227
Directory /workspace/4.hmac_wipe_secret/latest

Test location /workspace/coverage/default/40.hmac_alert_test.1115135260
Short name T260
Test name
Test status
Simulation time 16879659 ps
CPU time 0.61 seconds
Started Jul 01 04:43:54 PM PDT 24
Finished Jul 01 04:43:59 PM PDT 24
Peak memory 196212 kb
Host smart-fadf8fd9-66f4-4e59-9de0-22dd525ec183
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115135260 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_alert_test.1115135260
Directory /workspace/40.hmac_alert_test/latest

Test location /workspace/coverage/default/40.hmac_back_pressure.3921699233
Short name T407
Test name
Test status
Simulation time 1360014354 ps
CPU time 19.16 seconds
Started Jul 01 04:43:55 PM PDT 24
Finished Jul 01 04:44:19 PM PDT 24
Peak memory 200184 kb
Host smart-a02dc87f-cb9e-400e-9da9-79d67fab2f9f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3921699233 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_back_pressure.3921699233
Directory /workspace/40.hmac_back_pressure/latest

Test location /workspace/coverage/default/40.hmac_burst_wr.1061590068
Short name T380
Test name
Test status
Simulation time 2724698282 ps
CPU time 51.81 seconds
Started Jul 01 04:43:57 PM PDT 24
Finished Jul 01 04:44:54 PM PDT 24
Peak memory 200428 kb
Host smart-136aa1f8-4f95-4964-88c3-a93299e14a18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061590068 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_burst_wr.1061590068
Directory /workspace/40.hmac_burst_wr/latest

Test location /workspace/coverage/default/40.hmac_datapath_stress.3220073432
Short name T178
Test name
Test status
Simulation time 4199705676 ps
CPU time 332.19 seconds
Started Jul 01 04:43:55 PM PDT 24
Finished Jul 01 04:49:33 PM PDT 24
Peak memory 464964 kb
Host smart-efa74ea6-d6d2-42fb-bfdc-0433156d09ad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3220073432 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_datapath_stress.3220073432
Directory /workspace/40.hmac_datapath_stress/latest

Test location /workspace/coverage/default/40.hmac_error.2851891519
Short name T174
Test name
Test status
Simulation time 858317189 ps
CPU time 9.87 seconds
Started Jul 01 04:43:55 PM PDT 24
Finished Jul 01 04:44:10 PM PDT 24
Peak memory 200172 kb
Host smart-ff44e320-6c03-4f9d-982e-7083530f6e0b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851891519 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_error.2851891519
Directory /workspace/40.hmac_error/latest

Test location /workspace/coverage/default/40.hmac_long_msg.2222140724
Short name T276
Test name
Test status
Simulation time 10722621034 ps
CPU time 134.05 seconds
Started Jul 01 04:43:54 PM PDT 24
Finished Jul 01 04:46:13 PM PDT 24
Peak memory 200432 kb
Host smart-9b5b66e2-ddac-4829-981a-6b4a004436a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222140724 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_long_msg.2222140724
Directory /workspace/40.hmac_long_msg/latest

Test location /workspace/coverage/default/40.hmac_smoke.1865259794
Short name T172
Test name
Test status
Simulation time 3340010311 ps
CPU time 14.1 seconds
Started Jul 01 04:43:57 PM PDT 24
Finished Jul 01 04:44:16 PM PDT 24
Peak memory 200424 kb
Host smart-7d1121e5-e33d-4aef-9d4e-2553a152ffe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865259794 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_smoke.1865259794
Directory /workspace/40.hmac_smoke/latest

Test location /workspace/coverage/default/40.hmac_stress_all.2104516105
Short name T76
Test name
Test status
Simulation time 48836910136 ps
CPU time 1532.99 seconds
Started Jul 01 04:43:55 PM PDT 24
Finished Jul 01 05:09:33 PM PDT 24
Peak memory 792064 kb
Host smart-bee5e585-87c6-40ee-8b4d-a5066051e1d1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104516105 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.hmac_stress_all.2104516105
Directory /workspace/40.hmac_stress_all/latest

Test location /workspace/coverage/default/40.hmac_wipe_secret.2751156798
Short name T323
Test name
Test status
Simulation time 3169408469 ps
CPU time 20.43 seconds
Started Jul 01 04:43:55 PM PDT 24
Finished Jul 01 04:44:20 PM PDT 24
Peak memory 200396 kb
Host smart-6211b24a-689c-4f99-88aa-ff04dde0038c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751156798 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_wipe_secret.2751156798
Directory /workspace/40.hmac_wipe_secret/latest

Test location /workspace/coverage/default/41.hmac_alert_test.1367332202
Short name T338
Test name
Test status
Simulation time 14274688 ps
CPU time 0.58 seconds
Started Jul 01 04:44:03 PM PDT 24
Finished Jul 01 04:44:06 PM PDT 24
Peak memory 196224 kb
Host smart-5e43399a-b654-4f6f-927e-d407dd04e6f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367332202 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_alert_test.1367332202
Directory /workspace/41.hmac_alert_test/latest

Test location /workspace/coverage/default/41.hmac_back_pressure.1265871500
Short name T477
Test name
Test status
Simulation time 5146649041 ps
CPU time 25 seconds
Started Jul 01 04:44:00 PM PDT 24
Finished Jul 01 04:44:29 PM PDT 24
Peak memory 200372 kb
Host smart-ada6fd95-4863-4505-a269-8e1629ecd65d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1265871500 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_back_pressure.1265871500
Directory /workspace/41.hmac_back_pressure/latest

Test location /workspace/coverage/default/41.hmac_burst_wr.803609457
Short name T166
Test name
Test status
Simulation time 6768268823 ps
CPU time 64.66 seconds
Started Jul 01 04:44:02 PM PDT 24
Finished Jul 01 04:45:09 PM PDT 24
Peak memory 208724 kb
Host smart-7df651a9-c973-456b-a7d4-2becba30c06c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803609457 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_burst_wr.803609457
Directory /workspace/41.hmac_burst_wr/latest

Test location /workspace/coverage/default/41.hmac_datapath_stress.1442583451
Short name T415
Test name
Test status
Simulation time 5601936900 ps
CPU time 239.73 seconds
Started Jul 01 04:43:55 PM PDT 24
Finished Jul 01 04:48:00 PM PDT 24
Peak memory 442292 kb
Host smart-b98d823d-5999-4f9c-a81f-0e0aa9fc08a1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1442583451 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_datapath_stress.1442583451
Directory /workspace/41.hmac_datapath_stress/latest

Test location /workspace/coverage/default/41.hmac_error.2758524100
Short name T131
Test name
Test status
Simulation time 61954251 ps
CPU time 0.68 seconds
Started Jul 01 04:44:03 PM PDT 24
Finished Jul 01 04:44:06 PM PDT 24
Peak memory 196628 kb
Host smart-2c08948f-9868-4f95-ba8e-ba0a72c03704
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758524100 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_error.2758524100
Directory /workspace/41.hmac_error/latest

Test location /workspace/coverage/default/41.hmac_long_msg.3058635553
Short name T399
Test name
Test status
Simulation time 3361796250 ps
CPU time 182.09 seconds
Started Jul 01 04:43:57 PM PDT 24
Finished Jul 01 04:47:04 PM PDT 24
Peak memory 200416 kb
Host smart-367cca5a-0c93-476d-bb91-6e8d02f21fdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058635553 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_long_msg.3058635553
Directory /workspace/41.hmac_long_msg/latest

Test location /workspace/coverage/default/41.hmac_smoke.1827361739
Short name T284
Test name
Test status
Simulation time 7418820374 ps
CPU time 13.92 seconds
Started Jul 01 04:43:56 PM PDT 24
Finished Jul 01 04:44:15 PM PDT 24
Peak memory 200516 kb
Host smart-ba742242-2530-4985-8f73-fad7a1e4eb47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827361739 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_smoke.1827361739
Directory /workspace/41.hmac_smoke/latest

Test location /workspace/coverage/default/41.hmac_stress_all.2185943289
Short name T22
Test name
Test status
Simulation time 20123757922 ps
CPU time 1864.31 seconds
Started Jul 01 04:44:01 PM PDT 24
Finished Jul 01 05:15:09 PM PDT 24
Peak memory 724892 kb
Host smart-7d5196c0-a65c-4a8c-8e6e-2d814162972c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185943289 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.hmac_stress_all.2185943289
Directory /workspace/41.hmac_stress_all/latest

Test location /workspace/coverage/default/41.hmac_wipe_secret.990224508
Short name T356
Test name
Test status
Simulation time 1743334955 ps
CPU time 20.01 seconds
Started Jul 01 04:44:02 PM PDT 24
Finished Jul 01 04:44:25 PM PDT 24
Peak memory 200356 kb
Host smart-b8a982f0-dd5e-4e34-a064-2489931b3165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990224508 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_wipe_secret.990224508
Directory /workspace/41.hmac_wipe_secret/latest

Test location /workspace/coverage/default/42.hmac_alert_test.2270876262
Short name T396
Test name
Test status
Simulation time 32943938 ps
CPU time 0.59 seconds
Started Jul 01 04:44:03 PM PDT 24
Finished Jul 01 04:44:06 PM PDT 24
Peak memory 196224 kb
Host smart-f80353f3-7b3b-48f2-b8a9-58a31c736ccb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270876262 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_alert_test.2270876262
Directory /workspace/42.hmac_alert_test/latest

Test location /workspace/coverage/default/42.hmac_back_pressure.3223301799
Short name T198
Test name
Test status
Simulation time 5661931181 ps
CPU time 85.02 seconds
Started Jul 01 04:44:01 PM PDT 24
Finished Jul 01 04:45:29 PM PDT 24
Peak memory 200396 kb
Host smart-7417f618-0ef2-4f52-abc3-ae9d503e273c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3223301799 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_back_pressure.3223301799
Directory /workspace/42.hmac_back_pressure/latest

Test location /workspace/coverage/default/42.hmac_burst_wr.3644336167
Short name T349
Test name
Test status
Simulation time 5878064570 ps
CPU time 74.26 seconds
Started Jul 01 04:44:02 PM PDT 24
Finished Jul 01 04:45:19 PM PDT 24
Peak memory 200548 kb
Host smart-fa77e402-448f-437f-8bf4-f7ff0426e233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3644336167 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_burst_wr.3644336167
Directory /workspace/42.hmac_burst_wr/latest

Test location /workspace/coverage/default/42.hmac_datapath_stress.3320758003
Short name T285
Test name
Test status
Simulation time 7071877420 ps
CPU time 1459.66 seconds
Started Jul 01 04:44:03 PM PDT 24
Finished Jul 01 05:08:25 PM PDT 24
Peak memory 762580 kb
Host smart-604c7ee5-dfb7-48ac-bfa9-eaa4cfe6e55e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3320758003 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_datapath_stress.3320758003
Directory /workspace/42.hmac_datapath_stress/latest

Test location /workspace/coverage/default/42.hmac_error.3446709642
Short name T240
Test name
Test status
Simulation time 18040019482 ps
CPU time 80.1 seconds
Started Jul 01 04:44:05 PM PDT 24
Finished Jul 01 04:45:27 PM PDT 24
Peak memory 200332 kb
Host smart-ad264af6-b75b-484a-b6ca-8e2faa2b18e7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446709642 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_error.3446709642
Directory /workspace/42.hmac_error/latest

Test location /workspace/coverage/default/42.hmac_long_msg.1810751293
Short name T70
Test name
Test status
Simulation time 3332795067 ps
CPU time 43.97 seconds
Started Jul 01 04:44:04 PM PDT 24
Finished Jul 01 04:44:50 PM PDT 24
Peak memory 200248 kb
Host smart-599d1b7a-5547-48a1-aacf-6c2e4b00c27f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810751293 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_long_msg.1810751293
Directory /workspace/42.hmac_long_msg/latest

Test location /workspace/coverage/default/42.hmac_smoke.2065337880
Short name T377
Test name
Test status
Simulation time 2525871271 ps
CPU time 7.72 seconds
Started Jul 01 04:44:01 PM PDT 24
Finished Jul 01 04:44:12 PM PDT 24
Peak memory 200360 kb
Host smart-76f2d99f-f9a7-4811-9bee-f3255aa29e5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065337880 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_smoke.2065337880
Directory /workspace/42.hmac_smoke/latest

Test location /workspace/coverage/default/42.hmac_stress_all.552184419
Short name T348
Test name
Test status
Simulation time 18462299 ps
CPU time 0.61 seconds
Started Jul 01 04:44:02 PM PDT 24
Finished Jul 01 04:44:06 PM PDT 24
Peak memory 195976 kb
Host smart-b0ec6c8c-c1b1-45ee-a16a-6a14e2d2075a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552184419 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 42.hmac_stress_all.552184419
Directory /workspace/42.hmac_stress_all/latest

Test location /workspace/coverage/default/42.hmac_wipe_secret.2793382158
Short name T250
Test name
Test status
Simulation time 10764928588 ps
CPU time 92.82 seconds
Started Jul 01 04:44:03 PM PDT 24
Finished Jul 01 04:45:38 PM PDT 24
Peak memory 200432 kb
Host smart-3bccf600-fc4f-46a4-a1df-a334c607cf00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793382158 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_wipe_secret.2793382158
Directory /workspace/42.hmac_wipe_secret/latest

Test location /workspace/coverage/default/43.hmac_alert_test.3553235128
Short name T289
Test name
Test status
Simulation time 12239194 ps
CPU time 0.59 seconds
Started Jul 01 04:44:10 PM PDT 24
Finished Jul 01 04:44:12 PM PDT 24
Peak memory 195196 kb
Host smart-eab34698-7e0f-4247-8d45-103060207252
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553235128 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_alert_test.3553235128
Directory /workspace/43.hmac_alert_test/latest

Test location /workspace/coverage/default/43.hmac_back_pressure.3714060617
Short name T204
Test name
Test status
Simulation time 538322498 ps
CPU time 7.72 seconds
Started Jul 01 04:44:08 PM PDT 24
Finished Jul 01 04:44:17 PM PDT 24
Peak memory 200300 kb
Host smart-5a32a30d-fce8-41e0-8689-35a1d2930426
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3714060617 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_back_pressure.3714060617
Directory /workspace/43.hmac_back_pressure/latest

Test location /workspace/coverage/default/43.hmac_burst_wr.230593961
Short name T444
Test name
Test status
Simulation time 2803940016 ps
CPU time 52.51 seconds
Started Jul 01 04:44:08 PM PDT 24
Finished Jul 01 04:45:02 PM PDT 24
Peak memory 200460 kb
Host smart-0eb7d5a3-0e56-4139-86c4-0f8224af2a0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230593961 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_burst_wr.230593961
Directory /workspace/43.hmac_burst_wr/latest

Test location /workspace/coverage/default/43.hmac_datapath_stress.4036013058
Short name T242
Test name
Test status
Simulation time 3643740753 ps
CPU time 594.2 seconds
Started Jul 01 04:44:08 PM PDT 24
Finished Jul 01 04:54:04 PM PDT 24
Peak memory 628416 kb
Host smart-e807eac9-034a-410a-98c1-d0475be5f428
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4036013058 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_datapath_stress.4036013058
Directory /workspace/43.hmac_datapath_stress/latest

Test location /workspace/coverage/default/43.hmac_error.3225071010
Short name T212
Test name
Test status
Simulation time 98400357529 ps
CPU time 183.8 seconds
Started Jul 01 04:44:09 PM PDT 24
Finished Jul 01 04:47:15 PM PDT 24
Peak memory 200412 kb
Host smart-c17825ba-bcce-4e19-a25f-8f2798b0ceb7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225071010 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_error.3225071010
Directory /workspace/43.hmac_error/latest

Test location /workspace/coverage/default/43.hmac_long_msg.1621745209
Short name T392
Test name
Test status
Simulation time 3038444683 ps
CPU time 172.55 seconds
Started Jul 01 04:44:09 PM PDT 24
Finished Jul 01 04:47:04 PM PDT 24
Peak memory 200492 kb
Host smart-38e21329-70da-414f-9f47-3c962050af57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621745209 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_long_msg.1621745209
Directory /workspace/43.hmac_long_msg/latest

Test location /workspace/coverage/default/43.hmac_smoke.1392047901
Short name T245
Test name
Test status
Simulation time 109347802 ps
CPU time 5.38 seconds
Started Jul 01 04:44:02 PM PDT 24
Finished Jul 01 04:44:10 PM PDT 24
Peak memory 200404 kb
Host smart-bcb7baed-7db1-49b2-9e2e-e1a0ec788019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1392047901 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_smoke.1392047901
Directory /workspace/43.hmac_smoke/latest

Test location /workspace/coverage/default/43.hmac_stress_all.1063312773
Short name T347
Test name
Test status
Simulation time 1685231556 ps
CPU time 97.65 seconds
Started Jul 01 04:44:07 PM PDT 24
Finished Jul 01 04:45:47 PM PDT 24
Peak memory 200264 kb
Host smart-2cecf545-8a08-4398-9002-6cbf4c723534
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063312773 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.hmac_stress_all.1063312773
Directory /workspace/43.hmac_stress_all/latest

Test location /workspace/coverage/default/43.hmac_wipe_secret.2015187773
Short name T350
Test name
Test status
Simulation time 4467351489 ps
CPU time 63.66 seconds
Started Jul 01 04:44:09 PM PDT 24
Finished Jul 01 04:45:14 PM PDT 24
Peak memory 200472 kb
Host smart-2875f02e-26d3-4163-a7c6-25f81ddd749e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015187773 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_wipe_secret.2015187773
Directory /workspace/43.hmac_wipe_secret/latest

Test location /workspace/coverage/default/44.hmac_alert_test.2678264850
Short name T474
Test name
Test status
Simulation time 56621828 ps
CPU time 0.61 seconds
Started Jul 01 04:44:10 PM PDT 24
Finished Jul 01 04:44:12 PM PDT 24
Peak memory 195876 kb
Host smart-028b1c4b-8977-4c79-8858-46c642fafc56
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678264850 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_alert_test.2678264850
Directory /workspace/44.hmac_alert_test/latest

Test location /workspace/coverage/default/44.hmac_back_pressure.1045583628
Short name T29
Test name
Test status
Simulation time 3367704754 ps
CPU time 54.3 seconds
Started Jul 01 04:44:10 PM PDT 24
Finished Jul 01 04:45:06 PM PDT 24
Peak memory 200352 kb
Host smart-6e860743-fa8c-4762-b804-a58cb74206b8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1045583628 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_back_pressure.1045583628
Directory /workspace/44.hmac_back_pressure/latest

Test location /workspace/coverage/default/44.hmac_burst_wr.2330493406
Short name T157
Test name
Test status
Simulation time 10722486786 ps
CPU time 28.4 seconds
Started Jul 01 04:44:08 PM PDT 24
Finished Jul 01 04:44:39 PM PDT 24
Peak memory 200436 kb
Host smart-0394b8fd-e110-4c60-88b7-7390aa27dc3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330493406 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_burst_wr.2330493406
Directory /workspace/44.hmac_burst_wr/latest

Test location /workspace/coverage/default/44.hmac_datapath_stress.1838300591
Short name T200
Test name
Test status
Simulation time 8815120083 ps
CPU time 198.33 seconds
Started Jul 01 04:44:09 PM PDT 24
Finished Jul 01 04:47:29 PM PDT 24
Peak memory 612140 kb
Host smart-fd1c0d09-8c12-409b-b12b-a92fca48f1fe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1838300591 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_datapath_stress.1838300591
Directory /workspace/44.hmac_datapath_stress/latest

Test location /workspace/coverage/default/44.hmac_error.2500876210
Short name T39
Test name
Test status
Simulation time 364482643 ps
CPU time 19.44 seconds
Started Jul 01 04:44:10 PM PDT 24
Finished Jul 01 04:44:31 PM PDT 24
Peak memory 200292 kb
Host smart-05916f9f-1a5c-43bf-bb82-df376bf3f5a6
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500876210 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_error.2500876210
Directory /workspace/44.hmac_error/latest

Test location /workspace/coverage/default/44.hmac_long_msg.3992669841
Short name T448
Test name
Test status
Simulation time 11904099972 ps
CPU time 210.43 seconds
Started Jul 01 04:44:10 PM PDT 24
Finished Jul 01 04:47:42 PM PDT 24
Peak memory 208632 kb
Host smart-708182af-9354-4ecb-87be-7038f0aca519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992669841 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_long_msg.3992669841
Directory /workspace/44.hmac_long_msg/latest

Test location /workspace/coverage/default/44.hmac_smoke.2901736038
Short name T158
Test name
Test status
Simulation time 463121242 ps
CPU time 5.67 seconds
Started Jul 01 04:44:08 PM PDT 24
Finished Jul 01 04:44:15 PM PDT 24
Peak memory 200332 kb
Host smart-f1750ff2-7835-4c25-aa03-cf2f39188da5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901736038 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_smoke.2901736038
Directory /workspace/44.hmac_smoke/latest

Test location /workspace/coverage/default/44.hmac_stress_all.433300342
Short name T231
Test name
Test status
Simulation time 81573259004 ps
CPU time 1910.43 seconds
Started Jul 01 04:44:08 PM PDT 24
Finished Jul 01 05:16:00 PM PDT 24
Peak memory 725836 kb
Host smart-089f4f0d-ca4b-4f36-b00c-af544ecc7e4c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433300342 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 44.hmac_stress_all.433300342
Directory /workspace/44.hmac_stress_all/latest

Test location /workspace/coverage/default/44.hmac_wipe_secret.3621458719
Short name T25
Test name
Test status
Simulation time 17067746254 ps
CPU time 31.26 seconds
Started Jul 01 04:44:07 PM PDT 24
Finished Jul 01 04:44:40 PM PDT 24
Peak memory 200428 kb
Host smart-71a9a0fa-97a5-4a02-a15d-c0bcaf5b08fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621458719 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_wipe_secret.3621458719
Directory /workspace/44.hmac_wipe_secret/latest

Test location /workspace/coverage/default/45.hmac_alert_test.479864674
Short name T244
Test name
Test status
Simulation time 13381481 ps
CPU time 0.6 seconds
Started Jul 01 04:44:15 PM PDT 24
Finished Jul 01 04:44:17 PM PDT 24
Peak memory 196244 kb
Host smart-37944300-439a-4a15-842e-412458aca668
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479864674 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_alert_test.479864674
Directory /workspace/45.hmac_alert_test/latest

Test location /workspace/coverage/default/45.hmac_back_pressure.1158913764
Short name T1
Test name
Test status
Simulation time 759912099 ps
CPU time 11.9 seconds
Started Jul 01 04:44:16 PM PDT 24
Finished Jul 01 04:44:31 PM PDT 24
Peak memory 200288 kb
Host smart-51827ebd-c706-4c10-a30b-e212748ec748
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1158913764 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_back_pressure.1158913764
Directory /workspace/45.hmac_back_pressure/latest

Test location /workspace/coverage/default/45.hmac_burst_wr.475292232
Short name T241
Test name
Test status
Simulation time 1012438074 ps
CPU time 19.08 seconds
Started Jul 01 04:44:16 PM PDT 24
Finished Jul 01 04:44:39 PM PDT 24
Peak memory 200352 kb
Host smart-f385bdb7-b8da-4f64-b792-818d44d7ca47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475292232 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_burst_wr.475292232
Directory /workspace/45.hmac_burst_wr/latest

Test location /workspace/coverage/default/45.hmac_datapath_stress.952859961
Short name T509
Test name
Test status
Simulation time 6382621430 ps
CPU time 225.42 seconds
Started Jul 01 04:44:16 PM PDT 24
Finished Jul 01 04:48:04 PM PDT 24
Peak memory 643244 kb
Host smart-31f79c4e-79fb-4c2d-88d9-179be469a1a3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=952859961 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_datapath_stress.952859961
Directory /workspace/45.hmac_datapath_stress/latest

Test location /workspace/coverage/default/45.hmac_error.3815668591
Short name T135
Test name
Test status
Simulation time 4112483987 ps
CPU time 112.48 seconds
Started Jul 01 04:44:15 PM PDT 24
Finished Jul 01 04:46:10 PM PDT 24
Peak memory 200336 kb
Host smart-52c1d3dd-518e-4cdb-84b8-0c9c69fced07
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815668591 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_error.3815668591
Directory /workspace/45.hmac_error/latest

Test location /workspace/coverage/default/45.hmac_long_msg.173530685
Short name T357
Test name
Test status
Simulation time 31832035496 ps
CPU time 132.09 seconds
Started Jul 01 04:44:18 PM PDT 24
Finished Jul 01 04:46:33 PM PDT 24
Peak memory 200440 kb
Host smart-ad1f96ea-8036-44d4-971d-d9339ee3ff87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173530685 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_long_msg.173530685
Directory /workspace/45.hmac_long_msg/latest

Test location /workspace/coverage/default/45.hmac_smoke.3567301835
Short name T522
Test name
Test status
Simulation time 1362368343 ps
CPU time 5.19 seconds
Started Jul 01 04:44:09 PM PDT 24
Finished Jul 01 04:44:16 PM PDT 24
Peak memory 200316 kb
Host smart-fc74e631-31a0-45f1-9e67-738279d8d9a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567301835 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_smoke.3567301835
Directory /workspace/45.hmac_smoke/latest

Test location /workspace/coverage/default/45.hmac_stress_all.2044442577
Short name T389
Test name
Test status
Simulation time 107929010766 ps
CPU time 1387.98 seconds
Started Jul 01 04:44:16 PM PDT 24
Finished Jul 01 05:07:28 PM PDT 24
Peak memory 757692 kb
Host smart-3fd58afb-cd78-4287-aab2-d703cd45d18b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044442577 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.hmac_stress_all.2044442577
Directory /workspace/45.hmac_stress_all/latest

Test location /workspace/coverage/default/45.hmac_wipe_secret.3976391797
Short name T81
Test name
Test status
Simulation time 9852221832 ps
CPU time 127.9 seconds
Started Jul 01 04:44:18 PM PDT 24
Finished Jul 01 04:46:28 PM PDT 24
Peak memory 200476 kb
Host smart-6b7aa30a-809f-43d4-a780-db581f18622c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976391797 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_wipe_secret.3976391797
Directory /workspace/45.hmac_wipe_secret/latest

Test location /workspace/coverage/default/46.hmac_alert_test.1352076618
Short name T43
Test name
Test status
Simulation time 44192170 ps
CPU time 0.56 seconds
Started Jul 01 04:44:18 PM PDT 24
Finished Jul 01 04:44:21 PM PDT 24
Peak memory 195204 kb
Host smart-a0a1a434-873b-45ae-8586-b6e818861cc6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352076618 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_alert_test.1352076618
Directory /workspace/46.hmac_alert_test/latest

Test location /workspace/coverage/default/46.hmac_back_pressure.1701717484
Short name T398
Test name
Test status
Simulation time 1557294979 ps
CPU time 85.86 seconds
Started Jul 01 04:44:16 PM PDT 24
Finished Jul 01 04:45:45 PM PDT 24
Peak memory 200224 kb
Host smart-f0eccbb7-4e4d-4597-8fe6-35876e45c06a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1701717484 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_back_pressure.1701717484
Directory /workspace/46.hmac_back_pressure/latest

Test location /workspace/coverage/default/46.hmac_burst_wr.2880135228
Short name T331
Test name
Test status
Simulation time 882659123 ps
CPU time 49.75 seconds
Started Jul 01 04:44:16 PM PDT 24
Finished Jul 01 04:45:09 PM PDT 24
Peak memory 200516 kb
Host smart-b7be3140-6d62-46fa-b3e2-b0b3ab5c138b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880135228 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_burst_wr.2880135228
Directory /workspace/46.hmac_burst_wr/latest

Test location /workspace/coverage/default/46.hmac_datapath_stress.3453476837
Short name T233
Test name
Test status
Simulation time 8413427390 ps
CPU time 233.56 seconds
Started Jul 01 04:44:17 PM PDT 24
Finished Jul 01 04:48:13 PM PDT 24
Peak memory 662012 kb
Host smart-5fcc34e0-b9f3-468a-9cca-43ba1e145316
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3453476837 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_datapath_stress.3453476837
Directory /workspace/46.hmac_datapath_stress/latest

Test location /workspace/coverage/default/46.hmac_error.1215966221
Short name T181
Test name
Test status
Simulation time 6184293623 ps
CPU time 81.45 seconds
Started Jul 01 04:44:16 PM PDT 24
Finished Jul 01 04:45:41 PM PDT 24
Peak memory 200360 kb
Host smart-1fbe6b50-2c11-4610-8700-79efd55c24df
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215966221 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_error.1215966221
Directory /workspace/46.hmac_error/latest

Test location /workspace/coverage/default/46.hmac_long_msg.488293295
Short name T410
Test name
Test status
Simulation time 1989280199 ps
CPU time 113.32 seconds
Started Jul 01 04:44:15 PM PDT 24
Finished Jul 01 04:46:10 PM PDT 24
Peak memory 200308 kb
Host smart-55904580-e5f4-415f-8fba-14a57406c828
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488293295 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_long_msg.488293295
Directory /workspace/46.hmac_long_msg/latest

Test location /workspace/coverage/default/46.hmac_smoke.1433733724
Short name T420
Test name
Test status
Simulation time 285750310 ps
CPU time 5.2 seconds
Started Jul 01 04:44:18 PM PDT 24
Finished Jul 01 04:44:25 PM PDT 24
Peak memory 200356 kb
Host smart-f0ce740c-3c33-4db6-a79a-34675bfc8939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433733724 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_smoke.1433733724
Directory /workspace/46.hmac_smoke/latest

Test location /workspace/coverage/default/46.hmac_stress_all.238576224
Short name T521
Test name
Test status
Simulation time 65895285358 ps
CPU time 596.51 seconds
Started Jul 01 04:44:20 PM PDT 24
Finished Jul 01 04:54:18 PM PDT 24
Peak memory 200336 kb
Host smart-d339223b-685e-45d8-bf54-255823dd0b22
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238576224 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 46.hmac_stress_all.238576224
Directory /workspace/46.hmac_stress_all/latest

Test location /workspace/coverage/default/46.hmac_wipe_secret.2026527234
Short name T485
Test name
Test status
Simulation time 6391725164 ps
CPU time 102 seconds
Started Jul 01 04:44:16 PM PDT 24
Finished Jul 01 04:46:02 PM PDT 24
Peak memory 200432 kb
Host smart-613b3972-2242-4a36-9fde-0250da5a6256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026527234 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_wipe_secret.2026527234
Directory /workspace/46.hmac_wipe_secret/latest

Test location /workspace/coverage/default/47.hmac_alert_test.1711691927
Short name T197
Test name
Test status
Simulation time 30964564 ps
CPU time 0.57 seconds
Started Jul 01 04:44:24 PM PDT 24
Finished Jul 01 04:44:27 PM PDT 24
Peak memory 195204 kb
Host smart-fd818cc4-74e1-4847-a0e5-32c809ffeb3f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711691927 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_alert_test.1711691927
Directory /workspace/47.hmac_alert_test/latest

Test location /workspace/coverage/default/47.hmac_back_pressure.357104219
Short name T268
Test name
Test status
Simulation time 3829323601 ps
CPU time 61.99 seconds
Started Jul 01 04:44:16 PM PDT 24
Finished Jul 01 04:45:21 PM PDT 24
Peak memory 200404 kb
Host smart-a0e9391b-0c67-4349-97f8-9861f070cfbd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=357104219 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_back_pressure.357104219
Directory /workspace/47.hmac_back_pressure/latest

Test location /workspace/coverage/default/47.hmac_burst_wr.3628176564
Short name T513
Test name
Test status
Simulation time 262465582 ps
CPU time 7.12 seconds
Started Jul 01 04:44:23 PM PDT 24
Finished Jul 01 04:44:33 PM PDT 24
Peak memory 200396 kb
Host smart-bd05dba4-e422-420d-b9d6-b0675190cfe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628176564 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_burst_wr.3628176564
Directory /workspace/47.hmac_burst_wr/latest

Test location /workspace/coverage/default/47.hmac_datapath_stress.2419010861
Short name T299
Test name
Test status
Simulation time 12638228650 ps
CPU time 535.2 seconds
Started Jul 01 04:44:22 PM PDT 24
Finished Jul 01 04:53:19 PM PDT 24
Peak memory 669980 kb
Host smart-0593c03c-d93a-41c1-8dbc-932ed8d35ab4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2419010861 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_datapath_stress.2419010861
Directory /workspace/47.hmac_datapath_stress/latest

Test location /workspace/coverage/default/47.hmac_error.2746418823
Short name T423
Test name
Test status
Simulation time 17875049544 ps
CPU time 55.53 seconds
Started Jul 01 04:44:22 PM PDT 24
Finished Jul 01 04:45:20 PM PDT 24
Peak memory 200384 kb
Host smart-f49b15aa-7a00-4c29-b1c0-dff9f5aeec3a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746418823 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_error.2746418823
Directory /workspace/47.hmac_error/latest

Test location /workspace/coverage/default/47.hmac_long_msg.1771593818
Short name T302
Test name
Test status
Simulation time 7650047060 ps
CPU time 35.08 seconds
Started Jul 01 04:44:20 PM PDT 24
Finished Jul 01 04:44:56 PM PDT 24
Peak memory 200484 kb
Host smart-6a64b4cc-f1e3-402c-a7a5-b25cfe4dd399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771593818 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_long_msg.1771593818
Directory /workspace/47.hmac_long_msg/latest

Test location /workspace/coverage/default/47.hmac_smoke.357967012
Short name T163
Test name
Test status
Simulation time 989354817 ps
CPU time 8.4 seconds
Started Jul 01 04:44:16 PM PDT 24
Finished Jul 01 04:44:27 PM PDT 24
Peak memory 200292 kb
Host smart-7501e1b9-e161-41d5-b936-9f76c691fefc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357967012 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_smoke.357967012
Directory /workspace/47.hmac_smoke/latest

Test location /workspace/coverage/default/47.hmac_stress_all.314020711
Short name T431
Test name
Test status
Simulation time 24820839831 ps
CPU time 2726.89 seconds
Started Jul 01 04:44:23 PM PDT 24
Finished Jul 01 05:29:53 PM PDT 24
Peak memory 786864 kb
Host smart-1f3729f3-dc1c-46fe-a26b-1b216f0e8d0b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314020711 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 47.hmac_stress_all.314020711
Directory /workspace/47.hmac_stress_all/latest

Test location /workspace/coverage/default/47.hmac_wipe_secret.582273073
Short name T472
Test name
Test status
Simulation time 817211805 ps
CPU time 49.18 seconds
Started Jul 01 04:44:23 PM PDT 24
Finished Jul 01 04:45:15 PM PDT 24
Peak memory 200324 kb
Host smart-0473887e-ea70-4f92-b7b5-dc8054b42882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=582273073 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_wipe_secret.582273073
Directory /workspace/47.hmac_wipe_secret/latest

Test location /workspace/coverage/default/48.hmac_alert_test.378600198
Short name T359
Test name
Test status
Simulation time 57024824 ps
CPU time 0.57 seconds
Started Jul 01 04:44:26 PM PDT 24
Finished Jul 01 04:44:28 PM PDT 24
Peak memory 195116 kb
Host smart-ec83bde0-281f-46e0-b503-7beffb3f1f3b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378600198 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_alert_test.378600198
Directory /workspace/48.hmac_alert_test/latest

Test location /workspace/coverage/default/48.hmac_back_pressure.2357162220
Short name T144
Test name
Test status
Simulation time 2289984935 ps
CPU time 64.07 seconds
Started Jul 01 04:44:22 PM PDT 24
Finished Jul 01 04:45:28 PM PDT 24
Peak memory 200368 kb
Host smart-a8bedd84-2825-49d9-9231-6dda48621883
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2357162220 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_back_pressure.2357162220
Directory /workspace/48.hmac_back_pressure/latest

Test location /workspace/coverage/default/48.hmac_burst_wr.2931142900
Short name T482
Test name
Test status
Simulation time 20335795992 ps
CPU time 30.61 seconds
Started Jul 01 04:44:27 PM PDT 24
Finished Jul 01 04:44:59 PM PDT 24
Peak memory 200344 kb
Host smart-8a6c74fd-0076-4901-b215-06eb48f8fb8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931142900 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_burst_wr.2931142900
Directory /workspace/48.hmac_burst_wr/latest

Test location /workspace/coverage/default/48.hmac_datapath_stress.3615642437
Short name T262
Test name
Test status
Simulation time 3162398003 ps
CPU time 554.42 seconds
Started Jul 01 04:44:22 PM PDT 24
Finished Jul 01 04:53:39 PM PDT 24
Peak memory 722928 kb
Host smart-271eb3a1-21a9-421c-a966-6c47c860f67b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3615642437 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_datapath_stress.3615642437
Directory /workspace/48.hmac_datapath_stress/latest

Test location /workspace/coverage/default/48.hmac_error.1520107014
Short name T486
Test name
Test status
Simulation time 4257076064 ps
CPU time 85.42 seconds
Started Jul 01 04:44:20 PM PDT 24
Finished Jul 01 04:45:47 PM PDT 24
Peak memory 200320 kb
Host smart-8b11e29a-2cc7-42ea-9225-554f07d235df
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520107014 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_error.1520107014
Directory /workspace/48.hmac_error/latest

Test location /workspace/coverage/default/48.hmac_long_msg.149169790
Short name T517
Test name
Test status
Simulation time 3643353593 ps
CPU time 63.93 seconds
Started Jul 01 04:44:23 PM PDT 24
Finished Jul 01 04:45:30 PM PDT 24
Peak memory 216676 kb
Host smart-c1de5231-7aff-4afb-a864-e90817eca05e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149169790 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_long_msg.149169790
Directory /workspace/48.hmac_long_msg/latest

Test location /workspace/coverage/default/48.hmac_smoke.2180792016
Short name T454
Test name
Test status
Simulation time 791409406 ps
CPU time 1.43 seconds
Started Jul 01 04:44:24 PM PDT 24
Finished Jul 01 04:44:27 PM PDT 24
Peak memory 200312 kb
Host smart-2e016f7d-00ac-4eaf-8fe1-1eb27a4e7c1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180792016 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_smoke.2180792016
Directory /workspace/48.hmac_smoke/latest

Test location /workspace/coverage/default/48.hmac_stress_all.4139068162
Short name T247
Test name
Test status
Simulation time 236869803020 ps
CPU time 1461.5 seconds
Started Jul 01 04:44:24 PM PDT 24
Finished Jul 01 05:08:48 PM PDT 24
Peak memory 698548 kb
Host smart-980e8c03-106b-4ffb-90ad-b90962230bc5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139068162 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.hmac_stress_all.4139068162
Directory /workspace/48.hmac_stress_all/latest

Test location /workspace/coverage/default/48.hmac_wipe_secret.1202024305
Short name T337
Test name
Test status
Simulation time 15012434942 ps
CPU time 63.27 seconds
Started Jul 01 04:44:22 PM PDT 24
Finished Jul 01 04:45:28 PM PDT 24
Peak memory 200352 kb
Host smart-18d858b4-95f8-4525-9acf-0365de0a8de9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202024305 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_wipe_secret.1202024305
Directory /workspace/48.hmac_wipe_secret/latest

Test location /workspace/coverage/default/49.hmac_alert_test.3728133832
Short name T345
Test name
Test status
Simulation time 19578818 ps
CPU time 0.56 seconds
Started Jul 01 04:44:29 PM PDT 24
Finished Jul 01 04:44:31 PM PDT 24
Peak memory 195172 kb
Host smart-6aeb5d15-c60c-48a3-9ca3-553f85bc3891
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728133832 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_alert_test.3728133832
Directory /workspace/49.hmac_alert_test/latest

Test location /workspace/coverage/default/49.hmac_back_pressure.3344683003
Short name T26
Test name
Test status
Simulation time 2584378042 ps
CPU time 71.88 seconds
Started Jul 01 04:44:21 PM PDT 24
Finished Jul 01 04:45:35 PM PDT 24
Peak memory 200332 kb
Host smart-bf5215e2-02b8-4461-83a9-82c061c1ee44
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3344683003 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_back_pressure.3344683003
Directory /workspace/49.hmac_back_pressure/latest

Test location /workspace/coverage/default/49.hmac_burst_wr.1835727606
Short name T387
Test name
Test status
Simulation time 1110420153 ps
CPU time 15.15 seconds
Started Jul 01 04:44:24 PM PDT 24
Finished Jul 01 04:44:41 PM PDT 24
Peak memory 200356 kb
Host smart-624971f2-abc1-427f-9a10-1dffc8bc2e81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835727606 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_burst_wr.1835727606
Directory /workspace/49.hmac_burst_wr/latest

Test location /workspace/coverage/default/49.hmac_datapath_stress.2227533926
Short name T523
Test name
Test status
Simulation time 3679745980 ps
CPU time 644.73 seconds
Started Jul 01 04:44:22 PM PDT 24
Finished Jul 01 04:55:09 PM PDT 24
Peak memory 646340 kb
Host smart-bb573169-c3ec-490e-89aa-4a9987907eed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2227533926 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_datapath_stress.2227533926
Directory /workspace/49.hmac_datapath_stress/latest

Test location /workspace/coverage/default/49.hmac_error.4101799370
Short name T434
Test name
Test status
Simulation time 1366296029 ps
CPU time 15.96 seconds
Started Jul 01 04:44:26 PM PDT 24
Finished Jul 01 04:44:44 PM PDT 24
Peak memory 200100 kb
Host smart-d353e8aa-0858-472f-8a0e-eb627a969c48
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101799370 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_error.4101799370
Directory /workspace/49.hmac_error/latest

Test location /workspace/coverage/default/49.hmac_long_msg.1683675629
Short name T484
Test name
Test status
Simulation time 6748417761 ps
CPU time 97.74 seconds
Started Jul 01 04:44:22 PM PDT 24
Finished Jul 01 04:46:01 PM PDT 24
Peak memory 200476 kb
Host smart-1756adfc-a501-438f-b67e-15af55448b7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683675629 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_long_msg.1683675629
Directory /workspace/49.hmac_long_msg/latest

Test location /workspace/coverage/default/49.hmac_smoke.621425213
Short name T361
Test name
Test status
Simulation time 3011828344 ps
CPU time 15.45 seconds
Started Jul 01 04:44:22 PM PDT 24
Finished Jul 01 04:44:39 PM PDT 24
Peak memory 200388 kb
Host smart-f9875f72-9285-425d-ab2c-f7b3449dc3ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621425213 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_smoke.621425213
Directory /workspace/49.hmac_smoke/latest

Test location /workspace/coverage/default/49.hmac_stress_all.3511417904
Short name T209
Test name
Test status
Simulation time 36655551439 ps
CPU time 675.51 seconds
Started Jul 01 04:44:30 PM PDT 24
Finished Jul 01 04:55:48 PM PDT 24
Peak memory 324092 kb
Host smart-56fff558-42ba-42c9-9b4e-aaed98f4571d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511417904 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.hmac_stress_all.3511417904
Directory /workspace/49.hmac_stress_all/latest

Test location /workspace/coverage/default/49.hmac_wipe_secret.1381377867
Short name T130
Test name
Test status
Simulation time 16771886 ps
CPU time 0.85 seconds
Started Jul 01 04:44:24 PM PDT 24
Finished Jul 01 04:44:27 PM PDT 24
Peak memory 198288 kb
Host smart-082b81b9-d529-4d71-bcc3-f01d5d34a150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381377867 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_wipe_secret.1381377867
Directory /workspace/49.hmac_wipe_secret/latest

Test location /workspace/coverage/default/5.hmac_alert_test.3492345337
Short name T373
Test name
Test status
Simulation time 32673763 ps
CPU time 0.58 seconds
Started Jul 01 04:42:41 PM PDT 24
Finished Jul 01 04:42:57 PM PDT 24
Peak memory 195772 kb
Host smart-bc4c398e-8746-4f5d-8f25-75e00015c0f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492345337 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_alert_test.3492345337
Directory /workspace/5.hmac_alert_test/latest

Test location /workspace/coverage/default/5.hmac_back_pressure.1973748920
Short name T290
Test name
Test status
Simulation time 3561359918 ps
CPU time 49.79 seconds
Started Jul 01 04:42:38 PM PDT 24
Finished Jul 01 04:43:45 PM PDT 24
Peak memory 200396 kb
Host smart-b0b8ad3f-5e4c-4178-ba64-4c1c19f06400
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1973748920 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_back_pressure.1973748920
Directory /workspace/5.hmac_back_pressure/latest

Test location /workspace/coverage/default/5.hmac_burst_wr.2250293570
Short name T401
Test name
Test status
Simulation time 1947667195 ps
CPU time 26.39 seconds
Started Jul 01 04:42:35 PM PDT 24
Finished Jul 01 04:43:20 PM PDT 24
Peak memory 200360 kb
Host smart-11dd1f42-a47d-48aa-9aca-0645a7799137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250293570 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_burst_wr.2250293570
Directory /workspace/5.hmac_burst_wr/latest

Test location /workspace/coverage/default/5.hmac_datapath_stress.3641525589
Short name T61
Test name
Test status
Simulation time 3302957817 ps
CPU time 224.37 seconds
Started Jul 01 04:42:41 PM PDT 24
Finished Jul 01 04:46:41 PM PDT 24
Peak memory 437012 kb
Host smart-9be5b2c1-a5d3-4baa-822e-81ceee67cfb7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3641525589 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_datapath_stress.3641525589
Directory /workspace/5.hmac_datapath_stress/latest

Test location /workspace/coverage/default/5.hmac_error.969324828
Short name T169
Test name
Test status
Simulation time 6705983837 ps
CPU time 103.07 seconds
Started Jul 01 04:42:40 PM PDT 24
Finished Jul 01 04:44:39 PM PDT 24
Peak memory 200356 kb
Host smart-2a3b123a-0dfd-485e-b242-5f0fda70cef0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969324828 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_error.969324828
Directory /workspace/5.hmac_error/latest

Test location /workspace/coverage/default/5.hmac_long_msg.737693411
Short name T319
Test name
Test status
Simulation time 1652374389 ps
CPU time 15.6 seconds
Started Jul 01 04:42:39 PM PDT 24
Finished Jul 01 04:43:11 PM PDT 24
Peak memory 200360 kb
Host smart-a8f0e791-cf09-41d3-838b-3590390a290c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737693411 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_long_msg.737693411
Directory /workspace/5.hmac_long_msg/latest

Test location /workspace/coverage/default/5.hmac_smoke.3844040076
Short name T358
Test name
Test status
Simulation time 837165954 ps
CPU time 10.11 seconds
Started Jul 01 04:42:40 PM PDT 24
Finished Jul 01 04:43:06 PM PDT 24
Peak memory 200300 kb
Host smart-30719da3-3e27-4076-a867-4cc1a528ef95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844040076 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_smoke.3844040076
Directory /workspace/5.hmac_smoke/latest

Test location /workspace/coverage/default/5.hmac_stress_all.129274439
Short name T160
Test name
Test status
Simulation time 190167987963 ps
CPU time 3387.57 seconds
Started Jul 01 04:42:32 PM PDT 24
Finished Jul 01 05:39:18 PM PDT 24
Peak memory 762620 kb
Host smart-34f3cf88-6c38-401b-ba2e-bec2a30acc68
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129274439 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all.129274439
Directory /workspace/5.hmac_stress_all/latest

Test location /workspace/coverage/default/5.hmac_stress_all_with_rand_reset.1862862391
Short name T58
Test name
Test status
Simulation time 52020599809 ps
CPU time 1457.12 seconds
Started Jul 01 04:42:33 PM PDT 24
Finished Jul 01 05:07:09 PM PDT 24
Peak memory 319516 kb
Host smart-f3fb840d-60d6-4043-9bbc-d29eba18c0ff
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1862862391 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all_with_rand_reset.1862862391
Directory /workspace/5.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.hmac_wipe_secret.2180078607
Short name T121
Test name
Test status
Simulation time 4465383680 ps
CPU time 51.76 seconds
Started Jul 01 04:42:40 PM PDT 24
Finished Jul 01 04:43:48 PM PDT 24
Peak memory 200400 kb
Host smart-7a9b1604-6992-4168-9305-186e045bf067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180078607 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_wipe_secret.2180078607
Directory /workspace/5.hmac_wipe_secret/latest

Test location /workspace/coverage/default/6.hmac_alert_test.1818742707
Short name T45
Test name
Test status
Simulation time 134087045 ps
CPU time 0.61 seconds
Started Jul 01 04:42:42 PM PDT 24
Finished Jul 01 04:42:58 PM PDT 24
Peak memory 196980 kb
Host smart-845019a1-cb00-4a05-98e2-4abfe52531e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818742707 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_alert_test.1818742707
Directory /workspace/6.hmac_alert_test/latest

Test location /workspace/coverage/default/6.hmac_back_pressure.1882518976
Short name T303
Test name
Test status
Simulation time 369184800 ps
CPU time 17 seconds
Started Jul 01 04:42:39 PM PDT 24
Finished Jul 01 04:43:13 PM PDT 24
Peak memory 200268 kb
Host smart-4b0986cd-08f4-4a99-a3cc-c79a112b2b8f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1882518976 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_back_pressure.1882518976
Directory /workspace/6.hmac_back_pressure/latest

Test location /workspace/coverage/default/6.hmac_burst_wr.3860873985
Short name T75
Test name
Test status
Simulation time 6150855171 ps
CPU time 60.5 seconds
Started Jul 01 04:42:39 PM PDT 24
Finished Jul 01 04:43:56 PM PDT 24
Peak memory 200456 kb
Host smart-466f60b9-e9d1-4ea5-815d-09a42ac9d3e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860873985 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_burst_wr.3860873985
Directory /workspace/6.hmac_burst_wr/latest

Test location /workspace/coverage/default/6.hmac_datapath_stress.4196736243
Short name T32
Test name
Test status
Simulation time 1106263668 ps
CPU time 66.03 seconds
Started Jul 01 04:42:37 PM PDT 24
Finished Jul 01 04:44:00 PM PDT 24
Peak memory 320668 kb
Host smart-b7465f45-14b4-4fa2-a22b-5c83ed675ff5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4196736243 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_datapath_stress.4196736243
Directory /workspace/6.hmac_datapath_stress/latest

Test location /workspace/coverage/default/6.hmac_error.49666129
Short name T370
Test name
Test status
Simulation time 2249003431 ps
CPU time 113.69 seconds
Started Jul 01 04:42:35 PM PDT 24
Finished Jul 01 04:44:46 PM PDT 24
Peak memory 200348 kb
Host smart-3e24a6c8-7825-4391-81f0-0624c20d7c07
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49666129 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_error.49666129
Directory /workspace/6.hmac_error/latest

Test location /workspace/coverage/default/6.hmac_long_msg.3833251343
Short name T230
Test name
Test status
Simulation time 34056993364 ps
CPU time 132.72 seconds
Started Jul 01 04:42:41 PM PDT 24
Finished Jul 01 04:45:09 PM PDT 24
Peak memory 208588 kb
Host smart-ecb7812d-48e4-42d4-b751-615f4850c024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833251343 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_long_msg.3833251343
Directory /workspace/6.hmac_long_msg/latest

Test location /workspace/coverage/default/6.hmac_smoke.1210467025
Short name T188
Test name
Test status
Simulation time 3362612694 ps
CPU time 8.99 seconds
Started Jul 01 04:42:37 PM PDT 24
Finished Jul 01 04:43:03 PM PDT 24
Peak memory 200412 kb
Host smart-f5c997c2-bd1c-409b-a25b-e5f4e5787007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210467025 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_smoke.1210467025
Directory /workspace/6.hmac_smoke/latest

Test location /workspace/coverage/default/6.hmac_stress_all.428492026
Short name T128
Test name
Test status
Simulation time 46659176719 ps
CPU time 198.38 seconds
Started Jul 01 04:42:40 PM PDT 24
Finished Jul 01 04:46:15 PM PDT 24
Peak memory 200412 kb
Host smart-4c602bbb-4fa0-43f0-85d8-45aef89572e6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428492026 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all.428492026
Directory /workspace/6.hmac_stress_all/latest

Test location /workspace/coverage/default/6.hmac_wipe_secret.1097292189
Short name T270
Test name
Test status
Simulation time 31089530248 ps
CPU time 91.96 seconds
Started Jul 01 04:42:40 PM PDT 24
Finished Jul 01 04:44:28 PM PDT 24
Peak memory 200392 kb
Host smart-cff96c65-a6fe-4cc3-a505-ae45e81df605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097292189 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_wipe_secret.1097292189
Directory /workspace/6.hmac_wipe_secret/latest

Test location /workspace/coverage/default/7.hmac_alert_test.2531364547
Short name T412
Test name
Test status
Simulation time 33339653 ps
CPU time 0.59 seconds
Started Jul 01 04:42:40 PM PDT 24
Finished Jul 01 04:42:57 PM PDT 24
Peak memory 196196 kb
Host smart-77968b2b-39e4-4e44-9098-f41a347cac84
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531364547 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_alert_test.2531364547
Directory /workspace/7.hmac_alert_test/latest

Test location /workspace/coverage/default/7.hmac_back_pressure.2737874761
Short name T369
Test name
Test status
Simulation time 1070142738 ps
CPU time 62.41 seconds
Started Jul 01 04:42:42 PM PDT 24
Finished Jul 01 04:44:00 PM PDT 24
Peak memory 200296 kb
Host smart-4e0645d8-6eb5-4d8a-bbd7-481a189ac98a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2737874761 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_back_pressure.2737874761
Directory /workspace/7.hmac_back_pressure/latest

Test location /workspace/coverage/default/7.hmac_burst_wr.2874277850
Short name T227
Test name
Test status
Simulation time 1398483232 ps
CPU time 6.92 seconds
Started Jul 01 04:42:42 PM PDT 24
Finished Jul 01 04:43:03 PM PDT 24
Peak memory 200296 kb
Host smart-261fcbbf-c95c-404c-9517-57e9965a3f1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874277850 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_burst_wr.2874277850
Directory /workspace/7.hmac_burst_wr/latest

Test location /workspace/coverage/default/7.hmac_datapath_stress.1029632834
Short name T202
Test name
Test status
Simulation time 4611454026 ps
CPU time 880.03 seconds
Started Jul 01 04:42:44 PM PDT 24
Finished Jul 01 04:57:38 PM PDT 24
Peak memory 729664 kb
Host smart-ec3262db-b4c6-4282-b065-dcc6234b79cd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1029632834 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_datapath_stress.1029632834
Directory /workspace/7.hmac_datapath_stress/latest

Test location /workspace/coverage/default/7.hmac_error.1646694839
Short name T191
Test name
Test status
Simulation time 4677452886 ps
CPU time 82.7 seconds
Started Jul 01 04:42:42 PM PDT 24
Finished Jul 01 04:44:20 PM PDT 24
Peak memory 200404 kb
Host smart-3e99ec1e-bab4-4959-beae-18186dc1cd0b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646694839 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_error.1646694839
Directory /workspace/7.hmac_error/latest

Test location /workspace/coverage/default/7.hmac_long_msg.1840834741
Short name T413
Test name
Test status
Simulation time 5273295629 ps
CPU time 55.91 seconds
Started Jul 01 04:42:46 PM PDT 24
Finished Jul 01 04:43:56 PM PDT 24
Peak memory 200516 kb
Host smart-efbfbbeb-348a-4f79-bbf0-3b80e153a55d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840834741 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_long_msg.1840834741
Directory /workspace/7.hmac_long_msg/latest

Test location /workspace/coverage/default/7.hmac_smoke.916296253
Short name T510
Test name
Test status
Simulation time 567946230 ps
CPU time 3.95 seconds
Started Jul 01 04:42:50 PM PDT 24
Finished Jul 01 04:43:08 PM PDT 24
Peak memory 200308 kb
Host smart-4aa3c2b6-d2e9-4266-a5b7-ecd0ffbc532f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=916296253 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_smoke.916296253
Directory /workspace/7.hmac_smoke/latest

Test location /workspace/coverage/default/7.hmac_stress_all_with_rand_reset.505128729
Short name T16
Test name
Test status
Simulation time 104079450857 ps
CPU time 380.93 seconds
Started Jul 01 04:42:44 PM PDT 24
Finished Jul 01 04:49:20 PM PDT 24
Peak memory 216928 kb
Host smart-55b7da72-c6d1-4c4e-8afa-4b2f53764d24
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=505128729 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all_with_rand_reset.505128729
Directory /workspace/7.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.hmac_wipe_secret.2518098174
Short name T122
Test name
Test status
Simulation time 6281406151 ps
CPU time 81.91 seconds
Started Jul 01 04:42:50 PM PDT 24
Finished Jul 01 04:44:26 PM PDT 24
Peak memory 200428 kb
Host smart-36745292-23dc-4a31-ba01-8fb4b5ff0beb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2518098174 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_wipe_secret.2518098174
Directory /workspace/7.hmac_wipe_secret/latest

Test location /workspace/coverage/default/8.hmac_alert_test.1536484829
Short name T46
Test name
Test status
Simulation time 13646355 ps
CPU time 0.63 seconds
Started Jul 01 04:42:44 PM PDT 24
Finished Jul 01 04:42:59 PM PDT 24
Peak memory 195900 kb
Host smart-2f243b3f-6546-4623-8699-544754e01e43
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536484829 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_alert_test.1536484829
Directory /workspace/8.hmac_alert_test/latest

Test location /workspace/coverage/default/8.hmac_back_pressure.883338100
Short name T236
Test name
Test status
Simulation time 1584731187 ps
CPU time 88.92 seconds
Started Jul 01 04:42:44 PM PDT 24
Finished Jul 01 04:44:28 PM PDT 24
Peak memory 200264 kb
Host smart-63d96c2c-1208-4e9c-9c1a-b827d12d4180
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=883338100 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_back_pressure.883338100
Directory /workspace/8.hmac_back_pressure/latest

Test location /workspace/coverage/default/8.hmac_burst_wr.617855321
Short name T452
Test name
Test status
Simulation time 286037024 ps
CPU time 1.85 seconds
Started Jul 01 04:42:40 PM PDT 24
Finished Jul 01 04:42:58 PM PDT 24
Peak memory 200224 kb
Host smart-f93e5be3-52ee-4e64-92c5-312d80ae144b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617855321 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_burst_wr.617855321
Directory /workspace/8.hmac_burst_wr/latest

Test location /workspace/coverage/default/8.hmac_datapath_stress.1175006775
Short name T139
Test name
Test status
Simulation time 34477255978 ps
CPU time 1054.6 seconds
Started Jul 01 04:42:43 PM PDT 24
Finished Jul 01 05:00:33 PM PDT 24
Peak memory 701548 kb
Host smart-c70974ea-6443-4362-bd8f-0f4b4be49f8a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1175006775 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_datapath_stress.1175006775
Directory /workspace/8.hmac_datapath_stress/latest

Test location /workspace/coverage/default/8.hmac_error.2221879810
Short name T54
Test name
Test status
Simulation time 3062711758 ps
CPU time 166.68 seconds
Started Jul 01 04:42:43 PM PDT 24
Finished Jul 01 04:45:45 PM PDT 24
Peak memory 200368 kb
Host smart-edcf203c-d617-482e-83ef-dee328314ed4
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221879810 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_error.2221879810
Directory /workspace/8.hmac_error/latest

Test location /workspace/coverage/default/8.hmac_long_msg.3084823068
Short name T167
Test name
Test status
Simulation time 9001614432 ps
CPU time 129.72 seconds
Started Jul 01 04:42:40 PM PDT 24
Finished Jul 01 04:45:06 PM PDT 24
Peak memory 216792 kb
Host smart-1d6bd698-71b7-4489-b0d5-a52c0e2d4710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084823068 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_long_msg.3084823068
Directory /workspace/8.hmac_long_msg/latest

Test location /workspace/coverage/default/8.hmac_smoke.1165509899
Short name T137
Test name
Test status
Simulation time 28140777 ps
CPU time 1.27 seconds
Started Jul 01 04:42:50 PM PDT 24
Finished Jul 01 04:43:06 PM PDT 24
Peak memory 200300 kb
Host smart-907ccc63-fd65-4850-9aa8-dbea985e8c0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165509899 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_smoke.1165509899
Directory /workspace/8.hmac_smoke/latest

Test location /workspace/coverage/default/8.hmac_stress_all_with_rand_reset.1726412794
Short name T24
Test name
Test status
Simulation time 67556195948 ps
CPU time 4322.78 seconds
Started Jul 01 04:42:42 PM PDT 24
Finished Jul 01 05:55:00 PM PDT 24
Peak memory 780280 kb
Host smart-a932f71f-98e4-4b85-8927-54624c3e2733
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1726412794 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all_with_rand_reset.1726412794
Directory /workspace/8.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.hmac_wipe_secret.1339449546
Short name T378
Test name
Test status
Simulation time 14474321200 ps
CPU time 11.63 seconds
Started Jul 01 04:42:40 PM PDT 24
Finished Jul 01 04:43:08 PM PDT 24
Peak memory 200472 kb
Host smart-8a8edee6-04e1-4b11-bb30-3672635f84b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339449546 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_wipe_secret.1339449546
Directory /workspace/8.hmac_wipe_secret/latest

Test location /workspace/coverage/default/9.hmac_alert_test.585316875
Short name T322
Test name
Test status
Simulation time 38755499 ps
CPU time 0.57 seconds
Started Jul 01 04:42:50 PM PDT 24
Finished Jul 01 04:43:05 PM PDT 24
Peak memory 195196 kb
Host smart-578a7af6-fc26-4764-824b-993bf2e109a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585316875 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_alert_test.585316875
Directory /workspace/9.hmac_alert_test/latest

Test location /workspace/coverage/default/9.hmac_back_pressure.272097222
Short name T35
Test name
Test status
Simulation time 1394841698 ps
CPU time 79.79 seconds
Started Jul 01 04:42:42 PM PDT 24
Finished Jul 01 04:44:16 PM PDT 24
Peak memory 200392 kb
Host smart-02f65f17-a917-4cbc-b1c3-723d205c3cc8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=272097222 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_back_pressure.272097222
Directory /workspace/9.hmac_back_pressure/latest

Test location /workspace/coverage/default/9.hmac_burst_wr.215665423
Short name T194
Test name
Test status
Simulation time 8393045219 ps
CPU time 38.74 seconds
Started Jul 01 04:42:49 PM PDT 24
Finished Jul 01 04:43:42 PM PDT 24
Peak memory 208796 kb
Host smart-e55f4fcb-86e6-4147-b92e-e98fe4d04931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215665423 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_burst_wr.215665423
Directory /workspace/9.hmac_burst_wr/latest

Test location /workspace/coverage/default/9.hmac_datapath_stress.590734432
Short name T4
Test name
Test status
Simulation time 9643967976 ps
CPU time 1025.95 seconds
Started Jul 01 04:42:43 PM PDT 24
Finished Jul 01 05:00:03 PM PDT 24
Peak memory 724460 kb
Host smart-0d467416-7f31-4080-9f5c-d1a476299b0f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=590734432 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_datapath_stress.590734432
Directory /workspace/9.hmac_datapath_stress/latest

Test location /workspace/coverage/default/9.hmac_error.326009023
Short name T437
Test name
Test status
Simulation time 5687842933 ps
CPU time 104.7 seconds
Started Jul 01 04:42:48 PM PDT 24
Finished Jul 01 04:44:48 PM PDT 24
Peak memory 200448 kb
Host smart-bb7da050-1056-4806-9744-e5a62f9ea087
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326009023 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_error.326009023
Directory /workspace/9.hmac_error/latest

Test location /workspace/coverage/default/9.hmac_long_msg.4049150913
Short name T219
Test name
Test status
Simulation time 11551588367 ps
CPU time 149.45 seconds
Started Jul 01 04:42:40 PM PDT 24
Finished Jul 01 04:45:26 PM PDT 24
Peak memory 200416 kb
Host smart-3f881a09-b3b4-45b3-b211-caad8e29edd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049150913 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_long_msg.4049150913
Directory /workspace/9.hmac_long_msg/latest

Test location /workspace/coverage/default/9.hmac_smoke.1003475498
Short name T148
Test name
Test status
Simulation time 4727477930 ps
CPU time 14.05 seconds
Started Jul 01 04:42:47 PM PDT 24
Finished Jul 01 04:43:15 PM PDT 24
Peak memory 200380 kb
Host smart-c4fb4405-b559-4b82-955c-f0c5c4b8b044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003475498 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_smoke.1003475498
Directory /workspace/9.hmac_smoke/latest

Test location /workspace/coverage/default/9.hmac_stress_all.2245913069
Short name T141
Test name
Test status
Simulation time 21518322698 ps
CPU time 272.69 seconds
Started Jul 01 04:42:41 PM PDT 24
Finished Jul 01 04:47:29 PM PDT 24
Peak memory 200396 kb
Host smart-ad06b0e3-1a24-4056-b038-007e542f0697
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245913069 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all.2245913069
Directory /workspace/9.hmac_stress_all/latest

Test location /workspace/coverage/default/9.hmac_stress_all_with_rand_reset.1651600508
Short name T13
Test name
Test status
Simulation time 378175565574 ps
CPU time 1428.76 seconds
Started Jul 01 04:42:49 PM PDT 24
Finished Jul 01 05:06:52 PM PDT 24
Peak memory 645768 kb
Host smart-1b41a988-e1c3-41f2-99d2-da27868b96f9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1651600508 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all_with_rand_reset.1651600508
Directory /workspace/9.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.hmac_wipe_secret.474404735
Short name T206
Test name
Test status
Simulation time 20790823035 ps
CPU time 86.33 seconds
Started Jul 01 04:42:45 PM PDT 24
Finished Jul 01 04:44:26 PM PDT 24
Peak memory 200404 kb
Host smart-f84cd348-abd5-4ec5-a4fb-c3448c63e8dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474404735 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_wipe_secret.474404735
Directory /workspace/9.hmac_wipe_secret/latest
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