Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	18178212	1			T1	1802		T2	16857		T3	148746
all_values[1]	18178212	1			T1	1802		T2	16857		T3	148746
all_values[2]	18178212	1			T1	1802		T2	16857		T3	148746

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

267754

1

T3

3012

T10

3112

T6

54

auto[1]

54266882

1

T1

5406

T2

50571

T3

443226

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

46419168

1

T1

4112

T2

43934

T3

375560

auto[1]

8115468

1

T1

1294

T2

6637

T3

70678

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	98919	1			T3	15		T6	54		T24	852
all_values[0]	auto[0]	auto[1]	363	1			T3	4		T24	4		T51	2
all_values[0]	auto[1]	auto[0]	18058486	1			T1	1802		T2	16840		T3	148541
all_values[0]	auto[1]	auto[1]	20444	1			T2	17		T3	186		T5	2
all_values[1]	auto[0]	auto[0]	86560	1			T3	1070		T10	3112		T4	222
all_values[1]	auto[0]	auto[1]	253	1			T3	7		T25	1		T7	2
all_values[1]	auto[1]	auto[0]	18091058	1			T1	1802		T2	16857		T3	147660
all_values[1]	auto[1]	auto[1]	341	1			T3	9		T25	2		T7	6
all_values[2]	auto[0]	auto[0]	39333	1			T3	674		T16	344		T4	3
all_values[2]	auto[0]	auto[1]	42326	1			T3	1242		T4	26		T18	4782
all_values[2]	auto[1]	auto[0]	10044812	1			T1	508		T2	10237		T3	77600
all_values[2]	auto[1]	auto[1]	8051741	1			T1	1294		T2	6620		T3	69230