Group : hmac_env_pkg::hmac_env_cov::msg_len_cg
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Group : hmac_env_pkg::hmac_env_cov::msg_len_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
94.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv


Summary for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 18 1 17 94.44
Crosses 32 2 30 93.75


Variables for Group hmac_env_pkg::hmac_env_cov::msg_len_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
hmac_en 2 0 2 100.00 100 1 1 2
msg_len_lower_cp 15 0 15 100.00 100 1 1 0
msg_len_upper_cp 1 1 0 0.00 100 1 1 0


Crosses for Group hmac_env_pkg::hmac_env_cov::msg_len_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
msg_len_lower_cross 30 0 30 100.00 100 1 1 0
msg_len_upper_cross 2 2 0 0.00 100 1 1 0


Summary for Variable hmac_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for hmac_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 143368 1 T1 10 T2 14 T3 4004
auto[1] 152096 1 T1 6 T2 22 T3 2788


Summary for Variable msg_len_lower_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 15 0 15 100.00


User Defined Bins for msg_len_lower_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
len_2050_plus 107510 1 T2 15 T3 2277 T16 24
len_1026_2046 7872 1 T2 1 T3 148 T4 21
len_514_1022 6017 1 T3 113 T6 2 T4 16
len_2_510 4444 1 T2 1 T3 108 T6 4
len_2056 246 1 T6 3 T28 1 T71 3
len_2048 336 1 T3 5 T4 1 T71 1
len_2040 229 1 T6 1 T28 2 T71 1
len_1032 194 1 T28 3 T25 1 T7 5
len_1024 1968 1 T2 1 T3 4 T4 4
len_1016 613 1 T71 2 T7 6 T125 1
len_520 213 1 T6 1 T71 3 T25 2
len_512 383 1 T3 4 T4 2 T18 1
len_504 236 1 T3 2 T71 2 T25 2
len_8 1140 1 T3 5 T5 1 T18 2
len_0 16332 1 T1 8 T3 730 T5 5


Summary for Variable msg_len_upper_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 1 0 0.00


User Defined Bins for msg_len_upper_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
len_upper 0 1 1


Summary for Cross msg_len_lower_cross

Samples crossed: hmac_en msg_len_lower_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 30 0 30 100.00


Automatically Generated Cross Bins for msg_len_lower_cross

Bins
hmac_enmsg_len_lower_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] len_2050_plus 53054 1 T2 6 T3 1688 T16 11
auto[0] len_1026_2046 3922 1 T3 48 T4 17 T28 1
auto[0] len_514_1022 3703 1 T3 61 T6 2 T4 14
auto[0] len_2_510 2608 1 T3 11 T6 3 T4 11
auto[0] len_2056 153 1 T6 1 T28 1 T71 1
auto[0] len_2048 205 1 T3 4 T4 1 T71 1
auto[0] len_2040 140 1 T28 1 T71 1 T7 1
auto[0] len_1032 104 1 T25 1 T7 3 T125 1
auto[0] len_1024 309 1 T2 1 T3 4 T4 4
auto[0] len_1016 406 1 T7 2 T125 1 T126 1
auto[0] len_520 123 1 T6 1 T71 2 T7 3
auto[0] len_512 233 1 T3 4 T4 2 T127 1
auto[0] len_504 154 1 T3 1 T71 2 T25 1
auto[0] len_8 39 1 T9 1 T128 1 T73 5
auto[0] len_0 6532 1 T1 5 T3 181 T10 4
auto[1] len_2050_plus 54456 1 T2 9 T3 589 T16 13
auto[1] len_1026_2046 3950 1 T2 1 T3 100 T4 4
auto[1] len_514_1022 2314 1 T3 52 T4 2 T28 2
auto[1] len_2_510 1836 1 T2 1 T3 97 T6 1
auto[1] len_2056 93 1 T6 2 T71 2 T7 4
auto[1] len_2048 131 1 T3 1 T25 1 T31 1
auto[1] len_2040 89 1 T6 1 T28 1 T125 1
auto[1] len_1032 90 1 T28 3 T7 2 T126 1
auto[1] len_1024 1659 1 T18 1 T25 4 T7 3
auto[1] len_1016 207 1 T71 2 T7 4 T34 1
auto[1] len_520 90 1 T71 1 T25 2 T7 1
auto[1] len_512 150 1 T18 1 T71 5 T25 1
auto[1] len_504 82 1 T3 1 T25 1 T7 1
auto[1] len_8 1101 1 T3 5 T5 1 T18 2
auto[1] len_0 9800 1 T1 3 T3 549 T5 5


Summary for Cross msg_len_upper_cross

Samples crossed: hmac_en msg_len_upper_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 2 2 0 0.00 2


Automatically Generated Cross Bins for msg_len_upper_cross

Uncovered bins
hmac_enmsg_len_upper_cpCOUNTAT LEASTNUMBERSTATUS
* * -- -- 2

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%