Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::status_cg

Group : hmac_env_pkg::hmac_env_cov::status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	192	0	192	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	2
key_swap	2	0	2	100.00	100	1	1	2
sta_fifo_depth	8	0	8	100.00	100	1	1	0
sta_fifo_empty	2	0	2	100.00	100	1	1	2
sta_fifo_full	2	0	2	100.00	100	1	1	2

Crosses for Group hmac_env_pkg::hmac_env_cov::status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
fifo_empty_cross	32	0	32	100.00	100	1	1	0
fifo_full_cross	32	0	32	100.00	100	1	1	0
fifo_depth_cross	128	0	128	100.00	100	1	1	0

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4481329

1

T1

815

T2

3173

T3

33930

auto[1]

3065415

1

T1

18

T2

5271

T3

47500

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3027949

1

T1

506

T2

3147

T3

48130

auto[1]

4518795

1

T1

327

T2

5297

T3

33300

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3256225

1

T1

814

T2

3700

T3

37791

auto[1]

4290519

1

T1

19

T2

4744

T3

43639

---

Summary for Variable key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for key_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4493560

1

T1

49

T2

4466

T3

38374

auto[1]

3053184

1

T1

784

T2

3978

T3

43056

---

Summary for Variable sta_fifo_depth

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for sta_fifo_depth

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	6820310	1			T1	833		T2	7301		T3	60780
fifo_depth[1]	123822	1			T2	185		T3	1387		T6	6
fifo_depth[2]	95037	1			T2	192		T3	1346		T6	6
fifo_depth[3]	75325	1			T2	182		T3	1409		T4	30
fifo_depth[4]	69405	1			T2	174		T3	1622		T16	1
fifo_depth[5]	54633	1			T2	158		T3	1086		T16	1
fifo_depth[6]	43341	1			T2	123		T3	1093		T4	17
fifo_depth[7]	28618	1			T2	68		T3	693		T16	1

---

Summary for Variable sta_fifo_empty

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_empty

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

726434

1

T2

1143

T3

20650

T6

12

auto[1]

6820310

1

T1

833

T2

7301

T3

60780

---

Summary for Variable sta_fifo_full

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_full

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7537831

1

T1

833

T2

8444

T3

80543

auto[1]

8913

1

T3

887

T25

1

T142

224

---

Summary for Cross fifo_empty_cross

Samples crossed: sta_fifo_empty hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for fifo_empty_cross

Bins

sta_fifo_empty

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

33254

1

T3

1122

T16

1

T4

24

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

33056

1

T3

1664

T16

3

T4

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

41552

1

T3

5372

T16

1

T4

34

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

32409

1

T2

87

T3

633

T16

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

147895

1

T2

188

T3

1056

T4

27

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

32276

1

T3

618

T16

1

T4

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

30494

1

T2

173

T3

895

T4

54

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

29238

1

T2

46

T3

3085

T4

8

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

50821

1

T3

1134

T4

4

T48

550

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

40985

1

T3

229

T16

1

T4

36

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

43830

1

T2

75

T3

1582

T18

94

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

43696

1

T2

269

T3

967

T6

4

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

39086

1

T3

7

T6

8

T18

181

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

46383

1

T2

251

T3

407

T24

14

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

40943

1

T2

54

T3

774

T16

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

40516

1

T3

1105

T24

14

T28

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

185201

1

T1

1

T2

247

T3

3090

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

179075

1

T1

505

T2

37

T3

3836

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

189155

1

T3

2289

T6

22

T16

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

198611

1

T2

609

T3

3494

T10

1605

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

1581321

1

T1

30

T2

666

T3

1604

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

174142

1

T1

278

T3

4045

T10

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

183959

1

T2

481

T3

1266

T4

393

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

184587

1

T2

1166

T3

3722

T10

447

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

448030

1

T2

433

T3

3266

T5

1198

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

488606

1

T2

448

T3

6831

T6

20

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

467734

1

T2

465

T3

7204

T5

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

551934

1

T2

477

T3

5417

T5

2465

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

527471

1

T2

315

T3

1779

T10

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

473727

1

T1

1

T2

588

T3

3242

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

482814

1

T1

18

T2

1369

T3

5934

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

503943

1

T3

3761

T5

2

T10

1

---

Summary for Cross fifo_full_cross

Samples crossed: sta_fifo_full hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for fifo_full_cross

Bins

sta_fifo_full

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

218075

1

T1

1

T2

247

T3

4206

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

211669

1

T1

505

T2

37

T3

5493

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

229422

1

T3

7647

T6

22

T16

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

230598

1

T2

696

T3

4127

T10

1605

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

1728621

1

T1

30

T2

854

T3

2644

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

205825

1

T1

278

T3

4602

T10

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

213500

1

T2

654

T3

2000

T4

447

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

212908

1

T2

1212

T3

6317

T10

447

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

498602

1

T2

433

T3

4385

T5

1198

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

529150

1

T2

448

T3

7060

T6

20

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

511299

1

T2

540

T3

8786

T5

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

595512

1

T2

746

T3

6350

T5

2465

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

566429

1

T2

315

T3

1786

T10

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

519093

1

T1

1

T2

839

T3

3648

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

523488

1

T1

18

T2

1423

T3

6708

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

543640

1

T3

4784

T5

2

T10

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

380

1

T3

6

T9

86

T143

56

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

462

1

T3

7

T142

38

T9

30

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

1285

1

T3

14

T9

15

T143

219

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

422

1

T12

1

T9

22

T144

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

595

1

T3

16

T142

126

T9

22

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

593

1

T3

61

T142

27

T9

380

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

953

1

T3

161

T9

7

T143

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

917

1

T3

490

T25

1

T9

100

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

249

1

T3

15

T9

4

T145

54

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

441

1

T9

1

T145

20

T146

48

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

265

1

T145

128

T144

9

T147

24

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

118

1

T3

34

T9

1

T22

65

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

128

1

T9

18

T145

1

T146

8

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

1017

1

T3

1

T9

230

T145

26

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

269

1

T9

34

T143

2

T144

14

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

819

1

T3

82

T142

33

T9

430

---

Summary for Cross fifo_depth_cross

Samples crossed: sta_fifo_depth hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for fifo_depth_cross

Bins

sta_fifo_depth

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fifo_depth[0]

auto[0]

auto[0]

auto[0]

auto[0]

185201

1

T1

1

T2

247

T3

3090

fifo_depth[0]

auto[0]

auto[0]

auto[0]

auto[1]

179075

1

T1

505

T2

37

T3

3836

fifo_depth[0]

auto[0]

auto[0]

auto[1]

auto[0]

189155

1

T3

2289

T6

22

T16

1

fifo_depth[0]

auto[0]

auto[0]

auto[1]

auto[1]

198611

1

T2

609

T3

3494

T10

1605

fifo_depth[0]

auto[0]

auto[1]

auto[0]

auto[0]

1581321

1

T1

30

T2

666

T3

1604

fifo_depth[0]

auto[0]

auto[1]

auto[0]

auto[1]

174142

1

T1

278

T3

4045

T10

1

fifo_depth[0]

auto[0]

auto[1]

auto[1]

auto[0]

183959

1

T2

481

T3

1266

T4

393

fifo_depth[0]

auto[0]

auto[1]

auto[1]

auto[1]

184587

1

T2

1166

T3

3722

T10

447

fifo_depth[0]

auto[1]

auto[0]

auto[0]

auto[0]

448030

1

T2

433

T3

3266

T5

1198

fifo_depth[0]

auto[1]

auto[0]

auto[0]

auto[1]

488606

1

T2

448

T3

6831

T6

20

fifo_depth[0]

auto[1]

auto[0]

auto[1]

auto[0]

467734

1

T2

465

T3

7204

T5

1

fifo_depth[0]

auto[1]

auto[0]

auto[1]

auto[1]

551934

1

T2

477

T3

5417

T5

2465

fifo_depth[0]

auto[1]

auto[1]

auto[0]

auto[0]

527471

1

T2

315

T3

1779

T10

1

fifo_depth[0]

auto[1]

auto[1]

auto[0]

auto[1]

473727

1

T1

1

T2

588

T3

3242

fifo_depth[0]

auto[1]

auto[1]

auto[1]

auto[0]

482814

1

T1

18

T2

1369

T3

5934

fifo_depth[0]

auto[1]

auto[1]

auto[1]

auto[1]

503943

1

T3

3761

T5

2

T10

1

fifo_depth[1]

auto[0]

auto[0]

auto[0]

auto[0]

3355

1

T3

62

T16

1

T4

1

fifo_depth[1]

auto[0]

auto[0]

auto[0]

auto[1]

3860

1

T3

137

T139

13

T25

15

fifo_depth[1]

auto[0]

auto[0]

auto[1]

auto[0]

4292

1

T3

205

T4

8

T24

26

fifo_depth[1]

auto[0]

auto[0]

auto[1]

auto[1]

4451

1

T2

17

T3

125

T4

4

fifo_depth[1]

auto[0]

auto[1]

auto[0]

auto[0]

42853

1

T2

34

T3

57

T4

7

fifo_depth[1]

auto[0]

auto[1]

auto[0]

auto[1]

3536

1

T3

77

T4

2

T24

10

fifo_depth[1]

auto[0]

auto[1]

auto[1]

auto[0]

3803

1

T2

27

T3

16

T4

13

fifo_depth[1]

auto[0]

auto[1]

auto[1]

auto[1]

4261

1

T2

5

T3

115

T27

23

fifo_depth[1]

auto[1]

auto[0]

auto[0]

auto[0]

6873

1

T3

33

T4

1

T48

71

fifo_depth[1]

auto[1]

auto[0]

auto[0]

auto[1]

6332

1

T3

39

T16

1

T4

11

fifo_depth[1]

auto[1]

auto[0]

auto[1]

auto[0]

6744

1

T2

10

T3

250

T18

10

fifo_depth[1]

auto[1]

auto[0]

auto[1]

auto[1]

6920

1

T2

48

T3

95

T6

3

fifo_depth[1]

auto[1]

auto[1]

auto[0]

auto[0]

7197

1

T3

1

T6

3

T18

34

fifo_depth[1]

auto[1]

auto[1]

auto[0]

auto[1]

6958

1

T2

36

T3

18

T24

7

fifo_depth[1]

auto[1]

auto[1]

auto[1]

auto[0]

6276

1

T2

8

T3

78

T18

70

fifo_depth[1]

auto[1]

auto[1]

auto[1]

auto[1]

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131

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16

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1

T3

146

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2

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1

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2

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21

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56

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4

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34

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1

T3

37

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83

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T3

30

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11

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1

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9

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238

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16

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T2

53

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1

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19

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73

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71

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97

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63

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17

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218

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2

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T2

18

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37

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9

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1

T2

7

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101

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27

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T3

26

T48

95

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13

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T3

36

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7

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1

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T2

6

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269

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13

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1

T2

44

T3

83

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5

fifo_depth[3]

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3

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17

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T2

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29

T24

1

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T2

6

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80

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77

fifo_depth[3]

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T3

88

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1

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51

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63

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5

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153

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1

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T3

413

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6

T27

4

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1

T2

12

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120

T25

74

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1

T2

27

T3

49

T4

3

fifo_depth[4]

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1

T3

74

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1

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17

fifo_depth[4]

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24

T3

21

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7

fifo_depth[4]

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1

T2

6

T3

144

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8

fifo_depth[4]

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1

T3

43

T4

1

T48

77

fifo_depth[4]

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1

T3

35

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6

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51

fifo_depth[4]

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1

T2

14

T3

241

T18

17

fifo_depth[4]

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1

T2

41

T3

80

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10

fifo_depth[4]

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T18

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T2

43

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23

T27

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7

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63

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T3

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T3

60

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2

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1

fifo_depth[5]

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1

T3

108

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17

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fifo_depth[5]

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T3

157

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4

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1

T2

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T3

68

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62

fifo_depth[5]

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1

T2

21

T3

36

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4

fifo_depth[5]

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T3

64

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fifo_depth[5]

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1

T2

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6

fifo_depth[5]

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1

T2

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101

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24

fifo_depth[5]

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T3

35

T48

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14

fifo_depth[5]

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T3

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1

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fifo_depth[5]

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T2

11

T3

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fifo_depth[5]

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fifo_depth[5]

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20

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28

fifo_depth[5]

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T2

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54

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fifo_depth[5]

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44

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fifo_depth[6]

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T3

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12

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fifo_depth[6]

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1

T3

340

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fifo_depth[6]

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36

fifo_depth[6]

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22

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T3

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17

fifo_depth[6]

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fifo_depth[6]

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T27

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fifo_depth[6]

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1

T3

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66

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10

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35

T25

8

fifo_depth[6]

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1

T2

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T3

160

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11

fifo_depth[6]

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1

T2

26

T3

29

T4

6

fifo_depth[6]

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1

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26

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fifo_depth[6]

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1

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28

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17

T48

13

fifo_depth[6]

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1

T2

9

T3

57

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45

fifo_depth[6]

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1

T3

51

T25

24

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59

fifo_depth[7]

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1

T3

31

T25

2

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1

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1

T3

86

T25

8

T149

2

fifo_depth[7]

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1

T3

103

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7

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fifo_depth[7]

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1

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15

T25

18

fifo_depth[7]

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1

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T3

33

T25

2

fifo_depth[7]

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1

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1

fifo_depth[7]

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15

T3

27

T4

2

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1

T2

4

T3

102

T27

10

fifo_depth[7]

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1

T3

50

T48

42

T25

4

fifo_depth[7]

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1

T3

19

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25

T25

14

fifo_depth[7]

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1

T2

5

T3

98

T18

14

fifo_depth[7]

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1

T2

8

T3

28

T16

1

fifo_depth[7]

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1

T18

16

T25

2

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2

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1

T2

14

T3

17

T48

6

fifo_depth[7]

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1

T2

1

T3

32

T18

11

fifo_depth[7]

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1851

1

T3

25

T25

19

T75

35