Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	18178212	1			T1	1802		T2	16857		T3	148746
all_pins[1]	18178212	1			T1	1802		T2	16857		T3	148746
all_pins[2]	18178212	1			T1	1802		T2	16857		T3	148746

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	46461204	1			T1	4112		T2	43932		T3	376797
values[0x1]	8073432	1			T1	1294		T2	6639		T3	69441
transitions[0x0=>0x1]	8073232	1			T1	1294		T2	6639		T3	69437
transitions[0x1=>0x0]	8073242	1			T1	1294		T2	6639		T3	69437

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	18156886	1			T1	1802		T2	16838		T3	148544
all_pins[0]	values[0x1]	21326	1			T2	19		T3	202		T5	2
all_pins[0]	transitions[0x0=>0x1]	21245	1			T2	19		T3	202		T5	2
all_pins[0]	transitions[0x1=>0x0]	8051670	1			T1	1294		T2	6620		T3	69230
all_pins[1]	values[0x0]	18177847	1			T1	1802		T2	16857		T3	148737
all_pins[1]	values[0x1]	365	1			T3	9		T25	2		T7	6
all_pins[1]	transitions[0x0=>0x1]	302	1			T3	7		T25	2		T7	5
all_pins[1]	transitions[0x1=>0x0]	21263	1			T2	19		T3	200		T5	2
all_pins[2]	values[0x0]	10126471	1			T1	508		T2	10237		T3	79516
all_pins[2]	values[0x1]	8051741	1			T1	1294		T2	6620		T3	69230
all_pins[2]	transitions[0x0=>0x1]	8051685	1			T1	1294		T2	6620		T3	69228
all_pins[2]	transitions[0x1=>0x0]	309	1			T3	7		T25	2		T7	2