Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 0 18 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 0 18 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 1130 1 T3 27 T25 4 T7 31
all_values[1] 1130 1 T3 27 T25 4 T7 31
all_values[2] 1130 1 T3 27 T25 4 T7 31


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1674 1 T3 41 T25 6 T7 29
auto[1] 1716 1 T3 40 T25 6 T7 64


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1183 1 T3 37 T25 5 T7 45
auto[1] 2207 1 T3 44 T25 7 T7 48


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1903 1 T3 51 T25 6 T7 58
auto[1] 1487 1 T3 30 T25 6 T7 35


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 0 18 100.00
Automatically Generated Cross Bins 18 0 18 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 205 1 T3 7 T25 2 T7 5
all_values[0] auto[0] auto[0] auto[1] 99 1 T3 2 T7 2 T12 1
all_values[0] auto[0] auto[1] auto[0] 216 1 T3 6 T25 1 T7 15
all_values[0] auto[0] auto[1] auto[1] 110 1 T3 1 T7 1 T8 3
all_values[0] auto[1] auto[0] auto[1] 241 1 T3 3 T7 2 T12 2
all_values[0] auto[1] auto[1] auto[1] 259 1 T3 8 T25 1 T7 6
all_values[1] auto[0] auto[0] auto[0] 168 1 T3 3 T7 7 T12 1
all_values[1] auto[0] auto[0] auto[1] 139 1 T3 6 T25 1 T7 1
all_values[1] auto[0] auto[1] auto[0] 179 1 T3 5 T7 10 T12 2
all_values[1] auto[0] auto[1] auto[1] 149 1 T3 2 T7 5 T8 7
all_values[1] auto[1] auto[0] auto[1] 249 1 T3 7 T12 1 T8 6
all_values[1] auto[1] auto[1] auto[1] 246 1 T3 4 T25 3 T7 8
all_values[2] auto[0] auto[0] auto[0] 217 1 T3 7 T25 1 T7 4
all_values[2] auto[0] auto[0] auto[1] 108 1 T3 1 T8 3 T9 1
all_values[2] auto[0] auto[1] auto[0] 198 1 T3 9 T25 1 T7 4
all_values[2] auto[0] auto[1] auto[1] 115 1 T3 2 T7 4 T12 2
all_values[2] auto[1] auto[0] auto[1] 248 1 T3 5 T25 2 T7 8
all_values[2] auto[1] auto[1] auto[1] 244 1 T3 3 T7 11 T12 1


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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