Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::cfg_cg

Group : hmac_env_pkg::hmac_env_cov::cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	90	0	90	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_size	5	0	5	100.00	100	1	1	0
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	0
key_length	7	0	7	100.00	100	1	1	0
key_swap	2	0	2	100.00	100	1	1	2
sha_en	2	0	2	100.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cfg_cross	16	0	16	100.00	100	1	1	0
hmac_dis_x_sha_en	4	0	4	100.00	100	1	1	0
key_x_digest_mismatch	35	0	35	100.00	100	1	1	0
key_length_x_digest_size	35	0	35	100.00	100	1	1	0

Summary for Variable digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for digest_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sha2_invalid	4732	1			T2	3		T3	77		T5	5
sha2_none	4586	1			T1	2		T2	3		T3	72
sha2_512	7926	1			T2	5		T3	61		T5	1
sha2_384	7426	1			T1	2		T2	6		T3	64
sha2_256	6729	1			T1	2		T2	6		T3	75

---

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19336

1

T1

5

T2

10

T3

169

auto[1]

12489

1

T1

1

T2

15

T3

188

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

12391

1

T1

2

T2

11

T3

195

auto[1]

19434

1

T1

4

T2

14

T3

162

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

16635

1

T1

2

T2

14

T3

198

disabled

15190

1

T1

4

T2

11

T3

159

---

Summary for Variable key_length

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for key_length

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	5177	1			T1	2		T2	4		T3	66
key_none	7627	1			T1	2		T2	4		T3	51
key_1024	4565	1			T2	5		T3	38		T6	3
key_512	4091	1			T2	6		T3	47		T5	3
key_384	3672	1			T2	3		T3	51		T6	2
key_256	3440	1			T1	1		T2	2		T3	38
key_128	3136	1			T1	1		T2	1		T3	63

---

Summary for Variable key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for key_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19579

1

T1

3

T2

14

T3

180

auto[1]

12246

1

T1

3

T2

11

T3

177

---

Summary for Variable sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

31646

1

T1

6

T2

25

T3

356

disabled

179

1

T3

1

T27

3

T53

1

---

Summary for Cross cfg_cross

Samples crossed: hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cfg_cross

Bins

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

auto[0]

auto[0]

auto[0]

1751

1

T2

1

T3

30

T5

1

enabled

auto[0]

auto[0]

auto[1]

1635

1

T2

1

T3

22

T6

1

enabled

auto[0]

auto[1]

auto[0]

1740

1

T2

2

T3

30

T5

1

enabled

auto[0]

auto[1]

auto[1]

1825

1

T2

3

T3

26

T5

5

enabled

auto[1]

auto[0]

auto[0]

4387

1

T2

1

T3

15

T10

2

enabled

auto[1]

auto[0]

auto[1]

1729

1

T1

1

T2

2

T3

22

enabled

auto[1]

auto[1]

auto[0]

1836

1

T1

1

T2

4

T3

28

enabled

auto[1]

auto[1]

auto[1]

1732

1

T3

25

T5

2

T10

1

disabled

auto[0]

auto[0]

auto[0]

1389

1

T1

1

T2

1

T3

20

disabled

auto[0]

auto[0]

auto[1]

1279

1

T1

1

T2

1

T3

23

disabled

auto[0]

auto[1]

auto[0]

1375

1

T3

23

T6

1

T16

2

disabled

auto[0]

auto[1]

auto[1]

1397

1

T2

2

T3

21

T10

2

disabled

auto[1]

auto[0]

auto[0]

5804

1

T1

1

T2

3

T3

20

disabled

auto[1]

auto[0]

auto[1]

1362

1

T1

1

T3

17

T6

1

disabled

auto[1]

auto[1]

auto[0]

1297

1

T2

2

T3

14

T4

2

disabled

auto[1]

auto[1]

auto[1]

1287

1

T2

2

T3

21

T10

1

---

Summary for Cross hmac_dis_x_sha_en

Samples crossed: hmac_en sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	3	0	3	100.00
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for hmac_dis_x_sha_en

Bins

hmac_en

sha_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

enabled

16574

1

T1

2

T2

14

T3

197

enabled

disabled

61

1

T3

1

T138

1

T7

1

disabled

disabled

118

1

T27

3

T53

1

T7

1

User Defined Cross Bins for hmac_dis_x_sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

15072

1

T1

4

T2

11

T3

159

---

Summary for Cross key_x_digest_mismatch

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	35	0	35	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for key_x_digest_mismatch

Bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	sha2_invalid	1252	1			T2	1		T3	9		T5	2
key_invalid	sha2_none	956	1			T1	1		T3	13		T5	1
key_invalid	sha2_512	906	1			T2	1		T3	15		T16	2
key_invalid	sha2_384	1004	1			T1	1		T3	14		T10	1
key_invalid	sha2_256	946	1			T2	2		T3	15		T16	1
key_none	sha2_invalid	540	1			T2	1		T3	16		T6	2
key_none	sha2_none	605	1			T3	8		T5	1		T6	1
key_none	sha2_512	2588	1			T3	11		T16	1		T4	1
key_none	sha2_384	2210	1			T2	2		T3	7		T10	1
key_none	sha2_256	1641	1			T1	2		T3	9		T5	1
key_1024	sha2_invalid	601	1			T3	10		T6	2		T16	1
key_1024	sha2_none	585	1			T2	1		T3	6		T16	2
key_1024	sha2_512	1772	1			T2	3		T3	7		T16	1
key_1024	sha2_384	950	1			T2	1		T3	6		T16	1
key_512	sha2_invalid	583	1			T2	1		T3	8		T5	3
key_512	sha2_none	621	1			T3	13		T10	1		T6	1
key_512	sha2_512	644	1			T3	6		T6	1		T4	2
key_512	sha2_384	1296	1			T2	3		T3	12		T6	1
key_512	sha2_256	900	1			T2	1		T3	8		T10	1
key_384	sha2_invalid	576	1			T3	11		T16	1		T24	3
key_384	sha2_none	613	1			T3	7		T24	2		T28	3
key_384	sha2_512	673	1			T3	9		T16	1		T4	2
key_384	sha2_384	645	1			T3	8		T6	2		T4	1
key_384	sha2_256	1108	1			T2	3		T3	15		T16	2
key_256	sha2_invalid	600	1			T3	8		T4	1		T24	3
key_256	sha2_none	615	1			T1	1		T2	2		T3	7
key_256	sha2_512	691	1			T3	5		T5	1		T24	1
key_256	sha2_384	690	1			T3	8		T16	1		T27	2
key_256	sha2_256	798	1			T3	9		T4	2		T18	2
key_128	sha2_invalid	549	1			T3	15		T10	2		T24	1
key_128	sha2_none	567	1			T3	16		T5	1		T71	1
key_128	sha2_512	632	1			T2	1		T3	8		T6	1
key_128	sha2_384	613	1			T1	1		T3	8		T24	1
key_128	sha2_256	708	1			T3	11		T5	1		T16	1

User Defined Cross Bins for key_x_digest_mismatch

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

608

1

T3

8

T6

1

T4

2

---

Summary for Cross key_length_x_digest_size

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	35	0	35	100.00

Automatically Generated Cross Bins for key_length_x_digest_size

Bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	sha2_invalid	1252	1			T2	1		T3	9		T5	2
key_invalid	sha2_none	956	1			T1	1		T3	13		T5	1
key_invalid	sha2_512	906	1			T2	1		T3	15		T16	2
key_invalid	sha2_384	1004	1			T1	1		T3	14		T10	1
key_invalid	sha2_256	946	1			T2	2		T3	15		T16	1
key_none	sha2_invalid	540	1			T2	1		T3	16		T6	2
key_none	sha2_none	605	1			T3	8		T5	1		T6	1
key_none	sha2_512	2588	1			T3	11		T16	1		T4	1
key_none	sha2_384	2210	1			T2	2		T3	7		T10	1
key_none	sha2_256	1641	1			T1	2		T3	9		T5	1
key_1024	sha2_invalid	601	1			T3	10		T6	2		T16	1
key_1024	sha2_none	585	1			T2	1		T3	6		T16	2
key_1024	sha2_512	1772	1			T2	3		T3	7		T16	1
key_1024	sha2_384	950	1			T2	1		T3	6		T16	1
key_1024	sha2_256	608	1			T3	8		T6	1		T4	2
key_512	sha2_invalid	583	1			T2	1		T3	8		T5	3
key_512	sha2_none	621	1			T3	13		T10	1		T6	1
key_512	sha2_512	644	1			T3	6		T6	1		T4	2
key_512	sha2_384	1296	1			T2	3		T3	12		T6	1
key_512	sha2_256	900	1			T2	1		T3	8		T10	1
key_384	sha2_invalid	576	1			T3	11		T16	1		T24	3
key_384	sha2_none	613	1			T3	7		T24	2		T28	3
key_384	sha2_512	673	1			T3	9		T16	1		T4	2
key_384	sha2_384	645	1			T3	8		T6	2		T4	1
key_384	sha2_256	1108	1			T2	3		T3	15		T16	2
key_256	sha2_invalid	600	1			T3	8		T4	1		T24	3
key_256	sha2_none	615	1			T1	1		T2	2		T3	7
key_256	sha2_512	691	1			T3	5		T5	1		T24	1
key_256	sha2_384	690	1			T3	8		T16	1		T27	2
key_256	sha2_256	798	1			T3	9		T4	2		T18	2
key_128	sha2_invalid	549	1			T3	15		T10	2		T24	1
key_128	sha2_none	567	1			T3	16		T5	1		T71	1
key_128	sha2_512	632	1			T2	1		T3	8		T6	1
key_128	sha2_384	613	1			T1	1		T3	8		T24	1
key_128	sha2_256	708	1			T3	11		T5	1		T16	1