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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.52 95.95 94.29 100.00 87.18 92.33 99.49 99.42


Total test records in report: 658
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T115 /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.2399700854 Jul 02 09:39:39 AM PDT 24 Jul 02 09:39:42 AM PDT 24 178879477 ps
T531 /workspace/coverage/cover_reg_top/9.hmac_tl_errors.4028178244 Jul 02 09:39:33 AM PDT 24 Jul 02 09:39:36 AM PDT 24 916545427 ps
T532 /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.2892168621 Jul 02 09:39:36 AM PDT 24 Jul 02 09:39:41 AM PDT 24 197452729 ps
T533 /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.2019951601 Jul 02 09:39:46 AM PDT 24 Jul 02 09:39:49 AM PDT 24 48349219 ps
T534 /workspace/coverage/cover_reg_top/26.hmac_intr_test.1111648389 Jul 02 09:39:52 AM PDT 24 Jul 02 09:39:54 AM PDT 24 123091930 ps
T68 /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.4293250640 Jul 02 09:39:28 AM PDT 24 Jul 02 09:39:32 AM PDT 24 326358729 ps
T535 /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.305183730 Jul 02 09:39:24 AM PDT 24 Jul 02 09:39:26 AM PDT 24 140411164 ps
T536 /workspace/coverage/cover_reg_top/17.hmac_intr_test.616013544 Jul 02 09:39:48 AM PDT 24 Jul 02 09:39:50 AM PDT 24 30837122 ps
T102 /workspace/coverage/cover_reg_top/17.hmac_csr_rw.1504749676 Jul 02 09:39:47 AM PDT 24 Jul 02 09:39:49 AM PDT 24 15084783 ps
T116 /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.352616146 Jul 02 09:39:35 AM PDT 24 Jul 02 09:39:38 AM PDT 24 206253519 ps
T537 /workspace/coverage/cover_reg_top/42.hmac_intr_test.3798488238 Jul 02 09:39:57 AM PDT 24 Jul 02 09:39:59 AM PDT 24 26064854 ps
T538 /workspace/coverage/cover_reg_top/24.hmac_intr_test.1572551756 Jul 02 09:39:53 AM PDT 24 Jul 02 09:39:55 AM PDT 24 61333031 ps
T539 /workspace/coverage/cover_reg_top/11.hmac_intr_test.2304869323 Jul 02 09:39:35 AM PDT 24 Jul 02 09:39:36 AM PDT 24 11767623 ps
T540 /workspace/coverage/cover_reg_top/6.hmac_tl_errors.996083994 Jul 02 09:39:30 AM PDT 24 Jul 02 09:39:35 AM PDT 24 982425267 ps
T103 /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.897633544 Jul 02 09:39:34 AM PDT 24 Jul 02 09:39:36 AM PDT 24 70179035 ps
T104 /workspace/coverage/cover_reg_top/15.hmac_csr_rw.3950127624 Jul 02 09:39:46 AM PDT 24 Jul 02 09:39:47 AM PDT 24 25396444 ps
T541 /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.1523372087 Jul 02 09:39:29 AM PDT 24 Jul 02 09:39:31 AM PDT 24 103061345 ps
T117 /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.3045880059 Jul 02 09:39:33 AM PDT 24 Jul 02 09:39:35 AM PDT 24 190364533 ps
T542 /workspace/coverage/cover_reg_top/15.hmac_intr_test.2007140030 Jul 02 09:39:44 AM PDT 24 Jul 02 09:39:46 AM PDT 24 31154256 ps
T105 /workspace/coverage/cover_reg_top/1.hmac_csr_rw.3149621781 Jul 02 09:39:22 AM PDT 24 Jul 02 09:39:24 AM PDT 24 172303566 ps
T69 /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.2481560373 Jul 02 09:39:23 AM PDT 24 Jul 02 09:39:26 AM PDT 24 123091895 ps
T70 /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.3034203186 Jul 02 09:39:48 AM PDT 24 Jul 02 09:39:51 AM PDT 24 157309863 ps
T543 /workspace/coverage/cover_reg_top/8.hmac_tl_errors.2932119674 Jul 02 09:39:33 AM PDT 24 Jul 02 09:39:38 AM PDT 24 238405601 ps
T544 /workspace/coverage/cover_reg_top/17.hmac_tl_errors.572362114 Jul 02 09:39:45 AM PDT 24 Jul 02 09:39:50 AM PDT 24 189428840 ps
T129 /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.209916108 Jul 02 09:39:36 AM PDT 24 Jul 02 09:39:42 AM PDT 24 248422707 ps
T545 /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.184197713 Jul 02 09:39:21 AM PDT 24 Jul 02 09:39:22 AM PDT 24 18782458 ps
T134 /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.506182958 Jul 02 09:39:52 AM PDT 24 Jul 02 09:39:57 AM PDT 24 367300555 ps
T546 /workspace/coverage/cover_reg_top/3.hmac_intr_test.1974190991 Jul 02 09:39:32 AM PDT 24 Jul 02 09:39:33 AM PDT 24 15609008 ps
T547 /workspace/coverage/cover_reg_top/28.hmac_intr_test.3053012397 Jul 02 09:39:53 AM PDT 24 Jul 02 09:39:56 AM PDT 24 19016717 ps
T548 /workspace/coverage/cover_reg_top/44.hmac_intr_test.773731492 Jul 02 09:39:56 AM PDT 24 Jul 02 09:39:58 AM PDT 24 21173528 ps
T118 /workspace/coverage/cover_reg_top/14.hmac_csr_rw.4094873954 Jul 02 09:39:43 AM PDT 24 Jul 02 09:39:44 AM PDT 24 64296668 ps
T549 /workspace/coverage/cover_reg_top/33.hmac_intr_test.4196377968 Jul 02 09:39:52 AM PDT 24 Jul 02 09:39:54 AM PDT 24 35557821 ps
T550 /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.180832699 Jul 02 09:39:34 AM PDT 24 Jul 02 09:39:37 AM PDT 24 238445011 ps
T106 /workspace/coverage/cover_reg_top/2.hmac_csr_rw.903050867 Jul 02 09:39:26 AM PDT 24 Jul 02 09:39:27 AM PDT 24 88846291 ps
T107 /workspace/coverage/cover_reg_top/19.hmac_csr_rw.756536628 Jul 02 09:39:50 AM PDT 24 Jul 02 09:39:52 AM PDT 24 12334694 ps
T551 /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.2385399866 Jul 02 09:39:26 AM PDT 24 Jul 02 09:39:28 AM PDT 24 31045544 ps
T552 /workspace/coverage/cover_reg_top/13.hmac_intr_test.3361252898 Jul 02 09:39:42 AM PDT 24 Jul 02 09:39:43 AM PDT 24 177207347 ps
T553 /workspace/coverage/cover_reg_top/9.hmac_csr_rw.2255278816 Jul 02 09:39:37 AM PDT 24 Jul 02 09:39:39 AM PDT 24 527710570 ps
T554 /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.742247750 Jul 02 09:39:29 AM PDT 24 Jul 02 09:39:30 AM PDT 24 32785359 ps
T119 /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.3703308408 Jul 02 09:39:45 AM PDT 24 Jul 02 09:39:48 AM PDT 24 118298600 ps
T555 /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.1802448998 Jul 02 09:39:31 AM PDT 24 Jul 02 09:39:35 AM PDT 24 176478165 ps
T120 /workspace/coverage/cover_reg_top/10.hmac_csr_rw.910126646 Jul 02 09:39:37 AM PDT 24 Jul 02 09:39:39 AM PDT 24 13660132 ps
T556 /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.546935793 Jul 02 09:39:20 AM PDT 24 Jul 02 09:39:24 AM PDT 24 774582113 ps
T557 /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.3990009694 Jul 02 09:39:24 AM PDT 24 Jul 02 09:40:55 AM PDT 24 6122034093 ps
T558 /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.1329406351 Jul 02 09:39:22 AM PDT 24 Jul 02 09:39:29 AM PDT 24 362846369 ps
T559 /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.2608641129 Jul 02 09:39:46 AM PDT 24 Jul 02 09:39:49 AM PDT 24 109812632 ps
T560 /workspace/coverage/cover_reg_top/36.hmac_intr_test.1134521748 Jul 02 09:39:54 AM PDT 24 Jul 02 09:39:57 AM PDT 24 18048513 ps
T561 /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.1766000151 Jul 02 09:39:23 AM PDT 24 Jul 02 09:39:26 AM PDT 24 71131475 ps
T108 /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.472890031 Jul 02 09:39:18 AM PDT 24 Jul 02 09:39:24 AM PDT 24 1394829137 ps
T562 /workspace/coverage/cover_reg_top/4.hmac_intr_test.3100160912 Jul 02 09:39:28 AM PDT 24 Jul 02 09:39:29 AM PDT 24 47417518 ps
T109 /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.2841151804 Jul 02 09:39:30 AM PDT 24 Jul 02 09:39:39 AM PDT 24 184849905 ps
T111 /workspace/coverage/cover_reg_top/13.hmac_csr_rw.1075773615 Jul 02 09:39:42 AM PDT 24 Jul 02 09:39:43 AM PDT 24 17763551 ps
T563 /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.3169559902 Jul 02 09:39:33 AM PDT 24 Jul 02 09:39:36 AM PDT 24 127583399 ps
T564 /workspace/coverage/cover_reg_top/30.hmac_intr_test.3995731088 Jul 02 09:39:51 AM PDT 24 Jul 02 09:39:52 AM PDT 24 40608003 ps
T565 /workspace/coverage/cover_reg_top/12.hmac_csr_rw.3457640733 Jul 02 09:39:38 AM PDT 24 Jul 02 09:39:40 AM PDT 24 24880908 ps
T566 /workspace/coverage/cover_reg_top/10.hmac_intr_test.4091410557 Jul 02 09:39:37 AM PDT 24 Jul 02 09:39:38 AM PDT 24 29527194 ps
T567 /workspace/coverage/cover_reg_top/25.hmac_intr_test.2698189399 Jul 02 09:39:52 AM PDT 24 Jul 02 09:39:54 AM PDT 24 20144461 ps
T568 /workspace/coverage/cover_reg_top/18.hmac_tl_errors.4249261383 Jul 02 09:39:48 AM PDT 24 Jul 02 09:39:53 AM PDT 24 155640913 ps
T569 /workspace/coverage/cover_reg_top/5.hmac_csr_rw.4102066409 Jul 02 09:39:34 AM PDT 24 Jul 02 09:39:37 AM PDT 24 32266910 ps
T570 /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.1850510827 Jul 02 09:39:38 AM PDT 24 Jul 02 09:39:41 AM PDT 24 186921828 ps
T571 /workspace/coverage/cover_reg_top/7.hmac_intr_test.770127013 Jul 02 09:39:34 AM PDT 24 Jul 02 09:39:36 AM PDT 24 17417072 ps
T572 /workspace/coverage/cover_reg_top/15.hmac_tl_errors.3776202426 Jul 02 09:39:46 AM PDT 24 Jul 02 09:39:51 AM PDT 24 89660217 ps
T573 /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.3715742025 Jul 02 09:39:51 AM PDT 24 Jul 02 09:39:55 AM PDT 24 516193260 ps
T574 /workspace/coverage/cover_reg_top/3.hmac_csr_rw.389818336 Jul 02 09:39:24 AM PDT 24 Jul 02 09:39:25 AM PDT 24 20231794 ps
T575 /workspace/coverage/cover_reg_top/21.hmac_intr_test.1711011024 Jul 02 09:39:54 AM PDT 24 Jul 02 09:39:57 AM PDT 24 20323098 ps
T576 /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.1214134548 Jul 02 09:39:46 AM PDT 24 Jul 02 09:39:49 AM PDT 24 688849701 ps
T577 /workspace/coverage/cover_reg_top/23.hmac_intr_test.2271369746 Jul 02 09:39:52 AM PDT 24 Jul 02 09:39:54 AM PDT 24 31287785 ps
T578 /workspace/coverage/cover_reg_top/14.hmac_tl_errors.1558591326 Jul 02 09:39:42 AM PDT 24 Jul 02 09:39:45 AM PDT 24 456535656 ps
T579 /workspace/coverage/cover_reg_top/46.hmac_intr_test.900165095 Jul 02 09:39:55 AM PDT 24 Jul 02 09:39:58 AM PDT 24 17823920 ps
T135 /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.56860704 Jul 02 09:39:32 AM PDT 24 Jul 02 09:39:35 AM PDT 24 52191150 ps
T131 /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.3031581890 Jul 02 09:39:29 AM PDT 24 Jul 02 09:39:32 AM PDT 24 808831712 ps
T580 /workspace/coverage/cover_reg_top/11.hmac_tl_errors.3097158668 Jul 02 09:39:36 AM PDT 24 Jul 02 09:39:39 AM PDT 24 35155538 ps
T581 /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.2679998302 Jul 02 09:39:36 AM PDT 24 Jul 02 09:39:40 AM PDT 24 89454558 ps
T582 /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.910835887 Jul 02 09:39:37 AM PDT 24 Jul 02 09:39:39 AM PDT 24 172234413 ps
T583 /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.4144472260 Jul 02 09:39:28 AM PDT 24 Jul 02 09:39:30 AM PDT 24 251774026 ps
T584 /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.2397823187 Jul 02 09:39:47 AM PDT 24 Jul 02 09:39:50 AM PDT 24 96082991 ps
T585 /workspace/coverage/cover_reg_top/31.hmac_intr_test.3497732164 Jul 02 09:39:54 AM PDT 24 Jul 02 09:39:57 AM PDT 24 165430416 ps
T132 /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.3684315325 Jul 02 09:39:24 AM PDT 24 Jul 02 09:39:28 AM PDT 24 328421766 ps
T586 /workspace/coverage/cover_reg_top/12.hmac_tl_errors.2221372019 Jul 02 09:39:39 AM PDT 24 Jul 02 09:39:43 AM PDT 24 199336421 ps
T587 /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.175791288 Jul 02 09:39:42 AM PDT 24 Jul 02 09:39:45 AM PDT 24 456289806 ps
T588 /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.2367191494 Jul 02 09:39:23 AM PDT 24 Jul 02 09:39:26 AM PDT 24 371166046 ps
T589 /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.4005695133 Jul 02 09:39:25 AM PDT 24 Jul 02 09:39:35 AM PDT 24 451009149 ps
T112 /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.1996500745 Jul 02 09:39:23 AM PDT 24 Jul 02 09:39:27 AM PDT 24 317431498 ps
T590 /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.2412380857 Jul 02 09:39:23 AM PDT 24 Jul 02 09:39:40 AM PDT 24 1147483019 ps
T591 /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.4214529749 Jul 02 09:39:29 AM PDT 24 Jul 02 09:57:53 AM PDT 24 233856695171 ps
T137 /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.4121734139 Jul 02 09:39:41 AM PDT 24 Jul 02 09:39:43 AM PDT 24 185027921 ps
T592 /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.279492661 Jul 02 09:39:48 AM PDT 24 Jul 02 09:39:50 AM PDT 24 48130089 ps
T593 /workspace/coverage/cover_reg_top/34.hmac_intr_test.2007321736 Jul 02 09:39:53 AM PDT 24 Jul 02 09:39:55 AM PDT 24 25099130 ps
T113 /workspace/coverage/cover_reg_top/8.hmac_csr_rw.792611578 Jul 02 09:39:34 AM PDT 24 Jul 02 09:39:36 AM PDT 24 193609769 ps
T594 /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.2309186178 Jul 02 09:39:19 AM PDT 24 Jul 02 09:39:20 AM PDT 24 47676999 ps
T595 /workspace/coverage/cover_reg_top/14.hmac_intr_test.3112903102 Jul 02 09:39:43 AM PDT 24 Jul 02 09:39:44 AM PDT 24 50594244 ps
T596 /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.2653662842 Jul 02 09:39:19 AM PDT 24 Jul 02 09:39:22 AM PDT 24 168272310 ps
T597 /workspace/coverage/cover_reg_top/16.hmac_tl_errors.964219841 Jul 02 09:39:46 AM PDT 24 Jul 02 09:39:50 AM PDT 24 836436692 ps
T598 /workspace/coverage/cover_reg_top/45.hmac_intr_test.270441099 Jul 02 09:39:56 AM PDT 24 Jul 02 09:39:58 AM PDT 24 16278997 ps
T599 /workspace/coverage/cover_reg_top/7.hmac_tl_errors.36324666 Jul 02 09:39:36 AM PDT 24 Jul 02 09:39:41 AM PDT 24 862281640 ps
T600 /workspace/coverage/cover_reg_top/16.hmac_csr_rw.1853913688 Jul 02 09:39:46 AM PDT 24 Jul 02 09:39:48 AM PDT 24 58147883 ps
T601 /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.1228003808 Jul 02 09:39:38 AM PDT 24 Jul 02 09:39:42 AM PDT 24 75121177 ps
T602 /workspace/coverage/cover_reg_top/11.hmac_csr_rw.1902023800 Jul 02 09:39:36 AM PDT 24 Jul 02 09:39:39 AM PDT 24 248781844 ps
T603 /workspace/coverage/cover_reg_top/41.hmac_intr_test.1812173026 Jul 02 09:39:56 AM PDT 24 Jul 02 09:39:58 AM PDT 24 11917968 ps
T604 /workspace/coverage/cover_reg_top/9.hmac_intr_test.2024672194 Jul 02 09:39:32 AM PDT 24 Jul 02 09:39:33 AM PDT 24 229081096 ps
T605 /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.2196010770 Jul 02 09:39:42 AM PDT 24 Jul 02 09:39:44 AM PDT 24 327565693 ps
T606 /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.1620303891 Jul 02 09:39:35 AM PDT 24 Jul 02 09:39:37 AM PDT 24 59522477 ps
T607 /workspace/coverage/cover_reg_top/29.hmac_intr_test.645914665 Jul 02 09:39:51 AM PDT 24 Jul 02 09:39:53 AM PDT 24 18124302 ps
T608 /workspace/coverage/cover_reg_top/13.hmac_tl_errors.3462970587 Jul 02 09:39:41 AM PDT 24 Jul 02 09:39:45 AM PDT 24 510957628 ps
T72 /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.2302208313 Jul 02 09:39:43 AM PDT 24 Jul 02 09:39:47 AM PDT 24 793852489 ps
T609 /workspace/coverage/cover_reg_top/5.hmac_tl_errors.337296400 Jul 02 09:39:27 AM PDT 24 Jul 02 09:39:32 AM PDT 24 233738514 ps
T610 /workspace/coverage/cover_reg_top/0.hmac_tl_errors.559612514 Jul 02 09:39:21 AM PDT 24 Jul 02 09:39:25 AM PDT 24 187879116 ps
T611 /workspace/coverage/cover_reg_top/32.hmac_intr_test.937891144 Jul 02 09:39:51 AM PDT 24 Jul 02 09:39:52 AM PDT 24 32265745 ps
T612 /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.1403509072 Jul 02 09:39:49 AM PDT 24 Jul 02 09:39:51 AM PDT 24 921587566 ps
T613 /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.3082877172 Jul 02 09:39:46 AM PDT 24 Jul 02 09:39:50 AM PDT 24 732268237 ps
T614 /workspace/coverage/cover_reg_top/1.hmac_intr_test.129321905 Jul 02 09:39:22 AM PDT 24 Jul 02 09:39:24 AM PDT 24 11409421 ps
T615 /workspace/coverage/cover_reg_top/18.hmac_csr_rw.635851644 Jul 02 09:39:53 AM PDT 24 Jul 02 09:39:56 AM PDT 24 19758806 ps
T616 /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.2858627695 Jul 02 09:39:17 AM PDT 24 Jul 02 09:39:21 AM PDT 24 1309905850 ps
T617 /workspace/coverage/cover_reg_top/0.hmac_intr_test.1488336548 Jul 02 09:39:21 AM PDT 24 Jul 02 09:39:22 AM PDT 24 45868471 ps
T618 /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.2620965759 Jul 02 09:39:47 AM PDT 24 Jul 02 09:39:50 AM PDT 24 133388593 ps
T619 /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.1275753826 Jul 02 09:39:37 AM PDT 24 Jul 02 09:39:41 AM PDT 24 382671085 ps
T620 /workspace/coverage/cover_reg_top/38.hmac_intr_test.2191315082 Jul 02 09:39:51 AM PDT 24 Jul 02 09:39:53 AM PDT 24 34983008 ps
T621 /workspace/coverage/cover_reg_top/19.hmac_tl_errors.1474043280 Jul 02 09:39:53 AM PDT 24 Jul 02 09:39:56 AM PDT 24 204053891 ps
T622 /workspace/coverage/cover_reg_top/18.hmac_intr_test.2158172482 Jul 02 09:39:46 AM PDT 24 Jul 02 09:39:47 AM PDT 24 81072134 ps
T623 /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.3885506184 Jul 02 09:39:45 AM PDT 24 Jul 02 09:46:25 AM PDT 24 50517962921 ps
T624 /workspace/coverage/cover_reg_top/4.hmac_csr_rw.4033108235 Jul 02 09:39:30 AM PDT 24 Jul 02 09:39:32 AM PDT 24 111036524 ps
T625 /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.69235983 Jul 02 09:39:52 AM PDT 24 Jul 02 09:39:55 AM PDT 24 25262610 ps
T136 /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.245652401 Jul 02 09:39:30 AM PDT 24 Jul 02 09:39:32 AM PDT 24 201863383 ps
T626 /workspace/coverage/cover_reg_top/40.hmac_intr_test.1052950410 Jul 02 09:39:55 AM PDT 24 Jul 02 09:39:57 AM PDT 24 15980780 ps
T627 /workspace/coverage/cover_reg_top/35.hmac_intr_test.2779210286 Jul 02 09:39:52 AM PDT 24 Jul 02 09:39:54 AM PDT 24 24485301 ps
T628 /workspace/coverage/cover_reg_top/7.hmac_csr_rw.3400715412 Jul 02 09:39:34 AM PDT 24 Jul 02 09:39:36 AM PDT 24 25491794 ps
T629 /workspace/coverage/cover_reg_top/2.hmac_tl_errors.285881245 Jul 02 09:39:32 AM PDT 24 Jul 02 09:39:37 AM PDT 24 183245801 ps
T630 /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.775401724 Jul 02 09:39:46 AM PDT 24 Jul 02 09:39:48 AM PDT 24 43054116 ps
T631 /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.3175884675 Jul 02 09:39:24 AM PDT 24 Jul 02 09:39:39 AM PDT 24 640319368 ps
T632 /workspace/coverage/cover_reg_top/27.hmac_intr_test.3025626670 Jul 02 09:39:52 AM PDT 24 Jul 02 09:39:54 AM PDT 24 30485219 ps
T633 /workspace/coverage/cover_reg_top/8.hmac_intr_test.3961440256 Jul 02 09:39:35 AM PDT 24 Jul 02 09:39:37 AM PDT 24 33880278 ps
T130 /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.3543287569 Jul 02 09:39:31 AM PDT 24 Jul 02 09:39:34 AM PDT 24 378864626 ps
T634 /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.2980926313 Jul 02 09:39:22 AM PDT 24 Jul 02 09:39:25 AM PDT 24 189164883 ps
T635 /workspace/coverage/cover_reg_top/19.hmac_intr_test.2579724103 Jul 02 09:39:53 AM PDT 24 Jul 02 09:39:55 AM PDT 24 29938296 ps
T636 /workspace/coverage/cover_reg_top/1.hmac_tl_errors.3480393894 Jul 02 09:39:21 AM PDT 24 Jul 02 09:39:26 AM PDT 24 2422277049 ps
T637 /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.2471089909 Jul 02 09:39:50 AM PDT 24 Jul 02 09:39:53 AM PDT 24 594500723 ps
T638 /workspace/coverage/cover_reg_top/5.hmac_intr_test.4100195571 Jul 02 09:39:28 AM PDT 24 Jul 02 09:39:29 AM PDT 24 21018238 ps
T639 /workspace/coverage/cover_reg_top/39.hmac_intr_test.4009003644 Jul 02 09:39:52 AM PDT 24 Jul 02 09:39:54 AM PDT 24 14624907 ps
T640 /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.832039988 Jul 02 09:39:48 AM PDT 24 Jul 02 09:39:50 AM PDT 24 203934105 ps
T641 /workspace/coverage/cover_reg_top/16.hmac_intr_test.1202567828 Jul 02 09:39:45 AM PDT 24 Jul 02 09:39:46 AM PDT 24 14157430 ps
T642 /workspace/coverage/cover_reg_top/0.hmac_csr_rw.3965529979 Jul 02 09:39:23 AM PDT 24 Jul 02 09:39:24 AM PDT 24 48389396 ps
T643 /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.1264649547 Jul 02 09:39:55 AM PDT 24 Jul 02 09:39:59 AM PDT 24 37040598 ps
T644 /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.523175459 Jul 02 09:39:43 AM PDT 24 Jul 02 09:39:45 AM PDT 24 86556260 ps
T645 /workspace/coverage/cover_reg_top/43.hmac_intr_test.2260995396 Jul 02 09:39:55 AM PDT 24 Jul 02 09:39:57 AM PDT 24 37649419 ps
T646 /workspace/coverage/cover_reg_top/22.hmac_intr_test.250852101 Jul 02 09:39:51 AM PDT 24 Jul 02 09:39:53 AM PDT 24 34104545 ps
T647 /workspace/coverage/cover_reg_top/48.hmac_intr_test.2282987500 Jul 02 09:39:56 AM PDT 24 Jul 02 09:39:58 AM PDT 24 13088688 ps
T648 /workspace/coverage/cover_reg_top/47.hmac_intr_test.4171253371 Jul 02 09:40:09 AM PDT 24 Jul 02 09:40:11 AM PDT 24 40662275 ps
T649 /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.512777864 Jul 02 09:39:38 AM PDT 24 Jul 02 09:39:40 AM PDT 24 45979659 ps
T650 /workspace/coverage/cover_reg_top/4.hmac_tl_errors.4267121590 Jul 02 09:39:31 AM PDT 24 Jul 02 09:39:35 AM PDT 24 601147166 ps
T651 /workspace/coverage/cover_reg_top/37.hmac_intr_test.1209244936 Jul 02 09:39:51 AM PDT 24 Jul 02 09:39:52 AM PDT 24 49343264 ps
T652 /workspace/coverage/cover_reg_top/3.hmac_tl_errors.26222647 Jul 02 09:39:25 AM PDT 24 Jul 02 09:39:30 AM PDT 24 185421641 ps
T653 /workspace/coverage/cover_reg_top/2.hmac_intr_test.131852292 Jul 02 09:39:26 AM PDT 24 Jul 02 09:39:27 AM PDT 24 24376228 ps
T654 /workspace/coverage/cover_reg_top/49.hmac_intr_test.392400933 Jul 02 09:39:57 AM PDT 24 Jul 02 09:39:59 AM PDT 24 16294243 ps
T655 /workspace/coverage/cover_reg_top/12.hmac_intr_test.426858874 Jul 02 09:39:38 AM PDT 24 Jul 02 09:39:40 AM PDT 24 176158916 ps
T656 /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.2718819927 Jul 02 09:39:47 AM PDT 24 Jul 02 09:39:49 AM PDT 24 65081640 ps
T657 /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.1318092278 Jul 02 09:39:37 AM PDT 24 Jul 02 09:39:40 AM PDT 24 75566807 ps
T133 /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.931799411 Jul 02 09:39:48 AM PDT 24 Jul 02 09:39:53 AM PDT 24 404191939 ps
T658 /workspace/coverage/cover_reg_top/10.hmac_tl_errors.1548446260 Jul 02 09:39:39 AM PDT 24 Jul 02 09:39:42 AM PDT 24 48896804 ps

Test location /workspace/coverage/default/20.hmac_stress_all.3391053726
Short name T3
Test name
Test status
Simulation time 62538619711 ps
CPU time 1136.41 seconds
Started Jul 02 09:43:01 AM PDT 24
Finished Jul 02 10:01:58 AM PDT 24
Peak memory 674484 kb
Host smart-e3333894-8475-4649-b684-3ccdff97788d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391053726 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.hmac_stress_all.3391053726
Directory /workspace/20.hmac_stress_all/latest

Test location /workspace/coverage/default/2.hmac_stress_all_with_rand_reset.1596988632
Short name T7
Test name
Test status
Simulation time 123965485813 ps
CPU time 950.68 seconds
Started Jul 02 09:42:33 AM PDT 24
Finished Jul 02 09:58:25 AM PDT 24
Peak memory 216864 kb
Host smart-396b2bcd-4b37-48a3-8fbc-c925ef99463d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1596988632 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all_with_rand_reset.1596988632
Directory /workspace/2.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.hmac_smoke.1058763480
Short name T28
Test name
Test status
Simulation time 1330259082 ps
CPU time 9.71 seconds
Started Jul 02 09:43:25 AM PDT 24
Finished Jul 02 09:43:35 AM PDT 24
Peak memory 200432 kb
Host smart-091001ed-9af4-40d6-acef-71e011b3775d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058763480 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_smoke.1058763480
Directory /workspace/30.hmac_smoke/latest

Test location /workspace/coverage/default/4.hmac_stress_all_with_rand_reset.3537719197
Short name T9
Test name
Test status
Simulation time 66761480488 ps
CPU time 4140.52 seconds
Started Jul 02 09:42:48 AM PDT 24
Finished Jul 02 10:51:50 AM PDT 24
Peak memory 737564 kb
Host smart-ac245e91-b12d-45c0-9682-5c8a45181732
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3537719197 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all_with_rand_reset.3537719197
Directory /workspace/4.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.209916108
Short name T129
Test name
Test status
Simulation time 248422707 ps
CPU time 4.15 seconds
Started Jul 02 09:39:36 AM PDT 24
Finished Jul 02 09:39:42 AM PDT 24
Peak memory 199540 kb
Host smart-f361d921-dad9-4946-8c1e-28604cbb0abc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209916108 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_intg_err.209916108
Directory /workspace/11.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/9.hmac_stress_all_with_rand_reset.960574001
Short name T23
Test name
Test status
Simulation time 243856899855 ps
CPU time 10737.2 seconds
Started Jul 02 09:42:50 AM PDT 24
Finished Jul 02 12:41:50 PM PDT 24
Peak memory 955572 kb
Host smart-eedecb23-c3cf-423f-8b2e-24850012048c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=960574001 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all_with_rand_reset.960574001
Directory /workspace/9.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.hmac_sec_cm.3545675045
Short name T56
Test name
Test status
Simulation time 302888500 ps
CPU time 1.02 seconds
Started Jul 02 09:42:32 AM PDT 24
Finished Jul 02 09:42:34 AM PDT 24
Peak memory 219512 kb
Host smart-c6e0d84b-1781-4564-80d1-26318b269d73
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545675045 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_sec_cm.3545675045
Directory /workspace/2.hmac_sec_cm/latest

Test location /workspace/coverage/default/11.hmac_back_pressure.4035895391
Short name T29
Test name
Test status
Simulation time 2235374941 ps
CPU time 60.04 seconds
Started Jul 02 09:42:51 AM PDT 24
Finished Jul 02 09:43:52 AM PDT 24
Peak memory 200472 kb
Host smart-6fa2ca33-1131-449f-87dd-9149d3a33659
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4035895391 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_back_pressure.4035895391
Directory /workspace/11.hmac_back_pressure/latest

Test location /workspace/coverage/default/30.hmac_datapath_stress.423635492
Short name T18
Test name
Test status
Simulation time 1955694981 ps
CPU time 156.24 seconds
Started Jul 02 09:43:24 AM PDT 24
Finished Jul 02 09:46:02 AM PDT 24
Peak memory 593116 kb
Host smart-94c0e612-1afc-412a-8c96-3e58a808092c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=423635492 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_datapath_stress.423635492
Directory /workspace/30.hmac_datapath_stress/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_rw.1075773615
Short name T111
Test name
Test status
Simulation time 17763551 ps
CPU time 0.98 seconds
Started Jul 02 09:39:42 AM PDT 24
Finished Jul 02 09:39:43 AM PDT 24
Peak memory 199416 kb
Host smart-6a48cf4a-fae5-478b-ab5b-4936b96261bd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075773615 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_rw.1075773615
Directory /workspace/13.hmac_csr_rw/latest

Test location /workspace/coverage/default/2.hmac_long_msg.2199083273
Short name T140
Test name
Test status
Simulation time 2434247957 ps
CPU time 134.63 seconds
Started Jul 02 09:42:30 AM PDT 24
Finished Jul 02 09:44:45 AM PDT 24
Peak memory 200492 kb
Host smart-da0e2275-2149-4b42-87ce-1175dfbe4061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199083273 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_long_msg.2199083273
Directory /workspace/2.hmac_long_msg/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.3031581890
Short name T131
Test name
Test status
Simulation time 808831712 ps
CPU time 2.71 seconds
Started Jul 02 09:39:29 AM PDT 24
Finished Jul 02 09:39:32 AM PDT 24
Peak memory 199544 kb
Host smart-a78df8ec-bd16-4435-a3b6-12d5568fcf50
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031581890 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_intg_err.3031581890
Directory /workspace/6.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/17.hmac_alert_test.958986207
Short name T67
Test name
Test status
Simulation time 14619212 ps
CPU time 0.59 seconds
Started Jul 02 09:42:58 AM PDT 24
Finished Jul 02 09:43:00 AM PDT 24
Peak memory 195144 kb
Host smart-7ca2dfbb-f4a5-43c2-b95b-00407c6b0212
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958986207 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_alert_test.958986207
Directory /workspace/17.hmac_alert_test/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.2302208313
Short name T72
Test name
Test status
Simulation time 793852489 ps
CPU time 3.38 seconds
Started Jul 02 09:39:43 AM PDT 24
Finished Jul 02 09:39:47 AM PDT 24
Peak memory 199540 kb
Host smart-34fbdd31-1c25-4b3c-9fe2-7050f98b6ee8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302208313 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_intg_err.2302208313
Directory /workspace/14.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.2481560373
Short name T69
Test name
Test status
Simulation time 123091895 ps
CPU time 1.84 seconds
Started Jul 02 09:39:23 AM PDT 24
Finished Jul 02 09:39:26 AM PDT 24
Peak memory 199592 kb
Host smart-6950a375-f164-4706-bfb8-f8c2f778edbc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481560373 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_intg_err.2481560373
Directory /workspace/3.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.3543287569
Short name T130
Test name
Test status
Simulation time 378864626 ps
CPU time 1.84 seconds
Started Jul 02 09:39:31 AM PDT 24
Finished Jul 02 09:39:34 AM PDT 24
Peak memory 199552 kb
Host smart-c78c92cb-baea-42ad-919b-370df75a0445
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543287569 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_intg_err.3543287569
Directory /workspace/8.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.hmac_stress_all_with_rand_reset.1463467700
Short name T8
Test name
Test status
Simulation time 484425131516 ps
CPU time 3692.53 seconds
Started Jul 02 09:42:30 AM PDT 24
Finished Jul 02 10:44:04 AM PDT 24
Peak memory 828380 kb
Host smart-d65b2de5-e3fe-4b71-a36f-1dea345b4a01
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1463467700 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all_with_rand_reset.1463467700
Directory /workspace/0.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.472890031
Short name T108
Test name
Test status
Simulation time 1394829137 ps
CPU time 5.82 seconds
Started Jul 02 09:39:18 AM PDT 24
Finished Jul 02 09:39:24 AM PDT 24
Peak memory 199608 kb
Host smart-4c17fca7-079b-458f-9629-35fd307778d3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472890031 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_aliasing.472890031
Directory /workspace/0.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.1329406351
Short name T558
Test name
Test status
Simulation time 362846369 ps
CPU time 5.98 seconds
Started Jul 02 09:39:22 AM PDT 24
Finished Jul 02 09:39:29 AM PDT 24
Peak memory 199528 kb
Host smart-87c2818f-2594-4f0c-97e7-835a83155fee
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329406351 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_bit_bash.1329406351
Directory /workspace/0.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.2309186178
Short name T594
Test name
Test status
Simulation time 47676999 ps
CPU time 0.84 seconds
Started Jul 02 09:39:19 AM PDT 24
Finished Jul 02 09:39:20 AM PDT 24
Peak memory 199232 kb
Host smart-369fcc6f-b8b1-4a35-a7e1-4e8762345c8f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309186178 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_hw_reset.2309186178
Directory /workspace/0.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.1077921969
Short name T74
Test name
Test status
Simulation time 201456376514 ps
CPU time 826.49 seconds
Started Jul 02 09:39:22 AM PDT 24
Finished Jul 02 09:53:10 AM PDT 24
Peak memory 216012 kb
Host smart-de4b1f8d-4765-4ae6-84a1-701eb636a1d7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077921969 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.hmac_csr_mem_rw_with_rand_reset.1077921969
Directory /workspace/0.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_rw.3965529979
Short name T642
Test name
Test status
Simulation time 48389396 ps
CPU time 0.8 seconds
Started Jul 02 09:39:23 AM PDT 24
Finished Jul 02 09:39:24 AM PDT 24
Peak memory 199468 kb
Host smart-9ca2ae7f-d3ef-4082-ab4f-367b99bf77ca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965529979 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_rw.3965529979
Directory /workspace/0.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_intr_test.1488336548
Short name T617
Test name
Test status
Simulation time 45868471 ps
CPU time 0.58 seconds
Started Jul 02 09:39:21 AM PDT 24
Finished Jul 02 09:39:22 AM PDT 24
Peak memory 194624 kb
Host smart-1898509c-996a-410e-9145-4cfa48b30a13
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488336548 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_intr_test.1488336548
Directory /workspace/0.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.287098349
Short name T114
Test name
Test status
Simulation time 140332335 ps
CPU time 2.3 seconds
Started Jul 02 09:39:23 AM PDT 24
Finished Jul 02 09:39:26 AM PDT 24
Peak memory 199424 kb
Host smart-e149654b-44c8-41d0-8ef0-089a17f4ec98
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287098349 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_same_csr_
outstanding.287098349
Directory /workspace/0.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_errors.559612514
Short name T610
Test name
Test status
Simulation time 187879116 ps
CPU time 3.56 seconds
Started Jul 02 09:39:21 AM PDT 24
Finished Jul 02 09:39:25 AM PDT 24
Peak memory 199532 kb
Host smart-9bfb6245-5240-414b-9f84-e41d074c6470
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559612514 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_errors.559612514
Directory /workspace/0.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.2858627695
Short name T616
Test name
Test status
Simulation time 1309905850 ps
CPU time 3.77 seconds
Started Jul 02 09:39:17 AM PDT 24
Finished Jul 02 09:39:21 AM PDT 24
Peak memory 199600 kb
Host smart-533f61c4-6cfd-42c5-905c-a0bf427e32ec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858627695 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_intg_err.2858627695
Directory /workspace/0.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.546935793
Short name T556
Test name
Test status
Simulation time 774582113 ps
CPU time 3.48 seconds
Started Jul 02 09:39:20 AM PDT 24
Finished Jul 02 09:39:24 AM PDT 24
Peak memory 199524 kb
Host smart-3c82d4f2-b690-4cec-9a05-ba11e0271175
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546935793 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_aliasing.546935793
Directory /workspace/1.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.2412380857
Short name T590
Test name
Test status
Simulation time 1147483019 ps
CPU time 16.08 seconds
Started Jul 02 09:39:23 AM PDT 24
Finished Jul 02 09:39:40 AM PDT 24
Peak memory 198656 kb
Host smart-383b0314-9cff-42a2-8a3d-5118924d9f7b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412380857 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_bit_bash.2412380857
Directory /workspace/1.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.184197713
Short name T545
Test name
Test status
Simulation time 18782458 ps
CPU time 0.87 seconds
Started Jul 02 09:39:21 AM PDT 24
Finished Jul 02 09:39:22 AM PDT 24
Peak memory 198664 kb
Host smart-15b18402-14c1-4b9b-8176-d54cf054661a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184197713 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_hw_reset.184197713
Directory /workspace/1.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.3990009694
Short name T557
Test name
Test status
Simulation time 6122034093 ps
CPU time 90.46 seconds
Started Jul 02 09:39:24 AM PDT 24
Finished Jul 02 09:40:55 AM PDT 24
Peak memory 207844 kb
Host smart-5c1de0fc-b548-4242-8384-a048f5ce8dd2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990009694 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.hmac_csr_mem_rw_with_rand_reset.3990009694
Directory /workspace/1.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_rw.3149621781
Short name T105
Test name
Test status
Simulation time 172303566 ps
CPU time 0.99 seconds
Started Jul 02 09:39:22 AM PDT 24
Finished Jul 02 09:39:24 AM PDT 24
Peak memory 199332 kb
Host smart-69362c0b-9796-4bd1-b9ba-13b8f866567b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149621781 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_rw.3149621781
Directory /workspace/1.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_intr_test.129321905
Short name T614
Test name
Test status
Simulation time 11409421 ps
CPU time 0.62 seconds
Started Jul 02 09:39:22 AM PDT 24
Finished Jul 02 09:39:24 AM PDT 24
Peak memory 194624 kb
Host smart-07a18f4e-f996-49b8-a42f-dc7569102a65
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129321905 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_intr_test.129321905
Directory /workspace/1.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.2653662842
Short name T596
Test name
Test status
Simulation time 168272310 ps
CPU time 1.89 seconds
Started Jul 02 09:39:19 AM PDT 24
Finished Jul 02 09:39:22 AM PDT 24
Peak memory 199508 kb
Host smart-a32bab9e-4c59-4dd6-bde4-1a7b069cdbd0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653662842 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_same_csr
_outstanding.2653662842
Directory /workspace/1.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_errors.3480393894
Short name T636
Test name
Test status
Simulation time 2422277049 ps
CPU time 4.36 seconds
Started Jul 02 09:39:21 AM PDT 24
Finished Jul 02 09:39:26 AM PDT 24
Peak memory 199628 kb
Host smart-e1589c12-b316-4658-848e-ba2ead6432e8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480393894 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_errors.3480393894
Directory /workspace/1.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.2980926313
Short name T634
Test name
Test status
Simulation time 189164883 ps
CPU time 1.96 seconds
Started Jul 02 09:39:22 AM PDT 24
Finished Jul 02 09:39:25 AM PDT 24
Peak memory 199404 kb
Host smart-9cfd01d2-60ad-451b-98b4-a71cfadac15e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980926313 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_intg_err.2980926313
Directory /workspace/1.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.1228003808
Short name T601
Test name
Test status
Simulation time 75121177 ps
CPU time 2.17 seconds
Started Jul 02 09:39:38 AM PDT 24
Finished Jul 02 09:39:42 AM PDT 24
Peak memory 199668 kb
Host smart-bce62dc8-10e0-455e-a261-2c3e29d3f02d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228003808 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.hmac_csr_mem_rw_with_rand_reset.1228003808
Directory /workspace/10.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_rw.910126646
Short name T120
Test name
Test status
Simulation time 13660132 ps
CPU time 0.73 seconds
Started Jul 02 09:39:37 AM PDT 24
Finished Jul 02 09:39:39 AM PDT 24
Peak memory 197576 kb
Host smart-d30ed6d7-7577-4157-a0ec-6274c5480226
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910126646 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_rw.910126646
Directory /workspace/10.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_intr_test.4091410557
Short name T566
Test name
Test status
Simulation time 29527194 ps
CPU time 0.59 seconds
Started Jul 02 09:39:37 AM PDT 24
Finished Jul 02 09:39:38 AM PDT 24
Peak memory 194472 kb
Host smart-04047780-9c3a-465e-93dd-19eb3e4e1a8b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091410557 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_intr_test.4091410557
Directory /workspace/10.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.910835887
Short name T582
Test name
Test status
Simulation time 172234413 ps
CPU time 1.63 seconds
Started Jul 02 09:39:37 AM PDT 24
Finished Jul 02 09:39:39 AM PDT 24
Peak memory 199592 kb
Host smart-1c371f79-6101-4445-87e3-379801851af0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910835887 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_same_csr
_outstanding.910835887
Directory /workspace/10.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_errors.1548446260
Short name T658
Test name
Test status
Simulation time 48896804 ps
CPU time 1.27 seconds
Started Jul 02 09:39:39 AM PDT 24
Finished Jul 02 09:39:42 AM PDT 24
Peak memory 199484 kb
Host smart-19cc75fc-0993-4e4d-a1f0-81e77b0c18d1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548446260 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_errors.1548446260
Directory /workspace/10.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.1850510827
Short name T570
Test name
Test status
Simulation time 186921828 ps
CPU time 1.67 seconds
Started Jul 02 09:39:38 AM PDT 24
Finished Jul 02 09:39:41 AM PDT 24
Peak memory 199588 kb
Host smart-639f22ae-cc3e-4e07-ba7f-b16615a852b1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850510827 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_intg_err.1850510827
Directory /workspace/10.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.1318092278
Short name T657
Test name
Test status
Simulation time 75566807 ps
CPU time 1.71 seconds
Started Jul 02 09:39:37 AM PDT 24
Finished Jul 02 09:39:40 AM PDT 24
Peak memory 199760 kb
Host smart-7975fce5-7beb-4bd6-a5d0-d5a86b9cbd6e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318092278 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.hmac_csr_mem_rw_with_rand_reset.1318092278
Directory /workspace/11.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_rw.1902023800
Short name T602
Test name
Test status
Simulation time 248781844 ps
CPU time 0.94 seconds
Started Jul 02 09:39:36 AM PDT 24
Finished Jul 02 09:39:39 AM PDT 24
Peak memory 199268 kb
Host smart-e76e437d-83c6-4d65-a876-13dacfecc534
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902023800 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_rw.1902023800
Directory /workspace/11.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_intr_test.2304869323
Short name T539
Test name
Test status
Simulation time 11767623 ps
CPU time 0.56 seconds
Started Jul 02 09:39:35 AM PDT 24
Finished Jul 02 09:39:36 AM PDT 24
Peak memory 194424 kb
Host smart-aa75c37b-86dd-4c88-af4d-b5ae6cbc8d7d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304869323 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_intr_test.2304869323
Directory /workspace/11.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.2679998302
Short name T581
Test name
Test status
Simulation time 89454558 ps
CPU time 2.11 seconds
Started Jul 02 09:39:36 AM PDT 24
Finished Jul 02 09:39:40 AM PDT 24
Peak memory 199620 kb
Host smart-cec5d1e5-59b7-4206-82ce-5d9919f845b9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679998302 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_same_cs
r_outstanding.2679998302
Directory /workspace/11.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_errors.3097158668
Short name T580
Test name
Test status
Simulation time 35155538 ps
CPU time 1.74 seconds
Started Jul 02 09:39:36 AM PDT 24
Finished Jul 02 09:39:39 AM PDT 24
Peak memory 199520 kb
Host smart-5fc39443-c578-4a33-bcaf-af3f0026afa3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097158668 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_errors.3097158668
Directory /workspace/11.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.175791288
Short name T587
Test name
Test status
Simulation time 456289806 ps
CPU time 2.36 seconds
Started Jul 02 09:39:42 AM PDT 24
Finished Jul 02 09:39:45 AM PDT 24
Peak memory 199812 kb
Host smart-c7ef36b4-84b6-46c4-ac8e-886dafd61e33
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175791288 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.hmac_csr_mem_rw_with_rand_reset.175791288
Directory /workspace/12.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_rw.3457640733
Short name T565
Test name
Test status
Simulation time 24880908 ps
CPU time 0.79 seconds
Started Jul 02 09:39:38 AM PDT 24
Finished Jul 02 09:39:40 AM PDT 24
Peak memory 198844 kb
Host smart-e510e5d2-3fbb-4c22-836e-d9060ada5262
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457640733 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_rw.3457640733
Directory /workspace/12.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_intr_test.426858874
Short name T655
Test name
Test status
Simulation time 176158916 ps
CPU time 0.61 seconds
Started Jul 02 09:39:38 AM PDT 24
Finished Jul 02 09:39:40 AM PDT 24
Peak memory 194520 kb
Host smart-176b3b33-60b0-46fb-a845-319a87173187
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426858874 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_intr_test.426858874
Directory /workspace/12.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.832039988
Short name T640
Test name
Test status
Simulation time 203934105 ps
CPU time 1.19 seconds
Started Jul 02 09:39:48 AM PDT 24
Finished Jul 02 09:39:50 AM PDT 24
Peak memory 199000 kb
Host smart-eee553e6-a250-4bc6-ab6c-285e80579ea6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832039988 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_same_csr
_outstanding.832039988
Directory /workspace/12.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_errors.2221372019
Short name T586
Test name
Test status
Simulation time 199336421 ps
CPU time 2.53 seconds
Started Jul 02 09:39:39 AM PDT 24
Finished Jul 02 09:39:43 AM PDT 24
Peak memory 199520 kb
Host smart-c21a27ec-c0dd-4d0a-9c2f-145c0c88c85f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221372019 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_errors.2221372019
Directory /workspace/12.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.931799411
Short name T133
Test name
Test status
Simulation time 404191939 ps
CPU time 3.92 seconds
Started Jul 02 09:39:48 AM PDT 24
Finished Jul 02 09:39:53 AM PDT 24
Peak memory 199532 kb
Host smart-941d5f8a-1691-4fea-be6c-aad5c1be314a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931799411 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_intg_err.931799411
Directory /workspace/12.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.3885506184
Short name T623
Test name
Test status
Simulation time 50517962921 ps
CPU time 399.03 seconds
Started Jul 02 09:39:45 AM PDT 24
Finished Jul 02 09:46:25 AM PDT 24
Peak memory 216044 kb
Host smart-942130ce-0702-42bb-bf89-18cddff27412
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885506184 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.hmac_csr_mem_rw_with_rand_reset.3885506184
Directory /workspace/13.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_intr_test.3361252898
Short name T552
Test name
Test status
Simulation time 177207347 ps
CPU time 0.61 seconds
Started Jul 02 09:39:42 AM PDT 24
Finished Jul 02 09:39:43 AM PDT 24
Peak memory 194512 kb
Host smart-1a6810cf-a15d-4a3f-91d3-0a6215ca3231
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361252898 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_intr_test.3361252898
Directory /workspace/13.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.1214134548
Short name T576
Test name
Test status
Simulation time 688849701 ps
CPU time 1.14 seconds
Started Jul 02 09:39:46 AM PDT 24
Finished Jul 02 09:39:49 AM PDT 24
Peak memory 199416 kb
Host smart-744bd470-7ba5-4a43-bc85-8dec262cf66e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214134548 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_same_cs
r_outstanding.1214134548
Directory /workspace/13.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_errors.3462970587
Short name T608
Test name
Test status
Simulation time 510957628 ps
CPU time 2.94 seconds
Started Jul 02 09:39:41 AM PDT 24
Finished Jul 02 09:39:45 AM PDT 24
Peak memory 199580 kb
Host smart-0a469b50-074d-4fe0-af2f-da54efc5d68e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462970587 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_errors.3462970587
Directory /workspace/13.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.4121734139
Short name T137
Test name
Test status
Simulation time 185027921 ps
CPU time 1.84 seconds
Started Jul 02 09:39:41 AM PDT 24
Finished Jul 02 09:39:43 AM PDT 24
Peak memory 199536 kb
Host smart-292ab7f8-8a98-4158-805b-e234ad1484c0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121734139 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_intg_err.4121734139
Directory /workspace/13.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.2196010770
Short name T605
Test name
Test status
Simulation time 327565693 ps
CPU time 1.26 seconds
Started Jul 02 09:39:42 AM PDT 24
Finished Jul 02 09:39:44 AM PDT 24
Peak memory 199572 kb
Host smart-e85d00c3-5cc2-4cc0-9236-d642c086eb87
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196010770 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.hmac_csr_mem_rw_with_rand_reset.2196010770
Directory /workspace/14.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_rw.4094873954
Short name T118
Test name
Test status
Simulation time 64296668 ps
CPU time 0.72 seconds
Started Jul 02 09:39:43 AM PDT 24
Finished Jul 02 09:39:44 AM PDT 24
Peak memory 197884 kb
Host smart-c8627a96-d9ba-4c8f-bcf4-19dc2dd76909
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094873954 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_rw.4094873954
Directory /workspace/14.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_intr_test.3112903102
Short name T595
Test name
Test status
Simulation time 50594244 ps
CPU time 0.61 seconds
Started Jul 02 09:39:43 AM PDT 24
Finished Jul 02 09:39:44 AM PDT 24
Peak memory 194592 kb
Host smart-b475b864-1e12-4475-8e62-41658f5db8bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112903102 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_intr_test.3112903102
Directory /workspace/14.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.523175459
Short name T644
Test name
Test status
Simulation time 86556260 ps
CPU time 1.16 seconds
Started Jul 02 09:39:43 AM PDT 24
Finished Jul 02 09:39:45 AM PDT 24
Peak memory 199508 kb
Host smart-624a8ee4-9047-43c0-b46f-8d8b70646193
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523175459 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_same_csr
_outstanding.523175459
Directory /workspace/14.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_errors.1558591326
Short name T578
Test name
Test status
Simulation time 456535656 ps
CPU time 2.21 seconds
Started Jul 02 09:39:42 AM PDT 24
Finished Jul 02 09:39:45 AM PDT 24
Peak memory 199516 kb
Host smart-09969eed-3126-45ce-b06f-9052a7fc754c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558591326 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_errors.1558591326
Directory /workspace/14.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.2019951601
Short name T533
Test name
Test status
Simulation time 48349219 ps
CPU time 1.53 seconds
Started Jul 02 09:39:46 AM PDT 24
Finished Jul 02 09:39:49 AM PDT 24
Peak memory 199504 kb
Host smart-3d2b2775-7e0a-4c62-9f31-c06c9765e6b7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019951601 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.hmac_csr_mem_rw_with_rand_reset.2019951601
Directory /workspace/15.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_rw.3950127624
Short name T104
Test name
Test status
Simulation time 25396444 ps
CPU time 0.8 seconds
Started Jul 02 09:39:46 AM PDT 24
Finished Jul 02 09:39:47 AM PDT 24
Peak memory 199208 kb
Host smart-b1e0c47a-139d-4dcb-9ff8-babe5733b9eb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950127624 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_rw.3950127624
Directory /workspace/15.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_intr_test.2007140030
Short name T542
Test name
Test status
Simulation time 31154256 ps
CPU time 0.61 seconds
Started Jul 02 09:39:44 AM PDT 24
Finished Jul 02 09:39:46 AM PDT 24
Peak memory 194680 kb
Host smart-a9aae20c-0a79-4408-8c73-f78bfbf827ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007140030 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_intr_test.2007140030
Directory /workspace/15.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.3703308408
Short name T119
Test name
Test status
Simulation time 118298600 ps
CPU time 2.15 seconds
Started Jul 02 09:39:45 AM PDT 24
Finished Jul 02 09:39:48 AM PDT 24
Peak memory 199536 kb
Host smart-bd4e700a-637e-4563-a727-9a3a2c8e4fe1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703308408 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_same_cs
r_outstanding.3703308408
Directory /workspace/15.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_errors.3776202426
Short name T572
Test name
Test status
Simulation time 89660217 ps
CPU time 4.6 seconds
Started Jul 02 09:39:46 AM PDT 24
Finished Jul 02 09:39:51 AM PDT 24
Peak memory 199520 kb
Host smart-373ef365-1fe2-474f-bae6-731a08430e42
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776202426 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_errors.3776202426
Directory /workspace/15.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.3034203186
Short name T70
Test name
Test status
Simulation time 157309863 ps
CPU time 1.87 seconds
Started Jul 02 09:39:48 AM PDT 24
Finished Jul 02 09:39:51 AM PDT 24
Peak memory 199508 kb
Host smart-c9244ea5-6a91-468e-ada9-6bcb16227417
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034203186 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_intg_err.3034203186
Directory /workspace/15.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.3082877172
Short name T613
Test name
Test status
Simulation time 732268237 ps
CPU time 2.39 seconds
Started Jul 02 09:39:46 AM PDT 24
Finished Jul 02 09:39:50 AM PDT 24
Peak memory 199628 kb
Host smart-fe1a84ed-b4e2-45f9-bb81-8d13204b1b00
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082877172 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.hmac_csr_mem_rw_with_rand_reset.3082877172
Directory /workspace/16.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_rw.1853913688
Short name T600
Test name
Test status
Simulation time 58147883 ps
CPU time 0.78 seconds
Started Jul 02 09:39:46 AM PDT 24
Finished Jul 02 09:39:48 AM PDT 24
Peak memory 199432 kb
Host smart-600e18a1-fea5-4ff8-8718-8eecc51a5338
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853913688 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_rw.1853913688
Directory /workspace/16.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_intr_test.1202567828
Short name T641
Test name
Test status
Simulation time 14157430 ps
CPU time 0.61 seconds
Started Jul 02 09:39:45 AM PDT 24
Finished Jul 02 09:39:46 AM PDT 24
Peak memory 194536 kb
Host smart-5fba3ee6-a7f8-4314-a044-75c7e495f111
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202567828 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_intr_test.1202567828
Directory /workspace/16.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.2718819927
Short name T656
Test name
Test status
Simulation time 65081640 ps
CPU time 1.68 seconds
Started Jul 02 09:39:47 AM PDT 24
Finished Jul 02 09:39:49 AM PDT 24
Peak memory 199552 kb
Host smart-76c20907-1870-4c4f-87d4-1b2de0cb5d01
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718819927 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_same_cs
r_outstanding.2718819927
Directory /workspace/16.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_errors.964219841
Short name T597
Test name
Test status
Simulation time 836436692 ps
CPU time 4.1 seconds
Started Jul 02 09:39:46 AM PDT 24
Finished Jul 02 09:39:50 AM PDT 24
Peak memory 199600 kb
Host smart-3801d28f-2ce5-46cb-bf75-3ccecc90d7a5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964219841 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_errors.964219841
Directory /workspace/16.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.2620965759
Short name T618
Test name
Test status
Simulation time 133388593 ps
CPU time 1.79 seconds
Started Jul 02 09:39:47 AM PDT 24
Finished Jul 02 09:39:50 AM PDT 24
Peak memory 199540 kb
Host smart-3059c775-a9c8-4875-84b4-940705723876
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620965759 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_intg_err.2620965759
Directory /workspace/16.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.2608641129
Short name T559
Test name
Test status
Simulation time 109812632 ps
CPU time 2.33 seconds
Started Jul 02 09:39:46 AM PDT 24
Finished Jul 02 09:39:49 AM PDT 24
Peak memory 199572 kb
Host smart-057ca060-601b-4813-bca2-56c9b94c7bb5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608641129 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.hmac_csr_mem_rw_with_rand_reset.2608641129
Directory /workspace/17.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_rw.1504749676
Short name T102
Test name
Test status
Simulation time 15084783 ps
CPU time 0.69 seconds
Started Jul 02 09:39:47 AM PDT 24
Finished Jul 02 09:39:49 AM PDT 24
Peak memory 197336 kb
Host smart-78286d9c-9920-4e9a-a5b9-25d05138022c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504749676 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_rw.1504749676
Directory /workspace/17.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_intr_test.616013544
Short name T536
Test name
Test status
Simulation time 30837122 ps
CPU time 0.6 seconds
Started Jul 02 09:39:48 AM PDT 24
Finished Jul 02 09:39:50 AM PDT 24
Peak memory 194496 kb
Host smart-d5d770b1-5e0f-4de1-b3dc-b314eeb8911d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616013544 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_intr_test.616013544
Directory /workspace/17.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.775401724
Short name T630
Test name
Test status
Simulation time 43054116 ps
CPU time 1.17 seconds
Started Jul 02 09:39:46 AM PDT 24
Finished Jul 02 09:39:48 AM PDT 24
Peak memory 198020 kb
Host smart-38ca46d4-5ee5-4f18-9275-15cb16d70f0b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775401724 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_same_csr
_outstanding.775401724
Directory /workspace/17.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_errors.572362114
Short name T544
Test name
Test status
Simulation time 189428840 ps
CPU time 3.9 seconds
Started Jul 02 09:39:45 AM PDT 24
Finished Jul 02 09:39:50 AM PDT 24
Peak memory 199532 kb
Host smart-1e111810-9a88-4030-a337-18423a34aece
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572362114 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_errors.572362114
Directory /workspace/17.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.2397823187
Short name T584
Test name
Test status
Simulation time 96082991 ps
CPU time 1.71 seconds
Started Jul 02 09:39:47 AM PDT 24
Finished Jul 02 09:39:50 AM PDT 24
Peak memory 199524 kb
Host smart-5b9a8395-545d-4e01-b60e-7c1623235722
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397823187 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_intg_err.2397823187
Directory /workspace/17.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.3715742025
Short name T573
Test name
Test status
Simulation time 516193260 ps
CPU time 2.59 seconds
Started Jul 02 09:39:51 AM PDT 24
Finished Jul 02 09:39:55 AM PDT 24
Peak memory 199624 kb
Host smart-efe36dbd-b552-4d54-ab64-e7effbd6abee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715742025 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.hmac_csr_mem_rw_with_rand_reset.3715742025
Directory /workspace/18.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_rw.635851644
Short name T615
Test name
Test status
Simulation time 19758806 ps
CPU time 0.71 seconds
Started Jul 02 09:39:53 AM PDT 24
Finished Jul 02 09:39:56 AM PDT 24
Peak memory 197800 kb
Host smart-83ace246-f000-4bce-8558-1461278467f0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635851644 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_rw.635851644
Directory /workspace/18.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_intr_test.2158172482
Short name T622
Test name
Test status
Simulation time 81072134 ps
CPU time 0.59 seconds
Started Jul 02 09:39:46 AM PDT 24
Finished Jul 02 09:39:47 AM PDT 24
Peak memory 194476 kb
Host smart-88174876-551c-4430-bf6a-5ee9892228ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158172482 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_intr_test.2158172482
Directory /workspace/18.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.2471089909
Short name T637
Test name
Test status
Simulation time 594500723 ps
CPU time 2.33 seconds
Started Jul 02 09:39:50 AM PDT 24
Finished Jul 02 09:39:53 AM PDT 24
Peak memory 199520 kb
Host smart-9a0a7641-152c-43af-969b-8b57ade7f6f8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471089909 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_same_cs
r_outstanding.2471089909
Directory /workspace/18.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_errors.4249261383
Short name T568
Test name
Test status
Simulation time 155640913 ps
CPU time 3.41 seconds
Started Jul 02 09:39:48 AM PDT 24
Finished Jul 02 09:39:53 AM PDT 24
Peak memory 199516 kb
Host smart-2ba4dee5-d229-48c2-b9be-e8dba8ee58b4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249261383 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_errors.4249261383
Directory /workspace/18.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.1403509072
Short name T612
Test name
Test status
Simulation time 921587566 ps
CPU time 1.94 seconds
Started Jul 02 09:39:49 AM PDT 24
Finished Jul 02 09:39:51 AM PDT 24
Peak memory 199604 kb
Host smart-9f4ba1c0-074e-4862-975e-7b43344e043b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403509072 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_intg_err.1403509072
Directory /workspace/18.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.1264649547
Short name T643
Test name
Test status
Simulation time 37040598 ps
CPU time 2.32 seconds
Started Jul 02 09:39:55 AM PDT 24
Finished Jul 02 09:39:59 AM PDT 24
Peak memory 199540 kb
Host smart-9869ba72-0fa2-43e1-b5f7-6f6d6115c8db
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264649547 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.hmac_csr_mem_rw_with_rand_reset.1264649547
Directory /workspace/19.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_rw.756536628
Short name T107
Test name
Test status
Simulation time 12334694 ps
CPU time 0.66 seconds
Started Jul 02 09:39:50 AM PDT 24
Finished Jul 02 09:39:52 AM PDT 24
Peak memory 197756 kb
Host smart-6a2b321f-64f4-4151-bb79-e012e9d0cc93
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756536628 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_rw.756536628
Directory /workspace/19.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_intr_test.2579724103
Short name T635
Test name
Test status
Simulation time 29938296 ps
CPU time 0.59 seconds
Started Jul 02 09:39:53 AM PDT 24
Finished Jul 02 09:39:55 AM PDT 24
Peak memory 194560 kb
Host smart-eb12b8aa-6be0-452e-9cce-fbcdcb66c7ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579724103 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_intr_test.2579724103
Directory /workspace/19.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.69235983
Short name T625
Test name
Test status
Simulation time 25262610 ps
CPU time 1.09 seconds
Started Jul 02 09:39:52 AM PDT 24
Finished Jul 02 09:39:55 AM PDT 24
Peak memory 198144 kb
Host smart-4ae22680-728f-4559-9dd5-cc7bfcba60c4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69235983 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_same_csr_
outstanding.69235983
Directory /workspace/19.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_errors.1474043280
Short name T621
Test name
Test status
Simulation time 204053891 ps
CPU time 1.61 seconds
Started Jul 02 09:39:53 AM PDT 24
Finished Jul 02 09:39:56 AM PDT 24
Peak memory 199528 kb
Host smart-541d35b0-0692-4f40-b9c6-1fca6c52d5a0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474043280 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_errors.1474043280
Directory /workspace/19.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.506182958
Short name T134
Test name
Test status
Simulation time 367300555 ps
CPU time 2.84 seconds
Started Jul 02 09:39:52 AM PDT 24
Finished Jul 02 09:39:57 AM PDT 24
Peak memory 199536 kb
Host smart-414c5f1c-8cab-4687-a284-a23e6a190291
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506182958 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_intg_err.506182958
Directory /workspace/19.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.4005695133
Short name T589
Test name
Test status
Simulation time 451009149 ps
CPU time 9.35 seconds
Started Jul 02 09:39:25 AM PDT 24
Finished Jul 02 09:39:35 AM PDT 24
Peak memory 199216 kb
Host smart-b748b083-0a5f-42e5-aecf-f5487c938124
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005695133 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_aliasing.4005695133
Directory /workspace/2.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.748944889
Short name T530
Test name
Test status
Simulation time 1958120647 ps
CPU time 5.95 seconds
Started Jul 02 09:39:24 AM PDT 24
Finished Jul 02 09:39:31 AM PDT 24
Peak memory 199536 kb
Host smart-322cdc9e-2af7-41f9-b869-99c56341f51f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748944889 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_bit_bash.748944889
Directory /workspace/2.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.897633544
Short name T103
Test name
Test status
Simulation time 70179035 ps
CPU time 0.82 seconds
Started Jul 02 09:39:34 AM PDT 24
Finished Jul 02 09:39:36 AM PDT 24
Peak memory 199048 kb
Host smart-833f8954-318a-4294-94aa-771df49833cf
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897633544 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_hw_reset.897633544
Directory /workspace/2.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.305183730
Short name T535
Test name
Test status
Simulation time 140411164 ps
CPU time 1.86 seconds
Started Jul 02 09:39:24 AM PDT 24
Finished Jul 02 09:39:26 AM PDT 24
Peak memory 199672 kb
Host smart-68a4dad7-45b9-4edb-b52d-af92e8f589e6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305183730 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.hmac_csr_mem_rw_with_rand_reset.305183730
Directory /workspace/2.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_rw.903050867
Short name T106
Test name
Test status
Simulation time 88846291 ps
CPU time 0.71 seconds
Started Jul 02 09:39:26 AM PDT 24
Finished Jul 02 09:39:27 AM PDT 24
Peak memory 197628 kb
Host smart-dee9e987-a4aa-4e8e-9402-7272be7a25f6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903050867 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_rw.903050867
Directory /workspace/2.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_intr_test.131852292
Short name T653
Test name
Test status
Simulation time 24376228 ps
CPU time 0.6 seconds
Started Jul 02 09:39:26 AM PDT 24
Finished Jul 02 09:39:27 AM PDT 24
Peak memory 194528 kb
Host smart-ff5cfe57-596d-4986-b6c0-29b4698c956d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131852292 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_intr_test.131852292
Directory /workspace/2.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.2367191494
Short name T588
Test name
Test status
Simulation time 371166046 ps
CPU time 2.29 seconds
Started Jul 02 09:39:23 AM PDT 24
Finished Jul 02 09:39:26 AM PDT 24
Peak memory 199520 kb
Host smart-c6fd2812-f05e-4011-824b-37bb1db4dd93
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367191494 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_same_csr
_outstanding.2367191494
Directory /workspace/2.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_errors.285881245
Short name T629
Test name
Test status
Simulation time 183245801 ps
CPU time 3.85 seconds
Started Jul 02 09:39:32 AM PDT 24
Finished Jul 02 09:39:37 AM PDT 24
Peak memory 199420 kb
Host smart-4fb865f8-21ed-4537-8601-bade507bbef0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285881245 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_errors.285881245
Directory /workspace/2.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.3684315325
Short name T132
Test name
Test status
Simulation time 328421766 ps
CPU time 3.24 seconds
Started Jul 02 09:39:24 AM PDT 24
Finished Jul 02 09:39:28 AM PDT 24
Peak memory 199544 kb
Host smart-4cefe156-fb0b-4dfa-97c6-0414941deaa5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684315325 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_intg_err.3684315325
Directory /workspace/2.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.hmac_intr_test.231704252
Short name T528
Test name
Test status
Simulation time 31013830 ps
CPU time 0.64 seconds
Started Jul 02 09:39:54 AM PDT 24
Finished Jul 02 09:39:57 AM PDT 24
Peak memory 194508 kb
Host smart-392b2fbc-0fc1-47d1-889a-8f2d211d456b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231704252 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.hmac_intr_test.231704252
Directory /workspace/20.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.hmac_intr_test.1711011024
Short name T575
Test name
Test status
Simulation time 20323098 ps
CPU time 0.64 seconds
Started Jul 02 09:39:54 AM PDT 24
Finished Jul 02 09:39:57 AM PDT 24
Peak memory 194560 kb
Host smart-83ab6548-2ffd-4347-b6ce-c935578058b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711011024 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.hmac_intr_test.1711011024
Directory /workspace/21.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.hmac_intr_test.250852101
Short name T646
Test name
Test status
Simulation time 34104545 ps
CPU time 0.59 seconds
Started Jul 02 09:39:51 AM PDT 24
Finished Jul 02 09:39:53 AM PDT 24
Peak memory 194444 kb
Host smart-581a0193-2972-4393-88ae-e1eda7682aee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250852101 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.hmac_intr_test.250852101
Directory /workspace/22.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.hmac_intr_test.2271369746
Short name T577
Test name
Test status
Simulation time 31287785 ps
CPU time 0.61 seconds
Started Jul 02 09:39:52 AM PDT 24
Finished Jul 02 09:39:54 AM PDT 24
Peak memory 194488 kb
Host smart-99d8563a-1739-4a7c-a5e2-35176ff4e551
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271369746 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.hmac_intr_test.2271369746
Directory /workspace/23.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.hmac_intr_test.1572551756
Short name T538
Test name
Test status
Simulation time 61333031 ps
CPU time 0.61 seconds
Started Jul 02 09:39:53 AM PDT 24
Finished Jul 02 09:39:55 AM PDT 24
Peak memory 194612 kb
Host smart-06d8368d-e508-405d-9f69-9af8b6546b13
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572551756 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.hmac_intr_test.1572551756
Directory /workspace/24.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.hmac_intr_test.2698189399
Short name T567
Test name
Test status
Simulation time 20144461 ps
CPU time 0.58 seconds
Started Jul 02 09:39:52 AM PDT 24
Finished Jul 02 09:39:54 AM PDT 24
Peak memory 194448 kb
Host smart-347ec837-aead-4568-bff6-58385e14203c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698189399 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.hmac_intr_test.2698189399
Directory /workspace/25.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.hmac_intr_test.1111648389
Short name T534
Test name
Test status
Simulation time 123091930 ps
CPU time 0.63 seconds
Started Jul 02 09:39:52 AM PDT 24
Finished Jul 02 09:39:54 AM PDT 24
Peak memory 194480 kb
Host smart-98ff8ca1-bd3f-4a3c-980c-14e8c971a03f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111648389 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.hmac_intr_test.1111648389
Directory /workspace/26.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.hmac_intr_test.3025626670
Short name T632
Test name
Test status
Simulation time 30485219 ps
CPU time 0.61 seconds
Started Jul 02 09:39:52 AM PDT 24
Finished Jul 02 09:39:54 AM PDT 24
Peak memory 194576 kb
Host smart-379cbc1f-74fa-4db3-82b1-f80c0efce684
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025626670 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.hmac_intr_test.3025626670
Directory /workspace/27.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.hmac_intr_test.3053012397
Short name T547
Test name
Test status
Simulation time 19016717 ps
CPU time 0.63 seconds
Started Jul 02 09:39:53 AM PDT 24
Finished Jul 02 09:39:56 AM PDT 24
Peak memory 194648 kb
Host smart-1ab3315b-8cdb-488b-b000-26907b7d2a8d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053012397 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.hmac_intr_test.3053012397
Directory /workspace/28.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.hmac_intr_test.645914665
Short name T607
Test name
Test status
Simulation time 18124302 ps
CPU time 0.54 seconds
Started Jul 02 09:39:51 AM PDT 24
Finished Jul 02 09:39:53 AM PDT 24
Peak memory 194564 kb
Host smart-c60e2dea-20ee-49f3-b685-5b41a2020b66
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645914665 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.hmac_intr_test.645914665
Directory /workspace/29.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.1996500745
Short name T112
Test name
Test status
Simulation time 317431498 ps
CPU time 3.17 seconds
Started Jul 02 09:39:23 AM PDT 24
Finished Jul 02 09:39:27 AM PDT 24
Peak memory 199248 kb
Host smart-cecad878-1376-48fb-be72-fb0fe2cae5f7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996500745 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_aliasing.1996500745
Directory /workspace/3.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.3175884675
Short name T631
Test name
Test status
Simulation time 640319368 ps
CPU time 14.62 seconds
Started Jul 02 09:39:24 AM PDT 24
Finished Jul 02 09:39:39 AM PDT 24
Peak memory 199532 kb
Host smart-7dd073bc-ceaa-4abb-b364-1990a4e82cc3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175884675 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_bit_bash.3175884675
Directory /workspace/3.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.2385399866
Short name T551
Test name
Test status
Simulation time 31045544 ps
CPU time 0.71 seconds
Started Jul 02 09:39:26 AM PDT 24
Finished Jul 02 09:39:28 AM PDT 24
Peak memory 197596 kb
Host smart-72c86e35-fb37-48a6-9a23-6f9e7ff2d858
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385399866 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_hw_reset.2385399866
Directory /workspace/3.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.1766000151
Short name T561
Test name
Test status
Simulation time 71131475 ps
CPU time 1.94 seconds
Started Jul 02 09:39:23 AM PDT 24
Finished Jul 02 09:39:26 AM PDT 24
Peak memory 199608 kb
Host smart-dda411e6-3cc7-4086-9a68-1bbe7b280358
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766000151 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.hmac_csr_mem_rw_with_rand_reset.1766000151
Directory /workspace/3.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_rw.389818336
Short name T574
Test name
Test status
Simulation time 20231794 ps
CPU time 0.68 seconds
Started Jul 02 09:39:24 AM PDT 24
Finished Jul 02 09:39:25 AM PDT 24
Peak memory 197656 kb
Host smart-362e5054-74ea-4af7-a9c9-bb467234a06c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389818336 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_rw.389818336
Directory /workspace/3.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_intr_test.1974190991
Short name T546
Test name
Test status
Simulation time 15609008 ps
CPU time 0.62 seconds
Started Jul 02 09:39:32 AM PDT 24
Finished Jul 02 09:39:33 AM PDT 24
Peak memory 194432 kb
Host smart-6a371340-9ba8-4aaa-8219-846b40b9f1fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974190991 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_intr_test.1974190991
Directory /workspace/3.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.2399700854
Short name T115
Test name
Test status
Simulation time 178879477 ps
CPU time 2.18 seconds
Started Jul 02 09:39:39 AM PDT 24
Finished Jul 02 09:39:42 AM PDT 24
Peak memory 199368 kb
Host smart-3124ae25-9ab5-4c81-bfaa-37f8eb049aa8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399700854 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_same_csr
_outstanding.2399700854
Directory /workspace/3.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_errors.26222647
Short name T652
Test name
Test status
Simulation time 185421641 ps
CPU time 4.32 seconds
Started Jul 02 09:39:25 AM PDT 24
Finished Jul 02 09:39:30 AM PDT 24
Peak memory 199524 kb
Host smart-992be725-8a08-48d2-9951-2270fbc4d00f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26222647 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_errors.26222647
Directory /workspace/3.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.hmac_intr_test.3995731088
Short name T564
Test name
Test status
Simulation time 40608003 ps
CPU time 0.57 seconds
Started Jul 02 09:39:51 AM PDT 24
Finished Jul 02 09:39:52 AM PDT 24
Peak memory 194504 kb
Host smart-107472e2-1193-4cc2-b108-65a5a5363c9a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995731088 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.hmac_intr_test.3995731088
Directory /workspace/30.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.hmac_intr_test.3497732164
Short name T585
Test name
Test status
Simulation time 165430416 ps
CPU time 0.62 seconds
Started Jul 02 09:39:54 AM PDT 24
Finished Jul 02 09:39:57 AM PDT 24
Peak memory 194540 kb
Host smart-fe714203-2004-4c90-9289-2671f79b22e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497732164 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.hmac_intr_test.3497732164
Directory /workspace/31.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.hmac_intr_test.937891144
Short name T611
Test name
Test status
Simulation time 32265745 ps
CPU time 0.56 seconds
Started Jul 02 09:39:51 AM PDT 24
Finished Jul 02 09:39:52 AM PDT 24
Peak memory 194404 kb
Host smart-9839dbfd-cecc-4d92-83a6-f58e9ace0ef7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937891144 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.hmac_intr_test.937891144
Directory /workspace/32.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.hmac_intr_test.4196377968
Short name T549
Test name
Test status
Simulation time 35557821 ps
CPU time 0.56 seconds
Started Jul 02 09:39:52 AM PDT 24
Finished Jul 02 09:39:54 AM PDT 24
Peak memory 194380 kb
Host smart-a5f576d1-bc48-44ba-ae55-669c931b166b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196377968 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.hmac_intr_test.4196377968
Directory /workspace/33.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.hmac_intr_test.2007321736
Short name T593
Test name
Test status
Simulation time 25099130 ps
CPU time 0.63 seconds
Started Jul 02 09:39:53 AM PDT 24
Finished Jul 02 09:39:55 AM PDT 24
Peak memory 194548 kb
Host smart-d51985a2-968e-4697-8053-637ef4e21785
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007321736 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.hmac_intr_test.2007321736
Directory /workspace/34.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.hmac_intr_test.2779210286
Short name T627
Test name
Test status
Simulation time 24485301 ps
CPU time 0.6 seconds
Started Jul 02 09:39:52 AM PDT 24
Finished Jul 02 09:39:54 AM PDT 24
Peak memory 194560 kb
Host smart-9d89bdab-2173-469f-9512-0b2e2f956529
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779210286 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.hmac_intr_test.2779210286
Directory /workspace/35.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.hmac_intr_test.1134521748
Short name T560
Test name
Test status
Simulation time 18048513 ps
CPU time 0.65 seconds
Started Jul 02 09:39:54 AM PDT 24
Finished Jul 02 09:39:57 AM PDT 24
Peak memory 194512 kb
Host smart-3f0f7c1e-f187-4281-8773-482821e79033
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134521748 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.hmac_intr_test.1134521748
Directory /workspace/36.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.hmac_intr_test.1209244936
Short name T651
Test name
Test status
Simulation time 49343264 ps
CPU time 0.61 seconds
Started Jul 02 09:39:51 AM PDT 24
Finished Jul 02 09:39:52 AM PDT 24
Peak memory 194488 kb
Host smart-e6fd5cca-a3f1-4d36-99f2-41405211e3ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209244936 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.hmac_intr_test.1209244936
Directory /workspace/37.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.hmac_intr_test.2191315082
Short name T620
Test name
Test status
Simulation time 34983008 ps
CPU time 0.57 seconds
Started Jul 02 09:39:51 AM PDT 24
Finished Jul 02 09:39:53 AM PDT 24
Peak memory 194460 kb
Host smart-62d3559c-b610-48b9-bfd3-42d85e8cb093
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191315082 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.hmac_intr_test.2191315082
Directory /workspace/38.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.hmac_intr_test.4009003644
Short name T639
Test name
Test status
Simulation time 14624907 ps
CPU time 0.6 seconds
Started Jul 02 09:39:52 AM PDT 24
Finished Jul 02 09:39:54 AM PDT 24
Peak memory 194504 kb
Host smart-79d8ef46-003a-4b2d-a6d2-f0cc460d26c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009003644 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.hmac_intr_test.4009003644
Directory /workspace/39.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.2841151804
Short name T109
Test name
Test status
Simulation time 184849905 ps
CPU time 8.41 seconds
Started Jul 02 09:39:30 AM PDT 24
Finished Jul 02 09:39:39 AM PDT 24
Peak memory 199472 kb
Host smart-4824c6d0-860c-4881-93b4-855d72144b90
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841151804 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_aliasing.2841151804
Directory /workspace/4.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.4291541820
Short name T110
Test name
Test status
Simulation time 2033179107 ps
CPU time 6.06 seconds
Started Jul 02 09:39:28 AM PDT 24
Finished Jul 02 09:39:35 AM PDT 24
Peak memory 199580 kb
Host smart-22c25080-2beb-4704-9cd4-90e54f0e4f07
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291541820 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_bit_bash.4291541820
Directory /workspace/4.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.742247750
Short name T554
Test name
Test status
Simulation time 32785359 ps
CPU time 0.89 seconds
Started Jul 02 09:39:29 AM PDT 24
Finished Jul 02 09:39:30 AM PDT 24
Peak memory 198988 kb
Host smart-7e404565-ed41-4694-ae84-cbd4b28603e0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742247750 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_hw_reset.742247750
Directory /workspace/4.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.4214529749
Short name T591
Test name
Test status
Simulation time 233856695171 ps
CPU time 1103.62 seconds
Started Jul 02 09:39:29 AM PDT 24
Finished Jul 02 09:57:53 AM PDT 24
Peak memory 216192 kb
Host smart-f4018dc5-8116-4c0b-9345-f3363d6495b0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214529749 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.hmac_csr_mem_rw_with_rand_reset.4214529749
Directory /workspace/4.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_rw.4033108235
Short name T624
Test name
Test status
Simulation time 111036524 ps
CPU time 0.97 seconds
Started Jul 02 09:39:30 AM PDT 24
Finished Jul 02 09:39:32 AM PDT 24
Peak memory 199428 kb
Host smart-a664ebe0-e6ca-44d5-bb53-438ead19b6b2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033108235 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_rw.4033108235
Directory /workspace/4.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_intr_test.3100160912
Short name T562
Test name
Test status
Simulation time 47417518 ps
CPU time 0.58 seconds
Started Jul 02 09:39:28 AM PDT 24
Finished Jul 02 09:39:29 AM PDT 24
Peak memory 194536 kb
Host smart-79899804-126d-4e54-b313-07dea5772c76
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100160912 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_intr_test.3100160912
Directory /workspace/4.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.4144472260
Short name T583
Test name
Test status
Simulation time 251774026 ps
CPU time 1.29 seconds
Started Jul 02 09:39:28 AM PDT 24
Finished Jul 02 09:39:30 AM PDT 24
Peak memory 199516 kb
Host smart-0d73ead7-c0d0-4282-b84f-f13cfd660003
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144472260 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_same_csr
_outstanding.4144472260
Directory /workspace/4.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_errors.4267121590
Short name T650
Test name
Test status
Simulation time 601147166 ps
CPU time 3.23 seconds
Started Jul 02 09:39:31 AM PDT 24
Finished Jul 02 09:39:35 AM PDT 24
Peak memory 199512 kb
Host smart-87fcfc6b-fcbc-468e-bdc3-3f4d3cf2a871
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267121590 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_errors.4267121590
Directory /workspace/4.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.4293250640
Short name T68
Test name
Test status
Simulation time 326358729 ps
CPU time 3.98 seconds
Started Jul 02 09:39:28 AM PDT 24
Finished Jul 02 09:39:32 AM PDT 24
Peak memory 199512 kb
Host smart-44af0d4f-3305-4fc1-847c-b9694ee992ec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293250640 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_intg_err.4293250640
Directory /workspace/4.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.hmac_intr_test.1052950410
Short name T626
Test name
Test status
Simulation time 15980780 ps
CPU time 0.6 seconds
Started Jul 02 09:39:55 AM PDT 24
Finished Jul 02 09:39:57 AM PDT 24
Peak memory 194588 kb
Host smart-122df291-4c1b-452c-8973-2b8a68e3b4ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052950410 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.hmac_intr_test.1052950410
Directory /workspace/40.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.hmac_intr_test.1812173026
Short name T603
Test name
Test status
Simulation time 11917968 ps
CPU time 0.6 seconds
Started Jul 02 09:39:56 AM PDT 24
Finished Jul 02 09:39:58 AM PDT 24
Peak memory 194644 kb
Host smart-98e118a7-8e95-46cf-974d-ab5350129975
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812173026 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.hmac_intr_test.1812173026
Directory /workspace/41.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.hmac_intr_test.3798488238
Short name T537
Test name
Test status
Simulation time 26064854 ps
CPU time 0.6 seconds
Started Jul 02 09:39:57 AM PDT 24
Finished Jul 02 09:39:59 AM PDT 24
Peak memory 194536 kb
Host smart-229eec94-178f-4710-a12e-8287724c776b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798488238 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.hmac_intr_test.3798488238
Directory /workspace/42.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.hmac_intr_test.2260995396
Short name T645
Test name
Test status
Simulation time 37649419 ps
CPU time 0.59 seconds
Started Jul 02 09:39:55 AM PDT 24
Finished Jul 02 09:39:57 AM PDT 24
Peak memory 194464 kb
Host smart-1cf2c7f4-0f06-4c74-897b-637b8dc49a79
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260995396 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.hmac_intr_test.2260995396
Directory /workspace/43.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.hmac_intr_test.773731492
Short name T548
Test name
Test status
Simulation time 21173528 ps
CPU time 0.58 seconds
Started Jul 02 09:39:56 AM PDT 24
Finished Jul 02 09:39:58 AM PDT 24
Peak memory 194480 kb
Host smart-edf64980-74a0-4697-95d5-263c2cf3b368
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773731492 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.hmac_intr_test.773731492
Directory /workspace/44.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.hmac_intr_test.270441099
Short name T598
Test name
Test status
Simulation time 16278997 ps
CPU time 0.56 seconds
Started Jul 02 09:39:56 AM PDT 24
Finished Jul 02 09:39:58 AM PDT 24
Peak memory 194572 kb
Host smart-f8719ddb-c58e-4cb0-8a14-a314fc17311f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270441099 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.hmac_intr_test.270441099
Directory /workspace/45.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.hmac_intr_test.900165095
Short name T579
Test name
Test status
Simulation time 17823920 ps
CPU time 0.58 seconds
Started Jul 02 09:39:55 AM PDT 24
Finished Jul 02 09:39:58 AM PDT 24
Peak memory 194456 kb
Host smart-6dcaa4a7-e210-40b3-8799-80b4babd04e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900165095 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.hmac_intr_test.900165095
Directory /workspace/46.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.hmac_intr_test.4171253371
Short name T648
Test name
Test status
Simulation time 40662275 ps
CPU time 0.57 seconds
Started Jul 02 09:40:09 AM PDT 24
Finished Jul 02 09:40:11 AM PDT 24
Peak memory 194508 kb
Host smart-f83c85a8-016d-4ffd-ae15-e601bf234c95
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171253371 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.hmac_intr_test.4171253371
Directory /workspace/47.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.hmac_intr_test.2282987500
Short name T647
Test name
Test status
Simulation time 13088688 ps
CPU time 0.64 seconds
Started Jul 02 09:39:56 AM PDT 24
Finished Jul 02 09:39:58 AM PDT 24
Peak memory 194660 kb
Host smart-7da7af48-fb8b-4cc9-bade-b1a7c5fd9618
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282987500 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.hmac_intr_test.2282987500
Directory /workspace/48.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.hmac_intr_test.392400933
Short name T654
Test name
Test status
Simulation time 16294243 ps
CPU time 0.63 seconds
Started Jul 02 09:39:57 AM PDT 24
Finished Jul 02 09:39:59 AM PDT 24
Peak memory 194404 kb
Host smart-1f563950-4d1a-4dba-9527-abd3fe37e86e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392400933 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.hmac_intr_test.392400933
Directory /workspace/49.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.1523372087
Short name T541
Test name
Test status
Simulation time 103061345 ps
CPU time 1.81 seconds
Started Jul 02 09:39:29 AM PDT 24
Finished Jul 02 09:39:31 AM PDT 24
Peak memory 199516 kb
Host smart-0e971531-78e3-43cb-be84-21164d39fa79
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523372087 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.hmac_csr_mem_rw_with_rand_reset.1523372087
Directory /workspace/5.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_rw.4102066409
Short name T569
Test name
Test status
Simulation time 32266910 ps
CPU time 0.92 seconds
Started Jul 02 09:39:34 AM PDT 24
Finished Jul 02 09:39:37 AM PDT 24
Peak memory 198940 kb
Host smart-46964f49-a1be-423a-b7a0-a9a55229d66c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102066409 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_rw.4102066409
Directory /workspace/5.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_intr_test.4100195571
Short name T638
Test name
Test status
Simulation time 21018238 ps
CPU time 0.68 seconds
Started Jul 02 09:39:28 AM PDT 24
Finished Jul 02 09:39:29 AM PDT 24
Peak memory 194588 kb
Host smart-5f79dfd4-3813-43e5-9a7d-659bbe0013fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100195571 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_intr_test.4100195571
Directory /workspace/5.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.352616146
Short name T116
Test name
Test status
Simulation time 206253519 ps
CPU time 2.14 seconds
Started Jul 02 09:39:35 AM PDT 24
Finished Jul 02 09:39:38 AM PDT 24
Peak memory 199428 kb
Host smart-c6b42b4e-f496-4a62-b52c-6c3fcb042bca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352616146 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_same_csr_
outstanding.352616146
Directory /workspace/5.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_errors.337296400
Short name T609
Test name
Test status
Simulation time 233738514 ps
CPU time 4.12 seconds
Started Jul 02 09:39:27 AM PDT 24
Finished Jul 02 09:39:32 AM PDT 24
Peak memory 199536 kb
Host smart-b47d8601-405c-4806-8d3d-cd60a8216f62
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337296400 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_errors.337296400
Directory /workspace/5.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.245652401
Short name T136
Test name
Test status
Simulation time 201863383 ps
CPU time 1.8 seconds
Started Jul 02 09:39:30 AM PDT 24
Finished Jul 02 09:39:32 AM PDT 24
Peak memory 199552 kb
Host smart-fd78d426-91c6-4dd3-9db4-842e22d4d3ee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245652401 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_intg_err.245652401
Directory /workspace/5.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.1802448998
Short name T555
Test name
Test status
Simulation time 176478165 ps
CPU time 2.83 seconds
Started Jul 02 09:39:31 AM PDT 24
Finished Jul 02 09:39:35 AM PDT 24
Peak memory 199596 kb
Host smart-515f89cb-708f-43ab-80ff-a691e111f9a3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802448998 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.hmac_csr_mem_rw_with_rand_reset.1802448998
Directory /workspace/6.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_rw.1746033455
Short name T101
Test name
Test status
Simulation time 110705013 ps
CPU time 0.97 seconds
Started Jul 02 09:39:30 AM PDT 24
Finished Jul 02 09:39:32 AM PDT 24
Peak memory 199392 kb
Host smart-feecd672-e129-4f9b-9ccb-9b8e79d994e2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746033455 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_rw.1746033455
Directory /workspace/6.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_intr_test.1460644194
Short name T529
Test name
Test status
Simulation time 41640679 ps
CPU time 0.59 seconds
Started Jul 02 09:39:29 AM PDT 24
Finished Jul 02 09:39:30 AM PDT 24
Peak memory 194608 kb
Host smart-67993311-ef6d-436a-a146-aef41463d1ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460644194 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_intr_test.1460644194
Directory /workspace/6.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.1620303891
Short name T606
Test name
Test status
Simulation time 59522477 ps
CPU time 1.54 seconds
Started Jul 02 09:39:35 AM PDT 24
Finished Jul 02 09:39:37 AM PDT 24
Peak memory 199612 kb
Host smart-26d41785-10bc-49d1-b273-509e7249ca10
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620303891 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_same_csr
_outstanding.1620303891
Directory /workspace/6.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_errors.996083994
Short name T540
Test name
Test status
Simulation time 982425267 ps
CPU time 3.75 seconds
Started Jul 02 09:39:30 AM PDT 24
Finished Jul 02 09:39:35 AM PDT 24
Peak memory 199544 kb
Host smart-19ae2cbd-d99c-4965-9d4e-ad0de14c895b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996083994 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_errors.996083994
Directory /workspace/6.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.2892168621
Short name T532
Test name
Test status
Simulation time 197452729 ps
CPU time 3.04 seconds
Started Jul 02 09:39:36 AM PDT 24
Finished Jul 02 09:39:41 AM PDT 24
Peak memory 207776 kb
Host smart-6e1808fb-cf76-4fae-9e47-c01ac6ccddc0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892168621 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.hmac_csr_mem_rw_with_rand_reset.2892168621
Directory /workspace/7.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_rw.3400715412
Short name T628
Test name
Test status
Simulation time 25491794 ps
CPU time 0.83 seconds
Started Jul 02 09:39:34 AM PDT 24
Finished Jul 02 09:39:36 AM PDT 24
Peak memory 198644 kb
Host smart-6c7e7a57-d4a9-408c-bca9-98d60bebb122
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400715412 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_rw.3400715412
Directory /workspace/7.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_intr_test.770127013
Short name T571
Test name
Test status
Simulation time 17417072 ps
CPU time 0.58 seconds
Started Jul 02 09:39:34 AM PDT 24
Finished Jul 02 09:39:36 AM PDT 24
Peak memory 194508 kb
Host smart-333af238-0f0b-4b25-888f-64d9c770a868
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770127013 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_intr_test.770127013
Directory /workspace/7.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.3169559902
Short name T563
Test name
Test status
Simulation time 127583399 ps
CPU time 1.69 seconds
Started Jul 02 09:39:33 AM PDT 24
Finished Jul 02 09:39:36 AM PDT 24
Peak memory 199500 kb
Host smart-b9473c1c-adef-4565-9260-9c93dafac17b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169559902 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_same_csr
_outstanding.3169559902
Directory /workspace/7.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_errors.36324666
Short name T599
Test name
Test status
Simulation time 862281640 ps
CPU time 4.07 seconds
Started Jul 02 09:39:36 AM PDT 24
Finished Jul 02 09:39:41 AM PDT 24
Peak memory 199608 kb
Host smart-84b6aa12-8a80-4c08-97cd-123138aafb61
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36324666 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_errors.36324666
Directory /workspace/7.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.1275753826
Short name T619
Test name
Test status
Simulation time 382671085 ps
CPU time 3.26 seconds
Started Jul 02 09:39:37 AM PDT 24
Finished Jul 02 09:39:41 AM PDT 24
Peak memory 199448 kb
Host smart-2a256b36-91dc-4a4b-a221-675cde671e1e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275753826 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_intg_err.1275753826
Directory /workspace/7.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.180832699
Short name T550
Test name
Test status
Simulation time 238445011 ps
CPU time 1.72 seconds
Started Jul 02 09:39:34 AM PDT 24
Finished Jul 02 09:39:37 AM PDT 24
Peak memory 199612 kb
Host smart-9dff9ea0-8216-47d0-ad0c-7a497a54cf5f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180832699 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.hmac_csr_mem_rw_with_rand_reset.180832699
Directory /workspace/8.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_rw.792611578
Short name T113
Test name
Test status
Simulation time 193609769 ps
CPU time 0.83 seconds
Started Jul 02 09:39:34 AM PDT 24
Finished Jul 02 09:39:36 AM PDT 24
Peak memory 199068 kb
Host smart-928c3dfa-fca4-469f-909a-0b6b04a535ef
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792611578 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_rw.792611578
Directory /workspace/8.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_intr_test.3961440256
Short name T633
Test name
Test status
Simulation time 33880278 ps
CPU time 0.58 seconds
Started Jul 02 09:39:35 AM PDT 24
Finished Jul 02 09:39:37 AM PDT 24
Peak memory 194472 kb
Host smart-7ba1db59-0653-4dbc-a912-efb4cf55a94e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961440256 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_intr_test.3961440256
Directory /workspace/8.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.3045880059
Short name T117
Test name
Test status
Simulation time 190364533 ps
CPU time 1.24 seconds
Started Jul 02 09:39:33 AM PDT 24
Finished Jul 02 09:39:35 AM PDT 24
Peak memory 197936 kb
Host smart-5d03c565-00d3-4709-8008-44ac8206fa5b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045880059 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_same_csr
_outstanding.3045880059
Directory /workspace/8.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_errors.2932119674
Short name T543
Test name
Test status
Simulation time 238405601 ps
CPU time 4.32 seconds
Started Jul 02 09:39:33 AM PDT 24
Finished Jul 02 09:39:38 AM PDT 24
Peak memory 199464 kb
Host smart-e2bc1cf8-5209-48ae-aac7-613d0fc759d7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932119674 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_errors.2932119674
Directory /workspace/8.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.512777864
Short name T649
Test name
Test status
Simulation time 45979659 ps
CPU time 1.33 seconds
Started Jul 02 09:39:38 AM PDT 24
Finished Jul 02 09:39:40 AM PDT 24
Peak memory 199552 kb
Host smart-376f55b6-d593-443c-89d9-05e94da611ac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512777864 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.hmac_csr_mem_rw_with_rand_reset.512777864
Directory /workspace/9.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_rw.2255278816
Short name T553
Test name
Test status
Simulation time 527710570 ps
CPU time 1 seconds
Started Jul 02 09:39:37 AM PDT 24
Finished Jul 02 09:39:39 AM PDT 24
Peak memory 199384 kb
Host smart-9b9b5c5b-51bb-4b8f-9a84-4c96d5542f2d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255278816 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_rw.2255278816
Directory /workspace/9.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_intr_test.2024672194
Short name T604
Test name
Test status
Simulation time 229081096 ps
CPU time 0.6 seconds
Started Jul 02 09:39:32 AM PDT 24
Finished Jul 02 09:39:33 AM PDT 24
Peak memory 194524 kb
Host smart-e0be5a28-f81a-4b03-ac25-8cca125d22a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024672194 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_intr_test.2024672194
Directory /workspace/9.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.279492661
Short name T592
Test name
Test status
Simulation time 48130089 ps
CPU time 1.19 seconds
Started Jul 02 09:39:48 AM PDT 24
Finished Jul 02 09:39:50 AM PDT 24
Peak memory 197860 kb
Host smart-a0b2bb83-0b71-486e-bc91-a72a3632c0ca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279492661 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_same_csr_
outstanding.279492661
Directory /workspace/9.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_errors.4028178244
Short name T531
Test name
Test status
Simulation time 916545427 ps
CPU time 2.68 seconds
Started Jul 02 09:39:33 AM PDT 24
Finished Jul 02 09:39:36 AM PDT 24
Peak memory 199576 kb
Host smart-7845aef2-c738-4670-9b02-ddf435b784bd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028178244 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_errors.4028178244
Directory /workspace/9.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.56860704
Short name T135
Test name
Test status
Simulation time 52191150 ps
CPU time 1.72 seconds
Started Jul 02 09:39:32 AM PDT 24
Finished Jul 02 09:39:35 AM PDT 24
Peak memory 199564 kb
Host smart-93aa126b-c127-4b89-b9d7-50785f409e53
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56860704 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_intg_err.56860704
Directory /workspace/9.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.hmac_alert_test.692044369
Short name T483
Test name
Test status
Simulation time 34188718 ps
CPU time 0.56 seconds
Started Jul 02 09:42:28 AM PDT 24
Finished Jul 02 09:42:29 AM PDT 24
Peak memory 195204 kb
Host smart-a452326e-c58f-4afd-b926-9d8e8bfded13
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692044369 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_alert_test.692044369
Directory /workspace/0.hmac_alert_test/latest

Test location /workspace/coverage/default/0.hmac_back_pressure.2684450316
Short name T378
Test name
Test status
Simulation time 2193632344 ps
CPU time 119.59 seconds
Started Jul 02 09:42:26 AM PDT 24
Finished Jul 02 09:44:27 AM PDT 24
Peak memory 200404 kb
Host smart-402bbb35-ddc9-4cae-af91-e62f796b8cae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2684450316 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_back_pressure.2684450316
Directory /workspace/0.hmac_back_pressure/latest

Test location /workspace/coverage/default/0.hmac_burst_wr.2973107749
Short name T198
Test name
Test status
Simulation time 2244471366 ps
CPU time 28.28 seconds
Started Jul 02 09:42:26 AM PDT 24
Finished Jul 02 09:42:56 AM PDT 24
Peak memory 200448 kb
Host smart-5f03d88a-3084-4bf0-ae99-2edaf1fd6a2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2973107749 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_burst_wr.2973107749
Directory /workspace/0.hmac_burst_wr/latest

Test location /workspace/coverage/default/0.hmac_datapath_stress.2675395314
Short name T451
Test name
Test status
Simulation time 31562523570 ps
CPU time 818.8 seconds
Started Jul 02 09:42:28 AM PDT 24
Finished Jul 02 09:56:08 AM PDT 24
Peak memory 693864 kb
Host smart-31043d90-1b37-42b1-aee8-974201c02809
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2675395314 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_datapath_stress.2675395314
Directory /workspace/0.hmac_datapath_stress/latest

Test location /workspace/coverage/default/0.hmac_error.1004307809
Short name T153
Test name
Test status
Simulation time 9222449218 ps
CPU time 127.72 seconds
Started Jul 02 09:42:25 AM PDT 24
Finished Jul 02 09:44:35 AM PDT 24
Peak memory 200404 kb
Host smart-0ca4427b-2f49-429b-b6b6-b4dc8a04dc23
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004307809 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_error.1004307809
Directory /workspace/0.hmac_error/latest

Test location /workspace/coverage/default/0.hmac_long_msg.235866580
Short name T200
Test name
Test status
Simulation time 17008022503 ps
CPU time 57.48 seconds
Started Jul 02 09:42:27 AM PDT 24
Finished Jul 02 09:43:25 AM PDT 24
Peak memory 200428 kb
Host smart-376e2c22-3d10-4a19-b491-57cea149f2a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235866580 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_long_msg.235866580
Directory /workspace/0.hmac_long_msg/latest

Test location /workspace/coverage/default/0.hmac_sec_cm.566954054
Short name T59
Test name
Test status
Simulation time 58457947 ps
CPU time 0.85 seconds
Started Jul 02 09:42:30 AM PDT 24
Finished Jul 02 09:42:32 AM PDT 24
Peak memory 218412 kb
Host smart-2793b700-4bd8-4f87-8c21-2d2526a7ba20
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566954054 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_sec_cm.566954054
Directory /workspace/0.hmac_sec_cm/latest

Test location /workspace/coverage/default/0.hmac_smoke.3127895779
Short name T485
Test name
Test status
Simulation time 183048664 ps
CPU time 7.46 seconds
Started Jul 02 09:42:28 AM PDT 24
Finished Jul 02 09:42:36 AM PDT 24
Peak memory 200380 kb
Host smart-ee4408bc-2091-4687-b2af-8a6982037ecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127895779 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_smoke.3127895779
Directory /workspace/0.hmac_smoke/latest

Test location /workspace/coverage/default/0.hmac_stress_all.2591881236
Short name T201
Test name
Test status
Simulation time 15198560550 ps
CPU time 203.12 seconds
Started Jul 02 09:42:27 AM PDT 24
Finished Jul 02 09:45:51 AM PDT 24
Peak memory 200432 kb
Host smart-5ef73e66-5713-4ebf-abbb-dbf995c68eaf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591881236 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all.2591881236
Directory /workspace/0.hmac_stress_all/latest

Test location /workspace/coverage/default/0.hmac_test_hmac256_vectors.211947544
Short name T430
Test name
Test status
Simulation time 4502441820 ps
CPU time 66.78 seconds
Started Jul 02 09:42:29 AM PDT 24
Finished Jul 02 09:43:36 AM PDT 24
Peak memory 200468 kb
Host smart-7a9ea6e3-b617-45a1-ba63-3b77d1d9430e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=211947544 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac256_vectors.211947544
Directory /workspace/0.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_hmac384_vectors.2177081041
Short name T509
Test name
Test status
Simulation time 12545958723 ps
CPU time 90.19 seconds
Started Jul 02 09:42:32 AM PDT 24
Finished Jul 02 09:44:03 AM PDT 24
Peak memory 200412 kb
Host smart-1bf1dfb1-ee78-432f-9e1d-8c93565af410
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2177081041 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac384_vectors.2177081041
Directory /workspace/0.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_hmac512_vectors.1734926863
Short name T497
Test name
Test status
Simulation time 16410091948 ps
CPU time 88.86 seconds
Started Jul 02 09:42:30 AM PDT 24
Finished Jul 02 09:44:00 AM PDT 24
Peak memory 200456 kb
Host smart-a9767547-c469-449a-990d-fc7c28a211ff
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1734926863 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac512_vectors.1734926863
Directory /workspace/0.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha256_vectors.3030467209
Short name T420
Test name
Test status
Simulation time 369895162139 ps
CPU time 588.91 seconds
Started Jul 02 09:42:24 AM PDT 24
Finished Jul 02 09:52:15 AM PDT 24
Peak memory 200420 kb
Host smart-9b872334-91de-4b66-8004-268ee7668f28
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3030467209 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha256_vectors.3030467209
Directory /workspace/0.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha384_vectors.318584626
Short name T319
Test name
Test status
Simulation time 144694645599 ps
CPU time 2375.85 seconds
Started Jul 02 09:42:25 AM PDT 24
Finished Jul 02 10:22:03 AM PDT 24
Peak memory 216152 kb
Host smart-14ef6af7-617c-4c93-81d1-96ecfba918d3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=318584626 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha384_vectors.318584626
Directory /workspace/0.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha512_vectors.86420263
Short name T170
Test name
Test status
Simulation time 540349679677 ps
CPU time 2282.87 seconds
Started Jul 02 09:42:28 AM PDT 24
Finished Jul 02 10:20:32 AM PDT 24
Peak memory 215844 kb
Host smart-67e20c55-afc1-45a0-89b9-deaa5cc80a78
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_200_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=86420263 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha512_vectors.86420263
Directory /workspace/0.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/0.hmac_wipe_secret.359521911
Short name T181
Test name
Test status
Simulation time 774396175 ps
CPU time 13.49 seconds
Started Jul 02 09:42:25 AM PDT 24
Finished Jul 02 09:42:40 AM PDT 24
Peak memory 200268 kb
Host smart-9cc81165-1e44-439f-b3a2-7760104221ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359521911 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_wipe_secret.359521911
Directory /workspace/0.hmac_wipe_secret/latest

Test location /workspace/coverage/default/1.hmac_alert_test.745453359
Short name T256
Test name
Test status
Simulation time 34878822 ps
CPU time 0.57 seconds
Started Jul 02 09:42:29 AM PDT 24
Finished Jul 02 09:42:30 AM PDT 24
Peak memory 195176 kb
Host smart-5a506c6d-dc64-47a4-b628-83f3ff628ba0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745453359 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_alert_test.745453359
Directory /workspace/1.hmac_alert_test/latest

Test location /workspace/coverage/default/1.hmac_back_pressure.3259416847
Short name T425
Test name
Test status
Simulation time 1481123087 ps
CPU time 39.37 seconds
Started Jul 02 09:42:33 AM PDT 24
Finished Jul 02 09:43:13 AM PDT 24
Peak memory 200300 kb
Host smart-e4057c4f-b766-4d49-8020-822e18a0dc94
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3259416847 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_back_pressure.3259416847
Directory /workspace/1.hmac_back_pressure/latest

Test location /workspace/coverage/default/1.hmac_burst_wr.3149164507
Short name T449
Test name
Test status
Simulation time 2057864331 ps
CPU time 27.47 seconds
Started Jul 02 09:42:35 AM PDT 24
Finished Jul 02 09:43:03 AM PDT 24
Peak memory 200416 kb
Host smart-bfa4f920-b433-4071-b47e-1e64f4148649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149164507 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_burst_wr.3149164507
Directory /workspace/1.hmac_burst_wr/latest

Test location /workspace/coverage/default/1.hmac_datapath_stress.2523785876
Short name T498
Test name
Test status
Simulation time 4494863166 ps
CPU time 332.88 seconds
Started Jul 02 09:42:38 AM PDT 24
Finished Jul 02 09:48:12 AM PDT 24
Peak memory 611396 kb
Host smart-97bbe37e-c9dd-49f6-97f4-589cc7be860a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2523785876 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_datapath_stress.2523785876
Directory /workspace/1.hmac_datapath_stress/latest

Test location /workspace/coverage/default/1.hmac_error.3905936066
Short name T61
Test name
Test status
Simulation time 44823312 ps
CPU time 0.65 seconds
Started Jul 02 09:42:34 AM PDT 24
Finished Jul 02 09:42:36 AM PDT 24
Peak memory 196720 kb
Host smart-a1b11704-dca6-4c5a-b085-1c561e43eb3c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905936066 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_error.3905936066
Directory /workspace/1.hmac_error/latest

Test location /workspace/coverage/default/1.hmac_long_msg.3541550625
Short name T141
Test name
Test status
Simulation time 9248466964 ps
CPU time 133.65 seconds
Started Jul 02 09:42:34 AM PDT 24
Finished Jul 02 09:44:49 AM PDT 24
Peak memory 200468 kb
Host smart-b0f734c2-bf43-49bc-b79c-837bd8df22e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3541550625 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_long_msg.3541550625
Directory /workspace/1.hmac_long_msg/latest

Test location /workspace/coverage/default/1.hmac_sec_cm.4230252477
Short name T60
Test name
Test status
Simulation time 35284616 ps
CPU time 0.81 seconds
Started Jul 02 09:42:29 AM PDT 24
Finished Jul 02 09:42:31 AM PDT 24
Peak memory 218404 kb
Host smart-acc66ca7-88df-4974-927f-e251fd8cb88d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230252477 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_sec_cm.4230252477
Directory /workspace/1.hmac_sec_cm/latest

Test location /workspace/coverage/default/1.hmac_smoke.3256085964
Short name T347
Test name
Test status
Simulation time 3037312540 ps
CPU time 13.18 seconds
Started Jul 02 09:42:34 AM PDT 24
Finished Jul 02 09:42:48 AM PDT 24
Peak memory 200476 kb
Host smart-45a0682e-95b9-49fd-a6a9-1df78c46d2d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256085964 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_smoke.3256085964
Directory /workspace/1.hmac_smoke/latest

Test location /workspace/coverage/default/1.hmac_stress_all.1783034843
Short name T240
Test name
Test status
Simulation time 8013044088 ps
CPU time 656.86 seconds
Started Jul 02 09:42:31 AM PDT 24
Finished Jul 02 09:53:29 AM PDT 24
Peak memory 620476 kb
Host smart-4622e2ae-d723-4687-97e4-a2819802cd1d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783034843 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all.1783034843
Directory /workspace/1.hmac_stress_all/latest

Test location /workspace/coverage/default/1.hmac_stress_all_with_rand_reset.371946160
Short name T15
Test name
Test status
Simulation time 179100437951 ps
CPU time 1163.35 seconds
Started Jul 02 09:42:36 AM PDT 24
Finished Jul 02 10:02:01 AM PDT 24
Peak memory 733388 kb
Host smart-3c8f00c6-d479-4100-8a82-c82d0dd5e256
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=371946160 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all_with_rand_reset.371946160
Directory /workspace/1.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.hmac_test_hmac256_vectors.2060748886
Short name T64
Test name
Test status
Simulation time 6950493522 ps
CPU time 79.44 seconds
Started Jul 02 09:42:29 AM PDT 24
Finished Jul 02 09:43:50 AM PDT 24
Peak memory 200384 kb
Host smart-ae7b89a6-afaa-4c92-b399-77714d4d89c8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2060748886 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac256_vectors.2060748886
Directory /workspace/1.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_hmac384_vectors.2801136695
Short name T237
Test name
Test status
Simulation time 3202349563 ps
CPU time 54.7 seconds
Started Jul 02 09:42:35 AM PDT 24
Finished Jul 02 09:43:30 AM PDT 24
Peak memory 200404 kb
Host smart-f3820374-3924-4fbd-9bb3-ad766c0ddd61
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2801136695 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac384_vectors.2801136695
Directory /workspace/1.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_hmac512_vectors.2006815953
Short name T355
Test name
Test status
Simulation time 5120504327 ps
CPU time 76.87 seconds
Started Jul 02 09:42:35 AM PDT 24
Finished Jul 02 09:43:53 AM PDT 24
Peak memory 200404 kb
Host smart-4146572e-9b4a-4e13-a63b-8037f707259b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2006815953 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac512_vectors.2006815953
Directory /workspace/1.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha256_vectors.1484807805
Short name T216
Test name
Test status
Simulation time 495126080569 ps
CPU time 637.35 seconds
Started Jul 02 09:42:31 AM PDT 24
Finished Jul 02 09:53:09 AM PDT 24
Peak memory 200380 kb
Host smart-074b109b-7488-4430-9f45-b7df6f608283
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1484807805 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha256_vectors.1484807805
Directory /workspace/1.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha512_vectors.1336513605
Short name T486
Test name
Test status
Simulation time 450172693769 ps
CPU time 2368.22 seconds
Started Jul 02 09:42:29 AM PDT 24
Finished Jul 02 10:21:58 AM PDT 24
Peak memory 215780 kb
Host smart-3a750a8e-e520-41bf-9eb7-a516e7d1d484
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_200_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1336513605 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha512_vectors.1336513605
Directory /workspace/1.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/1.hmac_wipe_secret.2921667721
Short name T236
Test name
Test status
Simulation time 1787684626 ps
CPU time 22.33 seconds
Started Jul 02 09:42:32 AM PDT 24
Finished Jul 02 09:42:55 AM PDT 24
Peak memory 200316 kb
Host smart-0815de4e-b7ff-42a4-9bea-fff00bc2d2f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921667721 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_wipe_secret.2921667721
Directory /workspace/1.hmac_wipe_secret/latest

Test location /workspace/coverage/default/10.hmac_alert_test.4111358304
Short name T202
Test name
Test status
Simulation time 16782612 ps
CPU time 0.58 seconds
Started Jul 02 09:42:50 AM PDT 24
Finished Jul 02 09:42:52 AM PDT 24
Peak memory 196188 kb
Host smart-9f211d26-da34-4b5b-9608-36e23f26a43f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111358304 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_alert_test.4111358304
Directory /workspace/10.hmac_alert_test/latest

Test location /workspace/coverage/default/10.hmac_back_pressure.2090031813
Short name T52
Test name
Test status
Simulation time 1687292629 ps
CPU time 92.93 seconds
Started Jul 02 09:42:49 AM PDT 24
Finished Jul 02 09:44:23 AM PDT 24
Peak memory 200328 kb
Host smart-9468ebeb-2c0b-4ccf-9a93-332a9fd03df7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2090031813 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_back_pressure.2090031813
Directory /workspace/10.hmac_back_pressure/latest

Test location /workspace/coverage/default/10.hmac_burst_wr.2322244483
Short name T218
Test name
Test status
Simulation time 41571963612 ps
CPU time 45.22 seconds
Started Jul 02 09:42:53 AM PDT 24
Finished Jul 02 09:43:40 AM PDT 24
Peak memory 200540 kb
Host smart-27b2be66-6385-49cc-80eb-582f31c5d225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322244483 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_burst_wr.2322244483
Directory /workspace/10.hmac_burst_wr/latest

Test location /workspace/coverage/default/10.hmac_datapath_stress.993354643
Short name T284
Test name
Test status
Simulation time 30942900922 ps
CPU time 1028.92 seconds
Started Jul 02 09:42:55 AM PDT 24
Finished Jul 02 10:00:05 AM PDT 24
Peak memory 731564 kb
Host smart-bf04c7cf-1562-44d0-a322-4823514fe05b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=993354643 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_datapath_stress.993354643
Directory /workspace/10.hmac_datapath_stress/latest

Test location /workspace/coverage/default/10.hmac_error.2131180803
Short name T401
Test name
Test status
Simulation time 86804784506 ps
CPU time 96.25 seconds
Started Jul 02 09:42:55 AM PDT 24
Finished Jul 02 09:44:33 AM PDT 24
Peak memory 200424 kb
Host smart-cacd7203-28ba-47c3-a52a-9580bc957e7c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131180803 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_error.2131180803
Directory /workspace/10.hmac_error/latest

Test location /workspace/coverage/default/10.hmac_long_msg.3847763592
Short name T478
Test name
Test status
Simulation time 11148083640 ps
CPU time 140.14 seconds
Started Jul 02 09:42:48 AM PDT 24
Finished Jul 02 09:45:09 AM PDT 24
Peak memory 208636 kb
Host smart-b8c1b054-4541-433f-8f4f-470717761992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847763592 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_long_msg.3847763592
Directory /workspace/10.hmac_long_msg/latest

Test location /workspace/coverage/default/10.hmac_smoke.1161790693
Short name T303
Test name
Test status
Simulation time 4339615523 ps
CPU time 14.66 seconds
Started Jul 02 09:42:52 AM PDT 24
Finished Jul 02 09:43:08 AM PDT 24
Peak memory 200428 kb
Host smart-fc665ac6-9dce-40b7-bfa9-cebcb445f369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161790693 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_smoke.1161790693
Directory /workspace/10.hmac_smoke/latest

Test location /workspace/coverage/default/10.hmac_stress_all.796464033
Short name T176
Test name
Test status
Simulation time 1351396777 ps
CPU time 18.09 seconds
Started Jul 02 09:42:57 AM PDT 24
Finished Jul 02 09:43:16 AM PDT 24
Peak memory 200316 kb
Host smart-13373850-4691-4d5f-b061-e7bc2bb14311
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796464033 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 10.hmac_stress_all.796464033
Directory /workspace/10.hmac_stress_all/latest

Test location /workspace/coverage/default/10.hmac_wipe_secret.3103873353
Short name T89
Test name
Test status
Simulation time 32692585374 ps
CPU time 111.31 seconds
Started Jul 02 09:43:02 AM PDT 24
Finished Jul 02 09:44:55 AM PDT 24
Peak memory 200432 kb
Host smart-71c288e0-4e63-4eea-a3ad-85ea9bd9c94c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103873353 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_wipe_secret.3103873353
Directory /workspace/10.hmac_wipe_secret/latest

Test location /workspace/coverage/default/11.hmac_alert_test.1122103256
Short name T334
Test name
Test status
Simulation time 44633405 ps
CPU time 0.57 seconds
Started Jul 02 09:42:59 AM PDT 24
Finished Jul 02 09:43:01 AM PDT 24
Peak memory 196200 kb
Host smart-8a49f44f-a6b3-4820-8cc5-de7e047f83ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122103256 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_alert_test.1122103256
Directory /workspace/11.hmac_alert_test/latest

Test location /workspace/coverage/default/11.hmac_burst_wr.2232703902
Short name T321
Test name
Test status
Simulation time 8041385725 ps
CPU time 76.3 seconds
Started Jul 02 09:42:51 AM PDT 24
Finished Jul 02 09:44:09 AM PDT 24
Peak memory 200692 kb
Host smart-b681cf5a-d944-4f1c-96e7-ccafcd136d2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232703902 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_burst_wr.2232703902
Directory /workspace/11.hmac_burst_wr/latest

Test location /workspace/coverage/default/11.hmac_datapath_stress.2380456447
Short name T327
Test name
Test status
Simulation time 11074546677 ps
CPU time 540.59 seconds
Started Jul 02 09:42:54 AM PDT 24
Finished Jul 02 09:51:56 AM PDT 24
Peak memory 700976 kb
Host smart-eb2e3e39-c885-4139-9ac8-22db38147743
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2380456447 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_datapath_stress.2380456447
Directory /workspace/11.hmac_datapath_stress/latest

Test location /workspace/coverage/default/11.hmac_error.2257985981
Short name T196
Test name
Test status
Simulation time 6933699563 ps
CPU time 35.28 seconds
Started Jul 02 09:42:59 AM PDT 24
Finished Jul 02 09:43:35 AM PDT 24
Peak memory 200452 kb
Host smart-71f85e85-fc6b-416e-9ac3-8fa8133523d8
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257985981 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_error.2257985981
Directory /workspace/11.hmac_error/latest

Test location /workspace/coverage/default/11.hmac_long_msg.3110472922
Short name T280
Test name
Test status
Simulation time 11286061668 ps
CPU time 69.44 seconds
Started Jul 02 09:42:52 AM PDT 24
Finished Jul 02 09:44:02 AM PDT 24
Peak memory 200448 kb
Host smart-15935565-43a6-49e0-baab-70a2b1ae2ccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3110472922 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_long_msg.3110472922
Directory /workspace/11.hmac_long_msg/latest

Test location /workspace/coverage/default/11.hmac_smoke.2171068623
Short name T495
Test name
Test status
Simulation time 249381880 ps
CPU time 11.64 seconds
Started Jul 02 09:42:53 AM PDT 24
Finished Jul 02 09:43:05 AM PDT 24
Peak memory 200372 kb
Host smart-da058de1-a2af-40d7-b079-a0bcbb7404ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171068623 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_smoke.2171068623
Directory /workspace/11.hmac_smoke/latest

Test location /workspace/coverage/default/11.hmac_stress_all.1061908871
Short name T411
Test name
Test status
Simulation time 108727533014 ps
CPU time 2324.71 seconds
Started Jul 02 09:42:49 AM PDT 24
Finished Jul 02 10:21:35 AM PDT 24
Peak memory 807136 kb
Host smart-0ad43493-7f67-42e6-9f95-da6ef1cfec13
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061908871 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.hmac_stress_all.1061908871
Directory /workspace/11.hmac_stress_all/latest

Test location /workspace/coverage/default/11.hmac_wipe_secret.400352300
Short name T227
Test name
Test status
Simulation time 12697110931 ps
CPU time 43.9 seconds
Started Jul 02 09:42:48 AM PDT 24
Finished Jul 02 09:43:33 AM PDT 24
Peak memory 200444 kb
Host smart-970f3a90-eff8-4fca-aa2c-fddc5c03f3f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400352300 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_wipe_secret.400352300
Directory /workspace/11.hmac_wipe_secret/latest

Test location /workspace/coverage/default/12.hmac_alert_test.722330398
Short name T215
Test name
Test status
Simulation time 14980733 ps
CPU time 0.61 seconds
Started Jul 02 09:42:52 AM PDT 24
Finished Jul 02 09:42:54 AM PDT 24
Peak memory 196228 kb
Host smart-7ab365ac-9fa7-4c48-b2c7-fa4776af9874
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722330398 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_alert_test.722330398
Directory /workspace/12.hmac_alert_test/latest

Test location /workspace/coverage/default/12.hmac_back_pressure.3947657872
Short name T94
Test name
Test status
Simulation time 1230271229 ps
CPU time 17.99 seconds
Started Jul 02 09:43:02 AM PDT 24
Finished Jul 02 09:43:21 AM PDT 24
Peak memory 200348 kb
Host smart-48b9d3aa-6177-4e4b-8ed0-ec1b4960a125
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3947657872 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_back_pressure.3947657872
Directory /workspace/12.hmac_back_pressure/latest

Test location /workspace/coverage/default/12.hmac_burst_wr.4232193191
Short name T194
Test name
Test status
Simulation time 1406889784 ps
CPU time 19.98 seconds
Started Jul 02 09:42:52 AM PDT 24
Finished Jul 02 09:43:13 AM PDT 24
Peak memory 200376 kb
Host smart-d3665ea4-d5f4-442a-b5c7-d90d8354b4f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232193191 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_burst_wr.4232193191
Directory /workspace/12.hmac_burst_wr/latest

Test location /workspace/coverage/default/12.hmac_datapath_stress.2644372132
Short name T288
Test name
Test status
Simulation time 11057187411 ps
CPU time 454.91 seconds
Started Jul 02 09:42:53 AM PDT 24
Finished Jul 02 09:50:29 AM PDT 24
Peak memory 648736 kb
Host smart-a28578d5-775b-4550-8b17-d0f30b69c1c2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2644372132 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_datapath_stress.2644372132
Directory /workspace/12.hmac_datapath_stress/latest

Test location /workspace/coverage/default/12.hmac_error.1591662703
Short name T190
Test name
Test status
Simulation time 1773353387 ps
CPU time 31.63 seconds
Started Jul 02 09:42:49 AM PDT 24
Finished Jul 02 09:43:21 AM PDT 24
Peak memory 200364 kb
Host smart-d8df6293-30f9-4d26-ab6e-5729060b0605
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591662703 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_error.1591662703
Directory /workspace/12.hmac_error/latest

Test location /workspace/coverage/default/12.hmac_long_msg.749707443
Short name T357
Test name
Test status
Simulation time 2633564302 ps
CPU time 46.18 seconds
Started Jul 02 09:42:55 AM PDT 24
Finished Jul 02 09:43:43 AM PDT 24
Peak memory 200504 kb
Host smart-9990022e-eadf-40b2-aef6-a20cab3d4caf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749707443 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_long_msg.749707443
Directory /workspace/12.hmac_long_msg/latest

Test location /workspace/coverage/default/12.hmac_smoke.1540341419
Short name T516
Test name
Test status
Simulation time 1513608707 ps
CPU time 6.48 seconds
Started Jul 02 09:42:50 AM PDT 24
Finished Jul 02 09:42:58 AM PDT 24
Peak memory 200340 kb
Host smart-eb25c86f-6c75-40e8-bcc4-3e7f770e69f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540341419 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_smoke.1540341419
Directory /workspace/12.hmac_smoke/latest

Test location /workspace/coverage/default/12.hmac_stress_all.313629081
Short name T294
Test name
Test status
Simulation time 2198606392 ps
CPU time 118.28 seconds
Started Jul 02 09:42:52 AM PDT 24
Finished Jul 02 09:44:51 AM PDT 24
Peak memory 200424 kb
Host smart-1d02fb23-fbcd-448c-a8aa-131ee8bf2455
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313629081 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 12.hmac_stress_all.313629081
Directory /workspace/12.hmac_stress_all/latest

Test location /workspace/coverage/default/12.hmac_wipe_secret.2110073779
Short name T24
Test name
Test status
Simulation time 69642597043 ps
CPU time 127.13 seconds
Started Jul 02 09:42:50 AM PDT 24
Finished Jul 02 09:44:59 AM PDT 24
Peak memory 200432 kb
Host smart-1f2fd74f-79fa-447e-90a8-b1c7ad0b489c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110073779 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_wipe_secret.2110073779
Directory /workspace/12.hmac_wipe_secret/latest

Test location /workspace/coverage/default/13.hmac_alert_test.2567333271
Short name T431
Test name
Test status
Simulation time 15191158 ps
CPU time 0.57 seconds
Started Jul 02 09:43:00 AM PDT 24
Finished Jul 02 09:43:01 AM PDT 24
Peak memory 195804 kb
Host smart-9d7ca9af-3776-4911-b7f0-48ed76a5ee8b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567333271 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_alert_test.2567333271
Directory /workspace/13.hmac_alert_test/latest

Test location /workspace/coverage/default/13.hmac_back_pressure.310843316
Short name T100
Test name
Test status
Simulation time 1224392118 ps
CPU time 4.08 seconds
Started Jul 02 09:43:00 AM PDT 24
Finished Jul 02 09:43:04 AM PDT 24
Peak memory 200360 kb
Host smart-d248883b-1c01-43a9-874b-c8ae5eafd311
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=310843316 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_back_pressure.310843316
Directory /workspace/13.hmac_back_pressure/latest

Test location /workspace/coverage/default/13.hmac_burst_wr.3197638810
Short name T254
Test name
Test status
Simulation time 49356915876 ps
CPU time 55.27 seconds
Started Jul 02 09:42:58 AM PDT 24
Finished Jul 02 09:43:54 AM PDT 24
Peak memory 208652 kb
Host smart-4dbe396f-2437-459c-97b8-d2b0f33eb934
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197638810 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_burst_wr.3197638810
Directory /workspace/13.hmac_burst_wr/latest

Test location /workspace/coverage/default/13.hmac_datapath_stress.676633187
Short name T51
Test name
Test status
Simulation time 3712356388 ps
CPU time 763.67 seconds
Started Jul 02 09:42:55 AM PDT 24
Finished Jul 02 09:55:40 AM PDT 24
Peak memory 672684 kb
Host smart-5226b7e3-fe52-42bf-b93b-8bad2037699f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=676633187 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_datapath_stress.676633187
Directory /workspace/13.hmac_datapath_stress/latest

Test location /workspace/coverage/default/13.hmac_error.4140027096
Short name T1
Test name
Test status
Simulation time 181873855 ps
CPU time 9.73 seconds
Started Jul 02 09:42:55 AM PDT 24
Finished Jul 02 09:43:06 AM PDT 24
Peak memory 200240 kb
Host smart-71c176a5-e596-4da6-a179-0a5fa492e526
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140027096 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_error.4140027096
Directory /workspace/13.hmac_error/latest

Test location /workspace/coverage/default/13.hmac_long_msg.3789788747
Short name T317
Test name
Test status
Simulation time 2654286825 ps
CPU time 33.05 seconds
Started Jul 02 09:42:54 AM PDT 24
Finished Jul 02 09:43:29 AM PDT 24
Peak memory 200420 kb
Host smart-9a71740c-2f9e-494b-959b-0749301a1c3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789788747 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_long_msg.3789788747
Directory /workspace/13.hmac_long_msg/latest

Test location /workspace/coverage/default/13.hmac_smoke.1865715032
Short name T450
Test name
Test status
Simulation time 441455664 ps
CPU time 7.06 seconds
Started Jul 02 09:43:02 AM PDT 24
Finished Jul 02 09:43:10 AM PDT 24
Peak memory 200368 kb
Host smart-34da18a9-fc11-4f2d-8286-48fda0e13ce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865715032 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_smoke.1865715032
Directory /workspace/13.hmac_smoke/latest

Test location /workspace/coverage/default/13.hmac_stress_all.2862912678
Short name T525
Test name
Test status
Simulation time 69412319540 ps
CPU time 2659.89 seconds
Started Jul 02 09:43:01 AM PDT 24
Finished Jul 02 10:27:21 AM PDT 24
Peak memory 775272 kb
Host smart-523c250c-d8e7-4fb4-ac8e-8102593c014f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862912678 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.hmac_stress_all.2862912678
Directory /workspace/13.hmac_stress_all/latest

Test location /workspace/coverage/default/13.hmac_wipe_secret.3900262926
Short name T397
Test name
Test status
Simulation time 13276863628 ps
CPU time 75.14 seconds
Started Jul 02 09:42:55 AM PDT 24
Finished Jul 02 09:44:11 AM PDT 24
Peak memory 200448 kb
Host smart-c554ba12-97d6-4e6b-9841-b0d2c691291b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900262926 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_wipe_secret.3900262926
Directory /workspace/13.hmac_wipe_secret/latest

Test location /workspace/coverage/default/14.hmac_alert_test.3839344708
Short name T314
Test name
Test status
Simulation time 15952997 ps
CPU time 0.65 seconds
Started Jul 02 09:42:56 AM PDT 24
Finished Jul 02 09:42:58 AM PDT 24
Peak memory 196224 kb
Host smart-5d5d3411-38dd-4c6b-a3b0-ba3906674153
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839344708 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_alert_test.3839344708
Directory /workspace/14.hmac_alert_test/latest

Test location /workspace/coverage/default/14.hmac_back_pressure.1467607920
Short name T350
Test name
Test status
Simulation time 438153177 ps
CPU time 4.06 seconds
Started Jul 02 09:43:02 AM PDT 24
Finished Jul 02 09:43:07 AM PDT 24
Peak memory 200308 kb
Host smart-9751ef77-601f-42dd-a246-32edbc6b24c1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1467607920 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_back_pressure.1467607920
Directory /workspace/14.hmac_back_pressure/latest

Test location /workspace/coverage/default/14.hmac_burst_wr.753046166
Short name T4
Test name
Test status
Simulation time 15739084770 ps
CPU time 62.28 seconds
Started Jul 02 09:42:55 AM PDT 24
Finished Jul 02 09:43:59 AM PDT 24
Peak memory 208808 kb
Host smart-8176bafe-5021-4112-a2fe-669f52f39afd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753046166 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_burst_wr.753046166
Directory /workspace/14.hmac_burst_wr/latest

Test location /workspace/coverage/default/14.hmac_datapath_stress.3691769750
Short name T257
Test name
Test status
Simulation time 34042926717 ps
CPU time 334.68 seconds
Started Jul 02 09:43:00 AM PDT 24
Finished Jul 02 09:48:35 AM PDT 24
Peak memory 645860 kb
Host smart-7388ce44-ed04-4dec-a2de-08c8e7594c6d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3691769750 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_datapath_stress.3691769750
Directory /workspace/14.hmac_datapath_stress/latest

Test location /workspace/coverage/default/14.hmac_error.2337407262
Short name T299
Test name
Test status
Simulation time 7262854077 ps
CPU time 129.94 seconds
Started Jul 02 09:42:59 AM PDT 24
Finished Jul 02 09:45:10 AM PDT 24
Peak memory 200440 kb
Host smart-ca4c15f7-c500-471b-b020-b8462104a23c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337407262 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_error.2337407262
Directory /workspace/14.hmac_error/latest

Test location /workspace/coverage/default/14.hmac_long_msg.4027799270
Short name T98
Test name
Test status
Simulation time 3710250648 ps
CPU time 51.15 seconds
Started Jul 02 09:42:54 AM PDT 24
Finished Jul 02 09:43:47 AM PDT 24
Peak memory 200420 kb
Host smart-00e249b9-15de-413b-b64d-236e24e85e43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4027799270 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_long_msg.4027799270
Directory /workspace/14.hmac_long_msg/latest

Test location /workspace/coverage/default/14.hmac_smoke.3284581726
Short name T246
Test name
Test status
Simulation time 3147007082 ps
CPU time 8.28 seconds
Started Jul 02 09:42:55 AM PDT 24
Finished Jul 02 09:43:04 AM PDT 24
Peak memory 200388 kb
Host smart-a13d5500-8a84-4d6d-8e5a-18eb4ba364ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284581726 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_smoke.3284581726
Directory /workspace/14.hmac_smoke/latest

Test location /workspace/coverage/default/14.hmac_stress_all.497397096
Short name T433
Test name
Test status
Simulation time 35564984212 ps
CPU time 159.72 seconds
Started Jul 02 09:42:57 AM PDT 24
Finished Jul 02 09:45:37 AM PDT 24
Peak memory 200528 kb
Host smart-d0484716-b885-4e4a-acbc-6c4e719b1b18
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497397096 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 14.hmac_stress_all.497397096
Directory /workspace/14.hmac_stress_all/latest

Test location /workspace/coverage/default/14.hmac_wipe_secret.4181979621
Short name T307
Test name
Test status
Simulation time 18338278902 ps
CPU time 56.78 seconds
Started Jul 02 09:42:52 AM PDT 24
Finished Jul 02 09:43:50 AM PDT 24
Peak memory 200444 kb
Host smart-dbfa1ca4-d9dd-46bf-b0fa-4fcc1fec9c4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181979621 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_wipe_secret.4181979621
Directory /workspace/14.hmac_wipe_secret/latest

Test location /workspace/coverage/default/15.hmac_alert_test.125443151
Short name T391
Test name
Test status
Simulation time 15996786 ps
CPU time 0.58 seconds
Started Jul 02 09:42:53 AM PDT 24
Finished Jul 02 09:42:55 AM PDT 24
Peak memory 195844 kb
Host smart-5c08ec20-8cad-448b-9c09-f2da8244f16e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125443151 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_alert_test.125443151
Directory /workspace/15.hmac_alert_test/latest

Test location /workspace/coverage/default/15.hmac_back_pressure.3982784180
Short name T21
Test name
Test status
Simulation time 8093073287 ps
CPU time 98.2 seconds
Started Jul 02 09:42:53 AM PDT 24
Finished Jul 02 09:44:32 AM PDT 24
Peak memory 200492 kb
Host smart-694e5997-68d0-430a-8ec7-d74ddac4b46a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3982784180 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_back_pressure.3982784180
Directory /workspace/15.hmac_back_pressure/latest

Test location /workspace/coverage/default/15.hmac_burst_wr.3003843035
Short name T372
Test name
Test status
Simulation time 1300697056 ps
CPU time 68.64 seconds
Started Jul 02 09:42:52 AM PDT 24
Finished Jul 02 09:44:02 AM PDT 24
Peak memory 200440 kb
Host smart-eb088fca-00a0-416a-89d9-e2e90341eafe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003843035 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_burst_wr.3003843035
Directory /workspace/15.hmac_burst_wr/latest

Test location /workspace/coverage/default/15.hmac_datapath_stress.2306873078
Short name T203
Test name
Test status
Simulation time 5445650926 ps
CPU time 335.69 seconds
Started Jul 02 09:42:58 AM PDT 24
Finished Jul 02 09:48:34 AM PDT 24
Peak memory 638128 kb
Host smart-de8a7c11-21b9-470a-979c-eaa05386d932
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2306873078 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_datapath_stress.2306873078
Directory /workspace/15.hmac_datapath_stress/latest

Test location /workspace/coverage/default/15.hmac_error.3776301578
Short name T138
Test name
Test status
Simulation time 29082004292 ps
CPU time 100.22 seconds
Started Jul 02 09:42:59 AM PDT 24
Finished Jul 02 09:44:40 AM PDT 24
Peak memory 200420 kb
Host smart-65c62675-70c8-42a1-b83c-14898a586f9b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776301578 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_error.3776301578
Directory /workspace/15.hmac_error/latest

Test location /workspace/coverage/default/15.hmac_long_msg.3555807001
Short name T33
Test name
Test status
Simulation time 19018291983 ps
CPU time 123.33 seconds
Started Jul 02 09:42:54 AM PDT 24
Finished Jul 02 09:44:59 AM PDT 24
Peak memory 200772 kb
Host smart-bf2a0dee-1e40-4f44-adba-88acb96891d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555807001 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_long_msg.3555807001
Directory /workspace/15.hmac_long_msg/latest

Test location /workspace/coverage/default/15.hmac_smoke.1940066551
Short name T379
Test name
Test status
Simulation time 1335467488 ps
CPU time 5.75 seconds
Started Jul 02 09:43:01 AM PDT 24
Finished Jul 02 09:43:08 AM PDT 24
Peak memory 200356 kb
Host smart-28700b16-e92e-4674-b974-a90e41d30b71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940066551 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_smoke.1940066551
Directory /workspace/15.hmac_smoke/latest

Test location /workspace/coverage/default/15.hmac_stress_all.3267265703
Short name T471
Test name
Test status
Simulation time 64232143610 ps
CPU time 1501.37 seconds
Started Jul 02 09:42:55 AM PDT 24
Finished Jul 02 10:07:58 AM PDT 24
Peak memory 700796 kb
Host smart-fc8b103a-1ede-4658-83f9-e6c1fc63d346
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267265703 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.hmac_stress_all.3267265703
Directory /workspace/15.hmac_stress_all/latest

Test location /workspace/coverage/default/15.hmac_wipe_secret.4018338011
Short name T308
Test name
Test status
Simulation time 10925245225 ps
CPU time 88.64 seconds
Started Jul 02 09:42:53 AM PDT 24
Finished Jul 02 09:44:23 AM PDT 24
Peak memory 200400 kb
Host smart-e718dd12-ca78-428b-a6b0-a7f5a4f0d7d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018338011 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_wipe_secret.4018338011
Directory /workspace/15.hmac_wipe_secret/latest

Test location /workspace/coverage/default/16.hmac_alert_test.2394678534
Short name T297
Test name
Test status
Simulation time 40398118 ps
CPU time 0.57 seconds
Started Jul 02 09:42:58 AM PDT 24
Finished Jul 02 09:43:00 AM PDT 24
Peak memory 195096 kb
Host smart-df0dd603-6016-453b-b045-4c7caedf15f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394678534 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_alert_test.2394678534
Directory /workspace/16.hmac_alert_test/latest

Test location /workspace/coverage/default/16.hmac_back_pressure.2903736005
Short name T16
Test name
Test status
Simulation time 1156374866 ps
CPU time 68.06 seconds
Started Jul 02 09:42:56 AM PDT 24
Finished Jul 02 09:44:05 AM PDT 24
Peak memory 200600 kb
Host smart-32c5771d-e6a9-410c-b060-e4d00aad4fb4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2903736005 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_back_pressure.2903736005
Directory /workspace/16.hmac_back_pressure/latest

Test location /workspace/coverage/default/16.hmac_burst_wr.2450327064
Short name T313
Test name
Test status
Simulation time 7060585754 ps
CPU time 31.9 seconds
Started Jul 02 09:42:57 AM PDT 24
Finished Jul 02 09:43:30 AM PDT 24
Peak memory 200708 kb
Host smart-7d1c33ca-650c-493a-bc58-d09142e76ca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450327064 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_burst_wr.2450327064
Directory /workspace/16.hmac_burst_wr/latest

Test location /workspace/coverage/default/16.hmac_datapath_stress.2980671397
Short name T325
Test name
Test status
Simulation time 35121149771 ps
CPU time 1328.6 seconds
Started Jul 02 09:42:57 AM PDT 24
Finished Jul 02 10:05:07 AM PDT 24
Peak memory 792224 kb
Host smart-b633cd38-dc5f-4864-9e27-e519ebb789b8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2980671397 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_datapath_stress.2980671397
Directory /workspace/16.hmac_datapath_stress/latest

Test location /workspace/coverage/default/16.hmac_error.177756831
Short name T247
Test name
Test status
Simulation time 3411445322 ps
CPU time 61.95 seconds
Started Jul 02 09:42:58 AM PDT 24
Finished Jul 02 09:44:01 AM PDT 24
Peak memory 200332 kb
Host smart-62a8fef7-6a97-46ec-a55a-3bd967bb1ff1
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177756831 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_error.177756831
Directory /workspace/16.hmac_error/latest

Test location /workspace/coverage/default/16.hmac_long_msg.1828514847
Short name T261
Test name
Test status
Simulation time 7041208816 ps
CPU time 23.7 seconds
Started Jul 02 09:42:54 AM PDT 24
Finished Jul 02 09:43:18 AM PDT 24
Peak memory 200416 kb
Host smart-ae0c3cd2-6c73-4863-89a3-47da4c716cd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828514847 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_long_msg.1828514847
Directory /workspace/16.hmac_long_msg/latest

Test location /workspace/coverage/default/16.hmac_smoke.2253421598
Short name T469
Test name
Test status
Simulation time 892313765 ps
CPU time 6.6 seconds
Started Jul 02 09:43:02 AM PDT 24
Finished Jul 02 09:43:10 AM PDT 24
Peak memory 200356 kb
Host smart-914618d1-c294-465f-aaaf-a7b58191a98e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253421598 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_smoke.2253421598
Directory /workspace/16.hmac_smoke/latest

Test location /workspace/coverage/default/16.hmac_stress_all.3935102533
Short name T277
Test name
Test status
Simulation time 10488935726 ps
CPU time 361.45 seconds
Started Jul 02 09:42:58 AM PDT 24
Finished Jul 02 09:49:00 AM PDT 24
Peak memory 613860 kb
Host smart-d71604f3-4301-48c7-a95f-5f745cf94ad4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935102533 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.hmac_stress_all.3935102533
Directory /workspace/16.hmac_stress_all/latest

Test location /workspace/coverage/default/16.hmac_wipe_secret.2853541038
Short name T124
Test name
Test status
Simulation time 603372899 ps
CPU time 25.63 seconds
Started Jul 02 09:42:58 AM PDT 24
Finished Jul 02 09:43:25 AM PDT 24
Peak memory 200440 kb
Host smart-f56ff9a0-5c39-4eec-8e9a-db668a06fe74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853541038 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_wipe_secret.2853541038
Directory /workspace/16.hmac_wipe_secret/latest

Test location /workspace/coverage/default/17.hmac_back_pressure.2108022037
Short name T155
Test name
Test status
Simulation time 769072100 ps
CPU time 46.06 seconds
Started Jul 02 09:43:06 AM PDT 24
Finished Jul 02 09:43:54 AM PDT 24
Peak memory 200372 kb
Host smart-726b1af5-98ba-4894-9808-349a0e6b4574
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2108022037 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_back_pressure.2108022037
Directory /workspace/17.hmac_back_pressure/latest

Test location /workspace/coverage/default/17.hmac_burst_wr.4281823858
Short name T374
Test name
Test status
Simulation time 947875011 ps
CPU time 27.07 seconds
Started Jul 02 09:42:56 AM PDT 24
Finished Jul 02 09:43:24 AM PDT 24
Peak memory 200360 kb
Host smart-eed36964-9afa-42af-9c99-eb3de3a351ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281823858 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_burst_wr.4281823858
Directory /workspace/17.hmac_burst_wr/latest

Test location /workspace/coverage/default/17.hmac_datapath_stress.3030948759
Short name T31
Test name
Test status
Simulation time 30775756592 ps
CPU time 436.61 seconds
Started Jul 02 09:42:58 AM PDT 24
Finished Jul 02 09:50:16 AM PDT 24
Peak memory 692296 kb
Host smart-d7a0fa15-0b69-450a-ac59-a676031bdbd6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3030948759 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_datapath_stress.3030948759
Directory /workspace/17.hmac_datapath_stress/latest

Test location /workspace/coverage/default/17.hmac_error.144887975
Short name T305
Test name
Test status
Simulation time 3475391010 ps
CPU time 33.81 seconds
Started Jul 02 09:42:58 AM PDT 24
Finished Jul 02 09:43:32 AM PDT 24
Peak memory 200344 kb
Host smart-4cfe75b4-1193-479c-a3e6-1c86b6ed0198
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144887975 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_error.144887975
Directory /workspace/17.hmac_error/latest

Test location /workspace/coverage/default/17.hmac_long_msg.166773660
Short name T475
Test name
Test status
Simulation time 6945621627 ps
CPU time 41.51 seconds
Started Jul 02 09:42:58 AM PDT 24
Finished Jul 02 09:43:40 AM PDT 24
Peak memory 200424 kb
Host smart-94f4b32b-7ce4-4700-bb13-efac27d5b09d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166773660 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_long_msg.166773660
Directory /workspace/17.hmac_long_msg/latest

Test location /workspace/coverage/default/17.hmac_smoke.4032916546
Short name T37
Test name
Test status
Simulation time 1763694928 ps
CPU time 10.69 seconds
Started Jul 02 09:43:05 AM PDT 24
Finished Jul 02 09:43:18 AM PDT 24
Peak memory 200356 kb
Host smart-16aee6be-085b-45cc-ae6d-51aca9c2be0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032916546 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_smoke.4032916546
Directory /workspace/17.hmac_smoke/latest

Test location /workspace/coverage/default/17.hmac_stress_all.2824751840
Short name T39
Test name
Test status
Simulation time 54659208498 ps
CPU time 951.05 seconds
Started Jul 02 09:42:59 AM PDT 24
Finished Jul 02 09:58:51 AM PDT 24
Peak memory 618400 kb
Host smart-003f0b87-a15c-41df-bbf3-0faf95eefa87
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824751840 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.hmac_stress_all.2824751840
Directory /workspace/17.hmac_stress_all/latest

Test location /workspace/coverage/default/17.hmac_wipe_secret.3630467130
Short name T359
Test name
Test status
Simulation time 655015375 ps
CPU time 6.27 seconds
Started Jul 02 09:42:58 AM PDT 24
Finished Jul 02 09:43:06 AM PDT 24
Peak memory 200348 kb
Host smart-66067a3a-c41d-45b6-b144-2b2441a2c829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630467130 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_wipe_secret.3630467130
Directory /workspace/17.hmac_wipe_secret/latest

Test location /workspace/coverage/default/18.hmac_alert_test.1818370617
Short name T159
Test name
Test status
Simulation time 24565397 ps
CPU time 0.62 seconds
Started Jul 02 09:43:02 AM PDT 24
Finished Jul 02 09:43:04 AM PDT 24
Peak memory 195864 kb
Host smart-3fbefbb9-54f2-40a9-bf5a-7870c1e9b077
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818370617 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_alert_test.1818370617
Directory /workspace/18.hmac_alert_test/latest

Test location /workspace/coverage/default/18.hmac_back_pressure.2056707334
Short name T248
Test name
Test status
Simulation time 1751284527 ps
CPU time 25.73 seconds
Started Jul 02 09:42:58 AM PDT 24
Finished Jul 02 09:43:25 AM PDT 24
Peak memory 200420 kb
Host smart-9f6ba069-3668-44a5-a87b-5e0def337935
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2056707334 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_back_pressure.2056707334
Directory /workspace/18.hmac_back_pressure/latest

Test location /workspace/coverage/default/18.hmac_burst_wr.1825582512
Short name T526
Test name
Test status
Simulation time 3889966357 ps
CPU time 14.62 seconds
Started Jul 02 09:42:59 AM PDT 24
Finished Jul 02 09:43:14 AM PDT 24
Peak memory 200432 kb
Host smart-ba12d3a7-038b-4652-9ccf-6e915444b5fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825582512 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_burst_wr.1825582512
Directory /workspace/18.hmac_burst_wr/latest

Test location /workspace/coverage/default/18.hmac_datapath_stress.3998650050
Short name T239
Test name
Test status
Simulation time 13200363411 ps
CPU time 1322.66 seconds
Started Jul 02 09:42:57 AM PDT 24
Finished Jul 02 10:05:01 AM PDT 24
Peak memory 772216 kb
Host smart-c6c29cee-531b-4af6-a91e-f0f0affd450f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3998650050 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_datapath_stress.3998650050
Directory /workspace/18.hmac_datapath_stress/latest

Test location /workspace/coverage/default/18.hmac_error.1824448665
Short name T316
Test name
Test status
Simulation time 22590947020 ps
CPU time 75.56 seconds
Started Jul 02 09:42:57 AM PDT 24
Finished Jul 02 09:44:14 AM PDT 24
Peak memory 200364 kb
Host smart-8fb750cb-83c7-4a66-b6cc-0a1e6f9a2813
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824448665 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_error.1824448665
Directory /workspace/18.hmac_error/latest

Test location /workspace/coverage/default/18.hmac_long_msg.1636489937
Short name T466
Test name
Test status
Simulation time 21853096008 ps
CPU time 141.05 seconds
Started Jul 02 09:43:03 AM PDT 24
Finished Jul 02 09:45:25 AM PDT 24
Peak memory 208632 kb
Host smart-919a792c-d7d5-4c3a-8730-286e491bf446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1636489937 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_long_msg.1636489937
Directory /workspace/18.hmac_long_msg/latest

Test location /workspace/coverage/default/18.hmac_smoke.602245251
Short name T126
Test name
Test status
Simulation time 402038068 ps
CPU time 5.52 seconds
Started Jul 02 09:42:58 AM PDT 24
Finished Jul 02 09:43:04 AM PDT 24
Peak memory 200356 kb
Host smart-7e6e0e4a-8bd1-4b64-bf87-021d8dc5887e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602245251 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_smoke.602245251
Directory /workspace/18.hmac_smoke/latest

Test location /workspace/coverage/default/18.hmac_stress_all.1086388132
Short name T423
Test name
Test status
Simulation time 45137118020 ps
CPU time 138.91 seconds
Started Jul 02 09:42:58 AM PDT 24
Finished Jul 02 09:45:18 AM PDT 24
Peak memory 200440 kb
Host smart-0a736735-0588-4a42-814d-e518cc12316e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086388132 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.hmac_stress_all.1086388132
Directory /workspace/18.hmac_stress_all/latest

Test location /workspace/coverage/default/18.hmac_wipe_secret.3746691147
Short name T47
Test name
Test status
Simulation time 2935640833 ps
CPU time 80.21 seconds
Started Jul 02 09:42:57 AM PDT 24
Finished Jul 02 09:44:18 AM PDT 24
Peak memory 200456 kb
Host smart-e5fd4558-94c1-4ff0-a60f-f6c274058cf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746691147 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_wipe_secret.3746691147
Directory /workspace/18.hmac_wipe_secret/latest

Test location /workspace/coverage/default/19.hmac_alert_test.918028417
Short name T179
Test name
Test status
Simulation time 13302294 ps
CPU time 0.57 seconds
Started Jul 02 09:43:01 AM PDT 24
Finished Jul 02 09:43:02 AM PDT 24
Peak memory 195096 kb
Host smart-a594949b-1dcd-4324-9128-2599f098daf2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918028417 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_alert_test.918028417
Directory /workspace/19.hmac_alert_test/latest

Test location /workspace/coverage/default/19.hmac_back_pressure.2445814143
Short name T306
Test name
Test status
Simulation time 897275635 ps
CPU time 51.06 seconds
Started Jul 02 09:43:02 AM PDT 24
Finished Jul 02 09:43:54 AM PDT 24
Peak memory 200368 kb
Host smart-01b91fd4-2fa0-49d1-8c70-a9bc33d196f9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2445814143 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_back_pressure.2445814143
Directory /workspace/19.hmac_back_pressure/latest

Test location /workspace/coverage/default/19.hmac_burst_wr.718611536
Short name T421
Test name
Test status
Simulation time 36189088532 ps
CPU time 36.51 seconds
Started Jul 02 09:43:01 AM PDT 24
Finished Jul 02 09:43:38 AM PDT 24
Peak memory 200496 kb
Host smart-4c19b6b1-7308-4b59-ad1a-014e45150070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718611536 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_burst_wr.718611536
Directory /workspace/19.hmac_burst_wr/latest

Test location /workspace/coverage/default/19.hmac_datapath_stress.2360212851
Short name T395
Test name
Test status
Simulation time 5931613360 ps
CPU time 302.82 seconds
Started Jul 02 09:43:06 AM PDT 24
Finished Jul 02 09:48:11 AM PDT 24
Peak memory 660084 kb
Host smart-fe332222-0da1-4db9-94ca-bc3989bd9e9d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2360212851 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_datapath_stress.2360212851
Directory /workspace/19.hmac_datapath_stress/latest

Test location /workspace/coverage/default/19.hmac_error.1157123401
Short name T259
Test name
Test status
Simulation time 1478334465 ps
CPU time 18.68 seconds
Started Jul 02 09:43:09 AM PDT 24
Finished Jul 02 09:43:30 AM PDT 24
Peak memory 200352 kb
Host smart-fa5ef73b-d1f1-4b11-8e90-6f26241bcdc7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157123401 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_error.1157123401
Directory /workspace/19.hmac_error/latest

Test location /workspace/coverage/default/19.hmac_long_msg.3296806632
Short name T292
Test name
Test status
Simulation time 20129877572 ps
CPU time 186.84 seconds
Started Jul 02 09:43:02 AM PDT 24
Finished Jul 02 09:46:09 AM PDT 24
Peak memory 200504 kb
Host smart-b5b63ac9-5cc8-460e-93f0-575598cc02e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296806632 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_long_msg.3296806632
Directory /workspace/19.hmac_long_msg/latest

Test location /workspace/coverage/default/19.hmac_smoke.2805790708
Short name T219
Test name
Test status
Simulation time 633280294 ps
CPU time 10.81 seconds
Started Jul 02 09:43:01 AM PDT 24
Finished Jul 02 09:43:13 AM PDT 24
Peak memory 200376 kb
Host smart-e00e439a-ee6b-430b-ba44-fac8c5250de2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805790708 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_smoke.2805790708
Directory /workspace/19.hmac_smoke/latest

Test location /workspace/coverage/default/19.hmac_stress_all.1946212030
Short name T226
Test name
Test status
Simulation time 37126974126 ps
CPU time 959.31 seconds
Started Jul 02 09:43:02 AM PDT 24
Finished Jul 02 09:59:02 AM PDT 24
Peak memory 675948 kb
Host smart-4b3c8d46-0861-4c95-ad37-ad889f4e3a80
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946212030 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.hmac_stress_all.1946212030
Directory /workspace/19.hmac_stress_all/latest

Test location /workspace/coverage/default/19.hmac_wipe_secret.643279930
Short name T293
Test name
Test status
Simulation time 4967362610 ps
CPU time 62.9 seconds
Started Jul 02 09:43:04 AM PDT 24
Finished Jul 02 09:44:07 AM PDT 24
Peak memory 200612 kb
Host smart-007078fd-7a25-479e-b645-3077748363d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643279930 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_wipe_secret.643279930
Directory /workspace/19.hmac_wipe_secret/latest

Test location /workspace/coverage/default/2.hmac_alert_test.3328853598
Short name T461
Test name
Test status
Simulation time 65191896 ps
CPU time 0.59 seconds
Started Jul 02 09:42:31 AM PDT 24
Finished Jul 02 09:42:32 AM PDT 24
Peak memory 196204 kb
Host smart-1df8603b-8c60-4be1-b04f-c06e9adef5d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328853598 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_alert_test.3328853598
Directory /workspace/2.hmac_alert_test/latest

Test location /workspace/coverage/default/2.hmac_back_pressure.1823833604
Short name T26
Test name
Test status
Simulation time 1495043810 ps
CPU time 86.84 seconds
Started Jul 02 09:42:29 AM PDT 24
Finished Jul 02 09:43:57 AM PDT 24
Peak memory 200420 kb
Host smart-bde12c85-0324-49b1-8843-4484a50558ee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1823833604 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_back_pressure.1823833604
Directory /workspace/2.hmac_back_pressure/latest

Test location /workspace/coverage/default/2.hmac_burst_wr.100836063
Short name T145
Test name
Test status
Simulation time 2896945574 ps
CPU time 38.26 seconds
Started Jul 02 09:42:29 AM PDT 24
Finished Jul 02 09:43:08 AM PDT 24
Peak memory 200504 kb
Host smart-1466644a-9d8d-4cdc-8368-efcd813290cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100836063 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_burst_wr.100836063
Directory /workspace/2.hmac_burst_wr/latest

Test location /workspace/coverage/default/2.hmac_datapath_stress.3368791616
Short name T278
Test name
Test status
Simulation time 56385512101 ps
CPU time 1048.87 seconds
Started Jul 02 09:42:31 AM PDT 24
Finished Jul 02 10:00:02 AM PDT 24
Peak memory 754776 kb
Host smart-c6ab834b-d903-48d3-b55d-8ab39f9419b6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3368791616 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_datapath_stress.3368791616
Directory /workspace/2.hmac_datapath_stress/latest

Test location /workspace/coverage/default/2.hmac_error.2221072512
Short name T298
Test name
Test status
Simulation time 17891488279 ps
CPU time 109.58 seconds
Started Jul 02 09:42:34 AM PDT 24
Finished Jul 02 09:44:25 AM PDT 24
Peak memory 200400 kb
Host smart-6bee2ce4-9159-4051-9914-a4089bdda9b3
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221072512 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_error.2221072512
Directory /workspace/2.hmac_error/latest

Test location /workspace/coverage/default/2.hmac_smoke.1513840981
Short name T232
Test name
Test status
Simulation time 1896925459 ps
CPU time 8.86 seconds
Started Jul 02 09:42:29 AM PDT 24
Finished Jul 02 09:42:39 AM PDT 24
Peak memory 200348 kb
Host smart-bee42d45-b47e-4806-a9f5-24edecd826ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513840981 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_smoke.1513840981
Directory /workspace/2.hmac_smoke/latest

Test location /workspace/coverage/default/2.hmac_stress_all.2187916437
Short name T416
Test name
Test status
Simulation time 5847956635 ps
CPU time 296.59 seconds
Started Jul 02 09:42:30 AM PDT 24
Finished Jul 02 09:47:28 AM PDT 24
Peak memory 200432 kb
Host smart-cbdf0290-b9b9-4dbf-87a3-25fdfb68113f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187916437 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all.2187916437
Directory /workspace/2.hmac_stress_all/latest

Test location /workspace/coverage/default/2.hmac_test_hmac256_vectors.2989006783
Short name T172
Test name
Test status
Simulation time 7701981149 ps
CPU time 73.94 seconds
Started Jul 02 09:42:32 AM PDT 24
Finished Jul 02 09:43:47 AM PDT 24
Peak memory 200404 kb
Host smart-672e7feb-ff11-4d3c-9ba2-8687f754d4d9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2989006783 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac256_vectors.2989006783
Directory /workspace/2.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_hmac384_vectors.1952379058
Short name T154
Test name
Test status
Simulation time 7840644960 ps
CPU time 57.04 seconds
Started Jul 02 09:42:33 AM PDT 24
Finished Jul 02 09:43:31 AM PDT 24
Peak memory 200660 kb
Host smart-43c431c3-2a1a-4d43-b3a0-eaeaf7435260
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1952379058 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac384_vectors.1952379058
Directory /workspace/2.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_hmac512_vectors.3283596610
Short name T437
Test name
Test status
Simulation time 10082643652 ps
CPU time 129.33 seconds
Started Jul 02 09:42:38 AM PDT 24
Finished Jul 02 09:44:48 AM PDT 24
Peak memory 200448 kb
Host smart-33208ded-28cd-48d2-9763-271faf03a273
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3283596610 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac512_vectors.3283596610
Directory /workspace/2.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha256_vectors.1987987631
Short name T223
Test name
Test status
Simulation time 82729886095 ps
CPU time 588.87 seconds
Started Jul 02 09:42:32 AM PDT 24
Finished Jul 02 09:52:22 AM PDT 24
Peak memory 200340 kb
Host smart-ba318655-70ed-41d9-8d49-9681b1bc97ff
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1987987631 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha256_vectors.1987987631
Directory /workspace/2.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha384_vectors.1364498221
Short name T252
Test name
Test status
Simulation time 151464285827 ps
CPU time 2125.51 seconds
Started Jul 02 09:42:34 AM PDT 24
Finished Jul 02 10:18:01 AM PDT 24
Peak memory 215864 kb
Host smart-3c28f8cb-038d-401c-bfcd-24992f9b775e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1364498221 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha384_vectors.1364498221
Directory /workspace/2.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha512_vectors.2904137645
Short name T231
Test name
Test status
Simulation time 537037813392 ps
CPU time 2286.85 seconds
Started Jul 02 09:42:35 AM PDT 24
Finished Jul 02 10:20:43 AM PDT 24
Peak memory 216064 kb
Host smart-46fd559a-fa0c-42d4-81a8-15c5ed94c916
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_200_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2904137645 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha512_vectors.2904137645
Directory /workspace/2.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/2.hmac_wipe_secret.1615191371
Short name T86
Test name
Test status
Simulation time 17648994472 ps
CPU time 47.87 seconds
Started Jul 02 09:42:35 AM PDT 24
Finished Jul 02 09:43:23 AM PDT 24
Peak memory 200484 kb
Host smart-89f4a273-c51a-456c-a8aa-d105849df26f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615191371 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_wipe_secret.1615191371
Directory /workspace/2.hmac_wipe_secret/latest

Test location /workspace/coverage/default/20.hmac_alert_test.1591495747
Short name T214
Test name
Test status
Simulation time 50433753 ps
CPU time 0.6 seconds
Started Jul 02 09:43:07 AM PDT 24
Finished Jul 02 09:43:10 AM PDT 24
Peak memory 196196 kb
Host smart-0a1cc296-5390-4fc3-9ea2-29c8f306ba11
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591495747 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_alert_test.1591495747
Directory /workspace/20.hmac_alert_test/latest

Test location /workspace/coverage/default/20.hmac_back_pressure.1725673046
Short name T188
Test name
Test status
Simulation time 1677266378 ps
CPU time 99.75 seconds
Started Jul 02 09:43:05 AM PDT 24
Finished Jul 02 09:44:46 AM PDT 24
Peak memory 200352 kb
Host smart-3e71f89c-731e-46bd-889a-eb4411e7f151
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1725673046 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_back_pressure.1725673046
Directory /workspace/20.hmac_back_pressure/latest

Test location /workspace/coverage/default/20.hmac_burst_wr.2899415079
Short name T296
Test name
Test status
Simulation time 13860040198 ps
CPU time 49.56 seconds
Started Jul 02 09:43:05 AM PDT 24
Finished Jul 02 09:43:56 AM PDT 24
Peak memory 200368 kb
Host smart-c690e9c3-4719-44a0-8a10-1f26508b1e92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899415079 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_burst_wr.2899415079
Directory /workspace/20.hmac_burst_wr/latest

Test location /workspace/coverage/default/20.hmac_datapath_stress.736929161
Short name T156
Test name
Test status
Simulation time 10672541452 ps
CPU time 582.97 seconds
Started Jul 02 09:43:03 AM PDT 24
Finished Jul 02 09:52:46 AM PDT 24
Peak memory 643224 kb
Host smart-62c0e017-2542-4776-8c72-a46add15440b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=736929161 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_datapath_stress.736929161
Directory /workspace/20.hmac_datapath_stress/latest

Test location /workspace/coverage/default/20.hmac_error.1181083293
Short name T160
Test name
Test status
Simulation time 4476283929 ps
CPU time 38.71 seconds
Started Jul 02 09:43:03 AM PDT 24
Finished Jul 02 09:43:42 AM PDT 24
Peak memory 200276 kb
Host smart-8c808315-3180-4df4-bf01-8cda39bf3252
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181083293 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_error.1181083293
Directory /workspace/20.hmac_error/latest

Test location /workspace/coverage/default/20.hmac_long_msg.2459680572
Short name T282
Test name
Test status
Simulation time 11239334886 ps
CPU time 207.14 seconds
Started Jul 02 09:43:06 AM PDT 24
Finished Jul 02 09:46:35 AM PDT 24
Peak memory 216660 kb
Host smart-53e0efd5-6984-412d-9704-cae5b6f4dc4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459680572 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_long_msg.2459680572
Directory /workspace/20.hmac_long_msg/latest

Test location /workspace/coverage/default/20.hmac_smoke.4119355900
Short name T6
Test name
Test status
Simulation time 850667859 ps
CPU time 6.01 seconds
Started Jul 02 09:43:01 AM PDT 24
Finished Jul 02 09:43:08 AM PDT 24
Peak memory 200416 kb
Host smart-633607a6-a6d6-439e-ad85-632ab8fd9dde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119355900 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_smoke.4119355900
Directory /workspace/20.hmac_smoke/latest

Test location /workspace/coverage/default/20.hmac_wipe_secret.2318795123
Short name T45
Test name
Test status
Simulation time 342691420 ps
CPU time 15.54 seconds
Started Jul 02 09:43:08 AM PDT 24
Finished Jul 02 09:43:26 AM PDT 24
Peak memory 200372 kb
Host smart-f505bf76-4d7a-4513-aba0-9dd866c0d6e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318795123 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_wipe_secret.2318795123
Directory /workspace/20.hmac_wipe_secret/latest

Test location /workspace/coverage/default/21.hmac_alert_test.202846659
Short name T260
Test name
Test status
Simulation time 20304138 ps
CPU time 0.65 seconds
Started Jul 02 09:43:07 AM PDT 24
Finished Jul 02 09:43:10 AM PDT 24
Peak memory 196908 kb
Host smart-44bb3029-3dbc-438c-b5f0-142692fc8270
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202846659 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_alert_test.202846659
Directory /workspace/21.hmac_alert_test/latest

Test location /workspace/coverage/default/21.hmac_back_pressure.4265545911
Short name T388
Test name
Test status
Simulation time 363129775 ps
CPU time 19.9 seconds
Started Jul 02 09:43:01 AM PDT 24
Finished Jul 02 09:43:21 AM PDT 24
Peak memory 200412 kb
Host smart-4d2b2be0-2c96-4848-ab37-655bbcf8526a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4265545911 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_back_pressure.4265545911
Directory /workspace/21.hmac_back_pressure/latest

Test location /workspace/coverage/default/21.hmac_burst_wr.3775447021
Short name T302
Test name
Test status
Simulation time 679426950 ps
CPU time 32.51 seconds
Started Jul 02 09:43:02 AM PDT 24
Finished Jul 02 09:43:36 AM PDT 24
Peak memory 200292 kb
Host smart-6bbf7526-24f1-43dc-b063-52fe6c3ff246
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775447021 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_burst_wr.3775447021
Directory /workspace/21.hmac_burst_wr/latest

Test location /workspace/coverage/default/21.hmac_datapath_stress.1681348243
Short name T95
Test name
Test status
Simulation time 5874376065 ps
CPU time 465.58 seconds
Started Jul 02 09:43:08 AM PDT 24
Finished Jul 02 09:50:56 AM PDT 24
Peak memory 681584 kb
Host smart-d4b4d96b-4185-4818-b716-c79675494e5c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1681348243 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_datapath_stress.1681348243
Directory /workspace/21.hmac_datapath_stress/latest

Test location /workspace/coverage/default/21.hmac_error.3220823118
Short name T360
Test name
Test status
Simulation time 24868140294 ps
CPU time 80.79 seconds
Started Jul 02 09:43:05 AM PDT 24
Finished Jul 02 09:44:27 AM PDT 24
Peak memory 200192 kb
Host smart-277ebddc-04c4-4d47-8d7a-6b9736676666
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220823118 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_error.3220823118
Directory /workspace/21.hmac_error/latest

Test location /workspace/coverage/default/21.hmac_long_msg.2835144463
Short name T238
Test name
Test status
Simulation time 7006730100 ps
CPU time 118.92 seconds
Started Jul 02 09:43:04 AM PDT 24
Finished Jul 02 09:45:04 AM PDT 24
Peak memory 216728 kb
Host smart-208a19c3-4ab0-4559-bc2e-f80568023b0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835144463 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_long_msg.2835144463
Directory /workspace/21.hmac_long_msg/latest

Test location /workspace/coverage/default/21.hmac_smoke.1900121447
Short name T515
Test name
Test status
Simulation time 61590382 ps
CPU time 1.28 seconds
Started Jul 02 09:43:05 AM PDT 24
Finished Jul 02 09:43:07 AM PDT 24
Peak memory 199920 kb
Host smart-add05ee0-d3e5-40a7-91d8-826df143d83c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900121447 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_smoke.1900121447
Directory /workspace/21.hmac_smoke/latest

Test location /workspace/coverage/default/21.hmac_stress_all.2975515455
Short name T82
Test name
Test status
Simulation time 39578243597 ps
CPU time 455.02 seconds
Started Jul 02 09:43:02 AM PDT 24
Finished Jul 02 09:50:38 AM PDT 24
Peak memory 669208 kb
Host smart-f317d222-cc48-42ba-a869-95ce744f7b25
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975515455 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.hmac_stress_all.2975515455
Directory /workspace/21.hmac_stress_all/latest

Test location /workspace/coverage/default/21.hmac_wipe_secret.3427587239
Short name T253
Test name
Test status
Simulation time 30410118317 ps
CPU time 88.18 seconds
Started Jul 02 09:43:06 AM PDT 24
Finished Jul 02 09:44:36 AM PDT 24
Peak memory 200440 kb
Host smart-bf7d35a3-3692-4c47-b1a5-622632ccf6d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427587239 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_wipe_secret.3427587239
Directory /workspace/21.hmac_wipe_secret/latest

Test location /workspace/coverage/default/22.hmac_alert_test.2353596911
Short name T281
Test name
Test status
Simulation time 15612442 ps
CPU time 0.61 seconds
Started Jul 02 09:43:05 AM PDT 24
Finished Jul 02 09:43:07 AM PDT 24
Peak memory 196240 kb
Host smart-bcb38af9-a048-4806-bbaa-bdadf251f44a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353596911 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_alert_test.2353596911
Directory /workspace/22.hmac_alert_test/latest

Test location /workspace/coverage/default/22.hmac_back_pressure.3784701362
Short name T490
Test name
Test status
Simulation time 1077805433 ps
CPU time 10.86 seconds
Started Jul 02 09:43:09 AM PDT 24
Finished Jul 02 09:43:22 AM PDT 24
Peak memory 200376 kb
Host smart-78421d4e-a62c-4ef1-b503-1dc97c1c2454
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3784701362 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_back_pressure.3784701362
Directory /workspace/22.hmac_back_pressure/latest

Test location /workspace/coverage/default/22.hmac_burst_wr.47469273
Short name T189
Test name
Test status
Simulation time 3348995840 ps
CPU time 43.16 seconds
Started Jul 02 09:43:08 AM PDT 24
Finished Jul 02 09:43:54 AM PDT 24
Peak memory 200456 kb
Host smart-77dcddd0-a584-472a-98f5-47d10a461933
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47469273 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_burst_wr.47469273
Directory /workspace/22.hmac_burst_wr/latest

Test location /workspace/coverage/default/22.hmac_datapath_stress.675426106
Short name T48
Test name
Test status
Simulation time 17419689447 ps
CPU time 876.33 seconds
Started Jul 02 09:43:14 AM PDT 24
Finished Jul 02 09:57:51 AM PDT 24
Peak memory 723340 kb
Host smart-46bc8230-c826-4643-9269-d4391f1aabd7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=675426106 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_datapath_stress.675426106
Directory /workspace/22.hmac_datapath_stress/latest

Test location /workspace/coverage/default/22.hmac_error.2114025789
Short name T499
Test name
Test status
Simulation time 59068708 ps
CPU time 1.11 seconds
Started Jul 02 09:43:07 AM PDT 24
Finished Jul 02 09:43:10 AM PDT 24
Peak memory 200188 kb
Host smart-b50f897c-5352-4781-b118-13d72b2f8ea4
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114025789 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_error.2114025789
Directory /workspace/22.hmac_error/latest

Test location /workspace/coverage/default/22.hmac_long_msg.4136437599
Short name T268
Test name
Test status
Simulation time 13020745196 ps
CPU time 182.72 seconds
Started Jul 02 09:43:06 AM PDT 24
Finished Jul 02 09:46:10 AM PDT 24
Peak memory 200440 kb
Host smart-63b84f02-ce50-4001-a9c4-76abb7693576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136437599 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_long_msg.4136437599
Directory /workspace/22.hmac_long_msg/latest

Test location /workspace/coverage/default/22.hmac_smoke.3959418286
Short name T38
Test name
Test status
Simulation time 1902249759 ps
CPU time 6.82 seconds
Started Jul 02 09:43:08 AM PDT 24
Finished Jul 02 09:43:17 AM PDT 24
Peak memory 200356 kb
Host smart-def47081-df15-44a3-a7a4-1bfe42d823b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959418286 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_smoke.3959418286
Directory /workspace/22.hmac_smoke/latest

Test location /workspace/coverage/default/22.hmac_stress_all.400650806
Short name T191
Test name
Test status
Simulation time 23171805566 ps
CPU time 1306.24 seconds
Started Jul 02 09:43:08 AM PDT 24
Finished Jul 02 10:04:56 AM PDT 24
Peak memory 732216 kb
Host smart-6845eca6-4b65-4c0a-989f-9ff476d167dc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400650806 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 22.hmac_stress_all.400650806
Directory /workspace/22.hmac_stress_all/latest

Test location /workspace/coverage/default/22.hmac_wipe_secret.3211706988
Short name T489
Test name
Test status
Simulation time 1585737869 ps
CPU time 41.47 seconds
Started Jul 02 09:43:16 AM PDT 24
Finished Jul 02 09:43:58 AM PDT 24
Peak memory 200364 kb
Host smart-3ad611b7-b715-409e-953c-8c3969a5171a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211706988 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_wipe_secret.3211706988
Directory /workspace/22.hmac_wipe_secret/latest

Test location /workspace/coverage/default/23.hmac_alert_test.1926147429
Short name T343
Test name
Test status
Simulation time 45272934 ps
CPU time 0.59 seconds
Started Jul 02 09:43:10 AM PDT 24
Finished Jul 02 09:43:13 AM PDT 24
Peak memory 195148 kb
Host smart-4a880d20-9678-4018-a1af-40883c918a10
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926147429 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_alert_test.1926147429
Directory /workspace/23.hmac_alert_test/latest

Test location /workspace/coverage/default/23.hmac_back_pressure.3348289873
Short name T340
Test name
Test status
Simulation time 327911634 ps
CPU time 18.62 seconds
Started Jul 02 09:43:10 AM PDT 24
Finished Jul 02 09:43:31 AM PDT 24
Peak memory 200316 kb
Host smart-c30dd015-8ff9-4b1e-9936-26aa04bc6f0f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3348289873 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_back_pressure.3348289873
Directory /workspace/23.hmac_back_pressure/latest

Test location /workspace/coverage/default/23.hmac_burst_wr.1515231823
Short name T428
Test name
Test status
Simulation time 10009885133 ps
CPU time 42.42 seconds
Started Jul 02 09:43:07 AM PDT 24
Finished Jul 02 09:43:51 AM PDT 24
Peak memory 200420 kb
Host smart-70a56fb4-8ce3-4ccf-8dac-1a820139aa5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515231823 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_burst_wr.1515231823
Directory /workspace/23.hmac_burst_wr/latest

Test location /workspace/coverage/default/23.hmac_datapath_stress.4046302660
Short name T519
Test name
Test status
Simulation time 7966305570 ps
CPU time 634.3 seconds
Started Jul 02 09:43:08 AM PDT 24
Finished Jul 02 09:53:44 AM PDT 24
Peak memory 694576 kb
Host smart-15646da6-def1-4acd-a08f-c7e250ea5fe6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4046302660 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_datapath_stress.4046302660
Directory /workspace/23.hmac_datapath_stress/latest

Test location /workspace/coverage/default/23.hmac_error.1919117106
Short name T480
Test name
Test status
Simulation time 12971245456 ps
CPU time 81.31 seconds
Started Jul 02 09:43:09 AM PDT 24
Finished Jul 02 09:44:33 AM PDT 24
Peak memory 200416 kb
Host smart-1fe2f75b-09f1-497a-8270-f897fb0d1569
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919117106 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_error.1919117106
Directory /workspace/23.hmac_error/latest

Test location /workspace/coverage/default/23.hmac_long_msg.3545064746
Short name T335
Test name
Test status
Simulation time 7040056503 ps
CPU time 182.04 seconds
Started Jul 02 09:43:08 AM PDT 24
Finished Jul 02 09:46:12 AM PDT 24
Peak memory 200408 kb
Host smart-1c5f660e-dc52-4e59-9cfd-c89901967941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545064746 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_long_msg.3545064746
Directory /workspace/23.hmac_long_msg/latest

Test location /workspace/coverage/default/23.hmac_smoke.1851873889
Short name T342
Test name
Test status
Simulation time 405625641 ps
CPU time 9.6 seconds
Started Jul 02 09:43:08 AM PDT 24
Finished Jul 02 09:43:21 AM PDT 24
Peak memory 200380 kb
Host smart-33682ccb-231f-4e3e-ab1e-f9c978116e77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851873889 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_smoke.1851873889
Directory /workspace/23.hmac_smoke/latest

Test location /workspace/coverage/default/23.hmac_stress_all.3269897781
Short name T410
Test name
Test status
Simulation time 414831739 ps
CPU time 4.76 seconds
Started Jul 02 09:43:11 AM PDT 24
Finished Jul 02 09:43:17 AM PDT 24
Peak memory 200364 kb
Host smart-878e3396-5fee-41ed-8925-1fdbcea50632
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269897781 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.hmac_stress_all.3269897781
Directory /workspace/23.hmac_stress_all/latest

Test location /workspace/coverage/default/23.hmac_wipe_secret.3204539661
Short name T496
Test name
Test status
Simulation time 3169992596 ps
CPU time 66.69 seconds
Started Jul 02 09:43:08 AM PDT 24
Finished Jul 02 09:44:17 AM PDT 24
Peak memory 200412 kb
Host smart-1143835e-0f99-4e2a-ad34-9417da6b2e42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3204539661 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_wipe_secret.3204539661
Directory /workspace/23.hmac_wipe_secret/latest

Test location /workspace/coverage/default/24.hmac_alert_test.2985599876
Short name T152
Test name
Test status
Simulation time 41404094 ps
CPU time 0.58 seconds
Started Jul 02 09:43:09 AM PDT 24
Finished Jul 02 09:43:12 AM PDT 24
Peak memory 195156 kb
Host smart-17f9eb7b-feb8-47f3-a195-cc7983399417
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985599876 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_alert_test.2985599876
Directory /workspace/24.hmac_alert_test/latest

Test location /workspace/coverage/default/24.hmac_back_pressure.3828234476
Short name T270
Test name
Test status
Simulation time 592023400 ps
CPU time 4.39 seconds
Started Jul 02 09:43:10 AM PDT 24
Finished Jul 02 09:43:16 AM PDT 24
Peak memory 200380 kb
Host smart-d76e1586-9a45-4921-a6db-6ac8ddac1f9f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3828234476 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_back_pressure.3828234476
Directory /workspace/24.hmac_back_pressure/latest

Test location /workspace/coverage/default/24.hmac_burst_wr.3058361127
Short name T402
Test name
Test status
Simulation time 729380571 ps
CPU time 12.98 seconds
Started Jul 02 09:43:06 AM PDT 24
Finished Jul 02 09:43:22 AM PDT 24
Peak memory 200428 kb
Host smart-67498e2a-5de5-46b3-a9ab-827751dc52e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058361127 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_burst_wr.3058361127
Directory /workspace/24.hmac_burst_wr/latest

Test location /workspace/coverage/default/24.hmac_datapath_stress.3876265134
Short name T491
Test name
Test status
Simulation time 6053217537 ps
CPU time 1179 seconds
Started Jul 02 09:43:06 AM PDT 24
Finished Jul 02 10:02:47 AM PDT 24
Peak memory 691812 kb
Host smart-64813ae3-2cd0-4463-813c-d5aa9c5f9fd5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3876265134 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_datapath_stress.3876265134
Directory /workspace/24.hmac_datapath_stress/latest

Test location /workspace/coverage/default/24.hmac_error.693111286
Short name T375
Test name
Test status
Simulation time 12501293734 ps
CPU time 142.65 seconds
Started Jul 02 09:43:11 AM PDT 24
Finished Jul 02 09:45:35 AM PDT 24
Peak memory 200420 kb
Host smart-2a549a08-ff02-4853-9c3f-c3180b29e6b1
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693111286 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_error.693111286
Directory /workspace/24.hmac_error/latest

Test location /workspace/coverage/default/24.hmac_long_msg.3072847848
Short name T249
Test name
Test status
Simulation time 1479626343 ps
CPU time 14.01 seconds
Started Jul 02 09:43:08 AM PDT 24
Finished Jul 02 09:43:25 AM PDT 24
Peak memory 200392 kb
Host smart-cc89a4d2-7e6d-4efe-8b27-9aac51d0e06f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072847848 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_long_msg.3072847848
Directory /workspace/24.hmac_long_msg/latest

Test location /workspace/coverage/default/24.hmac_smoke.1669716204
Short name T442
Test name
Test status
Simulation time 583905149 ps
CPU time 2.4 seconds
Started Jul 02 09:43:10 AM PDT 24
Finished Jul 02 09:43:14 AM PDT 24
Peak memory 200372 kb
Host smart-b7d30457-8840-44d1-bf89-4f760bf201b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1669716204 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_smoke.1669716204
Directory /workspace/24.hmac_smoke/latest

Test location /workspace/coverage/default/24.hmac_stress_all.2764096694
Short name T84
Test name
Test status
Simulation time 258025432405 ps
CPU time 3252.47 seconds
Started Jul 02 09:43:10 AM PDT 24
Finished Jul 02 10:37:25 AM PDT 24
Peak memory 777120 kb
Host smart-ac8a5cb9-74c1-4155-bccb-bf8ba0b01e62
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764096694 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.hmac_stress_all.2764096694
Directory /workspace/24.hmac_stress_all/latest

Test location /workspace/coverage/default/24.hmac_wipe_secret.655735175
Short name T171
Test name
Test status
Simulation time 22937441559 ps
CPU time 26.62 seconds
Started Jul 02 09:43:09 AM PDT 24
Finished Jul 02 09:43:38 AM PDT 24
Peak memory 200416 kb
Host smart-0ef48979-4c5b-412c-bbf7-64e2f6c3d774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=655735175 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_wipe_secret.655735175
Directory /workspace/24.hmac_wipe_secret/latest

Test location /workspace/coverage/default/25.hmac_alert_test.1648700334
Short name T326
Test name
Test status
Simulation time 14139405 ps
CPU time 0.6 seconds
Started Jul 02 09:43:13 AM PDT 24
Finished Jul 02 09:43:14 AM PDT 24
Peak memory 196228 kb
Host smart-01de1cb1-8dd7-4b9d-9f65-807594d93abd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648700334 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_alert_test.1648700334
Directory /workspace/25.hmac_alert_test/latest

Test location /workspace/coverage/default/25.hmac_back_pressure.1781478263
Short name T414
Test name
Test status
Simulation time 1330615102 ps
CPU time 17.15 seconds
Started Jul 02 09:43:10 AM PDT 24
Finished Jul 02 09:43:29 AM PDT 24
Peak memory 200388 kb
Host smart-2faebbeb-aa14-46b3-a32b-03d9880e71b6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1781478263 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_back_pressure.1781478263
Directory /workspace/25.hmac_back_pressure/latest

Test location /workspace/coverage/default/25.hmac_burst_wr.3058988755
Short name T283
Test name
Test status
Simulation time 1270120625 ps
CPU time 13.42 seconds
Started Jul 02 09:43:11 AM PDT 24
Finished Jul 02 09:43:26 AM PDT 24
Peak memory 200376 kb
Host smart-12334cfa-acc6-4e36-8ac0-4a38ee96e749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058988755 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_burst_wr.3058988755
Directory /workspace/25.hmac_burst_wr/latest

Test location /workspace/coverage/default/25.hmac_datapath_stress.3849620831
Short name T43
Test name
Test status
Simulation time 4388152387 ps
CPU time 791.21 seconds
Started Jul 02 09:43:13 AM PDT 24
Finished Jul 02 09:56:25 AM PDT 24
Peak memory 692272 kb
Host smart-679a48c7-e6ab-4b56-ae1c-8c92a9ef2457
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3849620831 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_datapath_stress.3849620831
Directory /workspace/25.hmac_datapath_stress/latest

Test location /workspace/coverage/default/25.hmac_error.3992384653
Short name T241
Test name
Test status
Simulation time 697812443 ps
CPU time 38.29 seconds
Started Jul 02 09:43:12 AM PDT 24
Finished Jul 02 09:43:51 AM PDT 24
Peak memory 200312 kb
Host smart-0d49ffdb-0f82-42b1-955e-019d234263bd
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992384653 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_error.3992384653
Directory /workspace/25.hmac_error/latest

Test location /workspace/coverage/default/25.hmac_long_msg.3291338170
Short name T482
Test name
Test status
Simulation time 19392749850 ps
CPU time 169.68 seconds
Started Jul 02 09:43:08 AM PDT 24
Finished Jul 02 09:46:00 AM PDT 24
Peak memory 200412 kb
Host smart-a72286db-087d-4a48-99ca-0db2d9591e32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291338170 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_long_msg.3291338170
Directory /workspace/25.hmac_long_msg/latest

Test location /workspace/coverage/default/25.hmac_smoke.2492077824
Short name T389
Test name
Test status
Simulation time 223521948 ps
CPU time 10.68 seconds
Started Jul 02 09:43:10 AM PDT 24
Finished Jul 02 09:43:22 AM PDT 24
Peak memory 200360 kb
Host smart-b481a61c-96eb-4fca-9fb0-1dde06bcc571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492077824 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_smoke.2492077824
Directory /workspace/25.hmac_smoke/latest

Test location /workspace/coverage/default/25.hmac_stress_all.3488825682
Short name T365
Test name
Test status
Simulation time 225580376675 ps
CPU time 2039.95 seconds
Started Jul 02 09:43:11 AM PDT 24
Finished Jul 02 10:17:13 AM PDT 24
Peak memory 766048 kb
Host smart-f8e14032-f63f-4f10-bf40-aeba51e0e08e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488825682 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.hmac_stress_all.3488825682
Directory /workspace/25.hmac_stress_all/latest

Test location /workspace/coverage/default/25.hmac_wipe_secret.1567268205
Short name T123
Test name
Test status
Simulation time 1236129229 ps
CPU time 58.74 seconds
Started Jul 02 09:43:12 AM PDT 24
Finished Jul 02 09:44:12 AM PDT 24
Peak memory 200396 kb
Host smart-04b690ae-07f8-4c28-b70d-4b3cb90b055b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567268205 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_wipe_secret.1567268205
Directory /workspace/25.hmac_wipe_secret/latest

Test location /workspace/coverage/default/26.hmac_alert_test.1908551586
Short name T158
Test name
Test status
Simulation time 14264378 ps
CPU time 0.61 seconds
Started Jul 02 09:43:16 AM PDT 24
Finished Jul 02 09:43:17 AM PDT 24
Peak memory 195848 kb
Host smart-11e98280-1643-4245-be73-1a66d5dd6f23
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908551586 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_alert_test.1908551586
Directory /workspace/26.hmac_alert_test/latest

Test location /workspace/coverage/default/26.hmac_back_pressure.3224545048
Short name T13
Test name
Test status
Simulation time 1537803393 ps
CPU time 87.03 seconds
Started Jul 02 09:43:11 AM PDT 24
Finished Jul 02 09:44:40 AM PDT 24
Peak memory 200324 kb
Host smart-22b9206d-13b2-4c18-b2b0-59ace002ed9b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3224545048 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_back_pressure.3224545048
Directory /workspace/26.hmac_back_pressure/latest

Test location /workspace/coverage/default/26.hmac_burst_wr.3464263486
Short name T99
Test name
Test status
Simulation time 5209949217 ps
CPU time 19.72 seconds
Started Jul 02 09:43:12 AM PDT 24
Finished Jul 02 09:43:33 AM PDT 24
Peak memory 200444 kb
Host smart-c52ce8b2-7f92-4e98-9d8d-1a3147dc4815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464263486 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_burst_wr.3464263486
Directory /workspace/26.hmac_burst_wr/latest

Test location /workspace/coverage/default/26.hmac_datapath_stress.3244735991
Short name T168
Test name
Test status
Simulation time 2176439635 ps
CPU time 115.34 seconds
Started Jul 02 09:43:26 AM PDT 24
Finished Jul 02 09:45:22 AM PDT 24
Peak memory 585316 kb
Host smart-81bb9879-ca87-4be3-9ad1-f4df18d3186a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3244735991 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_datapath_stress.3244735991
Directory /workspace/26.hmac_datapath_stress/latest

Test location /workspace/coverage/default/26.hmac_error.2910749501
Short name T419
Test name
Test status
Simulation time 7252735294 ps
CPU time 209.97 seconds
Started Jul 02 09:43:15 AM PDT 24
Finished Jul 02 09:46:46 AM PDT 24
Peak memory 200384 kb
Host smart-38df3a8c-a1a9-4243-a3ee-9b59dbff61b1
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910749501 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_error.2910749501
Directory /workspace/26.hmac_error/latest

Test location /workspace/coverage/default/26.hmac_long_msg.901922012
Short name T2
Test name
Test status
Simulation time 1426768403 ps
CPU time 75.16 seconds
Started Jul 02 09:43:11 AM PDT 24
Finished Jul 02 09:44:28 AM PDT 24
Peak memory 200356 kb
Host smart-c53f1064-d2ad-4d35-894d-9102ffe806d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901922012 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_long_msg.901922012
Directory /workspace/26.hmac_long_msg/latest

Test location /workspace/coverage/default/26.hmac_smoke.402710948
Short name T206
Test name
Test status
Simulation time 118265934 ps
CPU time 1.97 seconds
Started Jul 02 09:43:11 AM PDT 24
Finished Jul 02 09:43:15 AM PDT 24
Peak memory 200336 kb
Host smart-cabeaa68-91f4-4ee6-8ab7-968df9364ae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=402710948 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_smoke.402710948
Directory /workspace/26.hmac_smoke/latest

Test location /workspace/coverage/default/26.hmac_stress_all.3572639092
Short name T440
Test name
Test status
Simulation time 335898895000 ps
CPU time 1456.09 seconds
Started Jul 02 09:43:12 AM PDT 24
Finished Jul 02 10:07:30 AM PDT 24
Peak memory 521852 kb
Host smart-800e74d6-dfb0-48d9-bc40-dd9417d0152d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572639092 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.hmac_stress_all.3572639092
Directory /workspace/26.hmac_stress_all/latest

Test location /workspace/coverage/default/26.hmac_wipe_secret.4293069361
Short name T358
Test name
Test status
Simulation time 4634880557 ps
CPU time 15.23 seconds
Started Jul 02 09:43:11 AM PDT 24
Finished Jul 02 09:43:28 AM PDT 24
Peak memory 200420 kb
Host smart-29f7cee2-132b-4829-8b1a-867fd33b5715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293069361 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_wipe_secret.4293069361
Directory /workspace/26.hmac_wipe_secret/latest

Test location /workspace/coverage/default/27.hmac_alert_test.4213507897
Short name T514
Test name
Test status
Simulation time 14144098 ps
CPU time 0.61 seconds
Started Jul 02 09:43:13 AM PDT 24
Finished Jul 02 09:43:14 AM PDT 24
Peak memory 196188 kb
Host smart-6a24e6e3-450b-469c-bd02-8f1ad6ca28c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213507897 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_alert_test.4213507897
Directory /workspace/27.hmac_alert_test/latest

Test location /workspace/coverage/default/27.hmac_back_pressure.591192259
Short name T376
Test name
Test status
Simulation time 875919489 ps
CPU time 46.96 seconds
Started Jul 02 09:43:18 AM PDT 24
Finished Jul 02 09:44:05 AM PDT 24
Peak memory 200356 kb
Host smart-8e46e818-b96b-4afb-aaad-d21d95b42968
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=591192259 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_back_pressure.591192259
Directory /workspace/27.hmac_back_pressure/latest

Test location /workspace/coverage/default/27.hmac_burst_wr.3570768128
Short name T262
Test name
Test status
Simulation time 540983898 ps
CPU time 15.04 seconds
Started Jul 02 09:43:13 AM PDT 24
Finished Jul 02 09:43:29 AM PDT 24
Peak memory 200360 kb
Host smart-57ed4bd8-4515-4d96-a268-dca2bb51bcab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570768128 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_burst_wr.3570768128
Directory /workspace/27.hmac_burst_wr/latest

Test location /workspace/coverage/default/27.hmac_datapath_stress.3651102569
Short name T470
Test name
Test status
Simulation time 12063447 ps
CPU time 0.75 seconds
Started Jul 02 09:43:11 AM PDT 24
Finished Jul 02 09:43:14 AM PDT 24
Peak memory 200056 kb
Host smart-848c8dd8-806a-4a1e-b999-f4647eb3da23
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3651102569 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_datapath_stress.3651102569
Directory /workspace/27.hmac_datapath_stress/latest

Test location /workspace/coverage/default/27.hmac_error.2759836790
Short name T417
Test name
Test status
Simulation time 6176435261 ps
CPU time 173.02 seconds
Started Jul 02 09:43:13 AM PDT 24
Finished Jul 02 09:46:07 AM PDT 24
Peak memory 200424 kb
Host smart-95c3fd09-5600-4306-abcf-906bda508e49
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759836790 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_error.2759836790
Directory /workspace/27.hmac_error/latest

Test location /workspace/coverage/default/27.hmac_long_msg.96876655
Short name T346
Test name
Test status
Simulation time 8480619544 ps
CPU time 73.16 seconds
Started Jul 02 09:43:13 AM PDT 24
Finished Jul 02 09:44:27 AM PDT 24
Peak memory 200380 kb
Host smart-773beff4-6ed8-4c03-ab57-8f79a147a434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96876655 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_long_msg.96876655
Directory /workspace/27.hmac_long_msg/latest

Test location /workspace/coverage/default/27.hmac_smoke.2222260021
Short name T125
Test name
Test status
Simulation time 562782516 ps
CPU time 9.54 seconds
Started Jul 02 09:43:13 AM PDT 24
Finished Jul 02 09:43:24 AM PDT 24
Peak memory 200372 kb
Host smart-a5e2cc77-9069-43d0-930f-10f2fa87be75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222260021 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_smoke.2222260021
Directory /workspace/27.hmac_smoke/latest

Test location /workspace/coverage/default/27.hmac_stress_all.1424356897
Short name T493
Test name
Test status
Simulation time 56549768850 ps
CPU time 4892.4 seconds
Started Jul 02 09:43:17 AM PDT 24
Finished Jul 02 11:04:50 AM PDT 24
Peak memory 878076 kb
Host smart-8063659c-8664-4519-9e41-34229befe33f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424356897 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.hmac_stress_all.1424356897
Directory /workspace/27.hmac_stress_all/latest

Test location /workspace/coverage/default/27.hmac_wipe_secret.3641163626
Short name T96
Test name
Test status
Simulation time 27126045874 ps
CPU time 103.55 seconds
Started Jul 02 09:43:17 AM PDT 24
Finished Jul 02 09:45:01 AM PDT 24
Peak memory 200416 kb
Host smart-42e7b704-c16f-44fc-8b55-9d37dc3bc59d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641163626 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_wipe_secret.3641163626
Directory /workspace/27.hmac_wipe_secret/latest

Test location /workspace/coverage/default/28.hmac_alert_test.2721403627
Short name T353
Test name
Test status
Simulation time 23212436 ps
CPU time 0.62 seconds
Started Jul 02 09:43:19 AM PDT 24
Finished Jul 02 09:43:20 AM PDT 24
Peak memory 197108 kb
Host smart-07129f04-ae7a-4d58-9c19-e541a3d20d62
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721403627 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_alert_test.2721403627
Directory /workspace/28.hmac_alert_test/latest

Test location /workspace/coverage/default/28.hmac_back_pressure.366340831
Short name T127
Test name
Test status
Simulation time 2186028277 ps
CPU time 30.75 seconds
Started Jul 02 09:43:17 AM PDT 24
Finished Jul 02 09:43:49 AM PDT 24
Peak memory 200408 kb
Host smart-b00e8b7a-713b-4793-8f9e-10b095d54ea9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=366340831 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_back_pressure.366340831
Directory /workspace/28.hmac_back_pressure/latest

Test location /workspace/coverage/default/28.hmac_burst_wr.3515523229
Short name T415
Test name
Test status
Simulation time 14157114806 ps
CPU time 34.63 seconds
Started Jul 02 09:43:18 AM PDT 24
Finished Jul 02 09:43:53 AM PDT 24
Peak memory 200480 kb
Host smart-e65ac793-381a-49ac-861a-07afabd994af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515523229 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_burst_wr.3515523229
Directory /workspace/28.hmac_burst_wr/latest

Test location /workspace/coverage/default/28.hmac_datapath_stress.3106648723
Short name T369
Test name
Test status
Simulation time 36686005147 ps
CPU time 633.54 seconds
Started Jul 02 09:43:17 AM PDT 24
Finished Jul 02 09:53:51 AM PDT 24
Peak memory 677060 kb
Host smart-94827d79-a2d0-49af-9596-642b080cb024
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3106648723 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_datapath_stress.3106648723
Directory /workspace/28.hmac_datapath_stress/latest

Test location /workspace/coverage/default/28.hmac_error.369498473
Short name T149
Test name
Test status
Simulation time 3306538593 ps
CPU time 115.15 seconds
Started Jul 02 09:43:20 AM PDT 24
Finished Jul 02 09:45:17 AM PDT 24
Peak memory 200392 kb
Host smart-5efb9ef6-5965-45e2-afd6-cd2d691cdb32
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369498473 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_error.369498473
Directory /workspace/28.hmac_error/latest

Test location /workspace/coverage/default/28.hmac_long_msg.1962072649
Short name T93
Test name
Test status
Simulation time 21018777357 ps
CPU time 87.52 seconds
Started Jul 02 09:43:15 AM PDT 24
Finished Jul 02 09:44:42 AM PDT 24
Peak memory 216768 kb
Host smart-19550f55-a5f7-4cc1-a984-677a48a9d433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962072649 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_long_msg.1962072649
Directory /workspace/28.hmac_long_msg/latest

Test location /workspace/coverage/default/28.hmac_smoke.2211913207
Short name T352
Test name
Test status
Simulation time 976010078 ps
CPU time 7.27 seconds
Started Jul 02 09:43:16 AM PDT 24
Finished Jul 02 09:43:24 AM PDT 24
Peak memory 200428 kb
Host smart-ce50d038-9613-46a8-b782-14cc0149c8c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211913207 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_smoke.2211913207
Directory /workspace/28.hmac_smoke/latest

Test location /workspace/coverage/default/28.hmac_stress_all.4029521542
Short name T83
Test name
Test status
Simulation time 166428970928 ps
CPU time 1002.39 seconds
Started Jul 02 09:43:21 AM PDT 24
Finished Jul 02 10:00:05 AM PDT 24
Peak memory 208676 kb
Host smart-18809a8c-66bb-4930-acdb-4f9b6040fdf7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029521542 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.hmac_stress_all.4029521542
Directory /workspace/28.hmac_stress_all/latest

Test location /workspace/coverage/default/28.hmac_wipe_secret.792184966
Short name T322
Test name
Test status
Simulation time 2777154921 ps
CPU time 39.08 seconds
Started Jul 02 09:43:21 AM PDT 24
Finished Jul 02 09:44:01 AM PDT 24
Peak memory 200436 kb
Host smart-6f283388-f0b5-4e30-8d1a-1b56eed0ef99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792184966 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_wipe_secret.792184966
Directory /workspace/28.hmac_wipe_secret/latest

Test location /workspace/coverage/default/29.hmac_alert_test.4264152910
Short name T468
Test name
Test status
Simulation time 40995309 ps
CPU time 0.57 seconds
Started Jul 02 09:43:24 AM PDT 24
Finished Jul 02 09:43:25 AM PDT 24
Peak memory 195848 kb
Host smart-0ccd9ed9-785c-483a-ad46-4a2e6ffe2eab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264152910 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_alert_test.4264152910
Directory /workspace/29.hmac_alert_test/latest

Test location /workspace/coverage/default/29.hmac_back_pressure.2464401675
Short name T66
Test name
Test status
Simulation time 979216972 ps
CPU time 52.15 seconds
Started Jul 02 09:43:20 AM PDT 24
Finished Jul 02 09:44:14 AM PDT 24
Peak memory 200340 kb
Host smart-afdc6a53-6605-4caa-8b4e-af7769f030ae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2464401675 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_back_pressure.2464401675
Directory /workspace/29.hmac_back_pressure/latest

Test location /workspace/coverage/default/29.hmac_burst_wr.3417303620
Short name T143
Test name
Test status
Simulation time 4238890923 ps
CPU time 28.02 seconds
Started Jul 02 09:43:25 AM PDT 24
Finished Jul 02 09:43:54 AM PDT 24
Peak memory 200444 kb
Host smart-5e3b6c54-83dd-428a-a651-130f131442be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417303620 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_burst_wr.3417303620
Directory /workspace/29.hmac_burst_wr/latest

Test location /workspace/coverage/default/29.hmac_datapath_stress.441928567
Short name T427
Test name
Test status
Simulation time 8054766727 ps
CPU time 1700.01 seconds
Started Jul 02 09:43:22 AM PDT 24
Finished Jul 02 10:11:43 AM PDT 24
Peak memory 772932 kb
Host smart-6b67c134-805d-4717-a6b2-b41573d97427
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=441928567 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_datapath_stress.441928567
Directory /workspace/29.hmac_datapath_stress/latest

Test location /workspace/coverage/default/29.hmac_error.490988433
Short name T341
Test name
Test status
Simulation time 659590127 ps
CPU time 11.98 seconds
Started Jul 02 09:43:25 AM PDT 24
Finished Jul 02 09:43:38 AM PDT 24
Peak memory 200264 kb
Host smart-34a5199f-79a8-44d3-80e2-a6c0df02ee74
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490988433 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_error.490988433
Directory /workspace/29.hmac_error/latest

Test location /workspace/coverage/default/29.hmac_long_msg.3328155706
Short name T42
Test name
Test status
Simulation time 10220066145 ps
CPU time 157.49 seconds
Started Jul 02 09:43:21 AM PDT 24
Finished Jul 02 09:46:00 AM PDT 24
Peak memory 200460 kb
Host smart-8d2f2912-a124-4b07-921c-8011eef390e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328155706 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_long_msg.3328155706
Directory /workspace/29.hmac_long_msg/latest

Test location /workspace/coverage/default/29.hmac_smoke.469444428
Short name T508
Test name
Test status
Simulation time 1217984148 ps
CPU time 16.06 seconds
Started Jul 02 09:43:20 AM PDT 24
Finished Jul 02 09:43:37 AM PDT 24
Peak memory 200396 kb
Host smart-fdb1f5cd-ddf8-404d-be06-42c91536ceb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469444428 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_smoke.469444428
Directory /workspace/29.hmac_smoke/latest

Test location /workspace/coverage/default/29.hmac_stress_all.2437536644
Short name T90
Test name
Test status
Simulation time 80774202327 ps
CPU time 1219.89 seconds
Started Jul 02 09:43:24 AM PDT 24
Finished Jul 02 10:03:45 AM PDT 24
Peak memory 481172 kb
Host smart-6b9ca746-3305-4189-9414-0ffb7473aa29
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437536644 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.hmac_stress_all.2437536644
Directory /workspace/29.hmac_stress_all/latest

Test location /workspace/coverage/default/29.hmac_wipe_secret.274460819
Short name T88
Test name
Test status
Simulation time 54045308576 ps
CPU time 144.19 seconds
Started Jul 02 09:43:30 AM PDT 24
Finished Jul 02 09:45:55 AM PDT 24
Peak memory 200428 kb
Host smart-7a4c1d6e-2b93-4145-b7ee-60012db5fe13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274460819 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_wipe_secret.274460819
Directory /workspace/29.hmac_wipe_secret/latest

Test location /workspace/coverage/default/3.hmac_alert_test.2209801769
Short name T405
Test name
Test status
Simulation time 28239672 ps
CPU time 0.58 seconds
Started Jul 02 09:42:36 AM PDT 24
Finished Jul 02 09:42:38 AM PDT 24
Peak memory 196224 kb
Host smart-adf290cd-687b-46cf-a29e-4991ad39f546
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209801769 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_alert_test.2209801769
Directory /workspace/3.hmac_alert_test/latest

Test location /workspace/coverage/default/3.hmac_back_pressure.922314037
Short name T46
Test name
Test status
Simulation time 474080555 ps
CPU time 24.89 seconds
Started Jul 02 09:42:35 AM PDT 24
Finished Jul 02 09:43:01 AM PDT 24
Peak memory 200404 kb
Host smart-0f154a36-ad06-4cbc-b526-d3a3747b5675
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=922314037 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_back_pressure.922314037
Directory /workspace/3.hmac_back_pressure/latest

Test location /workspace/coverage/default/3.hmac_burst_wr.3869735248
Short name T62
Test name
Test status
Simulation time 7813990217 ps
CPU time 71.13 seconds
Started Jul 02 09:42:32 AM PDT 24
Finished Jul 02 09:43:44 AM PDT 24
Peak memory 208684 kb
Host smart-db1fe7b3-ac12-4d22-89b3-cf5f55764ad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869735248 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_burst_wr.3869735248
Directory /workspace/3.hmac_burst_wr/latest

Test location /workspace/coverage/default/3.hmac_datapath_stress.1948399071
Short name T245
Test name
Test status
Simulation time 5168432130 ps
CPU time 55.2 seconds
Started Jul 02 09:42:32 AM PDT 24
Finished Jul 02 09:43:28 AM PDT 24
Peak memory 323596 kb
Host smart-0de9e447-c637-4e0e-892d-14320b06da49
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1948399071 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_datapath_stress.1948399071
Directory /workspace/3.hmac_datapath_stress/latest

Test location /workspace/coverage/default/3.hmac_error.3168998809
Short name T301
Test name
Test status
Simulation time 12440757772 ps
CPU time 230.74 seconds
Started Jul 02 09:42:33 AM PDT 24
Finished Jul 02 09:46:25 AM PDT 24
Peak memory 200432 kb
Host smart-e613c62f-795c-4834-bbf2-fb41bb97841d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168998809 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_error.3168998809
Directory /workspace/3.hmac_error/latest

Test location /workspace/coverage/default/3.hmac_long_msg.2682540731
Short name T406
Test name
Test status
Simulation time 315165781 ps
CPU time 17.3 seconds
Started Jul 02 09:42:34 AM PDT 24
Finished Jul 02 09:42:52 AM PDT 24
Peak memory 200420 kb
Host smart-2560aa37-b466-4beb-bc05-bcd0ad1dc69a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682540731 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_long_msg.2682540731
Directory /workspace/3.hmac_long_msg/latest

Test location /workspace/coverage/default/3.hmac_sec_cm.3218336811
Short name T57
Test name
Test status
Simulation time 159233210 ps
CPU time 1.02 seconds
Started Jul 02 09:42:37 AM PDT 24
Finished Jul 02 09:42:38 AM PDT 24
Peak memory 219616 kb
Host smart-a14f5c14-fa54-4fe4-a5b6-055e2c9ea8e1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218336811 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_sec_cm.3218336811
Directory /workspace/3.hmac_sec_cm/latest

Test location /workspace/coverage/default/3.hmac_smoke.231959112
Short name T267
Test name
Test status
Simulation time 17017780 ps
CPU time 0.8 seconds
Started Jul 02 09:42:32 AM PDT 24
Finished Jul 02 09:42:34 AM PDT 24
Peak memory 198372 kb
Host smart-4499400e-1b17-4633-a560-082b7a59046d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231959112 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_smoke.231959112
Directory /workspace/3.hmac_smoke/latest

Test location /workspace/coverage/default/3.hmac_stress_all.894146713
Short name T25
Test name
Test status
Simulation time 9408718271 ps
CPU time 633.13 seconds
Started Jul 02 09:42:37 AM PDT 24
Finished Jul 02 09:53:11 AM PDT 24
Peak memory 658288 kb
Host smart-4bf6735d-b42e-43d4-b9cb-a9695d9996f0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894146713 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all.894146713
Directory /workspace/3.hmac_stress_all/latest

Test location /workspace/coverage/default/3.hmac_stress_all_with_rand_reset.1836601076
Short name T14
Test name
Test status
Simulation time 55080663490 ps
CPU time 992.36 seconds
Started Jul 02 09:42:39 AM PDT 24
Finished Jul 02 09:59:12 AM PDT 24
Peak memory 619788 kb
Host smart-27ea5694-407d-40ec-87c8-5aa1baad5a53
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1836601076 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all_with_rand_reset.1836601076
Directory /workspace/3.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.hmac_test_hmac256_vectors.1286153077
Short name T320
Test name
Test status
Simulation time 1197466937 ps
CPU time 45.04 seconds
Started Jul 02 09:42:32 AM PDT 24
Finished Jul 02 09:43:18 AM PDT 24
Peak memory 200296 kb
Host smart-ea5aaa12-6817-432a-8c70-3f3d267043c1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1286153077 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac256_vectors.1286153077
Directory /workspace/3.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_hmac384_vectors.9145575
Short name T506
Test name
Test status
Simulation time 31835246590 ps
CPU time 74.5 seconds
Started Jul 02 09:42:35 AM PDT 24
Finished Jul 02 09:43:50 AM PDT 24
Peak memory 200412 kb
Host smart-7819250d-57ed-4a98-a7a8-140e609606fc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=9145575 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac384_vectors.9145575
Directory /workspace/3.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_hmac512_vectors.3190230705
Short name T274
Test name
Test status
Simulation time 34514847112 ps
CPU time 90.05 seconds
Started Jul 02 09:42:38 AM PDT 24
Finished Jul 02 09:44:08 AM PDT 24
Peak memory 200428 kb
Host smart-f815779a-55f1-4568-b6c3-6111e6f87a8c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3190230705 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac512_vectors.3190230705
Directory /workspace/3.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha256_vectors.197698507
Short name T263
Test name
Test status
Simulation time 19332672522 ps
CPU time 479.59 seconds
Started Jul 02 09:42:32 AM PDT 24
Finished Jul 02 09:50:33 AM PDT 24
Peak memory 200440 kb
Host smart-a6c305ab-ac0a-4da9-a725-a9493a7eeff9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=197698507 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha256_vectors.197698507
Directory /workspace/3.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha384_vectors.1179028386
Short name T500
Test name
Test status
Simulation time 40878688942 ps
CPU time 2215.76 seconds
Started Jul 02 09:42:31 AM PDT 24
Finished Jul 02 10:19:28 AM PDT 24
Peak memory 215884 kb
Host smart-650a82a9-7766-4b0f-aa32-9a1539fcb963
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1179028386 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha384_vectors.1179028386
Directory /workspace/3.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha512_vectors.1354945545
Short name T235
Test name
Test status
Simulation time 291776264501 ps
CPU time 2444.97 seconds
Started Jul 02 09:42:36 AM PDT 24
Finished Jul 02 10:23:22 AM PDT 24
Peak memory 216056 kb
Host smart-0f4dbf19-a2c0-43e2-ae98-f1607f2e1b80
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_200_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1354945545 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha512_vectors.1354945545
Directory /workspace/3.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/3.hmac_wipe_secret.3221155859
Short name T455
Test name
Test status
Simulation time 336410587 ps
CPU time 18.49 seconds
Started Jul 02 09:42:34 AM PDT 24
Finished Jul 02 09:42:53 AM PDT 24
Peak memory 200352 kb
Host smart-e8acaf9c-8408-4fae-9dc7-3811d54a9302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221155859 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_wipe_secret.3221155859
Directory /workspace/3.hmac_wipe_secret/latest

Test location /workspace/coverage/default/30.hmac_alert_test.15543074
Short name T54
Test name
Test status
Simulation time 23088640 ps
CPU time 0.58 seconds
Started Jul 02 09:43:22 AM PDT 24
Finished Jul 02 09:43:24 AM PDT 24
Peak memory 196188 kb
Host smart-aae3e363-b296-45ef-a534-5c4cc5ae9842
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15543074 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_alert_test.15543074
Directory /workspace/30.hmac_alert_test/latest

Test location /workspace/coverage/default/30.hmac_back_pressure.2852474
Short name T422
Test name
Test status
Simulation time 1504348863 ps
CPU time 18.85 seconds
Started Jul 02 09:43:22 AM PDT 24
Finished Jul 02 09:43:42 AM PDT 24
Peak memory 200316 kb
Host smart-2ce8103d-96f3-496c-b970-5c5601e742b9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2852474 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_back_pressure.2852474
Directory /workspace/30.hmac_back_pressure/latest

Test location /workspace/coverage/default/30.hmac_burst_wr.53082715
Short name T339
Test name
Test status
Simulation time 827879969 ps
CPU time 44.68 seconds
Started Jul 02 09:43:26 AM PDT 24
Finished Jul 02 09:44:11 AM PDT 24
Peak memory 200408 kb
Host smart-3e8b3cff-adba-4c18-a708-cf0dc2d50711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53082715 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_burst_wr.53082715
Directory /workspace/30.hmac_burst_wr/latest

Test location /workspace/coverage/default/30.hmac_error.8430593
Short name T345
Test name
Test status
Simulation time 5074545142 ps
CPU time 86.9 seconds
Started Jul 02 09:43:25 AM PDT 24
Finished Jul 02 09:44:53 AM PDT 24
Peak memory 200444 kb
Host smart-e2eb7869-c48d-494a-ac86-fd500a97dcc5
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8430593 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_error.8430593
Directory /workspace/30.hmac_error/latest

Test location /workspace/coverage/default/30.hmac_long_msg.1449749605
Short name T139
Test name
Test status
Simulation time 19103140032 ps
CPU time 64.51 seconds
Started Jul 02 09:43:26 AM PDT 24
Finished Jul 02 09:44:31 AM PDT 24
Peak memory 200560 kb
Host smart-08f87baa-e4ba-4a48-9bc6-b28c42a3db6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449749605 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_long_msg.1449749605
Directory /workspace/30.hmac_long_msg/latest

Test location /workspace/coverage/default/30.hmac_stress_all.919715439
Short name T505
Test name
Test status
Simulation time 73047766585 ps
CPU time 398.71 seconds
Started Jul 02 09:43:25 AM PDT 24
Finished Jul 02 09:50:05 AM PDT 24
Peak memory 658644 kb
Host smart-90673583-fd54-4b80-92db-88e2dee64383
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919715439 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 30.hmac_stress_all.919715439
Directory /workspace/30.hmac_stress_all/latest

Test location /workspace/coverage/default/30.hmac_wipe_secret.1494759375
Short name T399
Test name
Test status
Simulation time 12404245651 ps
CPU time 48.99 seconds
Started Jul 02 09:43:24 AM PDT 24
Finished Jul 02 09:44:14 AM PDT 24
Peak memory 200460 kb
Host smart-dff132c2-99b2-4662-96ef-0a1cc7a9aee2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494759375 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_wipe_secret.1494759375
Directory /workspace/30.hmac_wipe_secret/latest

Test location /workspace/coverage/default/31.hmac_alert_test.1928535219
Short name T392
Test name
Test status
Simulation time 11750169 ps
CPU time 0.57 seconds
Started Jul 02 09:43:28 AM PDT 24
Finished Jul 02 09:43:29 AM PDT 24
Peak memory 196188 kb
Host smart-a325b626-70b4-4112-9795-c01735106e56
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928535219 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_alert_test.1928535219
Directory /workspace/31.hmac_alert_test/latest

Test location /workspace/coverage/default/31.hmac_back_pressure.2697752104
Short name T457
Test name
Test status
Simulation time 7259104348 ps
CPU time 105.45 seconds
Started Jul 02 09:43:23 AM PDT 24
Finished Jul 02 09:45:10 AM PDT 24
Peak memory 200476 kb
Host smart-958c24bf-f78f-4867-9141-417fa2bd50a9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2697752104 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_back_pressure.2697752104
Directory /workspace/31.hmac_back_pressure/latest

Test location /workspace/coverage/default/31.hmac_burst_wr.2728533207
Short name T212
Test name
Test status
Simulation time 2120435593 ps
CPU time 35.93 seconds
Started Jul 02 09:43:28 AM PDT 24
Finished Jul 02 09:44:05 AM PDT 24
Peak memory 200380 kb
Host smart-c4ac3fc0-105f-456e-90b5-13b008c7177e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728533207 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_burst_wr.2728533207
Directory /workspace/31.hmac_burst_wr/latest

Test location /workspace/coverage/default/31.hmac_datapath_stress.793087230
Short name T228
Test name
Test status
Simulation time 23701628238 ps
CPU time 939.66 seconds
Started Jul 02 09:43:29 AM PDT 24
Finished Jul 02 09:59:10 AM PDT 24
Peak memory 694596 kb
Host smart-49cfed14-a77f-4fa8-9be2-8ecf7904951f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=793087230 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_datapath_stress.793087230
Directory /workspace/31.hmac_datapath_stress/latest

Test location /workspace/coverage/default/31.hmac_error.3059270651
Short name T479
Test name
Test status
Simulation time 1218976104 ps
CPU time 13.54 seconds
Started Jul 02 09:43:27 AM PDT 24
Finished Jul 02 09:43:41 AM PDT 24
Peak memory 200344 kb
Host smart-912dd666-0d3f-47ec-b466-b90a7999578d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059270651 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_error.3059270651
Directory /workspace/31.hmac_error/latest

Test location /workspace/coverage/default/31.hmac_long_msg.1811605669
Short name T291
Test name
Test status
Simulation time 36205766461 ps
CPU time 106.89 seconds
Started Jul 02 09:43:25 AM PDT 24
Finished Jul 02 09:45:13 AM PDT 24
Peak memory 200440 kb
Host smart-4cefec63-4d54-4e2a-913b-17ca7971b64c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811605669 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_long_msg.1811605669
Directory /workspace/31.hmac_long_msg/latest

Test location /workspace/coverage/default/31.hmac_smoke.4042339906
Short name T447
Test name
Test status
Simulation time 695731417 ps
CPU time 8.18 seconds
Started Jul 02 09:43:23 AM PDT 24
Finished Jul 02 09:43:32 AM PDT 24
Peak memory 200344 kb
Host smart-f58f2607-3dc0-4b71-949a-2df2e1606d84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042339906 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_smoke.4042339906
Directory /workspace/31.hmac_smoke/latest

Test location /workspace/coverage/default/31.hmac_stress_all.2538394501
Short name T462
Test name
Test status
Simulation time 68112123429 ps
CPU time 853.11 seconds
Started Jul 02 09:43:28 AM PDT 24
Finished Jul 02 09:57:42 AM PDT 24
Peak memory 200420 kb
Host smart-51da981d-1359-43c2-9ce4-c60aa6750582
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538394501 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.hmac_stress_all.2538394501
Directory /workspace/31.hmac_stress_all/latest

Test location /workspace/coverage/default/31.hmac_wipe_secret.647388959
Short name T41
Test name
Test status
Simulation time 3482835160 ps
CPU time 76.86 seconds
Started Jul 02 09:43:27 AM PDT 24
Finished Jul 02 09:44:45 AM PDT 24
Peak memory 200412 kb
Host smart-ea5f3a96-82c7-4659-9e5f-bc5ba894059d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647388959 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_wipe_secret.647388959
Directory /workspace/31.hmac_wipe_secret/latest

Test location /workspace/coverage/default/32.hmac_alert_test.155122363
Short name T386
Test name
Test status
Simulation time 24576603 ps
CPU time 0.58 seconds
Started Jul 02 09:43:34 AM PDT 24
Finished Jul 02 09:43:35 AM PDT 24
Peak memory 195832 kb
Host smart-f8be1fec-23b6-4ae3-9ff3-16c975cebcf0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155122363 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_alert_test.155122363
Directory /workspace/32.hmac_alert_test/latest

Test location /workspace/coverage/default/32.hmac_back_pressure.3610419655
Short name T418
Test name
Test status
Simulation time 1495650559 ps
CPU time 41.25 seconds
Started Jul 02 09:43:29 AM PDT 24
Finished Jul 02 09:44:11 AM PDT 24
Peak memory 200436 kb
Host smart-4229f4dd-57ce-467c-9c69-d799d92f1632
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3610419655 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_back_pressure.3610419655
Directory /workspace/32.hmac_back_pressure/latest

Test location /workspace/coverage/default/32.hmac_burst_wr.1336586945
Short name T404
Test name
Test status
Simulation time 1427079561 ps
CPU time 17.92 seconds
Started Jul 02 09:43:34 AM PDT 24
Finished Jul 02 09:43:52 AM PDT 24
Peak memory 200388 kb
Host smart-e3688cc1-c0c1-41a5-a6fb-803a153ba7f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336586945 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_burst_wr.1336586945
Directory /workspace/32.hmac_burst_wr/latest

Test location /workspace/coverage/default/32.hmac_datapath_stress.842263538
Short name T204
Test name
Test status
Simulation time 833749992 ps
CPU time 142.91 seconds
Started Jul 02 09:43:29 AM PDT 24
Finished Jul 02 09:45:52 AM PDT 24
Peak memory 593740 kb
Host smart-bd8ff863-9c34-4a7e-ac58-79f50ed8ac99
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=842263538 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_datapath_stress.842263538
Directory /workspace/32.hmac_datapath_stress/latest

Test location /workspace/coverage/default/32.hmac_error.2273599925
Short name T187
Test name
Test status
Simulation time 52810587540 ps
CPU time 152.41 seconds
Started Jul 02 09:43:28 AM PDT 24
Finished Jul 02 09:46:02 AM PDT 24
Peak memory 200476 kb
Host smart-cf3af4e3-199a-48c9-96ce-f7e0c91871c4
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273599925 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_error.2273599925
Directory /workspace/32.hmac_error/latest

Test location /workspace/coverage/default/32.hmac_long_msg.3755461972
Short name T251
Test name
Test status
Simulation time 68592251755 ps
CPU time 115.29 seconds
Started Jul 02 09:43:28 AM PDT 24
Finished Jul 02 09:45:25 AM PDT 24
Peak memory 200448 kb
Host smart-d9e5a938-503d-4fc8-b9fa-53ad576924db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755461972 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_long_msg.3755461972
Directory /workspace/32.hmac_long_msg/latest

Test location /workspace/coverage/default/32.hmac_smoke.1734272767
Short name T463
Test name
Test status
Simulation time 5336777955 ps
CPU time 15.86 seconds
Started Jul 02 09:43:34 AM PDT 24
Finished Jul 02 09:43:50 AM PDT 24
Peak memory 200444 kb
Host smart-4502e54e-376c-4411-a240-63d361c304ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734272767 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_smoke.1734272767
Directory /workspace/32.hmac_smoke/latest

Test location /workspace/coverage/default/32.hmac_stress_all.3468591839
Short name T370
Test name
Test status
Simulation time 181158656657 ps
CPU time 542.93 seconds
Started Jul 02 09:43:28 AM PDT 24
Finished Jul 02 09:52:32 AM PDT 24
Peak memory 621248 kb
Host smart-4bf214d6-587c-4cc1-a8b1-7d8f46489eb0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468591839 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.hmac_stress_all.3468591839
Directory /workspace/32.hmac_stress_all/latest

Test location /workspace/coverage/default/32.hmac_wipe_secret.3383788612
Short name T121
Test name
Test status
Simulation time 4350087418 ps
CPU time 70.78 seconds
Started Jul 02 09:43:28 AM PDT 24
Finished Jul 02 09:44:40 AM PDT 24
Peak memory 200480 kb
Host smart-f0d592c9-ae23-42ff-92f3-7726217dbf74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383788612 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_wipe_secret.3383788612
Directory /workspace/32.hmac_wipe_secret/latest

Test location /workspace/coverage/default/33.hmac_alert_test.1698323477
Short name T195
Test name
Test status
Simulation time 17843994 ps
CPU time 0.61 seconds
Started Jul 02 09:43:32 AM PDT 24
Finished Jul 02 09:43:34 AM PDT 24
Peak memory 196172 kb
Host smart-02557445-5cab-4e9f-8dd1-ce31ede3cfc6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698323477 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_alert_test.1698323477
Directory /workspace/33.hmac_alert_test/latest

Test location /workspace/coverage/default/33.hmac_back_pressure.213868976
Short name T403
Test name
Test status
Simulation time 6825195634 ps
CPU time 68.12 seconds
Started Jul 02 09:43:35 AM PDT 24
Finished Jul 02 09:44:43 AM PDT 24
Peak memory 215812 kb
Host smart-0e0178ea-14f7-4609-aa5b-29c754218a5a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=213868976 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_back_pressure.213868976
Directory /workspace/33.hmac_back_pressure/latest

Test location /workspace/coverage/default/33.hmac_burst_wr.12519244
Short name T142
Test name
Test status
Simulation time 692506490 ps
CPU time 35.39 seconds
Started Jul 02 09:43:32 AM PDT 24
Finished Jul 02 09:44:07 AM PDT 24
Peak memory 200340 kb
Host smart-8fee180b-97e2-420e-a317-664dddc55815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12519244 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_burst_wr.12519244
Directory /workspace/33.hmac_burst_wr/latest

Test location /workspace/coverage/default/33.hmac_datapath_stress.3384020263
Short name T75
Test name
Test status
Simulation time 1903113669 ps
CPU time 266.89 seconds
Started Jul 02 09:43:31 AM PDT 24
Finished Jul 02 09:47:59 AM PDT 24
Peak memory 565904 kb
Host smart-f93f6949-7102-4991-b6ce-6e72bf83db56
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3384020263 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_datapath_stress.3384020263
Directory /workspace/33.hmac_datapath_stress/latest

Test location /workspace/coverage/default/33.hmac_error.3843018949
Short name T53
Test name
Test status
Simulation time 56147524172 ps
CPU time 154.3 seconds
Started Jul 02 09:43:33 AM PDT 24
Finished Jul 02 09:46:08 AM PDT 24
Peak memory 200424 kb
Host smart-8dde0be2-4988-4c05-8ed3-6eb9246f1b65
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843018949 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_error.3843018949
Directory /workspace/33.hmac_error/latest

Test location /workspace/coverage/default/33.hmac_long_msg.4247619926
Short name T407
Test name
Test status
Simulation time 1184134378 ps
CPU time 66.18 seconds
Started Jul 02 09:43:32 AM PDT 24
Finished Jul 02 09:44:39 AM PDT 24
Peak memory 200380 kb
Host smart-8b0efa60-7d86-43b6-9588-6a01e54705ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247619926 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_long_msg.4247619926
Directory /workspace/33.hmac_long_msg/latest

Test location /workspace/coverage/default/33.hmac_smoke.26867920
Short name T331
Test name
Test status
Simulation time 646694135 ps
CPU time 8.72 seconds
Started Jul 02 09:43:33 AM PDT 24
Finished Jul 02 09:43:42 AM PDT 24
Peak memory 200340 kb
Host smart-f3b9b78b-7033-4dac-9c29-a9b2f9495963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26867920 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_smoke.26867920
Directory /workspace/33.hmac_smoke/latest

Test location /workspace/coverage/default/33.hmac_stress_all.1933578227
Short name T524
Test name
Test status
Simulation time 212031845947 ps
CPU time 1698.86 seconds
Started Jul 02 09:43:32 AM PDT 24
Finished Jul 02 10:11:52 AM PDT 24
Peak memory 775372 kb
Host smart-7930cf59-6db4-4dd5-9b34-ccb4c4790fd8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933578227 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.hmac_stress_all.1933578227
Directory /workspace/33.hmac_stress_all/latest

Test location /workspace/coverage/default/33.hmac_wipe_secret.3314977202
Short name T473
Test name
Test status
Simulation time 3098711910 ps
CPU time 44.37 seconds
Started Jul 02 09:43:32 AM PDT 24
Finished Jul 02 09:44:17 AM PDT 24
Peak memory 200448 kb
Host smart-3eb8066c-1690-444c-a313-435804863f8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314977202 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_wipe_secret.3314977202
Directory /workspace/33.hmac_wipe_secret/latest

Test location /workspace/coverage/default/34.hmac_alert_test.582507496
Short name T387
Test name
Test status
Simulation time 20677955 ps
CPU time 0.58 seconds
Started Jul 02 09:43:35 AM PDT 24
Finished Jul 02 09:43:36 AM PDT 24
Peak memory 195848 kb
Host smart-46516d39-a3b6-4c7f-9158-36b52e39f3b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582507496 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_alert_test.582507496
Directory /workspace/34.hmac_alert_test/latest

Test location /workspace/coverage/default/34.hmac_back_pressure.2064080777
Short name T459
Test name
Test status
Simulation time 4102106622 ps
CPU time 61.08 seconds
Started Jul 02 09:43:30 AM PDT 24
Finished Jul 02 09:44:32 AM PDT 24
Peak memory 216764 kb
Host smart-a2d1defc-8adb-4b2b-a535-469af8d2f37a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2064080777 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_back_pressure.2064080777
Directory /workspace/34.hmac_back_pressure/latest

Test location /workspace/coverage/default/34.hmac_burst_wr.4262896354
Short name T336
Test name
Test status
Simulation time 1580712865 ps
CPU time 21.8 seconds
Started Jul 02 09:43:36 AM PDT 24
Finished Jul 02 09:43:59 AM PDT 24
Peak memory 200400 kb
Host smart-f6cd3201-3fc9-4b54-ae4a-05fa8c495055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262896354 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_burst_wr.4262896354
Directory /workspace/34.hmac_burst_wr/latest

Test location /workspace/coverage/default/34.hmac_datapath_stress.3865330408
Short name T366
Test name
Test status
Simulation time 2816043362 ps
CPU time 115.94 seconds
Started Jul 02 09:43:37 AM PDT 24
Finished Jul 02 09:45:33 AM PDT 24
Peak memory 598156 kb
Host smart-bdf5b84b-b404-4411-b3c5-9f5399205bbf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3865330408 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_datapath_stress.3865330408
Directory /workspace/34.hmac_datapath_stress/latest

Test location /workspace/coverage/default/34.hmac_error.2690337287
Short name T363
Test name
Test status
Simulation time 10676134769 ps
CPU time 175.82 seconds
Started Jul 02 09:43:37 AM PDT 24
Finished Jul 02 09:46:33 AM PDT 24
Peak memory 200420 kb
Host smart-80efa18a-dc1d-4d60-9af1-084c1cd21d7d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690337287 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_error.2690337287
Directory /workspace/34.hmac_error/latest

Test location /workspace/coverage/default/34.hmac_long_msg.1030011191
Short name T441
Test name
Test status
Simulation time 5840565594 ps
CPU time 167.13 seconds
Started Jul 02 09:43:33 AM PDT 24
Finished Jul 02 09:46:21 AM PDT 24
Peak memory 216656 kb
Host smart-0d74f949-9041-4132-bcca-e334d34c271d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1030011191 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_long_msg.1030011191
Directory /workspace/34.hmac_long_msg/latest

Test location /workspace/coverage/default/34.hmac_smoke.1140393631
Short name T487
Test name
Test status
Simulation time 3485822783 ps
CPU time 13.42 seconds
Started Jul 02 09:43:33 AM PDT 24
Finished Jul 02 09:43:47 AM PDT 24
Peak memory 200456 kb
Host smart-51713e14-58f5-4fed-937b-27021b5221be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140393631 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_smoke.1140393631
Directory /workspace/34.hmac_smoke/latest

Test location /workspace/coverage/default/34.hmac_stress_all.2798186140
Short name T312
Test name
Test status
Simulation time 6002095587 ps
CPU time 290.12 seconds
Started Jul 02 09:43:37 AM PDT 24
Finished Jul 02 09:48:28 AM PDT 24
Peak memory 209968 kb
Host smart-cc19589a-0bcb-4dad-8146-a100f98ab1fe
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798186140 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.hmac_stress_all.2798186140
Directory /workspace/34.hmac_stress_all/latest

Test location /workspace/coverage/default/34.hmac_wipe_secret.3448097130
Short name T330
Test name
Test status
Simulation time 5590053319 ps
CPU time 36.08 seconds
Started Jul 02 09:43:37 AM PDT 24
Finished Jul 02 09:44:13 AM PDT 24
Peak memory 200428 kb
Host smart-4e67518a-f137-405c-8783-f305b7c7f625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448097130 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_wipe_secret.3448097130
Directory /workspace/34.hmac_wipe_secret/latest

Test location /workspace/coverage/default/35.hmac_alert_test.3498373247
Short name T229
Test name
Test status
Simulation time 10339916 ps
CPU time 0.55 seconds
Started Jul 02 09:43:39 AM PDT 24
Finished Jul 02 09:43:40 AM PDT 24
Peak memory 195088 kb
Host smart-09ae1b6d-229e-4e36-abaf-211e4ae730b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498373247 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_alert_test.3498373247
Directory /workspace/35.hmac_alert_test/latest

Test location /workspace/coverage/default/35.hmac_back_pressure.612856207
Short name T527
Test name
Test status
Simulation time 1294454052 ps
CPU time 73.12 seconds
Started Jul 02 09:43:37 AM PDT 24
Finished Jul 02 09:44:51 AM PDT 24
Peak memory 200292 kb
Host smart-d5e07e7f-db05-49b8-998a-a842ef8e1ce6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=612856207 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_back_pressure.612856207
Directory /workspace/35.hmac_back_pressure/latest

Test location /workspace/coverage/default/35.hmac_burst_wr.3182894517
Short name T315
Test name
Test status
Simulation time 2196294828 ps
CPU time 38.27 seconds
Started Jul 02 09:43:41 AM PDT 24
Finished Jul 02 09:44:20 AM PDT 24
Peak memory 200448 kb
Host smart-0e2198e0-e55e-4d83-8bd0-b6b9cb5b17e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182894517 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_burst_wr.3182894517
Directory /workspace/35.hmac_burst_wr/latest

Test location /workspace/coverage/default/35.hmac_datapath_stress.2392885987
Short name T36
Test name
Test status
Simulation time 12883331980 ps
CPU time 500.74 seconds
Started Jul 02 09:43:40 AM PDT 24
Finished Jul 02 09:52:01 AM PDT 24
Peak memory 668336 kb
Host smart-da3d5563-6f16-4a69-8a54-0691faf3f675
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2392885987 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_datapath_stress.2392885987
Directory /workspace/35.hmac_datapath_stress/latest

Test location /workspace/coverage/default/35.hmac_error.748617259
Short name T209
Test name
Test status
Simulation time 19685611243 ps
CPU time 80.58 seconds
Started Jul 02 09:43:47 AM PDT 24
Finished Jul 02 09:45:08 AM PDT 24
Peak memory 200472 kb
Host smart-2440ff2f-679a-40af-a42f-3be3090ecdc2
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748617259 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_error.748617259
Directory /workspace/35.hmac_error/latest

Test location /workspace/coverage/default/35.hmac_long_msg.1937393161
Short name T49
Test name
Test status
Simulation time 10382556875 ps
CPU time 45.31 seconds
Started Jul 02 09:43:37 AM PDT 24
Finished Jul 02 09:44:22 AM PDT 24
Peak memory 200492 kb
Host smart-927adbea-5f16-4fc3-8e72-083f9f723737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937393161 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_long_msg.1937393161
Directory /workspace/35.hmac_long_msg/latest

Test location /workspace/coverage/default/35.hmac_smoke.2496883666
Short name T271
Test name
Test status
Simulation time 329038086 ps
CPU time 3.09 seconds
Started Jul 02 09:43:37 AM PDT 24
Finished Jul 02 09:43:41 AM PDT 24
Peak memory 200420 kb
Host smart-823072fb-68d4-42ed-a785-31b35ede57b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496883666 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_smoke.2496883666
Directory /workspace/35.hmac_smoke/latest

Test location /workspace/coverage/default/35.hmac_stress_all.295484102
Short name T408
Test name
Test status
Simulation time 67835689073 ps
CPU time 1506.81 seconds
Started Jul 02 09:43:43 AM PDT 24
Finished Jul 02 10:08:51 AM PDT 24
Peak memory 716920 kb
Host smart-02e73b23-de56-4d38-8532-67d8b83f612f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295484102 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 35.hmac_stress_all.295484102
Directory /workspace/35.hmac_stress_all/latest

Test location /workspace/coverage/default/35.hmac_wipe_secret.4209211670
Short name T91
Test name
Test status
Simulation time 2444811868 ps
CPU time 30.7 seconds
Started Jul 02 09:43:43 AM PDT 24
Finished Jul 02 09:44:14 AM PDT 24
Peak memory 200448 kb
Host smart-b8e3805a-51f2-4550-a692-1d3e907df9b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209211670 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_wipe_secret.4209211670
Directory /workspace/35.hmac_wipe_secret/latest

Test location /workspace/coverage/default/36.hmac_alert_test.2260057058
Short name T518
Test name
Test status
Simulation time 15500548 ps
CPU time 0.59 seconds
Started Jul 02 09:43:41 AM PDT 24
Finished Jul 02 09:43:42 AM PDT 24
Peak memory 196204 kb
Host smart-8e645251-fe7d-4c90-85d0-0d1af8ebf0ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260057058 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_alert_test.2260057058
Directory /workspace/36.hmac_alert_test/latest

Test location /workspace/coverage/default/36.hmac_back_pressure.2134112558
Short name T213
Test name
Test status
Simulation time 1593641243 ps
CPU time 86.95 seconds
Started Jul 02 09:43:41 AM PDT 24
Finished Jul 02 09:45:08 AM PDT 24
Peak memory 200268 kb
Host smart-63931059-9bb3-4908-b6ca-52afe102e166
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2134112558 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_back_pressure.2134112558
Directory /workspace/36.hmac_back_pressure/latest

Test location /workspace/coverage/default/36.hmac_burst_wr.109184384
Short name T460
Test name
Test status
Simulation time 2428495034 ps
CPU time 43.87 seconds
Started Jul 02 09:43:40 AM PDT 24
Finished Jul 02 09:44:24 AM PDT 24
Peak memory 200420 kb
Host smart-b53c38f0-f7ab-4f11-9d2e-19b977b9272e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109184384 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_burst_wr.109184384
Directory /workspace/36.hmac_burst_wr/latest

Test location /workspace/coverage/default/36.hmac_datapath_stress.2309442543
Short name T517
Test name
Test status
Simulation time 6659298981 ps
CPU time 1375.37 seconds
Started Jul 02 09:43:42 AM PDT 24
Finished Jul 02 10:06:38 AM PDT 24
Peak memory 765632 kb
Host smart-fbf13e7a-9156-407f-ad56-c02c2e70a2ce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2309442543 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_datapath_stress.2309442543
Directory /workspace/36.hmac_datapath_stress/latest

Test location /workspace/coverage/default/36.hmac_error.574463624
Short name T163
Test name
Test status
Simulation time 464867134 ps
CPU time 24.27 seconds
Started Jul 02 09:43:41 AM PDT 24
Finished Jul 02 09:44:07 AM PDT 24
Peak memory 200276 kb
Host smart-d1dd1187-a48d-47bf-ad53-9fad510cfd11
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574463624 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_error.574463624
Directory /workspace/36.hmac_error/latest

Test location /workspace/coverage/default/36.hmac_long_msg.3250765202
Short name T173
Test name
Test status
Simulation time 2948134763 ps
CPU time 157.05 seconds
Started Jul 02 09:43:38 AM PDT 24
Finished Jul 02 09:46:15 AM PDT 24
Peak memory 200460 kb
Host smart-1a0fb1d1-cffa-4443-adbb-33d84cc8b4b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250765202 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_long_msg.3250765202
Directory /workspace/36.hmac_long_msg/latest

Test location /workspace/coverage/default/36.hmac_smoke.1912702627
Short name T377
Test name
Test status
Simulation time 945226914 ps
CPU time 8.03 seconds
Started Jul 02 09:43:48 AM PDT 24
Finished Jul 02 09:43:57 AM PDT 24
Peak memory 200368 kb
Host smart-f5534a90-5b22-48fc-a31e-860f8a0f685d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912702627 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_smoke.1912702627
Directory /workspace/36.hmac_smoke/latest

Test location /workspace/coverage/default/36.hmac_stress_all.1387041136
Short name T476
Test name
Test status
Simulation time 2014237677 ps
CPU time 93.92 seconds
Started Jul 02 09:43:42 AM PDT 24
Finished Jul 02 09:45:17 AM PDT 24
Peak memory 200352 kb
Host smart-d62b06d3-cd06-4be0-920f-ee365e68ee7f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387041136 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.hmac_stress_all.1387041136
Directory /workspace/36.hmac_stress_all/latest

Test location /workspace/coverage/default/36.hmac_wipe_secret.1771472001
Short name T289
Test name
Test status
Simulation time 6357693790 ps
CPU time 81.83 seconds
Started Jul 02 09:43:40 AM PDT 24
Finished Jul 02 09:45:02 AM PDT 24
Peak memory 200452 kb
Host smart-35b4e3aa-4b4e-4083-abb9-9b7ad82c70d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771472001 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_wipe_secret.1771472001
Directory /workspace/36.hmac_wipe_secret/latest

Test location /workspace/coverage/default/37.hmac_alert_test.38159681
Short name T361
Test name
Test status
Simulation time 14536572 ps
CPU time 0.57 seconds
Started Jul 02 09:43:48 AM PDT 24
Finished Jul 02 09:43:50 AM PDT 24
Peak memory 195180 kb
Host smart-03427415-4234-4034-aeaa-4ff54d4f9e28
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38159681 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_alert_test.38159681
Directory /workspace/37.hmac_alert_test/latest

Test location /workspace/coverage/default/37.hmac_back_pressure.3275340770
Short name T434
Test name
Test status
Simulation time 404076095 ps
CPU time 5.04 seconds
Started Jul 02 09:43:42 AM PDT 24
Finished Jul 02 09:43:48 AM PDT 24
Peak memory 200264 kb
Host smart-24955c6f-56d8-4f2e-a1c8-d7695d73ed0c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3275340770 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_back_pressure.3275340770
Directory /workspace/37.hmac_back_pressure/latest

Test location /workspace/coverage/default/37.hmac_burst_wr.3719340446
Short name T183
Test name
Test status
Simulation time 13632829304 ps
CPU time 40.66 seconds
Started Jul 02 09:43:43 AM PDT 24
Finished Jul 02 09:44:24 AM PDT 24
Peak memory 200428 kb
Host smart-5ae14aeb-b1ba-4c03-83e7-f7533020d321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719340446 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_burst_wr.3719340446
Directory /workspace/37.hmac_burst_wr/latest

Test location /workspace/coverage/default/37.hmac_datapath_stress.3744856337
Short name T472
Test name
Test status
Simulation time 4269828176 ps
CPU time 188.35 seconds
Started Jul 02 09:43:43 AM PDT 24
Finished Jul 02 09:46:52 AM PDT 24
Peak memory 474532 kb
Host smart-903a3e15-512c-4018-9cf4-9b9dbfe5e62e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3744856337 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_datapath_stress.3744856337
Directory /workspace/37.hmac_datapath_stress/latest

Test location /workspace/coverage/default/37.hmac_error.3358207939
Short name T255
Test name
Test status
Simulation time 3076499598 ps
CPU time 152.4 seconds
Started Jul 02 09:43:44 AM PDT 24
Finished Jul 02 09:46:17 AM PDT 24
Peak memory 200436 kb
Host smart-5d780d80-0b60-4e32-8bec-073c83fec511
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358207939 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_error.3358207939
Directory /workspace/37.hmac_error/latest

Test location /workspace/coverage/default/37.hmac_long_msg.3217207476
Short name T208
Test name
Test status
Simulation time 9579600332 ps
CPU time 181.96 seconds
Started Jul 02 09:43:42 AM PDT 24
Finished Jul 02 09:46:45 AM PDT 24
Peak memory 216804 kb
Host smart-4d0d8ccf-2b4f-43f3-8b1e-ec14f6bf5547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217207476 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_long_msg.3217207476
Directory /workspace/37.hmac_long_msg/latest

Test location /workspace/coverage/default/37.hmac_smoke.2415744650
Short name T413
Test name
Test status
Simulation time 1935577736 ps
CPU time 5.04 seconds
Started Jul 02 09:43:42 AM PDT 24
Finished Jul 02 09:43:48 AM PDT 24
Peak memory 200372 kb
Host smart-3e8e026e-1cbd-41db-98a9-9dee8127e454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415744650 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_smoke.2415744650
Directory /workspace/37.hmac_smoke/latest

Test location /workspace/coverage/default/37.hmac_stress_all.4053889599
Short name T80
Test name
Test status
Simulation time 132997762014 ps
CPU time 1327.85 seconds
Started Jul 02 09:43:44 AM PDT 24
Finished Jul 02 10:05:52 AM PDT 24
Peak memory 767900 kb
Host smart-e5e89ece-a278-407c-bcd4-8f7fbe81e369
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053889599 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.hmac_stress_all.4053889599
Directory /workspace/37.hmac_stress_all/latest

Test location /workspace/coverage/default/37.hmac_wipe_secret.639663784
Short name T504
Test name
Test status
Simulation time 8637834785 ps
CPU time 92.25 seconds
Started Jul 02 09:43:45 AM PDT 24
Finished Jul 02 09:45:18 AM PDT 24
Peak memory 200488 kb
Host smart-dfecd600-c28d-4b7e-ba1b-b33d59e49b21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639663784 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_wipe_secret.639663784
Directory /workspace/37.hmac_wipe_secret/latest

Test location /workspace/coverage/default/38.hmac_alert_test.1358257340
Short name T300
Test name
Test status
Simulation time 11638118 ps
CPU time 0.59 seconds
Started Jul 02 09:43:48 AM PDT 24
Finished Jul 02 09:43:50 AM PDT 24
Peak memory 195824 kb
Host smart-1ef24428-bcf2-4cf6-b2bb-3494f5c80c23
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358257340 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_alert_test.1358257340
Directory /workspace/38.hmac_alert_test/latest

Test location /workspace/coverage/default/38.hmac_back_pressure.170101918
Short name T166
Test name
Test status
Simulation time 6486221548 ps
CPU time 88.45 seconds
Started Jul 02 09:43:48 AM PDT 24
Finished Jul 02 09:45:18 AM PDT 24
Peak memory 208608 kb
Host smart-abd5168a-8aed-4497-b0b4-8543e79933eb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=170101918 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_back_pressure.170101918
Directory /workspace/38.hmac_back_pressure/latest

Test location /workspace/coverage/default/38.hmac_burst_wr.1798479069
Short name T481
Test name
Test status
Simulation time 2455005509 ps
CPU time 32.19 seconds
Started Jul 02 09:43:49 AM PDT 24
Finished Jul 02 09:44:23 AM PDT 24
Peak memory 200404 kb
Host smart-c2df4560-03c6-4a98-97af-a7fbc2291155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798479069 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_burst_wr.1798479069
Directory /workspace/38.hmac_burst_wr/latest

Test location /workspace/coverage/default/38.hmac_datapath_stress.2496807356
Short name T165
Test name
Test status
Simulation time 234589773 ps
CPU time 18.08 seconds
Started Jul 02 09:43:48 AM PDT 24
Finished Jul 02 09:44:07 AM PDT 24
Peak memory 200520 kb
Host smart-d7f46b8d-58e3-46b7-ab42-b115942a39cd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2496807356 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_datapath_stress.2496807356
Directory /workspace/38.hmac_datapath_stress/latest

Test location /workspace/coverage/default/38.hmac_error.3444845103
Short name T337
Test name
Test status
Simulation time 51797313684 ps
CPU time 199.8 seconds
Started Jul 02 09:43:50 AM PDT 24
Finished Jul 02 09:47:11 AM PDT 24
Peak memory 200480 kb
Host smart-a16a4fb0-2463-4254-91db-3fecf408af1d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444845103 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_error.3444845103
Directory /workspace/38.hmac_error/latest

Test location /workspace/coverage/default/38.hmac_long_msg.576220531
Short name T285
Test name
Test status
Simulation time 2728142689 ps
CPU time 25.69 seconds
Started Jul 02 09:43:48 AM PDT 24
Finished Jul 02 09:44:15 AM PDT 24
Peak memory 200420 kb
Host smart-bddba784-0206-4e58-beeb-cde0e1e4ed10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576220531 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_long_msg.576220531
Directory /workspace/38.hmac_long_msg/latest

Test location /workspace/coverage/default/38.hmac_smoke.2772591510
Short name T150
Test name
Test status
Simulation time 30365205 ps
CPU time 0.75 seconds
Started Jul 02 09:43:43 AM PDT 24
Finished Jul 02 09:43:44 AM PDT 24
Peak memory 196984 kb
Host smart-589609c5-1062-4fc1-ad7e-30ab1cb711f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772591510 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_smoke.2772591510
Directory /workspace/38.hmac_smoke/latest

Test location /workspace/coverage/default/38.hmac_stress_all.839333421
Short name T332
Test name
Test status
Simulation time 5277041924 ps
CPU time 93.1 seconds
Started Jul 02 09:43:48 AM PDT 24
Finished Jul 02 09:45:22 AM PDT 24
Peak memory 200444 kb
Host smart-63709747-d6fa-405f-a1c7-8171b203f53f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839333421 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 38.hmac_stress_all.839333421
Directory /workspace/38.hmac_stress_all/latest

Test location /workspace/coverage/default/38.hmac_wipe_secret.1427564954
Short name T324
Test name
Test status
Simulation time 9857795315 ps
CPU time 55.66 seconds
Started Jul 02 09:43:49 AM PDT 24
Finished Jul 02 09:44:45 AM PDT 24
Peak memory 200396 kb
Host smart-da5a4a9e-33ff-44ef-a069-9732c7d5cad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427564954 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_wipe_secret.1427564954
Directory /workspace/38.hmac_wipe_secret/latest

Test location /workspace/coverage/default/39.hmac_alert_test.309987272
Short name T55
Test name
Test status
Simulation time 16038097 ps
CPU time 0.6 seconds
Started Jul 02 09:43:51 AM PDT 24
Finished Jul 02 09:43:52 AM PDT 24
Peak memory 196880 kb
Host smart-6c087f8d-b237-4b90-a421-1c27db92a324
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309987272 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_alert_test.309987272
Directory /workspace/39.hmac_alert_test/latest

Test location /workspace/coverage/default/39.hmac_back_pressure.3758889901
Short name T258
Test name
Test status
Simulation time 435024296 ps
CPU time 25.27 seconds
Started Jul 02 09:43:47 AM PDT 24
Finished Jul 02 09:44:13 AM PDT 24
Peak memory 200348 kb
Host smart-cbfcee2a-dea3-4a43-b8d5-4cdbc7b449ab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3758889901 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_back_pressure.3758889901
Directory /workspace/39.hmac_back_pressure/latest

Test location /workspace/coverage/default/39.hmac_burst_wr.1561086192
Short name T494
Test name
Test status
Simulation time 5334556929 ps
CPU time 19.27 seconds
Started Jul 02 09:43:49 AM PDT 24
Finished Jul 02 09:44:09 AM PDT 24
Peak memory 200244 kb
Host smart-5ef41ede-e579-4925-aebb-f50a72d0d958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1561086192 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_burst_wr.1561086192
Directory /workspace/39.hmac_burst_wr/latest

Test location /workspace/coverage/default/39.hmac_datapath_stress.3234616331
Short name T178
Test name
Test status
Simulation time 8650513417 ps
CPU time 219.22 seconds
Started Jul 02 09:43:47 AM PDT 24
Finished Jul 02 09:47:26 AM PDT 24
Peak memory 633552 kb
Host smart-6d5d210d-22a7-4e33-b633-8a39b67d133a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3234616331 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_datapath_stress.3234616331
Directory /workspace/39.hmac_datapath_stress/latest

Test location /workspace/coverage/default/39.hmac_error.679243007
Short name T217
Test name
Test status
Simulation time 18872508178 ps
CPU time 71.68 seconds
Started Jul 02 09:43:51 AM PDT 24
Finished Jul 02 09:45:03 AM PDT 24
Peak memory 200408 kb
Host smart-ed0099a1-88fd-4e2a-845e-609e044b7c44
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679243007 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_error.679243007
Directory /workspace/39.hmac_error/latest

Test location /workspace/coverage/default/39.hmac_long_msg.468067660
Short name T244
Test name
Test status
Simulation time 42671929068 ps
CPU time 206.91 seconds
Started Jul 02 09:43:49 AM PDT 24
Finished Jul 02 09:47:18 AM PDT 24
Peak memory 200424 kb
Host smart-e0c0719a-21af-4805-9d75-46a793791318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468067660 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_long_msg.468067660
Directory /workspace/39.hmac_long_msg/latest

Test location /workspace/coverage/default/39.hmac_smoke.3670640535
Short name T477
Test name
Test status
Simulation time 669384880 ps
CPU time 4.38 seconds
Started Jul 02 09:43:47 AM PDT 24
Finished Jul 02 09:43:52 AM PDT 24
Peak memory 200328 kb
Host smart-21b42cc7-0b6d-4b8c-852e-3a6727da705e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670640535 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_smoke.3670640535
Directory /workspace/39.hmac_smoke/latest

Test location /workspace/coverage/default/39.hmac_stress_all.3849253551
Short name T12
Test name
Test status
Simulation time 200452057350 ps
CPU time 1224.77 seconds
Started Jul 02 09:43:50 AM PDT 24
Finished Jul 02 10:04:16 AM PDT 24
Peak memory 725860 kb
Host smart-bff1a450-7b4e-4ee2-9196-e4bb6c0cb659
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849253551 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.hmac_stress_all.3849253551
Directory /workspace/39.hmac_stress_all/latest

Test location /workspace/coverage/default/39.hmac_wipe_secret.453536100
Short name T368
Test name
Test status
Simulation time 1722836577 ps
CPU time 85.27 seconds
Started Jul 02 09:43:50 AM PDT 24
Finished Jul 02 09:45:16 AM PDT 24
Peak memory 200356 kb
Host smart-507f378f-dcd8-43ee-b846-70463a7ee362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453536100 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_wipe_secret.453536100
Directory /workspace/39.hmac_wipe_secret/latest

Test location /workspace/coverage/default/4.hmac_alert_test.3818453100
Short name T17
Test name
Test status
Simulation time 99028259 ps
CPU time 0.59 seconds
Started Jul 02 09:42:45 AM PDT 24
Finished Jul 02 09:42:47 AM PDT 24
Peak memory 196852 kb
Host smart-73fbfe0f-631d-46cc-b563-8d6d0f341580
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818453100 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_alert_test.3818453100
Directory /workspace/4.hmac_alert_test/latest

Test location /workspace/coverage/default/4.hmac_back_pressure.4156300528
Short name T185
Test name
Test status
Simulation time 1023471935 ps
CPU time 30.88 seconds
Started Jul 02 09:42:37 AM PDT 24
Finished Jul 02 09:43:09 AM PDT 24
Peak memory 200404 kb
Host smart-6f70437b-cb82-48f3-9403-9351e18967f5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4156300528 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_back_pressure.4156300528
Directory /workspace/4.hmac_back_pressure/latest

Test location /workspace/coverage/default/4.hmac_burst_wr.1416461748
Short name T197
Test name
Test status
Simulation time 5682884592 ps
CPU time 36.03 seconds
Started Jul 02 09:42:36 AM PDT 24
Finished Jul 02 09:43:13 AM PDT 24
Peak memory 216032 kb
Host smart-47406815-0e38-4ee9-8517-53cc7e8da458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416461748 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_burst_wr.1416461748
Directory /workspace/4.hmac_burst_wr/latest

Test location /workspace/coverage/default/4.hmac_datapath_stress.2347001089
Short name T5
Test name
Test status
Simulation time 5645820769 ps
CPU time 107.56 seconds
Started Jul 02 09:42:36 AM PDT 24
Finished Jul 02 09:44:25 AM PDT 24
Peak memory 448640 kb
Host smart-36a3d4f2-a383-4721-9009-3ccf2d1a13a3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2347001089 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_datapath_stress.2347001089
Directory /workspace/4.hmac_datapath_stress/latest

Test location /workspace/coverage/default/4.hmac_error.3149148868
Short name T445
Test name
Test status
Simulation time 2570020842 ps
CPU time 144.08 seconds
Started Jul 02 09:42:37 AM PDT 24
Finished Jul 02 09:45:02 AM PDT 24
Peak memory 200404 kb
Host smart-88bf0761-6703-4389-b23f-cb0aa1cff59f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149148868 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_error.3149148868
Directory /workspace/4.hmac_error/latest

Test location /workspace/coverage/default/4.hmac_long_msg.1454606436
Short name T272
Test name
Test status
Simulation time 4801257248 ps
CPU time 65.6 seconds
Started Jul 02 09:42:38 AM PDT 24
Finished Jul 02 09:43:44 AM PDT 24
Peak memory 200492 kb
Host smart-4fe9eea4-366e-4314-a689-441179412fff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454606436 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_long_msg.1454606436
Directory /workspace/4.hmac_long_msg/latest

Test location /workspace/coverage/default/4.hmac_sec_cm.61399806
Short name T58
Test name
Test status
Simulation time 172127669 ps
CPU time 1.01 seconds
Started Jul 02 09:42:45 AM PDT 24
Finished Jul 02 09:42:47 AM PDT 24
Peak memory 219500 kb
Host smart-c1a02b3f-8c2f-4a31-b7a2-ac3d697dbc10
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61399806 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_sec_cm.61399806
Directory /workspace/4.hmac_sec_cm/latest

Test location /workspace/coverage/default/4.hmac_smoke.3313798981
Short name T287
Test name
Test status
Simulation time 185181837 ps
CPU time 4.05 seconds
Started Jul 02 09:42:36 AM PDT 24
Finished Jul 02 09:42:41 AM PDT 24
Peak memory 200376 kb
Host smart-5a8cbdbd-a8d2-4d72-8e4f-79439ea01c77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313798981 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_smoke.3313798981
Directory /workspace/4.hmac_smoke/latest

Test location /workspace/coverage/default/4.hmac_stress_all.2003314294
Short name T446
Test name
Test status
Simulation time 303375013662 ps
CPU time 2241.01 seconds
Started Jul 02 09:42:44 AM PDT 24
Finished Jul 02 10:20:06 AM PDT 24
Peak memory 730992 kb
Host smart-4d0fcdb6-b1ad-4925-88d8-ac8bf9af3f32
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003314294 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all.2003314294
Directory /workspace/4.hmac_stress_all/latest

Test location /workspace/coverage/default/4.hmac_test_hmac256_vectors.699006416
Short name T390
Test name
Test status
Simulation time 22302382022 ps
CPU time 78.85 seconds
Started Jul 02 09:42:35 AM PDT 24
Finished Jul 02 09:43:55 AM PDT 24
Peak memory 200456 kb
Host smart-9b40d2d7-ed58-45b6-a1e4-0095a6e38a28
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=699006416 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac256_vectors.699006416
Directory /workspace/4.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_hmac384_vectors.622149347
Short name T507
Test name
Test status
Simulation time 16283253926 ps
CPU time 57 seconds
Started Jul 02 09:42:36 AM PDT 24
Finished Jul 02 09:43:34 AM PDT 24
Peak memory 200448 kb
Host smart-635f470c-cc58-462f-b2bc-9474be0c0447
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=622149347 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac384_vectors.622149347
Directory /workspace/4.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_hmac512_vectors.2934916620
Short name T354
Test name
Test status
Simulation time 26216261391 ps
CPU time 92.84 seconds
Started Jul 02 09:42:37 AM PDT 24
Finished Jul 02 09:44:11 AM PDT 24
Peak memory 200448 kb
Host smart-956ca9f9-48b9-417d-84be-e334597f6176
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2934916620 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac512_vectors.2934916620
Directory /workspace/4.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha256_vectors.435200709
Short name T329
Test name
Test status
Simulation time 122183242811 ps
CPU time 572 seconds
Started Jul 02 09:42:38 AM PDT 24
Finished Jul 02 09:52:11 AM PDT 24
Peak memory 200360 kb
Host smart-1eb52e54-def4-4efb-b723-b00bd3133e0f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=435200709 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha256_vectors.435200709
Directory /workspace/4.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha384_vectors.2546383506
Short name T250
Test name
Test status
Simulation time 277534116175 ps
CPU time 2517.82 seconds
Started Jul 02 09:42:38 AM PDT 24
Finished Jul 02 10:24:37 AM PDT 24
Peak memory 216640 kb
Host smart-3002242a-2489-413c-aea6-61870a7bdfd2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2546383506 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha384_vectors.2546383506
Directory /workspace/4.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha512_vectors.733515966
Short name T384
Test name
Test status
Simulation time 238623408714 ps
CPU time 2147.01 seconds
Started Jul 02 09:42:38 AM PDT 24
Finished Jul 02 10:18:26 AM PDT 24
Peak memory 215884 kb
Host smart-40221ae9-0770-47ab-8581-88a791f1ef63
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_200_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=733515966 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha512_vectors.733515966
Directory /workspace/4.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/4.hmac_wipe_secret.91939106
Short name T269
Test name
Test status
Simulation time 30359252815 ps
CPU time 134.32 seconds
Started Jul 02 09:42:36 AM PDT 24
Finished Jul 02 09:44:51 AM PDT 24
Peak memory 200452 kb
Host smart-f571828f-b0a2-497c-ac54-43d780ed548c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91939106 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_wipe_secret.91939106
Directory /workspace/4.hmac_wipe_secret/latest

Test location /workspace/coverage/default/40.hmac_alert_test.3095269488
Short name T40
Test name
Test status
Simulation time 13671412 ps
CPU time 0.57 seconds
Started Jul 02 09:43:52 AM PDT 24
Finished Jul 02 09:43:53 AM PDT 24
Peak memory 195160 kb
Host smart-8e9a0014-4f9a-462c-a0be-6d1c52e31b2a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095269488 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_alert_test.3095269488
Directory /workspace/40.hmac_alert_test/latest

Test location /workspace/coverage/default/40.hmac_back_pressure.2198326741
Short name T164
Test name
Test status
Simulation time 1948815765 ps
CPU time 29.02 seconds
Started Jul 02 09:43:49 AM PDT 24
Finished Jul 02 09:44:19 AM PDT 24
Peak memory 200148 kb
Host smart-b0ef0067-950b-409d-a55b-1fc4698712e5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2198326741 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_back_pressure.2198326741
Directory /workspace/40.hmac_back_pressure/latest

Test location /workspace/coverage/default/40.hmac_burst_wr.2013819783
Short name T276
Test name
Test status
Simulation time 13526448754 ps
CPU time 45.12 seconds
Started Jul 02 09:43:51 AM PDT 24
Finished Jul 02 09:44:37 AM PDT 24
Peak memory 200456 kb
Host smart-03d9282e-671d-4600-9e0e-de21a83e8c2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013819783 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_burst_wr.2013819783
Directory /workspace/40.hmac_burst_wr/latest

Test location /workspace/coverage/default/40.hmac_datapath_stress.3679042663
Short name T426
Test name
Test status
Simulation time 8328466131 ps
CPU time 211.6 seconds
Started Jul 02 09:43:52 AM PDT 24
Finished Jul 02 09:47:24 AM PDT 24
Peak memory 413384 kb
Host smart-1e63fa16-ba44-4048-96dd-d930bd1e7bed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3679042663 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_datapath_stress.3679042663
Directory /workspace/40.hmac_datapath_stress/latest

Test location /workspace/coverage/default/40.hmac_error.2948631191
Short name T10
Test name
Test status
Simulation time 2852959463 ps
CPU time 50.26 seconds
Started Jul 02 09:43:52 AM PDT 24
Finished Jul 02 09:44:43 AM PDT 24
Peak memory 200216 kb
Host smart-66b36eec-1388-4acf-9de1-13c9c5d1711d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948631191 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_error.2948631191
Directory /workspace/40.hmac_error/latest

Test location /workspace/coverage/default/40.hmac_long_msg.2861747790
Short name T398
Test name
Test status
Simulation time 7286773939 ps
CPU time 130.76 seconds
Started Jul 02 09:43:49 AM PDT 24
Finished Jul 02 09:46:01 AM PDT 24
Peak memory 208632 kb
Host smart-d0d8ceb8-7ee0-4252-b87f-a464a7f83eec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861747790 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_long_msg.2861747790
Directory /workspace/40.hmac_long_msg/latest

Test location /workspace/coverage/default/40.hmac_smoke.3832188701
Short name T502
Test name
Test status
Simulation time 314158687 ps
CPU time 4.25 seconds
Started Jul 02 09:43:50 AM PDT 24
Finished Jul 02 09:43:56 AM PDT 24
Peak memory 200400 kb
Host smart-cb8c2315-9a22-4592-9849-2e9002333c1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832188701 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_smoke.3832188701
Directory /workspace/40.hmac_smoke/latest

Test location /workspace/coverage/default/40.hmac_stress_all.2406528324
Short name T279
Test name
Test status
Simulation time 2368865885 ps
CPU time 43.48 seconds
Started Jul 02 09:43:52 AM PDT 24
Finished Jul 02 09:44:36 AM PDT 24
Peak memory 200444 kb
Host smart-5952c82b-98bd-4182-a53d-c4abe44855c3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406528324 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.hmac_stress_all.2406528324
Directory /workspace/40.hmac_stress_all/latest

Test location /workspace/coverage/default/40.hmac_wipe_secret.1431032935
Short name T207
Test name
Test status
Simulation time 4098032418 ps
CPU time 67.32 seconds
Started Jul 02 09:43:52 AM PDT 24
Finished Jul 02 09:45:00 AM PDT 24
Peak memory 200400 kb
Host smart-0df41b29-7ef5-422e-bed2-2004ffe7db85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1431032935 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_wipe_secret.1431032935
Directory /workspace/40.hmac_wipe_secret/latest

Test location /workspace/coverage/default/41.hmac_alert_test.3038489045
Short name T224
Test name
Test status
Simulation time 23874315 ps
CPU time 0.64 seconds
Started Jul 02 09:44:00 AM PDT 24
Finished Jul 02 09:44:01 AM PDT 24
Peak memory 196208 kb
Host smart-63adc8df-873f-4e3a-952e-f9252dbb4905
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038489045 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_alert_test.3038489045
Directory /workspace/41.hmac_alert_test/latest

Test location /workspace/coverage/default/41.hmac_back_pressure.1714990946
Short name T182
Test name
Test status
Simulation time 1166280510 ps
CPU time 62.83 seconds
Started Jul 02 09:44:02 AM PDT 24
Finished Jul 02 09:45:06 AM PDT 24
Peak memory 200312 kb
Host smart-3d294ba8-8fff-4d3a-a6b0-833686d173ab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1714990946 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_back_pressure.1714990946
Directory /workspace/41.hmac_back_pressure/latest

Test location /workspace/coverage/default/41.hmac_burst_wr.3485236812
Short name T65
Test name
Test status
Simulation time 6515967226 ps
CPU time 44.26 seconds
Started Jul 02 09:43:57 AM PDT 24
Finished Jul 02 09:44:42 AM PDT 24
Peak memory 200408 kb
Host smart-da5bd510-b54d-43c3-b238-5a4b3319c9fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3485236812 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_burst_wr.3485236812
Directory /workspace/41.hmac_burst_wr/latest

Test location /workspace/coverage/default/41.hmac_datapath_stress.885753625
Short name T264
Test name
Test status
Simulation time 9481736390 ps
CPU time 865.89 seconds
Started Jul 02 09:43:57 AM PDT 24
Finished Jul 02 09:58:24 AM PDT 24
Peak memory 754932 kb
Host smart-346f4507-79a5-4270-a6e1-73de2bac85a1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=885753625 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_datapath_stress.885753625
Directory /workspace/41.hmac_datapath_stress/latest

Test location /workspace/coverage/default/41.hmac_error.1041613155
Short name T211
Test name
Test status
Simulation time 35724933660 ps
CPU time 141.96 seconds
Started Jul 02 09:43:57 AM PDT 24
Finished Jul 02 09:46:20 AM PDT 24
Peak memory 200332 kb
Host smart-52ac4ba5-f203-4976-ac71-46f91a631f64
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041613155 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_error.1041613155
Directory /workspace/41.hmac_error/latest

Test location /workspace/coverage/default/41.hmac_long_msg.1675425796
Short name T521
Test name
Test status
Simulation time 7295854938 ps
CPU time 93.74 seconds
Started Jul 02 09:43:56 AM PDT 24
Finished Jul 02 09:45:30 AM PDT 24
Peak memory 200444 kb
Host smart-0ecf733e-fdb8-4526-a887-9d4d7537e520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675425796 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_long_msg.1675425796
Directory /workspace/41.hmac_long_msg/latest

Test location /workspace/coverage/default/41.hmac_smoke.2898320126
Short name T349
Test name
Test status
Simulation time 2934852757 ps
CPU time 13.76 seconds
Started Jul 02 09:43:56 AM PDT 24
Finished Jul 02 09:44:10 AM PDT 24
Peak memory 200428 kb
Host smart-9343bc33-8ccc-4aa7-881a-c4b4c634fc2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898320126 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_smoke.2898320126
Directory /workspace/41.hmac_smoke/latest

Test location /workspace/coverage/default/41.hmac_stress_all.642395432
Short name T81
Test name
Test status
Simulation time 115940444383 ps
CPU time 505.58 seconds
Started Jul 02 09:43:59 AM PDT 24
Finished Jul 02 09:52:25 AM PDT 24
Peak memory 208648 kb
Host smart-56693e0c-3ec6-4699-bc74-ab6fb33c7ec8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642395432 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 41.hmac_stress_all.642395432
Directory /workspace/41.hmac_stress_all/latest

Test location /workspace/coverage/default/41.hmac_wipe_secret.1866788590
Short name T503
Test name
Test status
Simulation time 5658201629 ps
CPU time 70.92 seconds
Started Jul 02 09:43:57 AM PDT 24
Finished Jul 02 09:45:09 AM PDT 24
Peak memory 200448 kb
Host smart-8cf88894-8e69-4758-b110-b0ef5eb0f59d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866788590 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_wipe_secret.1866788590
Directory /workspace/41.hmac_wipe_secret/latest

Test location /workspace/coverage/default/42.hmac_alert_test.2648586355
Short name T222
Test name
Test status
Simulation time 110353812 ps
CPU time 0.65 seconds
Started Jul 02 09:43:57 AM PDT 24
Finished Jul 02 09:43:59 AM PDT 24
Peak memory 196140 kb
Host smart-f8ba1d20-0002-431e-86be-7c66c93bd689
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648586355 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_alert_test.2648586355
Directory /workspace/42.hmac_alert_test/latest

Test location /workspace/coverage/default/42.hmac_back_pressure.2027298643
Short name T19
Test name
Test status
Simulation time 8704652335 ps
CPU time 81.53 seconds
Started Jul 02 09:44:00 AM PDT 24
Finished Jul 02 09:45:22 AM PDT 24
Peak memory 200404 kb
Host smart-75ea164c-b673-440d-bbeb-9a023d1774f8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2027298643 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_back_pressure.2027298643
Directory /workspace/42.hmac_back_pressure/latest

Test location /workspace/coverage/default/42.hmac_burst_wr.3523203353
Short name T444
Test name
Test status
Simulation time 6826643680 ps
CPU time 39.15 seconds
Started Jul 02 09:43:55 AM PDT 24
Finished Jul 02 09:44:34 AM PDT 24
Peak memory 208652 kb
Host smart-d3405246-1585-4465-ae8f-4a609a479292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523203353 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_burst_wr.3523203353
Directory /workspace/42.hmac_burst_wr/latest

Test location /workspace/coverage/default/42.hmac_datapath_stress.1091875070
Short name T448
Test name
Test status
Simulation time 6575523438 ps
CPU time 672.11 seconds
Started Jul 02 09:43:55 AM PDT 24
Finished Jul 02 09:55:08 AM PDT 24
Peak memory 664668 kb
Host smart-08bf2a9c-1644-4aa3-b139-77d849f4c76f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1091875070 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_datapath_stress.1091875070
Directory /workspace/42.hmac_datapath_stress/latest

Test location /workspace/coverage/default/42.hmac_error.841106113
Short name T520
Test name
Test status
Simulation time 5936005479 ps
CPU time 87.77 seconds
Started Jul 02 09:44:03 AM PDT 24
Finished Jul 02 09:45:31 AM PDT 24
Peak memory 200316 kb
Host smart-6988c14d-4893-44ee-b1cc-12d01152446d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841106113 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_error.841106113
Directory /workspace/42.hmac_error/latest

Test location /workspace/coverage/default/42.hmac_long_msg.3096077350
Short name T464
Test name
Test status
Simulation time 1082101033 ps
CPU time 58.25 seconds
Started Jul 02 09:44:01 AM PDT 24
Finished Jul 02 09:44:59 AM PDT 24
Peak memory 200384 kb
Host smart-1f22d97c-d622-4a64-ae73-44b0d8840618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096077350 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_long_msg.3096077350
Directory /workspace/42.hmac_long_msg/latest

Test location /workspace/coverage/default/42.hmac_smoke.2583392169
Short name T128
Test name
Test status
Simulation time 9337669347 ps
CPU time 15.54 seconds
Started Jul 02 09:43:57 AM PDT 24
Finished Jul 02 09:44:13 AM PDT 24
Peak memory 200352 kb
Host smart-5e76f75f-b4b0-41a4-8f39-78da6bcf26ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583392169 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_smoke.2583392169
Directory /workspace/42.hmac_smoke/latest

Test location /workspace/coverage/default/42.hmac_stress_all.4152423644
Short name T512
Test name
Test status
Simulation time 129473908041 ps
CPU time 1864.56 seconds
Started Jul 02 09:43:57 AM PDT 24
Finished Jul 02 10:15:02 AM PDT 24
Peak memory 743536 kb
Host smart-95dce029-b394-4c4f-9617-a8fc1ce11d50
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152423644 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.hmac_stress_all.4152423644
Directory /workspace/42.hmac_stress_all/latest

Test location /workspace/coverage/default/42.hmac_wipe_secret.3357268233
Short name T174
Test name
Test status
Simulation time 9353745099 ps
CPU time 102.75 seconds
Started Jul 02 09:44:01 AM PDT 24
Finished Jul 02 09:45:45 AM PDT 24
Peak memory 200420 kb
Host smart-d1918657-065e-4f00-a55e-dc00b7629019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357268233 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_wipe_secret.3357268233
Directory /workspace/42.hmac_wipe_secret/latest

Test location /workspace/coverage/default/43.hmac_alert_test.3549729402
Short name T396
Test name
Test status
Simulation time 14211282 ps
CPU time 0.56 seconds
Started Jul 02 09:43:59 AM PDT 24
Finished Jul 02 09:43:59 AM PDT 24
Peak memory 195856 kb
Host smart-b67a3786-406e-4a26-b496-2e7e7b4e982b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549729402 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_alert_test.3549729402
Directory /workspace/43.hmac_alert_test/latest

Test location /workspace/coverage/default/43.hmac_back_pressure.3524737339
Short name T409
Test name
Test status
Simulation time 1184126866 ps
CPU time 34.8 seconds
Started Jul 02 09:43:56 AM PDT 24
Finished Jul 02 09:44:32 AM PDT 24
Peak memory 200384 kb
Host smart-61d0e19b-c7c8-4d44-ba50-4ee31fc5fe76
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3524737339 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_back_pressure.3524737339
Directory /workspace/43.hmac_back_pressure/latest

Test location /workspace/coverage/default/43.hmac_burst_wr.3276632683
Short name T220
Test name
Test status
Simulation time 1095998650 ps
CPU time 10.44 seconds
Started Jul 02 09:43:59 AM PDT 24
Finished Jul 02 09:44:10 AM PDT 24
Peak memory 200352 kb
Host smart-42fdadb5-435f-4201-bc85-683f86e29280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276632683 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_burst_wr.3276632683
Directory /workspace/43.hmac_burst_wr/latest

Test location /workspace/coverage/default/43.hmac_datapath_stress.2791391622
Short name T394
Test name
Test status
Simulation time 3666522499 ps
CPU time 149.09 seconds
Started Jul 02 09:44:02 AM PDT 24
Finished Jul 02 09:46:32 AM PDT 24
Peak memory 465000 kb
Host smart-3ffd0d10-0058-4e28-b830-7673c7303cd1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2791391622 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_datapath_stress.2791391622
Directory /workspace/43.hmac_datapath_stress/latest

Test location /workspace/coverage/default/43.hmac_error.153488681
Short name T356
Test name
Test status
Simulation time 17611072755 ps
CPU time 85.81 seconds
Started Jul 02 09:44:01 AM PDT 24
Finished Jul 02 09:45:28 AM PDT 24
Peak memory 200408 kb
Host smart-faecfd9d-5a87-4c95-80b7-9523da69c045
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153488681 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_error.153488681
Directory /workspace/43.hmac_error/latest

Test location /workspace/coverage/default/43.hmac_long_msg.2368903980
Short name T474
Test name
Test status
Simulation time 1106110874 ps
CPU time 50.09 seconds
Started Jul 02 09:43:56 AM PDT 24
Finished Jul 02 09:44:47 AM PDT 24
Peak memory 200392 kb
Host smart-d746729f-a6d1-4294-8ece-5fb350b40b77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368903980 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_long_msg.2368903980
Directory /workspace/43.hmac_long_msg/latest

Test location /workspace/coverage/default/43.hmac_smoke.1187117481
Short name T522
Test name
Test status
Simulation time 312554691 ps
CPU time 13.49 seconds
Started Jul 02 09:43:59 AM PDT 24
Finished Jul 02 09:44:13 AM PDT 24
Peak memory 200404 kb
Host smart-67746a83-c960-4132-82ba-b4a47ab68bbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187117481 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_smoke.1187117481
Directory /workspace/43.hmac_smoke/latest

Test location /workspace/coverage/default/43.hmac_stress_all.3304938035
Short name T147
Test name
Test status
Simulation time 10877331442 ps
CPU time 511.4 seconds
Started Jul 02 09:44:00 AM PDT 24
Finished Jul 02 09:52:32 AM PDT 24
Peak memory 728824 kb
Host smart-d0b4213d-471a-44ad-abef-2ce70e9241b4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304938035 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.hmac_stress_all.3304938035
Directory /workspace/43.hmac_stress_all/latest

Test location /workspace/coverage/default/43.hmac_wipe_secret.1127416741
Short name T453
Test name
Test status
Simulation time 5266656057 ps
CPU time 96.25 seconds
Started Jul 02 09:44:04 AM PDT 24
Finished Jul 02 09:45:41 AM PDT 24
Peak memory 200496 kb
Host smart-267fa423-8b35-423f-80fc-3c68bef0e60e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127416741 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_wipe_secret.1127416741
Directory /workspace/43.hmac_wipe_secret/latest

Test location /workspace/coverage/default/44.hmac_alert_test.4214847991
Short name T193
Test name
Test status
Simulation time 12217238 ps
CPU time 0.61 seconds
Started Jul 02 09:44:08 AM PDT 24
Finished Jul 02 09:44:09 AM PDT 24
Peak memory 196232 kb
Host smart-070f77c1-72ca-4838-9d1e-60cf64907c43
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214847991 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_alert_test.4214847991
Directory /workspace/44.hmac_alert_test/latest

Test location /workspace/coverage/default/44.hmac_back_pressure.1181581482
Short name T385
Test name
Test status
Simulation time 1339156147 ps
CPU time 37.19 seconds
Started Jul 02 09:43:59 AM PDT 24
Finished Jul 02 09:44:37 AM PDT 24
Peak memory 200332 kb
Host smart-9950ab74-03c8-411b-8040-9a3e68f5a55b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1181581482 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_back_pressure.1181581482
Directory /workspace/44.hmac_back_pressure/latest

Test location /workspace/coverage/default/44.hmac_burst_wr.76412614
Short name T177
Test name
Test status
Simulation time 3132875961 ps
CPU time 26.98 seconds
Started Jul 02 09:44:04 AM PDT 24
Finished Jul 02 09:44:31 AM PDT 24
Peak memory 200420 kb
Host smart-c144f291-39fb-4402-a278-b3215bdb2749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76412614 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_burst_wr.76412614
Directory /workspace/44.hmac_burst_wr/latest

Test location /workspace/coverage/default/44.hmac_datapath_stress.1611736469
Short name T318
Test name
Test status
Simulation time 5929796962 ps
CPU time 1023.48 seconds
Started Jul 02 09:44:01 AM PDT 24
Finished Jul 02 10:01:06 AM PDT 24
Peak memory 742600 kb
Host smart-bd5d9e39-878e-485b-b5f1-9a0c24de4c15
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1611736469 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_datapath_stress.1611736469
Directory /workspace/44.hmac_datapath_stress/latest

Test location /workspace/coverage/default/44.hmac_error.2523543659
Short name T383
Test name
Test status
Simulation time 8128980489 ps
CPU time 97.92 seconds
Started Jul 02 09:43:59 AM PDT 24
Finished Jul 02 09:45:38 AM PDT 24
Peak memory 200396 kb
Host smart-abe99a4e-41c7-4d07-b80f-20d2b8017772
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523543659 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_error.2523543659
Directory /workspace/44.hmac_error/latest

Test location /workspace/coverage/default/44.hmac_long_msg.4116696827
Short name T286
Test name
Test status
Simulation time 9006708322 ps
CPU time 60.71 seconds
Started Jul 02 09:44:03 AM PDT 24
Finished Jul 02 09:45:04 AM PDT 24
Peak memory 216672 kb
Host smart-c427e1ae-0cad-4d47-88bb-e8f573100377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116696827 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_long_msg.4116696827
Directory /workspace/44.hmac_long_msg/latest

Test location /workspace/coverage/default/44.hmac_smoke.4282111053
Short name T34
Test name
Test status
Simulation time 967482124 ps
CPU time 9.74 seconds
Started Jul 02 09:44:02 AM PDT 24
Finished Jul 02 09:44:13 AM PDT 24
Peak memory 200396 kb
Host smart-db6f1828-901c-4d1d-9613-499608fa6139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282111053 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_smoke.4282111053
Directory /workspace/44.hmac_smoke/latest

Test location /workspace/coverage/default/44.hmac_stress_all.772852930
Short name T233
Test name
Test status
Simulation time 50406336002 ps
CPU time 640.69 seconds
Started Jul 02 09:44:05 AM PDT 24
Finished Jul 02 09:54:46 AM PDT 24
Peak memory 216844 kb
Host smart-26f3fd96-de0e-4869-8efd-1ed22b351be7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772852930 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 44.hmac_stress_all.772852930
Directory /workspace/44.hmac_stress_all/latest

Test location /workspace/coverage/default/44.hmac_wipe_secret.436149028
Short name T87
Test name
Test status
Simulation time 18268085063 ps
CPU time 115.93 seconds
Started Jul 02 09:44:01 AM PDT 24
Finished Jul 02 09:45:59 AM PDT 24
Peak memory 200444 kb
Host smart-cfb0e1a3-85a4-4a02-b45e-e1014cb4b6c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436149028 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_wipe_secret.436149028
Directory /workspace/44.hmac_wipe_secret/latest

Test location /workspace/coverage/default/45.hmac_alert_test.1792325107
Short name T234
Test name
Test status
Simulation time 26609930 ps
CPU time 0.59 seconds
Started Jul 02 09:44:07 AM PDT 24
Finished Jul 02 09:44:08 AM PDT 24
Peak memory 195880 kb
Host smart-8bf43651-d1f0-4d70-b796-0312a3d8debb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792325107 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_alert_test.1792325107
Directory /workspace/45.hmac_alert_test/latest

Test location /workspace/coverage/default/45.hmac_back_pressure.1886457244
Short name T438
Test name
Test status
Simulation time 1673537583 ps
CPU time 49.43 seconds
Started Jul 02 09:44:03 AM PDT 24
Finished Jul 02 09:44:53 AM PDT 24
Peak memory 200376 kb
Host smart-54a3082c-74f2-4cd5-83ee-2be979c34991
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1886457244 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_back_pressure.1886457244
Directory /workspace/45.hmac_back_pressure/latest

Test location /workspace/coverage/default/45.hmac_burst_wr.2870350015
Short name T146
Test name
Test status
Simulation time 1462015450 ps
CPU time 39.77 seconds
Started Jul 02 09:44:06 AM PDT 24
Finished Jul 02 09:44:46 AM PDT 24
Peak memory 200424 kb
Host smart-2ea95c80-bcdf-4b9f-b0e2-72993c989623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870350015 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_burst_wr.2870350015
Directory /workspace/45.hmac_burst_wr/latest

Test location /workspace/coverage/default/45.hmac_datapath_stress.814560980
Short name T35
Test name
Test status
Simulation time 343341006 ps
CPU time 59.24 seconds
Started Jul 02 09:44:06 AM PDT 24
Finished Jul 02 09:45:06 AM PDT 24
Peak memory 344420 kb
Host smart-7b4d1689-0ca4-4f9d-a1de-5d1aecabb372
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=814560980 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_datapath_stress.814560980
Directory /workspace/45.hmac_datapath_stress/latest

Test location /workspace/coverage/default/45.hmac_error.680496787
Short name T225
Test name
Test status
Simulation time 3139399303 ps
CPU time 86.8 seconds
Started Jul 02 09:44:07 AM PDT 24
Finished Jul 02 09:45:34 AM PDT 24
Peak memory 200408 kb
Host smart-2af1fe7a-5eff-41e4-9b21-a2b1d0415da0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680496787 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_error.680496787
Directory /workspace/45.hmac_error/latest

Test location /workspace/coverage/default/45.hmac_long_msg.55934890
Short name T523
Test name
Test status
Simulation time 8348890693 ps
CPU time 99.77 seconds
Started Jul 02 09:44:04 AM PDT 24
Finished Jul 02 09:45:44 AM PDT 24
Peak memory 200632 kb
Host smart-3a63c564-eac8-4321-ae74-bbfefb8737ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55934890 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_long_msg.55934890
Directory /workspace/45.hmac_long_msg/latest

Test location /workspace/coverage/default/45.hmac_smoke.3532753177
Short name T205
Test name
Test status
Simulation time 1145236913 ps
CPU time 7.09 seconds
Started Jul 02 09:44:05 AM PDT 24
Finished Jul 02 09:44:13 AM PDT 24
Peak memory 200364 kb
Host smart-4113f86f-5b62-4577-9b30-43d2a468a9d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532753177 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_smoke.3532753177
Directory /workspace/45.hmac_smoke/latest

Test location /workspace/coverage/default/45.hmac_stress_all.456046860
Short name T323
Test name
Test status
Simulation time 334774378079 ps
CPU time 3787.79 seconds
Started Jul 02 09:44:03 AM PDT 24
Finished Jul 02 10:47:12 AM PDT 24
Peak memory 822088 kb
Host smart-d51a6007-ae3d-4c61-9d28-c0e7a653d823
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456046860 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 45.hmac_stress_all.456046860
Directory /workspace/45.hmac_stress_all/latest

Test location /workspace/coverage/default/45.hmac_wipe_secret.3594222686
Short name T367
Test name
Test status
Simulation time 564764165 ps
CPU time 12.05 seconds
Started Jul 02 09:44:05 AM PDT 24
Finished Jul 02 09:44:18 AM PDT 24
Peak memory 200412 kb
Host smart-ef62cc5e-37a8-40e1-897e-0b18b37f22b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594222686 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_wipe_secret.3594222686
Directory /workspace/45.hmac_wipe_secret/latest

Test location /workspace/coverage/default/46.hmac_alert_test.1110795281
Short name T511
Test name
Test status
Simulation time 22684703 ps
CPU time 0.56 seconds
Started Jul 02 09:44:07 AM PDT 24
Finished Jul 02 09:44:08 AM PDT 24
Peak memory 195156 kb
Host smart-c299a013-bcfe-452b-9ae4-0317c1fa0d7d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110795281 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_alert_test.1110795281
Directory /workspace/46.hmac_alert_test/latest

Test location /workspace/coverage/default/46.hmac_back_pressure.1298472563
Short name T44
Test name
Test status
Simulation time 1211639409 ps
CPU time 68.72 seconds
Started Jul 02 09:44:05 AM PDT 24
Finished Jul 02 09:45:15 AM PDT 24
Peak memory 200332 kb
Host smart-24c7af8c-6914-4f1e-812c-f84f93b3f534
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1298472563 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_back_pressure.1298472563
Directory /workspace/46.hmac_back_pressure/latest

Test location /workspace/coverage/default/46.hmac_burst_wr.149579618
Short name T184
Test name
Test status
Simulation time 2472275540 ps
CPU time 17.21 seconds
Started Jul 02 09:44:04 AM PDT 24
Finished Jul 02 09:44:22 AM PDT 24
Peak memory 200392 kb
Host smart-0f6835e2-5b3f-47f6-8757-342d5404e679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149579618 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_burst_wr.149579618
Directory /workspace/46.hmac_burst_wr/latest

Test location /workspace/coverage/default/46.hmac_datapath_stress.2791843101
Short name T157
Test name
Test status
Simulation time 2881060934 ps
CPU time 474.91 seconds
Started Jul 02 09:44:07 AM PDT 24
Finished Jul 02 09:52:03 AM PDT 24
Peak memory 708100 kb
Host smart-8c1bbbde-1667-463d-9019-c67b9b984018
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2791843101 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_datapath_stress.2791843101
Directory /workspace/46.hmac_datapath_stress/latest

Test location /workspace/coverage/default/46.hmac_error.68059840
Short name T243
Test name
Test status
Simulation time 12638440945 ps
CPU time 185.77 seconds
Started Jul 02 09:44:07 AM PDT 24
Finished Jul 02 09:47:14 AM PDT 24
Peak memory 200456 kb
Host smart-981426e0-10c0-49ab-875d-9ec98314c03a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68059840 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_error.68059840
Directory /workspace/46.hmac_error/latest

Test location /workspace/coverage/default/46.hmac_long_msg.3065935678
Short name T161
Test name
Test status
Simulation time 44830007512 ps
CPU time 139.2 seconds
Started Jul 02 09:44:04 AM PDT 24
Finished Jul 02 09:46:24 AM PDT 24
Peak memory 200480 kb
Host smart-88fd429e-26cf-4359-a139-898defaabfa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3065935678 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_long_msg.3065935678
Directory /workspace/46.hmac_long_msg/latest

Test location /workspace/coverage/default/46.hmac_smoke.2403680042
Short name T186
Test name
Test status
Simulation time 1868677102 ps
CPU time 11.29 seconds
Started Jul 02 09:44:06 AM PDT 24
Finished Jul 02 09:44:18 AM PDT 24
Peak memory 200328 kb
Host smart-a48e479d-cfd4-42fb-bc56-c2f1a967111f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403680042 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_smoke.2403680042
Directory /workspace/46.hmac_smoke/latest

Test location /workspace/coverage/default/46.hmac_stress_all.2255279831
Short name T458
Test name
Test status
Simulation time 92259212084 ps
CPU time 2213.11 seconds
Started Jul 02 09:44:09 AM PDT 24
Finished Jul 02 10:21:03 AM PDT 24
Peak memory 762928 kb
Host smart-f86af0f3-bb08-4339-a936-9939ab6c8e60
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255279831 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.hmac_stress_all.2255279831
Directory /workspace/46.hmac_stress_all/latest

Test location /workspace/coverage/default/46.hmac_wipe_secret.2437840231
Short name T151
Test name
Test status
Simulation time 6407336502 ps
CPU time 109.02 seconds
Started Jul 02 09:44:10 AM PDT 24
Finished Jul 02 09:45:59 AM PDT 24
Peak memory 200424 kb
Host smart-e4869805-5244-427c-b1d1-5c6874e2f4e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437840231 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_wipe_secret.2437840231
Directory /workspace/46.hmac_wipe_secret/latest

Test location /workspace/coverage/default/47.hmac_alert_test.3406287664
Short name T192
Test name
Test status
Simulation time 13720791 ps
CPU time 0.57 seconds
Started Jul 02 09:44:18 AM PDT 24
Finished Jul 02 09:44:19 AM PDT 24
Peak memory 195164 kb
Host smart-aab9f4d5-b42c-44ea-a444-9728aebc30af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406287664 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_alert_test.3406287664
Directory /workspace/47.hmac_alert_test/latest

Test location /workspace/coverage/default/47.hmac_back_pressure.4068331486
Short name T11
Test name
Test status
Simulation time 1597664890 ps
CPU time 63.31 seconds
Started Jul 02 09:44:09 AM PDT 24
Finished Jul 02 09:45:14 AM PDT 24
Peak memory 200296 kb
Host smart-ce051da0-8a84-4886-9bee-3dba4894044c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4068331486 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_back_pressure.4068331486
Directory /workspace/47.hmac_back_pressure/latest

Test location /workspace/coverage/default/47.hmac_burst_wr.1819256737
Short name T436
Test name
Test status
Simulation time 419190652 ps
CPU time 2.87 seconds
Started Jul 02 09:44:08 AM PDT 24
Finished Jul 02 09:44:12 AM PDT 24
Peak memory 200400 kb
Host smart-eab01be6-d5d2-4e9c-adeb-68baaecdace3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819256737 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_burst_wr.1819256737
Directory /workspace/47.hmac_burst_wr/latest

Test location /workspace/coverage/default/47.hmac_datapath_stress.1630340896
Short name T456
Test name
Test status
Simulation time 10888492097 ps
CPU time 609.63 seconds
Started Jul 02 09:44:08 AM PDT 24
Finished Jul 02 09:54:19 AM PDT 24
Peak memory 688052 kb
Host smart-22f4ee88-8cc0-480b-9046-6e5ff17d4ac9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1630340896 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_datapath_stress.1630340896
Directory /workspace/47.hmac_datapath_stress/latest

Test location /workspace/coverage/default/47.hmac_error.1409368764
Short name T432
Test name
Test status
Simulation time 9075961592 ps
CPU time 62.83 seconds
Started Jul 02 09:44:08 AM PDT 24
Finished Jul 02 09:45:12 AM PDT 24
Peak memory 200416 kb
Host smart-4b34b3a2-8d49-461c-a61a-d580a24840fc
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409368764 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_error.1409368764
Directory /workspace/47.hmac_error/latest

Test location /workspace/coverage/default/47.hmac_long_msg.2653382560
Short name T484
Test name
Test status
Simulation time 8983941132 ps
CPU time 42.23 seconds
Started Jul 02 09:44:08 AM PDT 24
Finished Jul 02 09:44:51 AM PDT 24
Peak memory 200448 kb
Host smart-fc520681-d309-47a6-a937-1cbbccf0ddcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2653382560 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_long_msg.2653382560
Directory /workspace/47.hmac_long_msg/latest

Test location /workspace/coverage/default/47.hmac_smoke.1033075978
Short name T71
Test name
Test status
Simulation time 1020436655 ps
CPU time 14.13 seconds
Started Jul 02 09:44:09 AM PDT 24
Finished Jul 02 09:44:24 AM PDT 24
Peak memory 200308 kb
Host smart-59e81b4d-a83b-41f9-b58a-3657eb34430c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033075978 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_smoke.1033075978
Directory /workspace/47.hmac_smoke/latest

Test location /workspace/coverage/default/47.hmac_stress_all.3226459271
Short name T85
Test name
Test status
Simulation time 84271517 ps
CPU time 0.62 seconds
Started Jul 02 09:44:08 AM PDT 24
Finished Jul 02 09:44:09 AM PDT 24
Peak memory 195988 kb
Host smart-2b716603-2510-4364-a7d0-cc7c749e1147
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226459271 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.hmac_stress_all.3226459271
Directory /workspace/47.hmac_stress_all/latest

Test location /workspace/coverage/default/47.hmac_wipe_secret.3767296206
Short name T304
Test name
Test status
Simulation time 7674143842 ps
CPU time 49.64 seconds
Started Jul 02 09:44:08 AM PDT 24
Finished Jul 02 09:44:59 AM PDT 24
Peak memory 200424 kb
Host smart-c1520334-5735-4c3a-9d13-971076b51620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767296206 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_wipe_secret.3767296206
Directory /workspace/47.hmac_wipe_secret/latest

Test location /workspace/coverage/default/48.hmac_alert_test.2622043511
Short name T429
Test name
Test status
Simulation time 46948133 ps
CPU time 0.61 seconds
Started Jul 02 09:44:24 AM PDT 24
Finished Jul 02 09:44:26 AM PDT 24
Peak memory 196432 kb
Host smart-39f762f2-0c72-493c-b849-0eca99888db3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622043511 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_alert_test.2622043511
Directory /workspace/48.hmac_alert_test/latest

Test location /workspace/coverage/default/48.hmac_back_pressure.723938486
Short name T393
Test name
Test status
Simulation time 2853362964 ps
CPU time 81.52 seconds
Started Jul 02 09:44:21 AM PDT 24
Finished Jul 02 09:45:43 AM PDT 24
Peak memory 200468 kb
Host smart-cec6161d-2601-4d00-82a6-3ac3899d926d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=723938486 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_back_pressure.723938486
Directory /workspace/48.hmac_back_pressure/latest

Test location /workspace/coverage/default/48.hmac_burst_wr.378494308
Short name T344
Test name
Test status
Simulation time 484708457 ps
CPU time 4.88 seconds
Started Jul 02 09:44:13 AM PDT 24
Finished Jul 02 09:44:18 AM PDT 24
Peak memory 200376 kb
Host smart-a4e44700-9432-4b55-9062-bf613c29fd0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378494308 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_burst_wr.378494308
Directory /workspace/48.hmac_burst_wr/latest

Test location /workspace/coverage/default/48.hmac_datapath_stress.3184018241
Short name T290
Test name
Test status
Simulation time 4340002676 ps
CPU time 634.8 seconds
Started Jul 02 09:44:18 AM PDT 24
Finished Jul 02 09:54:54 AM PDT 24
Peak memory 626756 kb
Host smart-4af97181-74cf-4268-83d1-91f14ebab9bf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3184018241 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_datapath_stress.3184018241
Directory /workspace/48.hmac_datapath_stress/latest

Test location /workspace/coverage/default/48.hmac_error.1016997229
Short name T328
Test name
Test status
Simulation time 9604855955 ps
CPU time 46.7 seconds
Started Jul 02 09:44:21 AM PDT 24
Finished Jul 02 09:45:08 AM PDT 24
Peak memory 200356 kb
Host smart-cd372f0b-f75d-49e4-a6ee-9c713ba9ed80
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016997229 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_error.1016997229
Directory /workspace/48.hmac_error/latest

Test location /workspace/coverage/default/48.hmac_long_msg.3155909071
Short name T162
Test name
Test status
Simulation time 70819867222 ps
CPU time 203.45 seconds
Started Jul 02 09:44:20 AM PDT 24
Finished Jul 02 09:47:44 AM PDT 24
Peak memory 216828 kb
Host smart-60a9821e-d8b6-4279-a2b6-a067643f7433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155909071 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_long_msg.3155909071
Directory /workspace/48.hmac_long_msg/latest

Test location /workspace/coverage/default/48.hmac_smoke.2193073610
Short name T424
Test name
Test status
Simulation time 692710729 ps
CPU time 9.57 seconds
Started Jul 02 09:44:23 AM PDT 24
Finished Jul 02 09:44:33 AM PDT 24
Peak memory 200588 kb
Host smart-67209b1c-da00-4063-b8ec-9489d63b88f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193073610 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_smoke.2193073610
Directory /workspace/48.hmac_smoke/latest

Test location /workspace/coverage/default/48.hmac_stress_all.494188545
Short name T382
Test name
Test status
Simulation time 188841702297 ps
CPU time 1497.91 seconds
Started Jul 02 09:44:18 AM PDT 24
Finished Jul 02 10:09:17 AM PDT 24
Peak memory 718768 kb
Host smart-83036922-9122-430e-92c3-e8af7092f664
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494188545 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 48.hmac_stress_all.494188545
Directory /workspace/48.hmac_stress_all/latest

Test location /workspace/coverage/default/48.hmac_wipe_secret.1446422624
Short name T230
Test name
Test status
Simulation time 18472494155 ps
CPU time 119.96 seconds
Started Jul 02 09:44:19 AM PDT 24
Finished Jul 02 09:46:20 AM PDT 24
Peak memory 200468 kb
Host smart-bf3e1c1e-6783-41e6-9fc0-106dac8ac210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446422624 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_wipe_secret.1446422624
Directory /workspace/48.hmac_wipe_secret/latest

Test location /workspace/coverage/default/49.hmac_alert_test.1430353428
Short name T351
Test name
Test status
Simulation time 26667577 ps
CPU time 0.58 seconds
Started Jul 02 09:44:19 AM PDT 24
Finished Jul 02 09:44:20 AM PDT 24
Peak memory 195184 kb
Host smart-4b9a6014-5873-439c-9847-a7e7e78e9e9a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430353428 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_alert_test.1430353428
Directory /workspace/49.hmac_alert_test/latest

Test location /workspace/coverage/default/49.hmac_back_pressure.2331949641
Short name T381
Test name
Test status
Simulation time 4128688122 ps
CPU time 62.36 seconds
Started Jul 02 09:44:19 AM PDT 24
Finished Jul 02 09:45:22 AM PDT 24
Peak memory 200404 kb
Host smart-ab4e83fb-b898-490b-be2e-890689268b38
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2331949641 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_back_pressure.2331949641
Directory /workspace/49.hmac_back_pressure/latest

Test location /workspace/coverage/default/49.hmac_burst_wr.349464388
Short name T295
Test name
Test status
Simulation time 3975674477 ps
CPU time 34.82 seconds
Started Jul 02 09:44:26 AM PDT 24
Finished Jul 02 09:45:01 AM PDT 24
Peak memory 200400 kb
Host smart-bb25b2c0-7c08-4f5f-ab65-b8b3d9665cb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349464388 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_burst_wr.349464388
Directory /workspace/49.hmac_burst_wr/latest

Test location /workspace/coverage/default/49.hmac_datapath_stress.66872555
Short name T310
Test name
Test status
Simulation time 14959634357 ps
CPU time 699.19 seconds
Started Jul 02 09:44:19 AM PDT 24
Finished Jul 02 09:55:59 AM PDT 24
Peak memory 668692 kb
Host smart-5a3c1d48-576d-486d-8442-30f32545ca89
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=66872555 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_datapath_stress.66872555
Directory /workspace/49.hmac_datapath_stress/latest

Test location /workspace/coverage/default/49.hmac_error.3039501442
Short name T488
Test name
Test status
Simulation time 5453830767 ps
CPU time 67.01 seconds
Started Jul 02 09:44:20 AM PDT 24
Finished Jul 02 09:45:28 AM PDT 24
Peak memory 200444 kb
Host smart-d0f5f9e6-b339-44f1-add9-2705f247129e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039501442 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_error.3039501442
Directory /workspace/49.hmac_error/latest

Test location /workspace/coverage/default/49.hmac_long_msg.296340888
Short name T63
Test name
Test status
Simulation time 1462819601 ps
CPU time 3.47 seconds
Started Jul 02 09:44:20 AM PDT 24
Finished Jul 02 09:44:24 AM PDT 24
Peak memory 200332 kb
Host smart-9f1e9237-c88c-4c55-9015-500b8d1ef4b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296340888 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_long_msg.296340888
Directory /workspace/49.hmac_long_msg/latest

Test location /workspace/coverage/default/49.hmac_smoke.3373309037
Short name T311
Test name
Test status
Simulation time 497426888 ps
CPU time 4.54 seconds
Started Jul 02 09:44:20 AM PDT 24
Finished Jul 02 09:44:25 AM PDT 24
Peak memory 200256 kb
Host smart-bed11555-f9b7-41ef-a6ae-107f098381b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373309037 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_smoke.3373309037
Directory /workspace/49.hmac_smoke/latest

Test location /workspace/coverage/default/49.hmac_stress_all.3148438176
Short name T92
Test name
Test status
Simulation time 105927460198 ps
CPU time 3477.05 seconds
Started Jul 02 09:44:19 AM PDT 24
Finished Jul 02 10:42:17 AM PDT 24
Peak memory 780220 kb
Host smart-e97afc8e-7eff-4373-8a45-8ff7df92f322
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148438176 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.hmac_stress_all.3148438176
Directory /workspace/49.hmac_stress_all/latest

Test location /workspace/coverage/default/49.hmac_wipe_secret.126995442
Short name T510
Test name
Test status
Simulation time 631726258 ps
CPU time 28.9 seconds
Started Jul 02 09:44:20 AM PDT 24
Finished Jul 02 09:44:49 AM PDT 24
Peak memory 200420 kb
Host smart-ca5d3c2c-f848-4878-a455-b47526942a51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126995442 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_wipe_secret.126995442
Directory /workspace/49.hmac_wipe_secret/latest

Test location /workspace/coverage/default/5.hmac_alert_test.3147569517
Short name T167
Test name
Test status
Simulation time 14685271 ps
CPU time 0.58 seconds
Started Jul 02 09:42:44 AM PDT 24
Finished Jul 02 09:42:46 AM PDT 24
Peak memory 196896 kb
Host smart-90669116-d848-4a04-bfe0-6b3b714d560f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147569517 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_alert_test.3147569517
Directory /workspace/5.hmac_alert_test/latest

Test location /workspace/coverage/default/5.hmac_back_pressure.727254807
Short name T452
Test name
Test status
Simulation time 2808275584 ps
CPU time 38.62 seconds
Started Jul 02 09:42:46 AM PDT 24
Finished Jul 02 09:43:26 AM PDT 24
Peak memory 200400 kb
Host smart-67385d93-c045-4638-b0e4-0f6f325d2ec5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=727254807 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_back_pressure.727254807
Directory /workspace/5.hmac_back_pressure/latest

Test location /workspace/coverage/default/5.hmac_burst_wr.1890323972
Short name T467
Test name
Test status
Simulation time 303708282 ps
CPU time 15.67 seconds
Started Jul 02 09:42:46 AM PDT 24
Finished Jul 02 09:43:03 AM PDT 24
Peak memory 200408 kb
Host smart-da24314c-58ba-4f9c-94f4-9276db1061e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890323972 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_burst_wr.1890323972
Directory /workspace/5.hmac_burst_wr/latest

Test location /workspace/coverage/default/5.hmac_datapath_stress.231529364
Short name T76
Test name
Test status
Simulation time 17046237947 ps
CPU time 719.22 seconds
Started Jul 02 09:42:43 AM PDT 24
Finished Jul 02 09:54:43 AM PDT 24
Peak memory 704152 kb
Host smart-6d839072-37b5-4dae-8c38-e081431d1e8e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=231529364 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_datapath_stress.231529364
Directory /workspace/5.hmac_datapath_stress/latest

Test location /workspace/coverage/default/5.hmac_error.1207892581
Short name T371
Test name
Test status
Simulation time 190709578091 ps
CPU time 169.75 seconds
Started Jul 02 09:42:44 AM PDT 24
Finished Jul 02 09:45:35 AM PDT 24
Peak memory 200420 kb
Host smart-ecfbc7be-78a0-455a-976e-9cb472ba6673
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207892581 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_error.1207892581
Directory /workspace/5.hmac_error/latest

Test location /workspace/coverage/default/5.hmac_long_msg.1369381199
Short name T169
Test name
Test status
Simulation time 4131276048 ps
CPU time 222.04 seconds
Started Jul 02 09:42:44 AM PDT 24
Finished Jul 02 09:46:26 AM PDT 24
Peak memory 216864 kb
Host smart-a0cf4d10-1dd3-4c23-859f-385d0af79c7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369381199 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_long_msg.1369381199
Directory /workspace/5.hmac_long_msg/latest

Test location /workspace/coverage/default/5.hmac_smoke.33118341
Short name T380
Test name
Test status
Simulation time 429860345 ps
CPU time 5.24 seconds
Started Jul 02 09:42:46 AM PDT 24
Finished Jul 02 09:42:53 AM PDT 24
Peak memory 200316 kb
Host smart-996b5c8a-bdf0-4886-8989-e03118c52190
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33118341 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_smoke.33118341
Directory /workspace/5.hmac_smoke/latest

Test location /workspace/coverage/default/5.hmac_stress_all.738288899
Short name T79
Test name
Test status
Simulation time 112342651654 ps
CPU time 2863.59 seconds
Started Jul 02 09:42:45 AM PDT 24
Finished Jul 02 10:30:31 AM PDT 24
Peak memory 767636 kb
Host smart-4f087d6e-45ef-48bc-8119-327bbf45b46e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738288899 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all.738288899
Directory /workspace/5.hmac_stress_all/latest

Test location /workspace/coverage/default/5.hmac_stress_all_with_rand_reset.4020691432
Short name T30
Test name
Test status
Simulation time 144498411892 ps
CPU time 2548.76 seconds
Started Jul 02 09:42:45 AM PDT 24
Finished Jul 02 10:25:16 AM PDT 24
Peak memory 761508 kb
Host smart-8fc5c00d-e864-4052-b5e8-53b5cc5ed25f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4020691432 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all_with_rand_reset.4020691432
Directory /workspace/5.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.hmac_wipe_secret.2499855849
Short name T362
Test name
Test status
Simulation time 2557227940 ps
CPU time 104.74 seconds
Started Jul 02 09:42:44 AM PDT 24
Finished Jul 02 09:44:29 AM PDT 24
Peak memory 200468 kb
Host smart-af9cba9a-dd92-43fd-b897-158d621e2467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499855849 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_wipe_secret.2499855849
Directory /workspace/5.hmac_wipe_secret/latest

Test location /workspace/coverage/default/6.hmac_alert_test.3591316218
Short name T266
Test name
Test status
Simulation time 14903828 ps
CPU time 0.58 seconds
Started Jul 02 09:42:45 AM PDT 24
Finished Jul 02 09:42:47 AM PDT 24
Peak memory 195848 kb
Host smart-8279cba5-635c-41c6-9770-d035a5153f1b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591316218 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_alert_test.3591316218
Directory /workspace/6.hmac_alert_test/latest

Test location /workspace/coverage/default/6.hmac_back_pressure.1702252337
Short name T77
Test name
Test status
Simulation time 1157442333 ps
CPU time 66.16 seconds
Started Jul 02 09:42:44 AM PDT 24
Finished Jul 02 09:43:50 AM PDT 24
Peak memory 200416 kb
Host smart-68ba7950-4c8e-4f06-91f3-34b70c34e113
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1702252337 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_back_pressure.1702252337
Directory /workspace/6.hmac_back_pressure/latest

Test location /workspace/coverage/default/6.hmac_burst_wr.1432465648
Short name T199
Test name
Test status
Simulation time 2233269104 ps
CPU time 21.51 seconds
Started Jul 02 09:42:44 AM PDT 24
Finished Jul 02 09:43:07 AM PDT 24
Peak memory 200492 kb
Host smart-54cee8ec-2c93-45de-8806-46f69830a35f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432465648 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_burst_wr.1432465648
Directory /workspace/6.hmac_burst_wr/latest

Test location /workspace/coverage/default/6.hmac_datapath_stress.3096600226
Short name T443
Test name
Test status
Simulation time 6309071507 ps
CPU time 1408.7 seconds
Started Jul 02 09:42:44 AM PDT 24
Finished Jul 02 10:06:14 AM PDT 24
Peak memory 764372 kb
Host smart-e682301b-03ec-4082-9c5d-cd145504b471
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3096600226 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_datapath_stress.3096600226
Directory /workspace/6.hmac_datapath_stress/latest

Test location /workspace/coverage/default/6.hmac_error.1201089521
Short name T435
Test name
Test status
Simulation time 29799573880 ps
CPU time 125.47 seconds
Started Jul 02 09:42:43 AM PDT 24
Finished Jul 02 09:44:49 AM PDT 24
Peak memory 200368 kb
Host smart-33706b12-bef8-4bd0-a04f-d97923b60353
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201089521 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_error.1201089521
Directory /workspace/6.hmac_error/latest

Test location /workspace/coverage/default/6.hmac_long_msg.1629866769
Short name T501
Test name
Test status
Simulation time 1790422965 ps
CPU time 104.34 seconds
Started Jul 02 09:42:44 AM PDT 24
Finished Jul 02 09:44:30 AM PDT 24
Peak memory 200376 kb
Host smart-3f4721f6-da0f-4604-8b53-8d99607b14d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629866769 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_long_msg.1629866769
Directory /workspace/6.hmac_long_msg/latest

Test location /workspace/coverage/default/6.hmac_smoke.409659019
Short name T97
Test name
Test status
Simulation time 1617408202 ps
CPU time 5.2 seconds
Started Jul 02 09:42:44 AM PDT 24
Finished Jul 02 09:42:51 AM PDT 24
Peak memory 200440 kb
Host smart-681efaff-6147-4857-9dd4-348a42278fb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409659019 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_smoke.409659019
Directory /workspace/6.hmac_smoke/latest

Test location /workspace/coverage/default/6.hmac_stress_all.3061754415
Short name T333
Test name
Test status
Simulation time 42469654346 ps
CPU time 1305.26 seconds
Started Jul 02 09:42:45 AM PDT 24
Finished Jul 02 10:04:31 AM PDT 24
Peak memory 745960 kb
Host smart-3bafc1c7-0154-4b8c-b589-4cdb18b9db23
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061754415 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all.3061754415
Directory /workspace/6.hmac_stress_all/latest

Test location /workspace/coverage/default/6.hmac_stress_all_with_rand_reset.2089161544
Short name T22
Test name
Test status
Simulation time 290128491524 ps
CPU time 4842.22 seconds
Started Jul 02 09:42:44 AM PDT 24
Finished Jul 02 11:03:28 AM PDT 24
Peak memory 826388 kb
Host smart-1ebb9c98-2a3f-44e1-b9fe-b1aeabdfdfd5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2089161544 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all_with_rand_reset.2089161544
Directory /workspace/6.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.hmac_wipe_secret.344060296
Short name T122
Test name
Test status
Simulation time 21771470483 ps
CPU time 130.26 seconds
Started Jul 02 09:42:43 AM PDT 24
Finished Jul 02 09:44:54 AM PDT 24
Peak memory 200412 kb
Host smart-d0bee916-e1b2-41c5-89ad-05e6865d4f2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344060296 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_wipe_secret.344060296
Directory /workspace/6.hmac_wipe_secret/latest

Test location /workspace/coverage/default/7.hmac_alert_test.2056773131
Short name T338
Test name
Test status
Simulation time 25424364 ps
CPU time 0.59 seconds
Started Jul 02 09:42:48 AM PDT 24
Finished Jul 02 09:42:50 AM PDT 24
Peak memory 195196 kb
Host smart-f92774ed-8841-4a9a-808e-c5d6604e2a80
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056773131 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_alert_test.2056773131
Directory /workspace/7.hmac_alert_test/latest

Test location /workspace/coverage/default/7.hmac_back_pressure.2399253581
Short name T20
Test name
Test status
Simulation time 832524548 ps
CPU time 46.28 seconds
Started Jul 02 09:42:46 AM PDT 24
Finished Jul 02 09:43:34 AM PDT 24
Peak memory 200288 kb
Host smart-d349abb6-19dd-4497-941f-8c7c50d55085
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2399253581 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_back_pressure.2399253581
Directory /workspace/7.hmac_back_pressure/latest

Test location /workspace/coverage/default/7.hmac_burst_wr.2305433986
Short name T180
Test name
Test status
Simulation time 318454597 ps
CPU time 4.41 seconds
Started Jul 02 09:42:48 AM PDT 24
Finished Jul 02 09:42:53 AM PDT 24
Peak memory 200344 kb
Host smart-9d5ad654-2294-453b-8b5d-43b34b47a2b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305433986 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_burst_wr.2305433986
Directory /workspace/7.hmac_burst_wr/latest

Test location /workspace/coverage/default/7.hmac_datapath_stress.823043066
Short name T210
Test name
Test status
Simulation time 59735342271 ps
CPU time 663.88 seconds
Started Jul 02 09:42:44 AM PDT 24
Finished Jul 02 09:53:48 AM PDT 24
Peak memory 695704 kb
Host smart-8d630386-633d-463c-8c5c-3b5cf096dfae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=823043066 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_datapath_stress.823043066
Directory /workspace/7.hmac_datapath_stress/latest

Test location /workspace/coverage/default/7.hmac_error.3874222332
Short name T27
Test name
Test status
Simulation time 3325904645 ps
CPU time 185.71 seconds
Started Jul 02 09:42:43 AM PDT 24
Finished Jul 02 09:45:50 AM PDT 24
Peak memory 200312 kb
Host smart-f32d7eb9-d0fa-443f-9260-a27454c89f0a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874222332 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_error.3874222332
Directory /workspace/7.hmac_error/latest

Test location /workspace/coverage/default/7.hmac_long_msg.3674211656
Short name T275
Test name
Test status
Simulation time 22316579875 ps
CPU time 140.15 seconds
Started Jul 02 09:42:44 AM PDT 24
Finished Jul 02 09:45:06 AM PDT 24
Peak memory 200512 kb
Host smart-51a5dfae-28f8-4a61-a67e-a68a908f1ffc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674211656 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_long_msg.3674211656
Directory /workspace/7.hmac_long_msg/latest

Test location /workspace/coverage/default/7.hmac_smoke.639720503
Short name T265
Test name
Test status
Simulation time 216610246 ps
CPU time 2.74 seconds
Started Jul 02 09:42:50 AM PDT 24
Finished Jul 02 09:42:54 AM PDT 24
Peak memory 200356 kb
Host smart-ec7d6d55-377a-4f8c-b95e-202e549f7198
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639720503 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_smoke.639720503
Directory /workspace/7.hmac_smoke/latest

Test location /workspace/coverage/default/7.hmac_stress_all.2624483606
Short name T242
Test name
Test status
Simulation time 35578895781 ps
CPU time 91.81 seconds
Started Jul 02 09:42:49 AM PDT 24
Finished Jul 02 09:44:22 AM PDT 24
Peak memory 200456 kb
Host smart-b904df4d-baf4-486f-8b86-6da082d90e10
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624483606 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all.2624483606
Directory /workspace/7.hmac_stress_all/latest

Test location /workspace/coverage/default/7.hmac_wipe_secret.1794231172
Short name T221
Test name
Test status
Simulation time 1827963229 ps
CPU time 85.02 seconds
Started Jul 02 09:42:46 AM PDT 24
Finished Jul 02 09:44:12 AM PDT 24
Peak memory 200596 kb
Host smart-297b86e1-4066-4cf3-a265-916af9a8965d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794231172 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_wipe_secret.1794231172
Directory /workspace/7.hmac_wipe_secret/latest

Test location /workspace/coverage/default/8.hmac_alert_test.1048102923
Short name T175
Test name
Test status
Simulation time 17218531 ps
CPU time 0.57 seconds
Started Jul 02 09:42:49 AM PDT 24
Finished Jul 02 09:42:51 AM PDT 24
Peak memory 195828 kb
Host smart-ed9817c5-fed9-494c-9799-b9bc610175e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048102923 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_alert_test.1048102923
Directory /workspace/8.hmac_alert_test/latest

Test location /workspace/coverage/default/8.hmac_back_pressure.3101599439
Short name T50
Test name
Test status
Simulation time 3270397742 ps
CPU time 25.02 seconds
Started Jul 02 09:42:49 AM PDT 24
Finished Jul 02 09:43:16 AM PDT 24
Peak memory 200460 kb
Host smart-9d6641df-48b9-4340-b625-b074b0bf61e4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3101599439 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_back_pressure.3101599439
Directory /workspace/8.hmac_back_pressure/latest

Test location /workspace/coverage/default/8.hmac_burst_wr.2924072009
Short name T144
Test name
Test status
Simulation time 1417502713 ps
CPU time 19.13 seconds
Started Jul 02 09:42:45 AM PDT 24
Finished Jul 02 09:43:06 AM PDT 24
Peak memory 200400 kb
Host smart-efc02d75-85d3-47d7-a2c9-9c75a1c7b2b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924072009 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_burst_wr.2924072009
Directory /workspace/8.hmac_burst_wr/latest

Test location /workspace/coverage/default/8.hmac_datapath_stress.3409643163
Short name T148
Test name
Test status
Simulation time 2823744759 ps
CPU time 114.09 seconds
Started Jul 02 09:42:46 AM PDT 24
Finished Jul 02 09:44:41 AM PDT 24
Peak memory 464632 kb
Host smart-8d216660-a001-47dc-8edc-29788c91775a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3409643163 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_datapath_stress.3409643163
Directory /workspace/8.hmac_datapath_stress/latest

Test location /workspace/coverage/default/8.hmac_error.2935614879
Short name T364
Test name
Test status
Simulation time 10562266252 ps
CPU time 142.46 seconds
Started Jul 02 09:42:51 AM PDT 24
Finished Jul 02 09:45:15 AM PDT 24
Peak memory 200420 kb
Host smart-5dac195b-89d6-4ba3-932e-5b930a359c12
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935614879 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_error.2935614879
Directory /workspace/8.hmac_error/latest

Test location /workspace/coverage/default/8.hmac_long_msg.2972271620
Short name T348
Test name
Test status
Simulation time 44918118260 ps
CPU time 184.48 seconds
Started Jul 02 09:42:45 AM PDT 24
Finished Jul 02 09:45:51 AM PDT 24
Peak memory 200416 kb
Host smart-6e23e86f-609f-484d-a2fe-904c659b66e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972271620 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_long_msg.2972271620
Directory /workspace/8.hmac_long_msg/latest

Test location /workspace/coverage/default/8.hmac_smoke.242961756
Short name T465
Test name
Test status
Simulation time 496129106 ps
CPU time 8.47 seconds
Started Jul 02 09:42:48 AM PDT 24
Finished Jul 02 09:42:57 AM PDT 24
Peak memory 200432 kb
Host smart-677aca7c-099c-4eae-96a2-af9eb8efb82f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=242961756 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_smoke.242961756
Directory /workspace/8.hmac_smoke/latest

Test location /workspace/coverage/default/8.hmac_stress_all.1149294166
Short name T78
Test name
Test status
Simulation time 10292622986 ps
CPU time 131.38 seconds
Started Jul 02 09:42:48 AM PDT 24
Finished Jul 02 09:45:01 AM PDT 24
Peak memory 208632 kb
Host smart-9773dcb5-d334-4833-8898-e8e529e69ebe
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149294166 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all.1149294166
Directory /workspace/8.hmac_stress_all/latest

Test location /workspace/coverage/default/8.hmac_stress_all_with_rand_reset.999583719
Short name T73
Test name
Test status
Simulation time 38141642499 ps
CPU time 4557.51 seconds
Started Jul 02 09:42:47 AM PDT 24
Finished Jul 02 10:58:46 AM PDT 24
Peak memory 848540 kb
Host smart-418375e1-0116-459e-b43f-436b66c3bcf1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=999583719 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all_with_rand_reset.999583719
Directory /workspace/8.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.hmac_wipe_secret.4155548305
Short name T513
Test name
Test status
Simulation time 36788517095 ps
CPU time 90.75 seconds
Started Jul 02 09:42:45 AM PDT 24
Finished Jul 02 09:44:16 AM PDT 24
Peak memory 200404 kb
Host smart-4d944fec-9db3-48f0-82e9-118cb32f3eb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155548305 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_wipe_secret.4155548305
Directory /workspace/8.hmac_wipe_secret/latest

Test location /workspace/coverage/default/9.hmac_alert_test.2610437043
Short name T400
Test name
Test status
Simulation time 16362659 ps
CPU time 0.58 seconds
Started Jul 02 09:42:50 AM PDT 24
Finished Jul 02 09:42:52 AM PDT 24
Peak memory 196212 kb
Host smart-ea11263c-1609-404e-8891-696dd570d3ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610437043 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_alert_test.2610437043
Directory /workspace/9.hmac_alert_test/latest

Test location /workspace/coverage/default/9.hmac_back_pressure.3835090340
Short name T309
Test name
Test status
Simulation time 2987077426 ps
CPU time 41.23 seconds
Started Jul 02 09:42:51 AM PDT 24
Finished Jul 02 09:43:34 AM PDT 24
Peak memory 200400 kb
Host smart-95326470-65df-4219-ada8-58252a69be80
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3835090340 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_back_pressure.3835090340
Directory /workspace/9.hmac_back_pressure/latest

Test location /workspace/coverage/default/9.hmac_burst_wr.3152840133
Short name T492
Test name
Test status
Simulation time 5093362084 ps
CPU time 54.88 seconds
Started Jul 02 09:42:50 AM PDT 24
Finished Jul 02 09:43:46 AM PDT 24
Peak memory 216628 kb
Host smart-86fcb014-16b8-4787-95eb-74241b0190e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152840133 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_burst_wr.3152840133
Directory /workspace/9.hmac_burst_wr/latest

Test location /workspace/coverage/default/9.hmac_datapath_stress.3945941137
Short name T373
Test name
Test status
Simulation time 3433707072 ps
CPU time 744.55 seconds
Started Jul 02 09:42:50 AM PDT 24
Finished Jul 02 09:55:16 AM PDT 24
Peak memory 700476 kb
Host smart-d3296598-72c8-4e00-befc-345e4869ec2a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3945941137 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_datapath_stress.3945941137
Directory /workspace/9.hmac_datapath_stress/latest

Test location /workspace/coverage/default/9.hmac_error.1663197122
Short name T32
Test name
Test status
Simulation time 5665966439 ps
CPU time 75.74 seconds
Started Jul 02 09:42:49 AM PDT 24
Finished Jul 02 09:44:06 AM PDT 24
Peak memory 200416 kb
Host smart-fd13d427-188d-40ac-b577-d44c3d9216f6
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663197122 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_error.1663197122
Directory /workspace/9.hmac_error/latest

Test location /workspace/coverage/default/9.hmac_long_msg.2498560998
Short name T273
Test name
Test status
Simulation time 30950702835 ps
CPU time 135.84 seconds
Started Jul 02 09:42:49 AM PDT 24
Finished Jul 02 09:45:06 AM PDT 24
Peak memory 200448 kb
Host smart-53504051-dbaa-4d04-a1c5-e2c1450eb3ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498560998 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_long_msg.2498560998
Directory /workspace/9.hmac_long_msg/latest

Test location /workspace/coverage/default/9.hmac_smoke.2196927099
Short name T454
Test name
Test status
Simulation time 2070301412 ps
CPU time 7.26 seconds
Started Jul 02 09:42:46 AM PDT 24
Finished Jul 02 09:42:54 AM PDT 24
Peak memory 200424 kb
Host smart-daea793d-145f-4fdb-8a8b-afd1dae854bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196927099 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_smoke.2196927099
Directory /workspace/9.hmac_smoke/latest

Test location /workspace/coverage/default/9.hmac_stress_all.193399772
Short name T439
Test name
Test status
Simulation time 278365814315 ps
CPU time 801.06 seconds
Started Jul 02 09:42:49 AM PDT 24
Finished Jul 02 09:56:12 AM PDT 24
Peak memory 216860 kb
Host smart-180cd5a3-a821-4a5a-b4c5-4e54ea1ddf35
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193399772 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all.193399772
Directory /workspace/9.hmac_stress_all/latest

Test location /workspace/coverage/default/9.hmac_wipe_secret.3672245951
Short name T412
Test name
Test status
Simulation time 571893769 ps
CPU time 23.77 seconds
Started Jul 02 09:42:56 AM PDT 24
Finished Jul 02 09:43:21 AM PDT 24
Peak memory 200356 kb
Host smart-bc201875-49e1-46f0-89e7-c55a46417b21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672245951 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_wipe_secret.3672245951
Directory /workspace/9.hmac_wipe_secret/latest
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