Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	18908200	1			T1	81448		T2	441364		T3	52357
all_values[1]	18908200	1			T1	81448		T2	441364		T3	52357
all_values[2]	18908200	1			T1	81448		T2	441364		T3	52357

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

329749

1

T1

5966

T3

901

T14

6202

auto[1]

56394851

1

T1

238378

T2

132409

T3

156170

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

48255078

1

T1

210215

T2

117742

T3

136286

auto[1]

8469522

1

T1

34129

T2

146667

T3

20785

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	92449	1			T3	5		T22	1260		T27	1
all_values[0]	auto[0]	auto[1]	387	1			T22	6		T25	12		T45	2
all_values[0]	auto[1]	auto[0]	18794451	1			T1	81332		T2	440978		T3	52269
all_values[0]	auto[1]	auto[1]	20913	1			T1	116		T2	386		T3	83
all_values[1]	auto[0]	auto[0]	138911	1			T1	5966		T3	885		T4	45
all_values[1]	auto[0]	auto[1]	188	1			T3	1		T22	6		T25	5
all_values[1]	auto[1]	auto[0]	18768762	1			T1	75482		T2	441364		T3	51469
all_values[1]	auto[1]	auto[1]	339	1			T3	2		T22	14		T27	1
all_values[2]	auto[0]	auto[0]	55291	1			T3	8		T14	1546		T22	68
all_values[2]	auto[0]	auto[1]	42523	1			T3	2		T14	4656		T22	5
all_values[2]	auto[1]	auto[0]	10405214	1			T1	47435		T2	295083		T3	31650
all_values[2]	auto[1]	auto[1]	8405172	1			T1	34013		T2	146281		T3	20697