Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::msg_len_cg

Group : hmac_env_pkg::hmac_env_cov::msg_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
94.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	1	17	94.44
Crosses	32	2	30	93.75

Variables for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
hmac_en	2	0	2	100.00	100	1	1	2
msg_len_lower_cp	15	0	15	100.00	100	1	1	0
msg_len_upper_cp	1	1	0	0.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
msg_len_lower_cross	30	0	30	100.00	100	1	1	0
msg_len_upper_cross	2	2	0	0.00	100	1	1	0

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

145219

1

T1

2064

T2

338

T3

90

auto[1]

142530

1

T1

684

T3

70

T5

24

---

Summary for Variable msg_len_lower_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for msg_len_lower_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_2050_plus	109337	1			T1	983		T2	54		T3	55
len_1026_2046	7169	1			T1	322		T2	1		T5	3
len_514_1022	3439	1			T1	14		T2	57		T4	6
len_2_510	4849	1			T1	9		T2	49		T3	6
len_2056	261	1			T22	2		T27	3		T99	7
len_2048	347	1			T1	5		T3	1		T4	1
len_2040	392	1			T4	111		T16	1		T138	2
len_1032	318	1			T14	1		T138	3		T22	3
len_1024	1797	1			T1	3		T3	3		T4	1
len_1016	309	1			T1	5		T2	2		T138	3
len_520	218	1			T1	3		T2	2		T16	3
len_512	361	1			T1	1		T4	1		T16	4
len_504	260	1			T1	1		T2	1		T16	2
len_8	920	1			T1	3		T2	2		T14	16
len_0	13897	1			T1	25		T2	1		T3	15

---

Summary for Variable msg_len_upper_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	1	0	0.00

User Defined Bins for msg_len_upper_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
len_upper	0	1	1

---

Summary for Cross msg_len_lower_cross

Samples crossed: hmac_en msg_len_lower_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for msg_len_lower_cross

Bins

hmac_en	msg_len_lower_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	len_2050_plus	56975	1			T1	687		T2	54		T3	27
auto[0]	len_1026_2046	3707	1			T1	313		T2	1		T5	2
auto[0]	len_514_1022	1903	1			T1	8		T2	57		T4	6
auto[0]	len_2_510	2115	1			T1	6		T2	49		T3	5
auto[0]	len_2056	120	1			T22	2		T27	3		T99	3
auto[0]	len_2048	197	1			T1	3		T3	1		T4	1
auto[0]	len_2040	207	1			T4	44		T138	2		T22	1
auto[0]	len_1032	209	1			T138	1		T22	2		T27	2
auto[0]	len_1024	244	1			T1	2		T3	3		T4	1
auto[0]	len_1016	160	1			T1	4		T2	2		T138	2
auto[0]	len_520	123	1			T2	2		T16	3		T27	6
auto[0]	len_512	206	1			T4	1		T16	3		T22	5
auto[0]	len_504	171	1			T1	1		T2	1		T16	1
auto[0]	len_8	31	1			T2	2		T90	5		T139	2
auto[0]	len_0	6241	1			T1	8		T2	1		T3	9
auto[1]	len_2050_plus	52362	1			T1	296		T3	28		T5	4
auto[1]	len_1026_2046	3462	1			T1	9		T5	1		T17	4
auto[1]	len_514_1022	1536	1			T1	6		T17	2		T60	1
auto[1]	len_2_510	2734	1			T1	3		T3	1		T5	2
auto[1]	len_2056	141	1			T99	4		T45	4		T6	2
auto[1]	len_2048	150	1			T1	2		T61	1		T134	1
auto[1]	len_2040	185	1			T4	67		T16	1		T22	1
auto[1]	len_1032	109	1			T14	1		T138	2		T22	1
auto[1]	len_1024	1553	1			T1	1		T16	1		T18	62
auto[1]	len_1016	149	1			T1	1		T138	1		T22	3
auto[1]	len_520	95	1			T1	3		T22	1		T99	4
auto[1]	len_512	155	1			T1	1		T16	1		T22	1
auto[1]	len_504	89	1			T16	1		T27	5		T99	4
auto[1]	len_8	889	1			T1	3		T14	16		T59	3
auto[1]	len_0	7656	1			T1	17		T3	6		T5	5

---

Summary for Cross msg_len_upper_cross

Samples crossed: hmac_en msg_len_upper_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	2	2	0	0.00	2

Automatically Generated Cross Bins for msg_len_upper_cross

Uncovered bins

hmac_en	msg_len_upper_cp	COUNT	AT LEAST	NUMBER	STATUS
*	*	--	--	2