Group : hmac_env_pkg::hmac_env_cov::status_cg
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Group : hmac_env_pkg::hmac_env_cov::status_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv


Summary for Group hmac_env_pkg::hmac_env_cov::status_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 20 0 20 100.00
Crosses 192 0 192 100.00


Variables for Group hmac_env_pkg::hmac_env_cov::status_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
digest_swap 2 0 2 100.00 100 1 1 2
endian_swap 2 0 2 100.00 100 1 1 2
hmac_en 2 0 2 100.00 100 1 1 2
key_swap 2 0 2 100.00 100 1 1 2
sta_fifo_depth 8 0 8 100.00 100 1 1 0
sta_fifo_empty 2 0 2 100.00 100 1 1 2
sta_fifo_full 2 0 2 100.00 100 1 1 2


Crosses for Group hmac_env_pkg::hmac_env_cov::status_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
fifo_empty_cross 32 0 32 100.00 100 1 1 0
fifo_full_cross 32 0 32 100.00 100 1 1 0
fifo_depth_cross 128 0 128 100.00 100 1 1 0


Summary for Variable digest_swap

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for digest_swap

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 4702284 1 T1 18940 T2 147680 T3 10282
auto[1] 2939003 1 T1 15536 T3 12029 T5 3445


Summary for Variable endian_swap

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for endian_swap

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 2919785 1 T1 19085 T3 10589 T5 4128
auto[1] 4721502 1 T1 15391 T2 147680 T3 11722


Summary for Variable hmac_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for hmac_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3507623 1 T1 18380 T2 147680 T3 12829
auto[1] 4133664 1 T1 16096 T3 9482 T5 3353


Summary for Variable key_swap

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for key_swap

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 4662883 1 T1 20413 T2 147680 T3 9859
auto[1] 2978404 1 T1 14063 T3 12452 T5 2019


Summary for Variable sta_fifo_depth

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 8 0 8 100.00


User Defined Bins for sta_fifo_depth

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
fifo_depth[0] 6938058 1 T1 33347 T2 144040 T3 19263
fifo_depth[1] 121325 1 T1 519 T2 2650 T3 475
fifo_depth[2] 91013 1 T1 295 T2 777 T3 496
fifo_depth[3] 71472 1 T1 123 T2 183 T3 501
fifo_depth[4] 63926 1 T1 116 T2 23 T3 449
fifo_depth[5] 51332 1 T1 20 T2 6 T3 409
fifo_depth[6] 40386 1 T1 20 T2 1 T3 311
fifo_depth[7] 26861 1 T1 11 T3 211 T5 13


Summary for Variable sta_fifo_empty

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sta_fifo_empty

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 703229 1 T1 1129 T2 3640 T3 3048
auto[1] 6938058 1 T1 33347 T2 144040 T3 19263


Summary for Variable sta_fifo_full

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sta_fifo_full

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 7630688 1 T1 34476 T2 147680 T3 22311
auto[1] 10599 1 T22 269 T25 1131 T21 109


Summary for Cross fifo_empty_cross

Samples crossed: sta_fifo_empty hmac_en endian_swap digest_swap key_swap
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 32 0 32 100.00


Automatically Generated Cross Bins for fifo_empty_cross

Bins
sta_fifo_emptyhmac_enendian_swapdigest_swapkey_swapCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] 31498 1 T1 195 T3 47 T4 30
auto[0] auto[0] auto[0] auto[0] auto[1] 37069 1 T1 23 T3 354 T4 75
auto[0] auto[0] auto[0] auto[1] auto[0] 34710 1 T1 185 T3 47 T60 119
auto[0] auto[0] auto[0] auto[1] auto[1] 34767 1 T1 44 T3 119 T5 115
auto[0] auto[0] auto[1] auto[0] auto[0] 154312 1 T1 35 T2 3640 T3 199
auto[0] auto[0] auto[1] auto[0] auto[1] 37191 1 T1 42 T3 160 T15 1
auto[0] auto[0] auto[1] auto[1] auto[0] 27552 1 T1 97 T3 401 T60 212
auto[0] auto[0] auto[1] auto[1] auto[1] 34495 1 T1 37 T3 377 T4 24
auto[0] auto[1] auto[0] auto[0] auto[0] 39674 1 T1 77 T3 172 T60 12
auto[0] auto[1] auto[0] auto[0] auto[1] 38527 1 T1 5 T3 134 T14 210
auto[0] auto[1] auto[0] auto[1] auto[0] 39633 1 T3 5 T5 51 T60 79
auto[0] auto[1] auto[0] auto[1] auto[1] 32837 1 T1 98 T3 396 T14 265
auto[0] auto[1] auto[1] auto[0] auto[0] 40580 1 T1 282 T3 213 T14 207
auto[0] auto[1] auto[1] auto[0] auto[1] 47525 1 T1 5 T3 124 T5 5
auto[0] auto[1] auto[1] auto[1] auto[0] 39900 1 T1 4 T3 75 T16 1
auto[0] auto[1] auto[1] auto[1] auto[1] 32959 1 T3 225 T5 118 T61 1
auto[1] auto[0] auto[0] auto[0] auto[0] 188439 1 T1 4544 T3 361 T5 401
auto[1] auto[0] auto[0] auto[0] auto[1] 189322 1 T1 1180 T3 1808 T4 117
auto[1] auto[0] auto[0] auto[1] auto[0] 187178 1 T1 2809 T3 1448 T15 1
auto[1] auto[0] auto[0] auto[1] auto[1] 209450 1 T1 2545 T3 622 T5 1207
auto[1] auto[0] auto[1] auto[0] auto[0] 1735970 1 T1 529 T2 144040 T3 2209
auto[1] auto[0] auto[1] auto[0] auto[1] 204279 1 T1 1742 T3 1101 T15 2
auto[1] auto[0] auto[1] auto[1] auto[0] 194136 1 T1 2732 T3 1680 T5 337
auto[1] auto[0] auto[1] auto[1] auto[1] 207255 1 T1 1641 T3 1896 T4 176
auto[1] auto[1] auto[0] auto[0] auto[0] 455105 1 T1 2695 T3 925 T5 984
auto[1] auto[1] auto[0] auto[0] auto[1] 447715 1 T1 509 T3 980 T5 333
auto[1] auto[1] auto[0] auto[1] auto[0] 485318 1 T1 1044 T3 227 T5 1037
auto[1] auto[1] auto[0] auto[1] auto[1] 468543 1 T1 3132 T3 2944 T14 11948
auto[1] auto[1] auto[1] auto[0] auto[0] 553484 1 T1 5136 T3 1257 T5 206
auto[1] auto[1] auto[1] auto[0] auto[1] 501594 1 T1 1941 T3 238 T5 39
auto[1] auto[1] auto[1] auto[1] auto[0] 455394 1 T1 49 T3 593 T5 378
auto[1] auto[1] auto[1] auto[1] auto[1] 454876 1 T1 1119 T3 974 T5 202


Summary for Cross fifo_full_cross

Samples crossed: sta_fifo_full hmac_en endian_swap digest_swap key_swap
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 32 0 32 100.00


Automatically Generated Cross Bins for fifo_full_cross

Bins
sta_fifo_fullhmac_enendian_swapdigest_swapkey_swapCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] 218945 1 T1 4739 T3 408 T5 401
auto[0] auto[0] auto[0] auto[0] auto[1] 224835 1 T1 1203 T3 2162 T4 192
auto[0] auto[0] auto[0] auto[1] auto[0] 220809 1 T1 2994 T3 1495 T15 1
auto[0] auto[0] auto[0] auto[1] auto[1] 243625 1 T1 2589 T3 741 T5 1322
auto[0] auto[0] auto[1] auto[0] auto[0] 1889352 1 T1 564 T2 147680 T3 2408
auto[0] auto[0] auto[1] auto[0] auto[1] 240321 1 T1 1784 T3 1261 T15 3
auto[0] auto[0] auto[1] auto[1] auto[0] 220987 1 T1 2829 T3 2081 T5 337
auto[0] auto[0] auto[1] auto[1] auto[1] 240893 1 T1 1678 T3 2273 T4 200
auto[0] auto[1] auto[0] auto[0] auto[0] 493765 1 T1 2772 T3 1097 T5 984
auto[0] auto[1] auto[0] auto[0] auto[1] 485967 1 T1 514 T3 1114 T5 333
auto[0] auto[1] auto[0] auto[1] auto[0] 524425 1 T1 1044 T3 232 T5 1088
auto[0] auto[1] auto[0] auto[1] auto[1] 501273 1 T1 3230 T3 3340 T14 12213
auto[0] auto[1] auto[1] auto[0] auto[0] 593987 1 T1 5418 T3 1470 T5 206
auto[0] auto[1] auto[1] auto[0] auto[1] 548796 1 T1 1946 T3 362 T5 44
auto[0] auto[1] auto[1] auto[1] auto[0] 495032 1 T1 53 T3 668 T5 378
auto[0] auto[1] auto[1] auto[1] auto[1] 487676 1 T1 1119 T3 1199 T5 320
auto[1] auto[0] auto[0] auto[0] auto[0] 992 1 T25 147 T57 22 T153 10
auto[1] auto[0] auto[0] auto[0] auto[1] 1556 1 T22 6 T21 80 T56 2
auto[1] auto[0] auto[0] auto[1] auto[0] 1079 1 T21 1 T154 3 T56 256
auto[1] auto[0] auto[0] auto[1] auto[1] 592 1 T21 2 T56 9 T33 2
auto[1] auto[0] auto[1] auto[0] auto[0] 930 1 T22 8 T25 12 T56 1
auto[1] auto[0] auto[1] auto[0] auto[1] 1149 1 T22 160 T25 184 T21 7
auto[1] auto[0] auto[1] auto[1] auto[0] 701 1 T22 19 T25 220 T154 13
auto[1] auto[0] auto[1] auto[1] auto[1] 857 1 T22 18 T25 24 T57 30
auto[1] auto[1] auto[0] auto[0] auto[0] 1014 1 T25 544 T56 20 T33 45
auto[1] auto[1] auto[0] auto[0] auto[1] 275 1 T57 24 T153 9 T155 24
auto[1] auto[1] auto[0] auto[1] auto[0] 526 1 T22 13 T153 368 T156 7
auto[1] auto[1] auto[0] auto[1] auto[1] 107 1 T21 19 T156 8 T157 5
auto[1] auto[1] auto[1] auto[0] auto[0] 77 1 T158 3 T159 9 T108 11
auto[1] auto[1] auto[1] auto[0] auto[1] 323 1 T22 1 T156 8 T155 1
auto[1] auto[1] auto[1] auto[1] auto[0] 262 1 T22 44 T56 13 T57 13
auto[1] auto[1] auto[1] auto[1] auto[1] 159 1 T155 10 T160 1 T108 58


Summary for Cross fifo_depth_cross

Samples crossed: sta_fifo_depth hmac_en endian_swap digest_swap key_swap
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 128 0 128 100.00


Automatically Generated Cross Bins for fifo_depth_cross

Bins
sta_fifo_depthhmac_enendian_swapdigest_swapkey_swapCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
fifo_depth[0] auto[0] auto[0] auto[0] auto[0] 188439 1 T1 4544 T3 361 T5 401
fifo_depth[0] auto[0] auto[0] auto[0] auto[1] 189322 1 T1 1180 T3 1808 T4 117
fifo_depth[0] auto[0] auto[0] auto[1] auto[0] 187178 1 T1 2809 T3 1448 T15 1
fifo_depth[0] auto[0] auto[0] auto[1] auto[1] 209450 1 T1 2545 T3 622 T5 1207
fifo_depth[0] auto[0] auto[1] auto[0] auto[0] 1735970 1 T1 529 T2 144040 T3 2209
fifo_depth[0] auto[0] auto[1] auto[0] auto[1] 204279 1 T1 1742 T3 1101 T15 2
fifo_depth[0] auto[0] auto[1] auto[1] auto[0] 194136 1 T1 2732 T3 1680 T5 337
fifo_depth[0] auto[0] auto[1] auto[1] auto[1] 207255 1 T1 1641 T3 1896 T4 176
fifo_depth[0] auto[1] auto[0] auto[0] auto[0] 455105 1 T1 2695 T3 925 T5 984
fifo_depth[0] auto[1] auto[0] auto[0] auto[1] 447715 1 T1 509 T3 980 T5 333
fifo_depth[0] auto[1] auto[0] auto[1] auto[0] 485318 1 T1 1044 T3 227 T5 1037
fifo_depth[0] auto[1] auto[0] auto[1] auto[1] 468543 1 T1 3132 T3 2944 T14 11948
fifo_depth[0] auto[1] auto[1] auto[0] auto[0] 553484 1 T1 5136 T3 1257 T5 206
fifo_depth[0] auto[1] auto[1] auto[0] auto[1] 501594 1 T1 1941 T3 238 T5 39
fifo_depth[0] auto[1] auto[1] auto[1] auto[0] 455394 1 T1 49 T3 593 T5 378
fifo_depth[0] auto[1] auto[1] auto[1] auto[1] 454876 1 T1 1119 T3 974 T5 202
fifo_depth[1] auto[0] auto[0] auto[0] auto[0] 3565 1 T1 31 T3 8 T4 1
fifo_depth[1] auto[0] auto[0] auto[0] auto[1] 3641 1 T1 13 T3 52 T4 2
fifo_depth[1] auto[0] auto[0] auto[1] auto[0] 3391 1 T1 87 T3 6 T60 24
fifo_depth[1] auto[0] auto[0] auto[1] auto[1] 3905 1 T1 22 T3 21 T5 23
fifo_depth[1] auto[0] auto[1] auto[0] auto[0] 43618 1 T1 17 T2 2650 T3 31
fifo_depth[1] auto[0] auto[1] auto[0] auto[1] 4645 1 T1 15 T3 18 T60 1
fifo_depth[1] auto[0] auto[1] auto[1] auto[0] 3330 1 T1 52 T3 64 T60 42
fifo_depth[1] auto[0] auto[1] auto[1] auto[1] 4529 1 T1 20 T3 59 T4 5
fifo_depth[1] auto[1] auto[0] auto[0] auto[0] 6318 1 T1 42 T3 27 T60 1
fifo_depth[1] auto[1] auto[0] auto[0] auto[1] 5728 1 T1 3 T3 25 T14 41
fifo_depth[1] auto[1] auto[0] auto[1] auto[0] 5923 1 T3 1 T5 7 T60 16
fifo_depth[1] auto[1] auto[0] auto[1] auto[1] 5269 1 T1 43 T3 65 T14 34
fifo_depth[1] auto[1] auto[1] auto[0] auto[0] 8482 1 T1 169 T3 34 T14 29
fifo_depth[1] auto[1] auto[1] auto[0] auto[1] 6897 1 T1 2 T3 21 T5 1
fifo_depth[1] auto[1] auto[1] auto[1] auto[0] 6342 1 T1 3 T3 9 T16 1
fifo_depth[1] auto[1] auto[1] auto[1] auto[1] 5742 1 T3 34 T5 21 T22 21
fifo_depth[2] auto[0] auto[0] auto[0] auto[0] 2806 1 T1 31 T3 7 T4 29
fifo_depth[2] auto[0] auto[0] auto[0] auto[1] 2602 1 T1 3 T3 52 T4 25
fifo_depth[2] auto[0] auto[0] auto[1] auto[0] 2572 1 T1 50 T3 7 T60 20
fifo_depth[2] auto[0] auto[0] auto[1] auto[1] 2878 1 T1 14 T3 16 T5 21
fifo_depth[2] auto[0] auto[1] auto[0] auto[0] 29472 1 T1 10 T2 777 T3 33
fifo_depth[2] auto[0] auto[1] auto[0] auto[1] 3538 1 T1 12 T3 18 T60 2
fifo_depth[2] auto[0] auto[1] auto[1] auto[0] 2504 1 T1 25 T3 80 T60 23
fifo_depth[2] auto[0] auto[1] auto[1] auto[1] 3679 1 T1 6 T3 55 T4 4
fifo_depth[2] auto[1] auto[0] auto[0] auto[0] 5112 1 T1 27 T3 24 T60 1
fifo_depth[2] auto[1] auto[0] auto[0] auto[1] 4658 1 T1 2 T3 24 T14 38
fifo_depth[2] auto[1] auto[0] auto[1] auto[0] 4905 1 T3 2 T5 8 T60 10
fifo_depth[2] auto[1] auto[0] auto[1] auto[1] 4337 1 T1 37 T3 70 T14 40
fifo_depth[2] auto[1] auto[1] auto[0] auto[0] 6274 1 T1 75 T3 37 T14 30
fifo_depth[2] auto[1] auto[1] auto[0] auto[1] 5674 1 T1 2 T3 30 T14 266
fifo_depth[2] auto[1] auto[1] auto[1] auto[0] 5376 1 T1 1 T3 12 T17 2
fifo_depth[2] auto[1] auto[1] auto[1] auto[1] 4626 1 T3 29 T5 23 T61 1
fifo_depth[3] auto[0] auto[0] auto[0] auto[0] 2180 1 T1 23 T3 3 T17 3
fifo_depth[3] auto[0] auto[0] auto[0] auto[1] 2041 1 T3 55 T4 2 T22 116
fifo_depth[3] auto[0] auto[0] auto[1] auto[0] 1849 1 T1 30 T3 7 T60 20
fifo_depth[3] auto[0] auto[0] auto[1] auto[1] 2230 1 T1 3 T3 17 T5 19
fifo_depth[3] auto[0] auto[1] auto[0] auto[0] 21504 1 T1 2 T2 183 T3 41
fifo_depth[3] auto[0] auto[1] auto[0] auto[1] 3032 1 T1 6 T3 27 T60 4
fifo_depth[3] auto[0] auto[1] auto[1] auto[0] 1926 1 T1 8 T3 68 T60 38
fifo_depth[3] auto[0] auto[1] auto[1] auto[1] 2790 1 T1 8 T3 62 T4 4
fifo_depth[3] auto[1] auto[0] auto[0] auto[0] 4334 1 T1 6 T3 31 T60 2
fifo_depth[3] auto[1] auto[0] auto[0] auto[1] 3741 1 T3 24 T14 42 T60 8
fifo_depth[3] auto[1] auto[0] auto[1] auto[0] 4051 1 T3 2 T5 8 T60 12
fifo_depth[3] auto[1] auto[0] auto[1] auto[1] 3407 1 T1 13 T3 56 T14 39
fifo_depth[3] auto[1] auto[1] auto[0] auto[0] 5040 1 T1 23 T3 36 T14 34
fifo_depth[3] auto[1] auto[1] auto[0] auto[1] 4956 1 T1 1 T3 29 T14 274
fifo_depth[3] auto[1] auto[1] auto[1] auto[0] 4439 1 T3 13 T17 4 T62 4
fifo_depth[3] auto[1] auto[1] auto[1] auto[1] 3952 1 T3 30 T5 19 T22 18
fifo_depth[4] auto[0] auto[0] auto[0] auto[0] 2162 1 T1 71 T3 5 T17 4
fifo_depth[4] auto[0] auto[0] auto[0] auto[1] 1967 1 T1 3 T3 54 T4 25
fifo_depth[4] auto[0] auto[0] auto[1] auto[0] 1669 1 T1 15 T3 4 T60 16
fifo_depth[4] auto[0] auto[0] auto[1] auto[1] 2221 1 T1 2 T3 17 T5 22
fifo_depth[4] auto[0] auto[1] auto[0] auto[0] 16118 1 T1 2 T2 23 T3 29
fifo_depth[4] auto[0] auto[1] auto[0] auto[1] 2908 1 T1 3 T3 20 T60 2
fifo_depth[4] auto[0] auto[1] auto[1] auto[0] 1816 1 T1 7 T3 65 T60 33
fifo_depth[4] auto[0] auto[1] auto[1] auto[1] 2765 1 T1 2 T3 59 T4 4
fifo_depth[4] auto[1] auto[0] auto[0] auto[0] 4077 1 T1 2 T3 30 T60 1
fifo_depth[4] auto[1] auto[0] auto[0] auto[1] 3747 1 T3 21 T14 39 T60 4
fifo_depth[4] auto[1] auto[0] auto[1] auto[0] 4077 1 T5 12 T60 7 T22 17
fifo_depth[4] auto[1] auto[0] auto[1] auto[1] 3267 1 T1 4 T3 55 T14 46
fifo_depth[4] auto[1] auto[1] auto[0] auto[0] 4416 1 T1 5 T3 33 T14 28
fifo_depth[4] auto[1] auto[1] auto[0] auto[1] 4784 1 T3 15 T14 293 T16 1
fifo_depth[4] auto[1] auto[1] auto[1] auto[0] 4111 1 T3 13 T17 2 T62 3
fifo_depth[4] auto[1] auto[1] auto[1] auto[1] 3821 1 T3 29 T5 18 T22 6
fifo_depth[5] auto[0] auto[0] auto[0] auto[0] 1653 1 T1 10 T3 8 T17 2
fifo_depth[5] auto[0] auto[0] auto[0] auto[1] 1630 1 T3 43 T4 3 T22 103
fifo_depth[5] auto[0] auto[0] auto[1] auto[0] 1272 1 T1 3 T3 5 T60 12
fifo_depth[5] auto[0] auto[0] auto[1] auto[1] 1736 1 T1 1 T3 16 T5 13
fifo_depth[5] auto[0] auto[1] auto[0] auto[0] 11587 1 T2 6 T3 28 T138 1
fifo_depth[5] auto[0] auto[1] auto[0] auto[1] 2383 1 T1 1 T3 25 T60 1
fifo_depth[5] auto[0] auto[1] auto[1] auto[0] 1403 1 T1 1 T3 49 T60 36
fifo_depth[5] auto[0] auto[1] auto[1] auto[1] 2097 1 T1 1 T3 62 T4 1
fifo_depth[5] auto[1] auto[0] auto[0] auto[0] 3392 1 T3 18 T59 31 T133 13
fifo_depth[5] auto[1] auto[0] auto[0] auto[1] 3010 1 T3 17 T14 24 T60 3
fifo_depth[5] auto[1] auto[0] auto[1] auto[0] 3488 1 T5 7 T60 10 T22 17
fifo_depth[5] auto[1] auto[0] auto[1] auto[1] 2847 1 T1 1 T3 51 T14 33
fifo_depth[5] auto[1] auto[1] auto[0] auto[0] 3871 1 T1 2 T3 33 T14 23
fifo_depth[5] auto[1] auto[1] auto[0] auto[1] 3983 1 T3 10 T5 3 T14 220
fifo_depth[5] auto[1] auto[1] auto[1] auto[0] 3696 1 T3 13 T17 2 T62 5
fifo_depth[5] auto[1] auto[1] auto[1] auto[1] 3284 1 T3 31 T5 20 T22 10
fifo_depth[6] auto[0] auto[0] auto[0] auto[0] 1352 1 T1 6 T3 5 T17 1
fifo_depth[6] auto[0] auto[0] auto[0] auto[1] 1294 1 T1 2 T3 32 T4 9
fifo_depth[6] auto[0] auto[0] auto[1] auto[0] 1101 1 T3 7 T60 15 T22 23
fifo_depth[6] auto[0] auto[0] auto[1] auto[1] 1509 1 T3 15 T5 7 T4 1
fifo_depth[6] auto[0] auto[1] auto[0] auto[0] 8179 1 T1 2 T2 1 T3 19
fifo_depth[6] auto[0] auto[1] auto[0] auto[1] 1804 1 T1 4 T3 23 T22 95
fifo_depth[6] auto[0] auto[1] auto[1] auto[0] 1164 1 T1 3 T3 41 T60 22
fifo_depth[6] auto[0] auto[1] auto[1] auto[1] 1519 1 T3 43 T4 1 T60 15
fifo_depth[6] auto[1] auto[0] auto[0] auto[0] 2670 1 T3 12 T22 1 T59 17
fifo_depth[6] auto[1] auto[0] auto[0] auto[1] 2556 1 T3 13 T14 12 T60 2
fifo_depth[6] auto[1] auto[0] auto[1] auto[0] 2728 1 T5 3 T60 7 T22 14
fifo_depth[6] auto[1] auto[0] auto[1] auto[1] 2280 1 T3 35 T14 27 T22 67
fifo_depth[6] auto[1] auto[1] auto[0] auto[0] 3055 1 T1 3 T3 18 T14 23
fifo_depth[6] auto[1] auto[1] auto[0] auto[1] 3267 1 T3 10 T14 178 T62 11
fifo_depth[6] auto[1] auto[1] auto[1] auto[0] 3088 1 T3 6 T17 4 T138 1
fifo_depth[6] auto[1] auto[1] auto[1] auto[1] 2820 1 T3 32 T5 12 T22 11
fifo_depth[7] auto[0] auto[0] auto[0] auto[0] 978 1 T1 8 T3 4 T17 1
fifo_depth[7] auto[0] auto[0] auto[0] auto[1] 1031 1 T3 31 T4 1 T22 42
fifo_depth[7] auto[0] auto[0] auto[1] auto[0] 906 1 T3 8 T60 10 T22 19
fifo_depth[7] auto[0] auto[0] auto[1] auto[1] 1046 1 T1 1 T3 8 T5 6
fifo_depth[7] auto[0] auto[1] auto[0] auto[0] 4994 1 T3 14 T138 1 T63 28
fifo_depth[7] auto[0] auto[1] auto[0] auto[1] 1177 1 T1 1 T3 14 T22 69
fifo_depth[7] auto[0] auto[1] auto[1] auto[0] 790 1 T3 19 T60 12 T63 1
fifo_depth[7] auto[0] auto[1] auto[1] auto[1] 948 1 T3 19 T4 2 T60 6
fifo_depth[7] auto[1] auto[0] auto[0] auto[0] 1728 1 T3 16 T60 3 T61 1
fifo_depth[7] auto[1] auto[0] auto[0] auto[1] 1701 1 T3 6 T14 11 T60 8
fifo_depth[7] auto[1] auto[0] auto[1] auto[0] 1848 1 T5 2 T60 7 T22 10
fifo_depth[7] auto[1] auto[0] auto[1] auto[1] 1616 1 T3 35 T14 18 T22 49
fifo_depth[7] auto[1] auto[1] auto[0] auto[0] 2033 1 T1 1 T3 9 T14 20
fifo_depth[7] auto[1] auto[1] auto[0] auto[1] 2255 1 T3 4 T5 1 T14 123
fifo_depth[7] auto[1] auto[1] auto[1] auto[0] 2053 1 T3 4 T17 2 T61 2
fifo_depth[7] auto[1] auto[1] auto[1] auto[1] 1757 1 T3 20 T5 4 T22 5

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