Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	18908200	1			T1	81448		T2	441364		T3	52357
all_pins[1]	18908200	1			T1	81448		T2	441364		T3	52357
all_pins[2]	18908200	1			T1	81448		T2	441364		T3	52357

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	48297291	1			T1	210212		T2	117742		T3	136277
values[0x1]	8427309	1			T1	34132		T2	146667		T3	20794
transitions[0x0=>0x1]	8427145	1			T1	34132		T2	146667		T3	20793
transitions[0x1=>0x0]	8427153	1			T1	34132		T2	146667		T3	20793

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	18886423	1			T1	81329		T2	440978		T3	52262
all_pins[0]	values[0x1]	21777	1			T1	119		T2	386		T3	95
all_pins[0]	transitions[0x0=>0x1]	21716	1			T1	119		T2	386		T3	95
all_pins[0]	transitions[0x1=>0x0]	8405119	1			T1	34013		T2	146281		T3	20697
all_pins[1]	values[0x0]	18907840	1			T1	81448		T2	441364		T3	52355
all_pins[1]	values[0x1]	360	1			T3	2		T22	14		T27	1
all_pins[1]	transitions[0x0=>0x1]	309	1			T3	1		T22	13		T25	4
all_pins[1]	transitions[0x1=>0x0]	21726	1			T1	119		T2	386		T3	94
all_pins[2]	values[0x0]	10503028	1			T1	47435		T2	295083		T3	31660
all_pins[2]	values[0x1]	8405172	1			T1	34013		T2	146281		T3	20697
all_pins[2]	transitions[0x0=>0x1]	8405120	1			T1	34013		T2	146281		T3	20697
all_pins[2]	transitions[0x1=>0x0]	308	1			T3	2		T22	11		T27	1