Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 0 18 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 0 18 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 1026 1 T3 11 T22 29 T27 4
all_values[1] 1026 1 T3 11 T22 29 T27 4
all_values[2] 1026 1 T3 11 T22 29 T27 4


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1497 1 T3 18 T22 36 T27 3
auto[1] 1581 1 T3 15 T22 51 T27 9


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1101 1 T3 14 T22 31 T27 6
auto[1] 1977 1 T3 19 T22 56 T27 6


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1762 1 T3 19 T22 50 T27 9
auto[1] 1316 1 T3 14 T22 37 T27 3


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 0 18 100.00
Automatically Generated Cross Bins 18 0 18 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 186 1 T3 2 T22 8 T27 1
all_values[0] auto[0] auto[0] auto[1] 107 1 T22 2 T25 1 T90 3
all_values[0] auto[0] auto[1] auto[0] 189 1 T22 9 T27 1 T25 3
all_values[0] auto[0] auto[1] auto[1] 106 1 T3 2 T22 1 T27 1
all_values[0] auto[1] auto[0] auto[1] 222 1 T3 2 T22 2 T25 6
all_values[0] auto[1] auto[1] auto[1] 216 1 T3 5 T22 7 T27 1
all_values[1] auto[0] auto[0] auto[0] 145 1 T3 3 T22 1 T25 3
all_values[1] auto[0] auto[0] auto[1] 123 1 T3 1 T22 5 T25 3
all_values[1] auto[0] auto[1] auto[0] 191 1 T3 3 T22 4 T27 2
all_values[1] auto[0] auto[1] auto[1] 148 1 T3 1 T22 3 T27 1
all_values[1] auto[1] auto[0] auto[1] 199 1 T3 2 T22 4 T25 7
all_values[1] auto[1] auto[1] auto[1] 220 1 T3 1 T22 12 T27 1
all_values[2] auto[0] auto[0] auto[0] 191 1 T3 4 T22 6 T25 8
all_values[2] auto[0] auto[0] auto[1] 94 1 T3 1 T22 2 T27 1
all_values[2] auto[0] auto[1] auto[0] 199 1 T3 2 T22 3 T27 2
all_values[2] auto[0] auto[1] auto[1] 83 1 T22 6 T25 2 T6 1
all_values[2] auto[1] auto[0] auto[1] 230 1 T3 3 T22 6 T27 1
all_values[2] auto[1] auto[1] auto[1] 229 1 T3 1 T22 6 T25 5


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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