Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::cfg_cg

Group : hmac_env_pkg::hmac_env_cov::cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	90	0	90	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_size	5	0	5	100.00	100	1	1	0
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	0
key_length	7	0	7	100.00	100	1	1	0
key_swap	2	0	2	100.00	100	1	1	2
sha_en	2	0	2	100.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cfg_cross	16	0	16	100.00	100	1	1	0
hmac_dis_x_sha_en	4	0	4	100.00	100	1	1	0
key_x_digest_mismatch	35	0	35	100.00	100	1	1	0
key_length_x_digest_size	35	0	35	100.00	100	1	1	0

Summary for Variable digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for digest_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sha2_invalid	4795	1			T1	39		T3	18		T5	7
sha2_none	4716	1			T1	36		T3	20		T5	4
sha2_512	8005	1			T1	42		T2	386		T3	22
sha2_384	7851	1			T1	41		T3	23		T5	4
sha2_256	6913	1			T1	45		T3	31		T5	5

---

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20126

1

T1

107

T2

386

T3

52

auto[1]

12569

1

T1

99

T3

64

T5

10

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

12484

1

T1

106

T3

49

T5

13

auto[1]

20211

1

T1

100

T2

386

T3

67

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

16700

1

T1

99

T3

49

T5

15

disabled

15995

1

T1

107

T2

386

T3

67

---

Summary for Variable key_length

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for key_length

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	5202	1			T1	37		T3	17		T5	4
key_none	8081	1			T1	33		T2	386		T3	18
key_1024	4620	1			T1	28		T3	13		T5	4
key_512	4201	1			T1	20		T3	15		T5	3
key_384	3714	1			T1	24		T3	22		T5	3
key_256	3494	1			T1	32		T3	14		T5	2
key_128	3298	1			T1	32		T3	17		T5	5

---

Summary for Variable key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for key_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20187

1

T1

116

T2

386

T3

58

auto[1]

12508

1

T1

90

T3

58

T5

11

---

Summary for Variable sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

32432

1

T1

206

T2

386

T3

116

disabled

263

1

T62

3

T63

3

T22

4

---

Summary for Cross cfg_cross

Samples crossed: hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cfg_cross

Bins

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

auto[0]

auto[0]

auto[0]

1815

1

T1

11

T3

4

T5

3

enabled

auto[0]

auto[0]

auto[1]

1670

1

T1

13

T3

5

T5

2

enabled

auto[0]

auto[1]

auto[0]

1653

1

T1

14

T3

3

T5

2

enabled

auto[0]

auto[1]

auto[1]

1774

1

T1

14

T3

10

T14

8

enabled

auto[1]

auto[0]

auto[0]

4437

1

T1

21

T3

7

T5

3

enabled

auto[1]

auto[0]

auto[1]

1775

1

T1

11

T3

2

T5

3

enabled

auto[1]

auto[1]

auto[0]

1866

1

T1

10

T3

11

T5

1

enabled

auto[1]

auto[1]

auto[1]

1710

1

T1

5

T3

7

T5

1

disabled

auto[0]

auto[0]

auto[0]

1430

1

T1

16

T3

3

T5

1

disabled

auto[0]

auto[0]

auto[1]

1366

1

T1

12

T3

10

T4

1

disabled

auto[0]

auto[1]

auto[0]

1350

1

T1

15

T3

7

T15

1

disabled

auto[0]

auto[1]

auto[1]

1426

1

T1

11

T3

7

T5

5

disabled

auto[1]

auto[0]

auto[0]

6207

1

T1

13

T2

386

T3

14

disabled

auto[1]

auto[0]

auto[1]

1426

1

T1

10

T3

7

T15

3

disabled

auto[1]

auto[1]

auto[0]

1429

1

T1

16

T3

9

T5

1

disabled

auto[1]

auto[1]

auto[1]

1361

1

T1

14

T3

10

T4

2

---

Summary for Cross hmac_dis_x_sha_en

Samples crossed: hmac_en sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	3	0	3	100.00
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for hmac_dis_x_sha_en

Bins

hmac_en

sha_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

enabled

16593

1

T1

99

T3

49

T5

15

enabled

disabled

107

1

T62

1

T22

2

T96

2

disabled

disabled

156

1

T62

2

T63

3

T22

2

User Defined Cross Bins for hmac_dis_x_sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

15839

1

T1

107

T2

386

T3

67

---

Summary for Cross key_x_digest_mismatch

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	35	0	35	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for key_x_digest_mismatch

Bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	sha2_invalid	1301	1			T1	12		T3	2		T5	1
key_invalid	sha2_none	965	1			T1	4		T3	4		T5	1
key_invalid	sha2_512	934	1			T1	5		T3	1		T14	1
key_invalid	sha2_384	948	1			T1	6		T3	6		T5	1
key_invalid	sha2_256	956	1			T1	10		T3	4		T5	1
key_none	sha2_invalid	574	1			T1	4		T3	4		T14	1
key_none	sha2_none	641	1			T1	8		T3	1		T14	3
key_none	sha2_512	2600	1			T1	9		T2	386		T3	3
key_none	sha2_384	2577	1			T1	10		T3	6		T5	1
key_none	sha2_256	1639	1			T1	2		T3	4		T14	2
key_1024	sha2_invalid	550	1			T1	2		T5	2		T14	1
key_1024	sha2_none	591	1			T1	4		T3	6		T5	1
key_1024	sha2_512	1795	1			T1	11		T15	2		T60	2
key_1024	sha2_384	954	1			T1	6		T3	3		T15	1
key_512	sha2_invalid	572	1			T1	4		T3	3		T5	2
key_512	sha2_none	673	1			T1	4		T3	2		T4	2
key_512	sha2_512	650	1			T1	2		T3	5		T14	3
key_512	sha2_384	1286	1			T1	3		T3	1		T14	1
key_512	sha2_256	955	1			T1	7		T3	3		T5	1
key_384	sha2_invalid	604	1			T1	4		T3	6		T14	1
key_384	sha2_none	613	1			T1	7		T3	4		T5	1
key_384	sha2_512	655	1			T1	3		T3	3		T14	1
key_384	sha2_384	672	1			T1	4		T3	2		T16	1
key_384	sha2_256	1126	1			T1	6		T3	6		T5	2
key_256	sha2_invalid	591	1			T1	5		T3	2		T5	1
key_256	sha2_none	628	1			T1	4		T3	1		T5	1
key_256	sha2_512	692	1			T1	7		T3	5		T14	1
key_256	sha2_384	702	1			T1	6		T3	3		T14	1
key_256	sha2_256	837	1			T1	8		T3	3		T14	2
key_128	sha2_invalid	582	1			T1	8		T3	1		T5	1
key_128	sha2_none	593	1			T1	5		T3	2		T14	3
key_128	sha2_512	665	1			T1	5		T3	5		T5	1
key_128	sha2_384	688	1			T1	6		T3	2		T5	2
key_128	sha2_256	712	1			T1	8		T3	7		T5	1

User Defined Cross Bins for key_x_digest_mismatch

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

675

1

T1

4

T3

4

T4

2

---

Summary for Cross key_length_x_digest_size

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	35	0	35	100.00

Automatically Generated Cross Bins for key_length_x_digest_size

Bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	sha2_invalid	1301	1			T1	12		T3	2		T5	1
key_invalid	sha2_none	965	1			T1	4		T3	4		T5	1
key_invalid	sha2_512	934	1			T1	5		T3	1		T14	1
key_invalid	sha2_384	948	1			T1	6		T3	6		T5	1
key_invalid	sha2_256	956	1			T1	10		T3	4		T5	1
key_none	sha2_invalid	574	1			T1	4		T3	4		T14	1
key_none	sha2_none	641	1			T1	8		T3	1		T14	3
key_none	sha2_512	2600	1			T1	9		T2	386		T3	3
key_none	sha2_384	2577	1			T1	10		T3	6		T5	1
key_none	sha2_256	1639	1			T1	2		T3	4		T14	2
key_1024	sha2_invalid	550	1			T1	2		T5	2		T14	1
key_1024	sha2_none	591	1			T1	4		T3	6		T5	1
key_1024	sha2_512	1795	1			T1	11		T15	2		T60	2
key_1024	sha2_384	954	1			T1	6		T3	3		T15	1
key_1024	sha2_256	675	1			T1	4		T3	4		T4	2
key_512	sha2_invalid	572	1			T1	4		T3	3		T5	2
key_512	sha2_none	673	1			T1	4		T3	2		T4	2
key_512	sha2_512	650	1			T1	2		T3	5		T14	3
key_512	sha2_384	1286	1			T1	3		T3	1		T14	1
key_512	sha2_256	955	1			T1	7		T3	3		T5	1
key_384	sha2_invalid	604	1			T1	4		T3	6		T14	1
key_384	sha2_none	613	1			T1	7		T3	4		T5	1
key_384	sha2_512	655	1			T1	3		T3	3		T14	1
key_384	sha2_384	672	1			T1	4		T3	2		T16	1
key_384	sha2_256	1126	1			T1	6		T3	6		T5	2
key_256	sha2_invalid	591	1			T1	5		T3	2		T5	1
key_256	sha2_none	628	1			T1	4		T3	1		T5	1
key_256	sha2_512	692	1			T1	7		T3	5		T14	1
key_256	sha2_384	702	1			T1	6		T3	3		T14	1
key_256	sha2_256	837	1			T1	8		T3	3		T14	2
key_128	sha2_invalid	582	1			T1	8		T3	1		T5	1
key_128	sha2_none	593	1			T1	5		T3	2		T14	3
key_128	sha2_512	665	1			T1	5		T3	5		T5	1
key_128	sha2_384	688	1			T1	6		T3	2		T5	2
key_128	sha2_256	712	1			T1	8		T3	7		T5	1